From 23d3fe115c1f81a080c4f282bb998e7ccf02e03c Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Mon, 9 Nov 2020 13:11:23 +0500 Subject: [PATCH] Bus-buffer testing start --- el2_dec.anno.json | 1706 ++ el2_dec.fir | 17171 ++++++++++++++++ el2_dec.v | 14144 +++++++++++++ el2_dec_decode_ctl.anno.json | 1492 ++ el2_dec_decode_ctl.fir | 5032 +++++ el2_dec_decode_ctl.v | 2824 ++- el2_dec_gpr_ctl.anno.json | 37 + el2_dec_gpr_ctl.fir | 2074 ++ el2_dec_gpr_ctl.v | 1522 ++ el2_dec_ib_ctl.anno.json | 183 + el2_dec_ib_ctl.fir | 71 + el2_dec_ib_ctl.v | 98 + el2_dec_tlu_ctl.anno.json | 508 + el2_dec_tlu_ctl.fir | 8034 ++++++++ el2_dec_tlu_ctl.v | 7181 +++++++ el2_dec_trigger.anno.json | 45 + el2_dec_trigger.fir | 1457 ++ el2_dec_trigger.v | 613 + src/main/scala/dec/el2_dec.scala | 713 + src/main/scala/dec/el2_dec_decode_ctl.scala | 827 + src/main/scala/dec/el2_dec_gpr_ctl.scala | 58 + src/main/scala/dec/el2_dec_ib_ctl.scala | 99 + src/main/scala/dec/el2_dec_tlu_ctl.scala | 2872 +++ src/main/scala/dec/el2_dec_trigger.scala | 20 + .../chisel-module-template.kotlin_module | Bin 16 -> 0 bytes target/scala-2.12/classes/dec/CSR_VAL.class | Bin 0 -> 4081 bytes target/scala-2.12/classes/dec/CSRs.class | Bin 0 -> 23329 bytes target/scala-2.12/classes/dec/csr_tlu.class | Bin 0 -> 214220 bytes .../scala-2.12/classes/dec/dec_decode$.class | Bin 0 -> 3900 bytes .../dec/dec_decode$delayedInit$body.class | Bin 0 -> 757 bytes .../scala-2.12/classes/dec/dec_decode.class | Bin 0 -> 799 bytes target/scala-2.12/classes/dec/dec_main$.class | Bin 0 -> 3856 bytes .../dec/dec_main$delayedInit$body.class | Bin 0 -> 734 bytes target/scala-2.12/classes/dec/dec_main.class | Bin 0 -> 777 bytes target/scala-2.12/classes/dec/dec_trig$.class | Bin 0 -> 3880 bytes .../dec/dec_trig$delayedInit$body.class | Bin 0 -> 742 bytes target/scala-2.12/classes/dec/dec_trig.class | Bin 0 -> 785 bytes .../scala-2.12/classes/dec/el2_CSR_IO.class | Bin 0 -> 82414 bytes target/scala-2.12/classes/dec/el2_dec.class | Bin 0 -> 211279 bytes .../scala-2.12/classes/dec/el2_dec_IO.class | Bin 0 -> 82218 bytes .../classes/dec/el2_dec_decode_csr_read.class | Bin 0 -> 58681 bytes .../dec/el2_dec_decode_csr_read_IO.class | Bin 0 -> 43478 bytes .../dec/el2_dec_decode_ctl$$anon$1.class | Bin 0 -> 17799 bytes .../classes/dec/el2_dec_decode_ctl.class | Bin 0 -> 558087 bytes .../classes/dec/el2_dec_gpr_ctl.class | Bin 0 -> 52629 bytes .../classes/dec/el2_dec_gpr_ctl_IO.class | Bin 0 -> 4008 bytes .../classes/dec/el2_dec_ib_ctl.class | Bin 0 -> 44105 bytes .../classes/dec/el2_dec_ib_ctl_IO.class | Bin 0 -> 42974 bytes .../classes/dec/el2_dec_timer_ctl.class | Bin 0 -> 60165 bytes .../classes/dec/el2_dec_timer_ctl_IO.class | Bin 0 -> 5579 bytes .../classes/dec/el2_dec_tlu_ctl.class | Bin 0 -> 183283 bytes .../classes/dec/el2_dec_tlu_ctl_IO.class | Bin 0 -> 75823 bytes .../classes/dec/el2_dec_trigger$$anon$1.class | Bin 0 -> 2383 bytes .../classes/dec/el2_dec_trigger.class | Bin 0 -> 52072 bytes target/scala-2.12/classes/dec/gpr_gen$.class | Bin 0 -> 3875 bytes .../dec/gpr_gen$delayedInit$body.class | Bin 0 -> 736 bytes target/scala-2.12/classes/dec/gpr_gen.class | Bin 0 -> 780 bytes target/scala-2.12/classes/dec/ib_gen$.class | Bin 0 -> 3867 bytes .../classes/dec/ib_gen$delayedInit$body.class | Bin 0 -> 729 bytes target/scala-2.12/classes/dec/ib_gen.class | Bin 0 -> 774 bytes target/scala-2.12/classes/dec/tlu_gen$.class | Bin 0 -> 3876 bytes .../dec/tlu_gen$delayedInit$body.class | Bin 0 -> 736 bytes target/scala-2.12/classes/dec/tlu_gen.class | Bin 0 -> 780 bytes 63 files changed, 67362 insertions(+), 1419 deletions(-) create mode 100644 el2_dec.anno.json create mode 100644 el2_dec.fir create mode 100644 el2_dec.v create mode 100644 el2_dec_decode_ctl.anno.json create mode 100644 el2_dec_decode_ctl.fir create mode 100644 el2_dec_gpr_ctl.anno.json create mode 100644 el2_dec_gpr_ctl.fir create mode 100644 el2_dec_gpr_ctl.v create mode 100644 el2_dec_ib_ctl.anno.json create mode 100644 el2_dec_ib_ctl.fir create mode 100644 el2_dec_ib_ctl.v create mode 100644 el2_dec_tlu_ctl.anno.json create mode 100644 el2_dec_tlu_ctl.fir create mode 100644 el2_dec_tlu_ctl.v create mode 100644 el2_dec_trigger.anno.json create mode 100644 el2_dec_trigger.fir create mode 100644 el2_dec_trigger.v create mode 100644 src/main/scala/dec/el2_dec.scala create mode 100644 src/main/scala/dec/el2_dec_decode_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_gpr_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_ib_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_tlu_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_trigger.scala delete mode 100644 target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module create mode 100644 target/scala-2.12/classes/dec/CSR_VAL.class create mode 100644 target/scala-2.12/classes/dec/CSRs.class create mode 100644 target/scala-2.12/classes/dec/csr_tlu.class create mode 100644 target/scala-2.12/classes/dec/dec_decode$.class create mode 100644 target/scala-2.12/classes/dec/dec_decode$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_decode.class create mode 100644 target/scala-2.12/classes/dec/dec_main$.class create mode 100644 target/scala-2.12/classes/dec/dec_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_main.class create mode 100644 target/scala-2.12/classes/dec/dec_trig$.class create mode 100644 target/scala-2.12/classes/dec/dec_trig$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_trig.class create mode 100644 target/scala-2.12/classes/dec/el2_CSR_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_csr_read.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_csr_read_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_gpr_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_gpr_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_ib_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_ib_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_timer_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_timer_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_tlu_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_tlu_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_trigger$$anon$1.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_trigger.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen$.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen.class create mode 100644 target/scala-2.12/classes/dec/ib_gen$.class create mode 100644 target/scala-2.12/classes/dec/ib_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/ib_gen.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen$.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen.class diff --git a/el2_dec.anno.json b/el2_dec.anno.json new file mode 100644 index 00000000..8fcfe6bb --- /dev/null +++ b/el2_dec.anno.json @@ -0,0 +1,1706 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_low", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_pc4", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_hist", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_commit_cmt", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_store_data_bypass_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_predict_t", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_br_immed_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_pc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_immed_d", + "sources":[ + "~el2_dec|el2_dec>io_core_id", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_csr_ren_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_debug_wdata_rs1_d", + "sources":[ + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_lsu_offset_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_pred_correct_npc_x", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_pc_x" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_slt", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_start_error", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_sub", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_by", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_div_p_valid", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_decode_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_en_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_data_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data", + "~el2_dec|el2_dec>io_lsu_result_m", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_leak_one_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_valid", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_path_r", + "sources":[ + "~el2_dec|el2_dec>io_rst_vec", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_nmi_vec", + "~el2_dec|el2_dec>io_lsu_fir_addr", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_exu_npc_r", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_type", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_word", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_en_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_unsign", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_select_pc_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_dbg_rddata", + "sources":[ + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_csr_write", + "sources":[ + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_lor", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_bge", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_div_p_rem", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_lower_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_pja", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_data_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data", + "~el2_dec|el2_dec>io_lsu_result_m", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_lsu_valid_raw_d", + "sources":[ + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_valid", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_toffset", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_br_start_error", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_en_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_pret", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_load_ldst_bypass_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_div_cancel", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_middle", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_middle_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_bne", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_way", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_land", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_sll", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_valid", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_valid_r", + "~el2_dec|el2_dec>io_exu_i0_br_mp_r", + "~el2_dec|el2_dec>io_exu_pmu_i0_br_ataken" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_data_en", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_blt", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_rs2_sign", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_alu_decode_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_add", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_lxor", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_beq", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_jal", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_div_p_unsign", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_valid", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_br_error", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_predict_index_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_bp_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_load", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_predict_btag_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_bp_btag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_prett", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_csr_imm", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_dbg_cmd_fail", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_unsign", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_pcall", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_fence_i_r", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_error", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_gpr_i0_rs2_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_hist", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_predict_fghr_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_bp_fghr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_store", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_gpr_i0_rs1_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_predict_nt", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_kill_writeb_r", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_noredir_r", + "sources":[ + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_srl", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_half", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_en_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_rs1_sign", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_way", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_way" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_err_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_sra", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_ctl_en", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_exc_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_dec|el2_dec_trigger>io_dec_i0_trigger_match_d" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec.fir b/el2_dec.fir new file mode 100644 index 00000000..026c8013 --- /dev/null +++ b/el2_dec.fir @@ -0,0 +1,17171 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec : + module el2_dec_ib_ctl : + input clock : Clock + input reset : Reset + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31] + io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20] + node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21] + node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20] + node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21] + node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] + ib0_debug_in <= _T_23 @[Mux.scala 27:72] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22] + + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_dec_ctl : + input clock : Clock + input reset : Reset + output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] + node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] + node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] + node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] + node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] + node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] + node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] + node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] + node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] + node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] + node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] + node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] + node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] + node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] + node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] + node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] + node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] + node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] + node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] + node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] + node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] + node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] + node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] + node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] + node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] + io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] + node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] + node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] + node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] + node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] + node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] + io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] + node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] + node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] + node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] + node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] + node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] + node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] + node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] + node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] + node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] + node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] + node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] + node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] + node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] + io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] + node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] + node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] + node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] + node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] + node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] + node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] + node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] + node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] + node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] + node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] + io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] + node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] + node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] + node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] + io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] + node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] + node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] + node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] + node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] + node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] + node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] + node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] + io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] + node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] + node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] + node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] + node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] + node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] + node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] + node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] + node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] + node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] + node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] + node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] + io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] + node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] + node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] + io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] + node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] + node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] + io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] + node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] + node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] + io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] + node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] + node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] + node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] + node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] + node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] + node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] + node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] + node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] + node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] + node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] + node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] + node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] + node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] + io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] + node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] + node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] + node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] + node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] + node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] + node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] + node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] + node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] + node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] + node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] + node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] + node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] + node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] + node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] + node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] + io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] + node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] + node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] + node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] + node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] + node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] + node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] + node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] + node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] + node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] + io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] + node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] + node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] + node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] + node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] + node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] + node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] + node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] + node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] + node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] + node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] + node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] + node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] + node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] + node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] + node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] + node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] + node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] + node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] + io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] + node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] + node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] + node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] + node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] + node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] + node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] + node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] + node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] + node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] + io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] + node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] + node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] + node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] + node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] + io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] + node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] + node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] + node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] + node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] + io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] + node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] + node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] + node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] + node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] + node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] + io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] + node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] + node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] + node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] + node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] + node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] + node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] + node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] + node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] + node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] + node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] + node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] + io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] + node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] + node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] + node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] + node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] + node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] + node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] + node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] + node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] + node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] + node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] + node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] + node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] + node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] + node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] + node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] + node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] + node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] + node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] + node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] + node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] + node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] + node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] + node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] + io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] + node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] + node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] + io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] + node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] + node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] + node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] + node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] + io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] + node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] + node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] + node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] + node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] + io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] + node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] + node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] + node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] + node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] + io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] + node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] + node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] + node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] + node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] + io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] + node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] + io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] + node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] + node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] + node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] + node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] + io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] + node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] + node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] + node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] + io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] + node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] + node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] + io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] + node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] + node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] + node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] + node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] + node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] + node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] + node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] + node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] + node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] + node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] + node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] + node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] + node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] + node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] + node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] + node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] + node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] + io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] + node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] + node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] + node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] + node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] + node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] + node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] + node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] + node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] + node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] + node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] + node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] + node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] + node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] + node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] + node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] + node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] + node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] + node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] + node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] + node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] + node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] + node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] + io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] + node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] + node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] + io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] + node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] + node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] + node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] + node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] + node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] + node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] + node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] + node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] + node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] + node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] + node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] + node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] + node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] + node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] + node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] + node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] + node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] + io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] + node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] + node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] + node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] + node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] + node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] + node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] + node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] + node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] + node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] + node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] + node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] + node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] + node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] + node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] + io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] + node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] + node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] + node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] + io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] + node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] + node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] + node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] + io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] + node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] + node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] + io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] + node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] + node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] + node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] + io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] + node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] + node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] + node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] + node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] + node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] + node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] + node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] + node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] + node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] + node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] + io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] + node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] + node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] + node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] + node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] + io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] + node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] + node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] + node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] + node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] + io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] + node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] + node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] + node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] + io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] + node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] + node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] + node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] + node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] + io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] + node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] + io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] + node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] + node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] + io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] + node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] + node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] + node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] + node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] + node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] + node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] + node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] + node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] + node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] + node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] + io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] + node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] + node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] + node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] + node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] + node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] + node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] + node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] + node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] + node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] + node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] + node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] + node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] + node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] + node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] + node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] + node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] + node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] + node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] + node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] + node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] + node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] + node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] + node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] + node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] + node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] + node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] + node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] + node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] + node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] + node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] + node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] + node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] + node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] + node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] + node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] + node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] + node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] + node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] + node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] + io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] + node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] + node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] + node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] + node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] + node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] + node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] + node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] + node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] + node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] + node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] + node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] + node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] + node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] + node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] + node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] + node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] + node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] + node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] + node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] + node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] + node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] + node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] + node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] + node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] + node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] + node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] + node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] + node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] + node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] + node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] + node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] + node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] + node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] + node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] + node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] + node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] + node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] + node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] + node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] + node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] + node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] + io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] + node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] + node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] + node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] + node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] + node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] + node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] + node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] + node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] + node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] + node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] + node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] + node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] + node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] + node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] + node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] + node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] + node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] + node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] + node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] + node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] + node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] + node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] + node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] + node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] + node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] + node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] + node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] + node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] + node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] + node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] + node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] + node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] + node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] + node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] + node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] + node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] + node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] + node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] + node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] + node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] + node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] + node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] + node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] + node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] + node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] + node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] + node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] + node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] + node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] + node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] + node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] + node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] + node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] + node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] + node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] + node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] + node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] + node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] + node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] + node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] + node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] + node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] + node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] + node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] + node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] + node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] + node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] + node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] + node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] + node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] + node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] + node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] + node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] + node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] + node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] + node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] + node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] + node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] + node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] + node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] + node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] + node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] + node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] + node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] + node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] + node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] + node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] + node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] + node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] + node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] + node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] + node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] + node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] + node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] + node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] + node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] + node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] + node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] + node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] + node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] + node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] + node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] + node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] + node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] + node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] + node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] + node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] + node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] + node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] + node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] + node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] + node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] + node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] + node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] + node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] + node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] + node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] + node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] + node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] + node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] + node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] + node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] + node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] + node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] + node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] + node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] + node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] + node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] + node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] + node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] + node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] + node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] + node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] + node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] + node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] + node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] + node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] + node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] + node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] + node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] + node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] + node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] + node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] + node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] + node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] + node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] + node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] + node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] + node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] + node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] + node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] + node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] + node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] + node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] + node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] + node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] + node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] + node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] + node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] + node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] + node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] + node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] + node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] + node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] + node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] + node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] + node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] + node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] + node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] + node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] + node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] + node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] + node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] + node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] + node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] + node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] + node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] + node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] + node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] + node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] + node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] + node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] + node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] + node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] + node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] + node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] + node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] + node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] + node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] + node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] + node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] + node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] + node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] + node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] + node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] + node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] + node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] + node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] + node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] + node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] + node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] + node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] + node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] + node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] + node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] + node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] + node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] + node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] + node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] + node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] + node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] + node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] + node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] + node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] + node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] + node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] + node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] + node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] + node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] + node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] + node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] + node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] + node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] + node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] + node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] + node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] + node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] + node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] + node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] + node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] + node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] + node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] + node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] + node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] + node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] + node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] + node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] + node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] + node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] + node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] + node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] + node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] + node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] + node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] + node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] + node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] + node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] + node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] + node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] + node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] + node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] + node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] + node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] + node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] + node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] + node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] + node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] + node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] + node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] + node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] + node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] + node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] + node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] + node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] + node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] + node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] + node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] + node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] + node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] + node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] + node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] + io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_decode_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + + wire _T : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>} @[el2_dec_decode_ctl.scala 126:27] + _T.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.unshfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.shfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.grev <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulh <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bdep <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bext <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + io.mul_p.bfp <= _T.bfp @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_w <= _T.crc32c_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_h <= _T.crc32c_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_b <= _T.crc32c_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_w <= _T.crc32_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_h <= _T.crc32_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_b <= _T.crc32_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.unshfl <= _T.unshfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.shfl <= _T.shfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.grev <= _T.grev @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulr <= _T.clmulr @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulh <= _T.clmulh @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmul <= _T.clmul @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bdep <= _T.bdep @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bext <= _T.bext @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.low <= _T.low @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs2_sign <= _T.rs2_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs1_sign <= _T.rs1_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.valid <= _T.valid @[el2_dec_decode_ctl.scala 126:12] + wire leak1_i1_stall_in : UInt<1> + leak1_i1_stall_in <= UInt<1>("h00") + wire leak1_i0_stall_in : UInt<1> + leak1_i0_stall_in <= UInt<1>("h00") + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 130:17] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 131:17] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 132:17] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] + wire i0_rs1_depth_d : UInt<2> + i0_rs1_depth_d <= UInt<1>("h00") + wire i0_rs2_depth_d : UInt<2> + i0_rs2_depth_d <= UInt<1>("h00") + wire cam_wen : UInt<4> + cam_wen <= UInt<1>("h00") + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam_write : UInt<1> + cam_write <= UInt<1>("h00") + wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] + wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] + wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] + wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] + wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] + wire i0_rs1bypass : UInt<3> + i0_rs1bypass <= UInt<1>("h00") + wire i0_rs2bypass : UInt<3> + i0_rs2bypass <= UInt<1>("h00") + wire illegal_lockout : UInt<1> + illegal_lockout <= UInt<1>("h00") + wire postsync_stall : UInt<1> + postsync_stall <= UInt<1>("h00") + wire ps_stall_in : UInt<1> + ps_stall_in <= UInt<1>("h00") + wire i0_pipe_en : UInt<4> + i0_pipe_en <= UInt<1>("h00") + wire i0_load_block_d : UInt<1> + i0_load_block_d <= UInt<1>("h00") + wire load_ldst_bypass_d : UInt<1> + load_ldst_bypass_d <= UInt<1>("h00") + wire store_data_bypass_d : UInt<1> + store_data_bypass_d <= UInt<1>("h00") + wire store_data_bypass_m : UInt<1> + store_data_bypass_m <= UInt<1>("h00") + wire tlu_wr_pause_r1 : UInt<1> + tlu_wr_pause_r1 <= UInt<1>("h00") + wire tlu_wr_pause_r2 : UInt<1> + tlu_wr_pause_r2 <= UInt<1>("h00") + wire leak1_i1_stall : UInt<1> + leak1_i1_stall <= UInt<1>("h00") + wire leak1_i0_stall : UInt<1> + leak1_i0_stall <= UInt<1>("h00") + wire pause_stall : UInt<1> + pause_stall <= UInt<1>("h00") + wire flush_final_r : UInt<1> + flush_final_r <= UInt<1>("h00") + wire illegal_lockout_in : UInt<1> + illegal_lockout_in <= UInt<1>("h00") + wire lsu_idle : UInt<1> + lsu_idle <= UInt<1>("h00") + wire pause_state_in : UInt<1> + pause_state_in <= UInt<1>("h00") + wire leak1_mode : UInt<1> + leak1_mode <= UInt<1>("h00") + wire i0_pcall : UInt<1> + i0_pcall <= UInt<1>("h00") + wire i0_pja : UInt<1> + i0_pja <= UInt<1>("h00") + wire i0_pret : UInt<1> + i0_pret <= UInt<1>("h00") + wire i0_legal_decode_d : UInt<1> + i0_legal_decode_d <= UInt<1>("h00") + wire i0_pcall_raw : UInt<1> + i0_pcall_raw <= UInt<1>("h00") + wire i0_pja_raw : UInt<1> + i0_pja_raw <= UInt<1>("h00") + wire i0_pret_raw : UInt<1> + i0_pret_raw <= UInt<1>("h00") + wire i0_br_offset : UInt<12> + i0_br_offset <= UInt<1>("h00") + wire i0_csr_write_only_d : UInt<1> + i0_csr_write_only_d <= UInt<1>("h00") + wire i0_jal : UInt<1> + i0_jal <= UInt<1>("h00") + wire i0_wen_r : UInt<1> + i0_wen_r <= UInt<1>("h00") + wire i0_x_ctl_en : UInt<1> + i0_x_ctl_en <= UInt<1>("h00") + wire i0_r_ctl_en : UInt<1> + i0_r_ctl_en <= UInt<1>("h00") + wire i0_wb_ctl_en : UInt<1> + i0_wb_ctl_en <= UInt<1>("h00") + wire i0_x_data_en : UInt<1> + i0_x_data_en <= UInt<1>("h00") + wire i0_r_data_en : UInt<1> + i0_r_data_en <= UInt<1>("h00") + wire i0_wb_data_en : UInt<1> + i0_wb_data_en <= UInt<1>("h00") + wire i0_wb1_data_en : UInt<1> + i0_wb1_data_en <= UInt<1>("h00") + wire i0_nonblock_load_stall : UInt<1> + i0_nonblock_load_stall <= UInt<1>("h00") + wire csr_read : UInt<1> + csr_read <= UInt<1>("h00") + wire lsu_decode_d : UInt<1> + lsu_decode_d <= UInt<1>("h00") + wire mul_decode_d : UInt<1> + mul_decode_d <= UInt<1>("h00") + wire div_decode_d : UInt<1> + div_decode_d <= UInt<1>("h00") + wire write_csr_data : UInt<32> + write_csr_data <= UInt<1>("h00") + wire i0_result_corr_r : UInt<32> + i0_result_corr_r <= UInt<1>("h00") + wire presync_stall : UInt<1> + presync_stall <= UInt<1>("h00") + wire i0_nonblock_div_stall : UInt<1> + i0_nonblock_div_stall <= UInt<1>("h00") + wire debug_fence : UInt<1> + debug_fence <= UInt<1>("h00") + wire i0_immed_d : UInt<32> + i0_immed_d <= UInt<1>("h00") + wire i0_result_x : UInt<32> + i0_result_x <= UInt<1>("h00") + wire i0_result_r : UInt<32> + i0_result_r <= UInt<1>("h00") + node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[el2_dec_decode_ctl.scala 211:51] + node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[el2_dec_decode_ctl.scala 212:32] + node _T_3 = or(_T_1, _T_2) @[el2_dec_decode_ctl.scala 211:73] + node _T_4 = xor(io.dec_tlu_flush_extint, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 213:32] + node _T_5 = or(_T_3, _T_4) @[el2_dec_decode_ctl.scala 212:56] + node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[el2_dec_decode_ctl.scala 214:32] + node _T_7 = or(_T_5, _T_6) @[el2_dec_decode_ctl.scala 213:56] + node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[el2_dec_decode_ctl.scala 215:32] + node _T_9 = or(_T_7, _T_8) @[el2_dec_decode_ctl.scala 214:56] + node _T_10 = xor(pause_state_in, pause_stall) @[el2_dec_decode_ctl.scala 216:32] + node _T_11 = or(_T_9, _T_10) @[el2_dec_decode_ctl.scala 215:56] + node _T_12 = xor(ps_stall_in, postsync_stall) @[el2_dec_decode_ctl.scala 217:32] + node _T_13 = or(_T_11, _T_12) @[el2_dec_decode_ctl.scala 216:56] + node _T_14 = xor(io.exu_flush_final, flush_final_r) @[el2_dec_decode_ctl.scala 218:32] + node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56] + node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32] + node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56] + inst data_gated_cgc of rvclkhdr @[el2_dec_decode_ctl.scala 221:29] + data_gated_cgc.clock <= clock + data_gated_cgc.reset <= reset + data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 222:31] + data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 223:31] + data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 224:31] + node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 229:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 229:60] + io.dec_i0_predict_p_d.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 230:38] + io.dec_i0_predict_p_d.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:38] + io.dec_i0_predict_p_d.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:38] + io.dec_i0_predict_p_d.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 233:38] + io.dec_i0_predict_p_d.pja <= i0_pja @[el2_dec_decode_ctl.scala 234:38] + io.dec_i0_predict_p_d.pret <= i0_pret @[el2_dec_decode_ctl.scala 235:38] + io.dec_i0_predict_p_d.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 236:38] + io.dec_i0_predict_p_d.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 237:38] + io.dec_i0_predict_p_d.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 238:38] + node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 239:55] + io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 239:38] + node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 240:75] + node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 240:90] + node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 240:103] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:56] + node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 240:54] + node _T_23 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 243:67] + node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 243:47] + node _T_25 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 243:96] + node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 243:71] + node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:116] + node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 243:114] + node _T_28 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 244:47] + node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:69] + node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 244:67] + node _T_30 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 245:57] + node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 245:74] + node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 245:96] + node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 246:67] + node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 246:89] + node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 246:87] + io.dec_i0_predict_p_d.br_error <= _T_34 @[el2_dec_decode_ctl.scala 246:51] + node _T_35 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:84] + node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:106] + node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 247:104] + io.dec_i0_predict_p_d.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 247:51] + io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 248:32] + io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 249:32] + node _T_38 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 250:47] + node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 250:81] + node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 250:79] + io.dec_i0_predict_p_d.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 251:44] + io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 252:32] + io.dec_i0_predict_p_d.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 253:51] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 259:36] + i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 262:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 262:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 262:9] + i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 262:9] + i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 262:9] + i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 262:9] + i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 262:9] + i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 262:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 262:9] + i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 262:9] + i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 262:9] + i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 262:9] + i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 262:9] + i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 262:9] + i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 262:9] + i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 262:9] + i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 262:9] + i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 262:9] + i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 262:9] + i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 262:9] + i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 262:9] + i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 262:9] + i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 262:9] + i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 262:9] + i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 262:9] + i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 262:9] + i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 262:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 262:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 262:9] + node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 263:25] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 263:43] + when _T_41 : @[el2_dec_decode_ctl.scala 263:50] + wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 264:35] + _T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 264:20] + i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 264:20] + i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 264:20] + i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 264:20] + i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 264:20] + i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 264:20] + i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 264:20] + i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 264:20] + i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 264:20] + i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 264:20] + i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 264:20] + i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 264:20] + i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 264:20] + i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 264:20] + i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 264:20] + i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 264:20] + i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 264:20] + i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 264:20] + i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 264:20] + i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 264:20] + i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 264:20] + i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 264:20] + i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 264:20] + i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 264:20] + i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 264:20] + i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 264:20] + i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] + i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] + i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20] + i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20] + i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20] + skip @[el2_dec_decode_ctl.scala 263:50] + io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 274:25] + node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 277:38] + node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 277:49] + node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 277:58] + node _T_45 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 279:46] + node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 279:50] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 279:26] + node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 279:66] + node _T_48 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:46] + node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:50] + node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 280:66] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 281:20] + io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 283:26] + io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 284:26] + io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 286:20] + io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 287:20] + io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 288:20] + io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 289:20] + io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 290:20] + io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 291:20] + io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 292:20] + io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 293:20] + io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 294:20] + io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 295:20] + io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 296:20] + io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 297:20] + io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 298:20] + io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 299:20] + io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 300:22] + io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 301:22] + io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 302:22] + node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 306:158] + node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 306:126] + node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 306:158] + node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 306:126] + node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 306:126] + node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 306:158] + node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 306:126] + node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 306:126] + node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 306:126] + node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 306:158] + node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72] + node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] + node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72] + wire _T_87 : UInt<4> @[Mux.scala 27:72] + _T_87 <= _T_86 @[Mux.scala 27:72] + cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 306:11] + cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 308:25] + node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 309:54] + node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 312:59] + node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 314:63] + node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 315:60] + node _T_88 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 317:43] + node nonblock_load_rd = mux(_T_88, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 317:31] + node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 321:116] + reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_89 : @[Reg.scala 28:19] + nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 322:56] + node _T_90 = eq(cam_inv_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 324:45] + node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 324:26] + node _T_93 = eq(cam_data_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 325:45] + node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 325:27] + wire _T_96 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_96.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[0].rd <= _T_96.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].tag <= _T_96.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].wb <= _T_96.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 326:14] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 327:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 327:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 327:11] + cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_97 : @[el2_dec_decode_ctl.scala 329:39] + cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 332:17] + node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_99 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_102 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 337:64] + node _T_104 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 337:95] + node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 337:44] + when _T_106 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 342:44] + node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 342:95] + when _T_111 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_112 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_112.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 350:47] + _T_113.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 350:47] + _T_113.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 350:47] + _T_113.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 350:47] + _T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[0].rd <= _T_113.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].tag <= _T_113.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].wb <= _T_113.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 351:28] + node _T_116 = eq(cam_inv_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 324:45] + node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 324:26] + node _T_119 = eq(cam_data_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 325:45] + node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 325:27] + wire _T_122 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_122.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[1].rd <= _T_122.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].tag <= _T_122.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].wb <= _T_122.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 326:14] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 327:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 327:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 327:11] + cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_123 : @[el2_dec_decode_ctl.scala 329:39] + cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 332:17] + node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_125 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_128 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 337:64] + node _T_130 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 337:95] + node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 337:44] + when _T_132 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 342:44] + node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 342:95] + when _T_137 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_138 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_138.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 350:47] + _T_139.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 350:47] + _T_139.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 350:47] + _T_139.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 350:47] + _T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[1].rd <= _T_139.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].tag <= _T_139.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].wb <= _T_139.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 351:28] + node _T_142 = eq(cam_inv_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 324:45] + node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 324:26] + node _T_145 = eq(cam_data_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 325:45] + node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 325:27] + wire _T_148 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_148.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[2].rd <= _T_148.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].tag <= _T_148.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].wb <= _T_148.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 326:14] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 327:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 327:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 327:11] + cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_149 : @[el2_dec_decode_ctl.scala 329:39] + cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 332:17] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_151 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_154 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 337:64] + node _T_156 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 337:95] + node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 337:44] + when _T_158 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 342:44] + node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 342:95] + when _T_163 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_164 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_164.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 350:47] + _T_165.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 350:47] + _T_165.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 350:47] + _T_165.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 350:47] + _T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[2].rd <= _T_165.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].tag <= _T_165.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].wb <= _T_165.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 351:28] + node _T_168 = eq(cam_inv_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 324:45] + node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 324:26] + node _T_171 = eq(cam_data_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 325:45] + node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 325:27] + wire _T_174 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_174.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[3].rd <= _T_174.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].tag <= _T_174.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].wb <= _T_174.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 326:14] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 327:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 327:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 327:11] + cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_175 : @[el2_dec_decode_ctl.scala 329:39] + cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 332:17] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_177 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_180 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 337:64] + node _T_182 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 337:95] + node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 337:44] + when _T_184 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 342:44] + node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 342:95] + when _T_189 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_190 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_190.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 350:47] + _T_191.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 350:47] + _T_191.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 350:47] + _T_191.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 350:47] + _T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[3].rd <= _T_191.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].tag <= _T_191.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].wb <= _T_191.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 351:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 354:29] + node _T_194 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 356:44] + node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 356:76] + node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 357:95] + node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 357:95] + node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 357:95] + node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 357:99] + node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 357:64] + node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 357:109] + node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 357:106] + io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 357:28] + node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 358:54] + node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 358:66] + node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 358:97] + node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 358:137] + node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 358:149] + node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 358:180] + node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 358:118] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 360:26] + node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_210 = and(_T_209, cam[0].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_212 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 362:136] + node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_215 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 362:197] + node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, cam[1].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_221 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 362:136] + node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_224 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 362:197] + node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_228 = and(_T_227, cam[2].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_230 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 362:136] + node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_233 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 362:197] + node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_237 = and(_T_236, cam[3].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_239 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 362:136] + node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_242 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 362:197] + node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 363:69] + node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 363:69] + node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 363:69] + node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 363:102] + node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 363:102] + node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 363:102] + node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 363:134] + node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 363:134] + node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 363:134] + io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 364:29] + node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 365:38] + node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 365:51] + i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 365:25] + node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 374:34] + node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 374:32] + node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 386:16] + node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 386:30] + node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 387:6] + node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16] + node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 387:30] + node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:18] + node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 388:16] + node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 388:30] + node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16] + node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16] + node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 378:49] + d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 378:21] + inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 395:22] + i0_dec.clock <= clock + i0_dec.reset <= reset + i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 396:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 397:12] + reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 399:45] + _T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 399:45] + lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 399:11] + node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 402:73] + node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 402:71] + node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 402:53] + leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 402:21] + reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 403:56] + _T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 403:56] + leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 403:21] + leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 404:14] + node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 405:45] + node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 405:83] + node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 405:81] + node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 405:63] + leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 405:21] + reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 406:56] + _T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 406:56] + leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 406:21] + node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 410:29] + node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 410:36] + node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 410:46] + node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 410:53] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58] + node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58] + node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 411:46] + node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 411:51] + node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 411:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 411:79] + node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 411:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 411:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 411:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 412:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 412:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 412:98] + node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 412:89] + node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 412:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98] + node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 413:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 413:67] + node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 413:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 414:38] + i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 414:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38] + i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 415:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 416:38] + i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 416:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38] + i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 417:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 418:41] + node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 418:55] + node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 418:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 418:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 418:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 418:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 418:113] + node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] + node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] + node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] + node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 418:26] + i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 418:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 420:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 420:65] + node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 420:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 420:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 420:111] + node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 420:101] + node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 420:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 421:32] + i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 421:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32] + i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 422:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:35] + node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 423:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:52] + node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 423:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:67] + node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 423:65] + i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 423:15] + io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 426:21] + io.div_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 427:21] + io.div_p.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 428:21] + io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 430:21] + io.mul_p.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 431:21] + io.mul_p.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 432:21] + io.mul_p.low <= i0_dp.low @[el2_dec_decode_ctl.scala 433:21] + reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 435:58] + _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 435:58] + io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 435:23] + wire _T_340 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_dec_decode_ctl.scala 437:27] + _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store_data_bypass_m <= _T_340.store_data_bypass_m @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.load_ldst_bypass_d <= _T_340.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store_data_bypass_d <= _T_340.store_data_bypass_d @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.dma <= _T_340.dma @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.unsign <= _T_340.unsign @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store <= _T_340.store @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.load <= _T_340.load @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.dword <= _T_340.dword @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.word <= _T_340.word @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.half <= _T_340.half @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.by <= _T_340.by @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.fast_int <= _T_340.fast_int @[el2_dec_decode_ctl.scala 437:12] + when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 438:29] + io.lsu_p.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 439:24] + io.lsu_p.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:24] + io.lsu_p.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:24] + io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:24] + skip @[el2_dec_decode_ctl.scala 438:29] + else : @[el2_dec_decode_ctl.scala 443:15] + io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 444:35] + io.lsu_p.load <= i0_dp.load @[el2_dec_decode_ctl.scala 445:35] + io.lsu_p.store <= i0_dp.store @[el2_dec_decode_ctl.scala 446:35] + io.lsu_p.by <= i0_dp.by @[el2_dec_decode_ctl.scala 447:35] + io.lsu_p.half <= i0_dp.half @[el2_dec_decode_ctl.scala 448:35] + io.lsu_p.word <= i0_dp.word @[el2_dec_decode_ctl.scala 449:35] + io.lsu_p.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 450:35] + io.lsu_p.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 451:35] + io.lsu_p.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 452:35] + io.lsu_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 453:35] + skip @[el2_dec_decode_ctl.scala 443:15] + io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 457:21] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 458:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 458:36] + csr_read <= _T_342 @[el2_dec_decode_ctl.scala 458:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 460:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 460:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 461:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 461:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 462:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59] + node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 463:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 465:41] + node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 465:39] + i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 465:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 466:42] + node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 466:58] + io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 466:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 469:30] + io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 469:24] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 470:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 474:48] + io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 474:20] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 477:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 477:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 477:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 477:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 477:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 477:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 477:117] + io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 477:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 479:52] + csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 479:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:51] + csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 480:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51] + csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 481:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:53] + csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 482:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:51] + csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 483:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 486:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 486:48] + inst rvclkhdr of rvclkhdr_1 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_363 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + csrimm_x <= _T_362 @[el2_lib.scala 491:16] + node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:62] + inst rvclkhdr_1 of rvclkhdr_2 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 491:16] + node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 490:15] + wire _T_366 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58] + node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58] + node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58] + node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58] + node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58] + node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58] + node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58] + node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58] + node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58] + node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58] + node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58] + node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58] + node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58] + node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58] + node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58] + node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58] + node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58] + node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] + node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] + node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] + node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 490:53] + node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] + node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 491:5] + node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] + wire csr_mask_x : UInt<32> @[Mux.scala 27:72] + csr_mask_x <= _T_399 @[Mux.scala 27:72] + node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 494:38] + node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 494:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 495:35] + node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72] + node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] + wire write_csr_data_x : UInt @[Mux.scala 27:72] + write_csr_data_x <= _T_407 @[Mux.scala 27:72] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 498:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 498:47] + node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 498:109] + node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 498:91] + node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 498:76] + node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 499:44] + node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:61] + node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 499:59] + pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 499:18] + reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 500:50] + _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 500:50] + pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 500:15] + io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 501:22] + reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 502:29] + _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 502:29] + tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 502:19] + reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29] + _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 503:29] + tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 503:19] + node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 505:44] + node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 505:64] + node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 505:61] + node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 505:41] + io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 505:25] + node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 508:59] + node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 508:59] + node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 509:8] + node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 508:30] + node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 510:34] + node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 510:46] + node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 510:61] + node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 510:75] + node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 510:99] + inst rvclkhdr_2 of rvclkhdr_3 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_429 <= write_csr_data_in @[el2_lib.scala 491:16] + write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 511:18] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 517:44] + node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 517:30] + io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 517:24] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 519:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 519:53] + node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 521:67] + node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 521:48] + node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 522:67] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 522:48] + node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 523:40] + debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 523:21] + node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 526:34] + node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 526:57] + node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 526:73] + node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 526:91] + node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 529:36] + node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 529:60] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 529:104] + node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 529:112] + node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 529:99] + node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 529:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 531:34] + io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 532:24] + node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 533:40] + node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 533:51] + node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 533:37] + wire _T_446 : UInt<1>[16] @[el2_lib.scala 161:48] + _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_447 = cat(_T_446[0], _T_446[1]) @[Cat.scala 29:58] + node _T_448 = cat(_T_447, _T_446[2]) @[Cat.scala 29:58] + node _T_449 = cat(_T_448, _T_446[3]) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_446[4]) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_446[5]) @[Cat.scala 29:58] + node _T_452 = cat(_T_451, _T_446[6]) @[Cat.scala 29:58] + node _T_453 = cat(_T_452, _T_446[7]) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_446[8]) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_446[9]) @[Cat.scala 29:58] + node _T_456 = cat(_T_455, _T_446[10]) @[Cat.scala 29:58] + node _T_457 = cat(_T_456, _T_446[11]) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_446[12]) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_446[13]) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 534:27] + node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 537:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 537:47] + node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:44] + node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 538:42] + inst rvclkhdr_3 of rvclkhdr_4 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_465 <= i0_inst_d @[el2_lib.scala 491:16] + io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 539:23] + node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 540:40] + node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 540:61] + node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 540:59] + illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 540:22] + reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 541:54] + _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 541:54] + illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 541:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 542:42] + node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 544:40] + node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 544:59] + node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 544:81] + node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 544:95] + node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 545:20] + node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 545:45] + node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 545:62] + node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 546:19] + node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 546:36] + node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 546:34] + node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 545:79] + node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 546:47] + node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 546:72] + node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 547:21] + node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 547:45] + node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 549:65] + node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 549:39] + node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:63] + node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 550:38] + node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 551:38] + node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 551:57] + node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:46] + node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 555:44] + node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:63] + node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 555:61] + node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:91] + node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 555:89] + io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 555:22] + node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46] + node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 556:44] + node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63] + node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 556:61] + node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91] + node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 556:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 557:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 560:28] + node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 561:51] + node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 561:49] + io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 561:27] + node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 562:47] + io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 562:29] + node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:46] + io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 563:29] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 567:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 568:31] + node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 570:37] + presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 570:22] + reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 571:53] + _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 571:53] + postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 571:18] + node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 573:56] + node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 573:54] + node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 573:39] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 573:88] + node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 573:69] + ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 573:15] + node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 575:50] + io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 575:26] + node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 577:40] + lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 577:16] + node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 578:40] + mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 578:16] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 579:40] + div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 579:16] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 581:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 581:45] + io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 581:29] + d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 584:26] + node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 585:40] + d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 585:26] + node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:50] + d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 586:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 587:26] + node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 589:44] + node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 589:61] + d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 589:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 592:26] + d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 593:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26] + wire _T_519 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[2] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[3] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58] + node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58] + node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58] + node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 596:56] + d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 596:26] + node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 599:33] + inst rvclkhdr_4 of rvclkhdr_5 @[el2_lib.scala 495:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 498:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 501:33] + _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_525.i0trigger <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_525.fence_i <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.icaf_type <= UInt<2>("h00") @[el2_lib.scala 501:33] + _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 501:33] + reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 501:16] + _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 501:16] + _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 501:16] + _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 501:16] + _T_526.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 501:16] + _T_526.i0trigger <= d_t.i0trigger @[el2_lib.scala 501:16] + _T_526.fence_i <= d_t.fence_i @[el2_lib.scala 501:16] + _T_526.icaf_type <= d_t.icaf_type @[el2_lib.scala 501:16] + _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 501:16] + _T_526.icaf <= d_t.icaf @[el2_lib.scala 501:16] + _T_526.legal <= d_t.legal @[el2_lib.scala 501:16] + x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 599:7] + x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 599:7] + x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 599:7] + x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 599:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 601:10] + x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 601:10] + x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 601:10] + x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 601:10] + wire _T_527 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58] + node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58] + node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58] + node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 602:39] + node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 602:37] + x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 602:20] + node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 604:36] + inst rvclkhdr_5 of rvclkhdr_6 @[el2_lib.scala 495:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 498:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 501:33] + _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_534.i0trigger <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_534.fence_i <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.icaf_type <= UInt<2>("h00") @[el2_lib.scala 501:33] + _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 501:33] + reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 501:16] + _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 501:16] + _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 501:16] + _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 501:16] + _T_535.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 501:16] + _T_535.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 501:16] + _T_535.fence_i <= x_t_in.fence_i @[el2_lib.scala 501:16] + _T_535.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 501:16] + _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 501:16] + _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 501:16] + _T_535.legal <= x_t_in.legal @[el2_lib.scala 501:16] + r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 604:7] + r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 604:7] + r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 604:7] + r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 604:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 605:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 605:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 606:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 608:10] + r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 608:10] + r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 608:10] + r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 608:10] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 610:56] + wire _T_537 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_537[0] <= _T_536 @[el2_lib.scala 161:48] + _T_537[1] <= _T_536 @[el2_lib.scala 161:48] + _T_537[2] <= _T_536 @[el2_lib.scala 161:48] + _T_537[3] <= _T_536 @[el2_lib.scala 161:48] + node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] + node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] + node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 610:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 610:95] + r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 610:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 611:33] + node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 613:35] + when _T_543 : @[el2_dec_decode_ctl.scala 613:43] + wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 613:51] + r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 613:51] + r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 613:51] + r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 613:51] + skip @[el2_dec_decode_ctl.scala 613:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 615:39] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 616:53] + io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 616:39] + reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 619:52] + _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 619:52] + flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 619:17] + node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:46] + node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 621:44] + node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:60] + node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 621:58] + node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:88] + node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 621:86] + io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 621:22] + node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 623:16] + i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 623:11] + node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 624:16] + i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 624:11] + node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 625:16] + i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 625:11] + node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 627:49] + node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 627:38] + io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 627:24] + node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49] + node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 628:38] + io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 628:24] + node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:48] + node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 629:37] + io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 630:19] + io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 631:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 633:38] + node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 634:27] + node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38] + node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 638:5] + node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72] + wire _T_566 : UInt<32> @[Mux.scala 27:72] + _T_566 <= _T_565 @[Mux.scala 27:72] + io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 636:21] + node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 641:38] + wire _T_568 : UInt<1>[20] @[el2_lib.scala 161:48] + _T_568[0] <= _T_567 @[el2_lib.scala 161:48] + _T_568[1] <= _T_567 @[el2_lib.scala 161:48] + _T_568[2] <= _T_567 @[el2_lib.scala 161:48] + _T_568[3] <= _T_567 @[el2_lib.scala 161:48] + _T_568[4] <= _T_567 @[el2_lib.scala 161:48] + _T_568[5] <= _T_567 @[el2_lib.scala 161:48] + _T_568[6] <= _T_567 @[el2_lib.scala 161:48] + _T_568[7] <= _T_567 @[el2_lib.scala 161:48] + _T_568[8] <= _T_567 @[el2_lib.scala 161:48] + _T_568[9] <= _T_567 @[el2_lib.scala 161:48] + _T_568[10] <= _T_567 @[el2_lib.scala 161:48] + _T_568[11] <= _T_567 @[el2_lib.scala 161:48] + _T_568[12] <= _T_567 @[el2_lib.scala 161:48] + _T_568[13] <= _T_567 @[el2_lib.scala 161:48] + _T_568[14] <= _T_567 @[el2_lib.scala 161:48] + _T_568[15] <= _T_567 @[el2_lib.scala 161:48] + _T_568[16] <= _T_567 @[el2_lib.scala 161:48] + _T_568[17] <= _T_567 @[el2_lib.scala 161:48] + _T_568[18] <= _T_567 @[el2_lib.scala 161:48] + _T_568[19] <= _T_567 @[el2_lib.scala 161:48] + node _T_569 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58] + node _T_570 = cat(_T_569, _T_568[2]) @[Cat.scala 29:58] + node _T_571 = cat(_T_570, _T_568[3]) @[Cat.scala 29:58] + node _T_572 = cat(_T_571, _T_568[4]) @[Cat.scala 29:58] + node _T_573 = cat(_T_572, _T_568[5]) @[Cat.scala 29:58] + node _T_574 = cat(_T_573, _T_568[6]) @[Cat.scala 29:58] + node _T_575 = cat(_T_574, _T_568[7]) @[Cat.scala 29:58] + node _T_576 = cat(_T_575, _T_568[8]) @[Cat.scala 29:58] + node _T_577 = cat(_T_576, _T_568[9]) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_568[10]) @[Cat.scala 29:58] + node _T_579 = cat(_T_578, _T_568[11]) @[Cat.scala 29:58] + node _T_580 = cat(_T_579, _T_568[12]) @[Cat.scala 29:58] + node _T_581 = cat(_T_580, _T_568[13]) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_568[14]) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_568[15]) @[Cat.scala 29:58] + node _T_584 = cat(_T_583, _T_568[16]) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58] + node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58] + node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 641:46] + node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58] + wire _T_590 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_591 = cat(_T_590[0], _T_590[1]) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_590[2]) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_590[3]) @[Cat.scala 29:58] + node _T_594 = cat(_T_593, _T_590[4]) @[Cat.scala 29:58] + node _T_595 = cat(_T_594, _T_590[5]) @[Cat.scala 29:58] + node _T_596 = cat(_T_595, _T_590[6]) @[Cat.scala 29:58] + node _T_597 = cat(_T_596, _T_590[7]) @[Cat.scala 29:58] + node _T_598 = cat(_T_597, _T_590[8]) @[Cat.scala 29:58] + node _T_599 = cat(_T_598, _T_590[9]) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_590[10]) @[Cat.scala 29:58] + node _T_601 = cat(_T_600, _T_590[11]) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_590[12]) @[Cat.scala 29:58] + node _T_603 = cat(_T_602, _T_590[13]) @[Cat.scala 29:58] + node _T_604 = cat(_T_603, _T_590[14]) @[Cat.scala 29:58] + node _T_605 = cat(_T_604, _T_590[15]) @[Cat.scala 29:58] + node _T_606 = cat(_T_605, _T_590[16]) @[Cat.scala 29:58] + node _T_607 = cat(_T_606, _T_590[17]) @[Cat.scala 29:58] + node _T_608 = cat(_T_607, _T_590[18]) @[Cat.scala 29:58] + node _T_609 = cat(_T_608, _T_590[19]) @[Cat.scala 29:58] + node _T_610 = cat(_T_609, _T_590[20]) @[Cat.scala 29:58] + node _T_611 = cat(_T_610, _T_590[21]) @[Cat.scala 29:58] + node _T_612 = cat(_T_611, _T_590[22]) @[Cat.scala 29:58] + node _T_613 = cat(_T_612, _T_590[23]) @[Cat.scala 29:58] + node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58] + node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58] + node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 642:43] + node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58] + node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 643:38] + wire _T_620 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_620[0] <= _T_619 @[el2_lib.scala 161:48] + _T_620[1] <= _T_619 @[el2_lib.scala 161:48] + _T_620[2] <= _T_619 @[el2_lib.scala 161:48] + _T_620[3] <= _T_619 @[el2_lib.scala 161:48] + _T_620[4] <= _T_619 @[el2_lib.scala 161:48] + _T_620[5] <= _T_619 @[el2_lib.scala 161:48] + _T_620[6] <= _T_619 @[el2_lib.scala 161:48] + _T_620[7] <= _T_619 @[el2_lib.scala 161:48] + _T_620[8] <= _T_619 @[el2_lib.scala 161:48] + _T_620[9] <= _T_619 @[el2_lib.scala 161:48] + _T_620[10] <= _T_619 @[el2_lib.scala 161:48] + _T_620[11] <= _T_619 @[el2_lib.scala 161:48] + node _T_621 = cat(_T_620[0], _T_620[1]) @[Cat.scala 29:58] + node _T_622 = cat(_T_621, _T_620[2]) @[Cat.scala 29:58] + node _T_623 = cat(_T_622, _T_620[3]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_620[4]) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_620[5]) @[Cat.scala 29:58] + node _T_626 = cat(_T_625, _T_620[6]) @[Cat.scala 29:58] + node _T_627 = cat(_T_626, _T_620[7]) @[Cat.scala 29:58] + node _T_628 = cat(_T_627, _T_620[8]) @[Cat.scala 29:58] + node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58] + node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58] + node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 643:46] + node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 643:56] + node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 643:63] + node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58] + node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58] + node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58] + node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 644:30] + wire _T_640 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58] + node _T_644 = cat(_T_643, _T_640[4]) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_640[5]) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_640[6]) @[Cat.scala 29:58] + node _T_647 = cat(_T_646, _T_640[7]) @[Cat.scala 29:58] + node _T_648 = cat(_T_647, _T_640[8]) @[Cat.scala 29:58] + node _T_649 = cat(_T_648, _T_640[9]) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58] + node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58] + node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58] + node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 645:26] + node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 645:43] + wire _T_655 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_656 = cat(_T_655[0], _T_655[1]) @[Cat.scala 29:58] + node _T_657 = cat(_T_656, _T_655[2]) @[Cat.scala 29:58] + node _T_658 = cat(_T_657, _T_655[3]) @[Cat.scala 29:58] + node _T_659 = cat(_T_658, _T_655[4]) @[Cat.scala 29:58] + node _T_660 = cat(_T_659, _T_655[5]) @[Cat.scala 29:58] + node _T_661 = cat(_T_660, _T_655[6]) @[Cat.scala 29:58] + node _T_662 = cat(_T_661, _T_655[7]) @[Cat.scala 29:58] + node _T_663 = cat(_T_662, _T_655[8]) @[Cat.scala 29:58] + node _T_664 = cat(_T_663, _T_655[9]) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_655[10]) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_655[11]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_655[12]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_655[13]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_655[14]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_655[15]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_655[16]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_655[17]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_655[18]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_655[19]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_655[20]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_655[21]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_655[22]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_655[23]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58] + node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 645:72] + node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58] + node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_686 = mux(i0_jalimm20, _T_638, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_687 = mux(i0_uiimm20, _T_652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_688 = mux(_T_654, _T_683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_689 = or(_T_684, _T_685) @[Mux.scala 27:72] + node _T_690 = or(_T_689, _T_686) @[Mux.scala 27:72] + node _T_691 = or(_T_690, _T_687) @[Mux.scala 27:72] + node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72] + wire _T_693 : UInt<32> @[Mux.scala 27:72] + _T_693 <= _T_692 @[Mux.scala 27:72] + i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 640:14] + node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 647:46] + i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 647:24] + node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 649:44] + i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 649:29] + node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44] + i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 650:29] + node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44] + i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 651:29] + node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 653:71] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_698 : @[Reg.scala 16:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_699 : @[Reg.scala 16:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 655:83] + reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 655:72] + _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 655:72] + node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58] + i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 655:14] + node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 657:43] + node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 657:49] + node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 657:53] + i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 657:29] + node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 658:43] + node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 658:49] + node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 658:53] + i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 658:29] + node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 659:43] + node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 659:49] + node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 659:53] + i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 659:29] + node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 660:44] + node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 660:50] + i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 660:29] + node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 661:44] + node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 661:50] + i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 661:29] + node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 662:44] + node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 662:50] + i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 662:29] + node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 663:44] + node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 663:50] + i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 663:29] + node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 665:27] + node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 666:27] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 668:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 669:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 670:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 672:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 672:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 673:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 674:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 676:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 676:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 677:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 677:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 678:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 678:29] + node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 680:34] + inst rvclkhdr_6 of rvclkhdr_7 @[el2_lib.scala 495:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 498:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 501:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 501:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 501:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 501:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 501:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 501:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 501:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 501:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 501:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 501:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 680:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 680:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 680:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 680:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 680:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 680:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 680:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 680:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 680:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 681:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 682:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 682:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 682:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 683:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 683:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 683:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 683:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 683:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 684:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 684:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 684:22] + node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 686:36] + inst rvclkhdr_7 of rvclkhdr_8 @[el2_lib.scala 495:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 498:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 501:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 501:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 501:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 501:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 501:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 501:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 501:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 501:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 501:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 501:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 686:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 686:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 686:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 686:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 686:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 686:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 686:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 686:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 686:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 687:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 687:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 688:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 690:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 691:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 691:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 692:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 692:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 693:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 693:22] + node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 695:37] + inst rvclkhdr_8 of rvclkhdr_9 @[el2_lib.scala 495:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 498:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 501:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 501:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 501:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 501:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 501:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 501:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 501:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 501:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 501:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 501:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 695:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 695:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 695:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 695:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 695:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 695:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 695:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 695:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 695:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 697:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 698:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 698:40] + i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 698:25] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:49] + node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 699:47] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 699:63] + io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 699:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 700:26] + node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 702:57] + inst rvclkhdr_9 of rvclkhdr_10 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_result_r_raw <= i0_result_x @[el2_lib.scala 491:16] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 708:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 708:56] + node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 708:32] + i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 708:26] + i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 709:26] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 713:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 713:51] + node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 713:27] + i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 713:21] + node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 714:54] + node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 714:52] + node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 714:66] + wire _T_770 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_771 = cat(_T_770[0], _T_770[1]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_770[2]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_770[3]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_770[4]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_770[5]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_770[6]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_770[7]) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, _T_770[8]) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58] + node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58] + node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 714:30] + io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 714:24] + wire last_br_immed_d : UInt<12> + last_br_immed_d <= UInt<1>("h00") + node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 716:48] + wire _T_784 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_785 = cat(_T_784[0], _T_784[1]) @[Cat.scala 29:58] + node _T_786 = cat(_T_785, _T_784[2]) @[Cat.scala 29:58] + node _T_787 = cat(_T_786, _T_784[3]) @[Cat.scala 29:58] + node _T_788 = cat(_T_787, _T_784[4]) @[Cat.scala 29:58] + node _T_789 = cat(_T_788, _T_784[5]) @[Cat.scala 29:58] + node _T_790 = cat(_T_789, _T_784[6]) @[Cat.scala 29:58] + node _T_791 = cat(_T_790, _T_784[7]) @[Cat.scala 29:58] + node _T_792 = cat(_T_791, _T_784[8]) @[Cat.scala 29:58] + node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58] + node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 716:25] + last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 716:19] + wire last_br_immed_x : UInt<12> + last_br_immed_x <= UInt<1>("h00") + node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 718:58] + inst rvclkhdr_10 of rvclkhdr_11 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_798 <= last_br_immed_d @[el2_lib.scala 491:16] + last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 718:19] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 722:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 722:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 724:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 724:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 724:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 725:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 725:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 724:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 726:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 726:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 725:59] + node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 730:51] + node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 731:26] + node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 731:24] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 731:51] + node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 731:39] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 731:72] + node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 730:65] + node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 733:53] + io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 733:29] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 734:55] + node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 736:62] + node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 736:60] + node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 736:81] + node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 736:79] + node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 736:39] + reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 738:54] + _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 738:54] + io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 738:21] + node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 741:49] + node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 741:88] + node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 741:69] + node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:25] + node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 742:64] + node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 742:45] + node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 741:102] + i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 741:26] + node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 744:59] + reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_829 : @[Reg.scala 28:19] + _T_830 <= i0r.rd @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 744:19] + node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 751:34] + node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 751:57] + inst rvclkhdr_11 of rvclkhdr_12 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + div_inst <= _T_831 @[el2_lib.scala 491:16] + node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 752:49] + inst rvclkhdr_12 of rvclkhdr_13 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_x <= i0_inst_d @[el2_lib.scala 491:16] + node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49] + inst rvclkhdr_13 of rvclkhdr_14 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_r <= i0_inst_x @[el2_lib.scala 491:16] + node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 755:50] + inst rvclkhdr_14 of rvclkhdr_15 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_wb <= i0_inst_r @[el2_lib.scala 491:16] + node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:53] + inst rvclkhdr_15 of rvclkhdr_16 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_837 <= i0_inst_wb @[el2_lib.scala 491:16] + io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 756:22] + node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53] + inst rvclkhdr_16 of rvclkhdr_17 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 491:16] + node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 759:49] + inst rvclkhdr_17 of rvclkhdr_18 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_840 <= i0_pc_wb @[el2_lib.scala 491:16] + io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 759:20] + node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:56] + inst rvclkhdr_18 of rvclkhdr_19 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 491:16] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 762:27] + node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 206:24] + node _T_845 = bits(_T_843, 12, 1) @[el2_lib.scala 206:40] + node _T_846 = add(_T_844, _T_845) @[el2_lib.scala 206:31] + node _T_847 = bits(_T_842, 31, 13) @[el2_lib.scala 207:20] + node _T_848 = add(_T_847, UInt<1>("h01")) @[el2_lib.scala 207:27] + node _T_849 = tail(_T_848, 1) @[el2_lib.scala 207:27] + node _T_850 = bits(_T_842, 31, 13) @[el2_lib.scala 208:20] + node _T_851 = sub(_T_850, UInt<1>("h01")) @[el2_lib.scala 208:27] + node _T_852 = tail(_T_851, 1) @[el2_lib.scala 208:27] + node _T_853 = bits(_T_843, 12, 12) @[el2_lib.scala 209:22] + node _T_854 = bits(_T_846, 12, 12) @[el2_lib.scala 210:39] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_lib.scala 210:28] + node _T_856 = xor(_T_853, _T_855) @[el2_lib.scala 210:26] + node _T_857 = bits(_T_856, 0, 0) @[el2_lib.scala 210:64] + node _T_858 = bits(_T_842, 31, 13) @[el2_lib.scala 210:76] + node _T_859 = eq(_T_853, UInt<1>("h00")) @[el2_lib.scala 211:20] + node _T_860 = bits(_T_846, 12, 12) @[el2_lib.scala 211:39] + node _T_861 = and(_T_859, _T_860) @[el2_lib.scala 211:26] + node _T_862 = bits(_T_861, 0, 0) @[el2_lib.scala 211:64] + node _T_863 = bits(_T_846, 12, 12) @[el2_lib.scala 212:39] + node _T_864 = eq(_T_863, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_865 = and(_T_853, _T_864) @[el2_lib.scala 212:26] + node _T_866 = bits(_T_865, 0, 0) @[el2_lib.scala 212:64] + node _T_867 = mux(_T_857, _T_858, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_868 = mux(_T_862, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_869 = mux(_T_866, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_870 = or(_T_867, _T_868) @[Mux.scala 27:72] + node _T_871 = or(_T_870, _T_869) @[Mux.scala 27:72] + wire _T_872 : UInt<19> @[Mux.scala 27:72] + _T_872 <= _T_871 @[Mux.scala 27:72] + node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 212:94] + node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 767:51] + io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 767:25] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 771:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 772:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 774:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 774:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 774:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 775:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 775:58] + node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 777:44] + node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 777:81] + wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 777:109] + _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 777:61] + node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 777:24] + i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 777:18] + i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 777:18] + i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 777:18] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:83] + node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 778:63] + node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 778:24] + i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 778:18] + node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44] + node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:81] + wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 779:109] + _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 779:61] + node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 779:24] + i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 779:18] + i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 779:18] + i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 779:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:83] + node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 780:63] + node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 780:24] + i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 780:18] + i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 790:21] + node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 791:43] + node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 791:74] + node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 791:58] + node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 791:78] + load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 791:27] + node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:59] + node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 792:43] + node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 792:63] + store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 792:25] + store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 793:25] + node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 797:62] + node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 797:119] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 797:89] + node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 799:62] + node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 799:119] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 799:89] + node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 802:41] + node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 802:66] + node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 802:45] + node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 802:104] + node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 802:108] + node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 802:149] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 802:175] + node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 802:196] + node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 802:153] + node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58] + node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58] + i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 802:18] + node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 804:41] + node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 804:67] + node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 804:45] + node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 804:105] + node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 804:109] + node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 804:149] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 804:175] + node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 804:196] + node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 804:153] + node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58] + i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 804:18] + node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 806:54] + node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 806:71] + node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 806:89] + node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 806:75] + node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 806:109] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 806:96] + node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 806:113] + node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 806:93] + node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58] + io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 806:34] + node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54] + node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71] + node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89] + node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 807:75] + node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96] + node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113] + node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 807:93] + node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58] + io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 807:34] + node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 810:17] + node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 810:21] + node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 811:17] + node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 811:21] + node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 812:19] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 812:6] + node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:38] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 812:25] + node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 812:23] + node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 812:42] + node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 812:78] + node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_967 = or(_T_964, _T_965) @[Mux.scala 27:72] + node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72] + wire _T_969 : UInt<32> @[Mux.scala 27:72] + _T_969 <= _T_968 @[Mux.scala 27:72] + io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 809:31] + node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 815:17] + node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 815:21] + node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 816:17] + node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 816:21] + node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 817:19] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:6] + node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:38] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:25] + node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 817:23] + node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 817:42] + node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 817:78] + node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_984 = or(_T_981, _T_982) @[Mux.scala 27:72] + node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72] + wire _T_986 : UInt<32> @[Mux.scala 27:72] + _T_986 <= _T_985 @[Mux.scala 27:72] + io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 814:31] + node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 819:68] + node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 819:50] + node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:89] + node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 819:87] + node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:114] + node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 819:112] + node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 819:131] + io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 819:26] + node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 821:6] + node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 821:27] + node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 821:39] + node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 821:53] + node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 821:70] + node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27] + node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 822:39] + node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 822:54] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 822:74] + node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 822:84] + node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58] + node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72] + wire _T_1009 : UInt<12> @[Mux.scala 27:72] + _T_1009 <= _T_1008 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 820:23] + + extmodule TEC_RV_ICG_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_26 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_27 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_28 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_29 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_30 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_31 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_32 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_33 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_34 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_35 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_36 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_37 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_38 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_39 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_40 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_41 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_42 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_43 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_43 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_43 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_44 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_44 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_44 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_45 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_45 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_45 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_46 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_46 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_46 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_47 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_47 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_47 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_48 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_48 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_48 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_49 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_49 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_49 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_50 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_50 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_50 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_gpr_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} + + wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 11:30] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 12:30] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 13:22] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 14:22] + wire gpr_wr_en : UInt<32> @[el2_dec_gpr_ctl.scala 15:22] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 16:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 18:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 19:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 21:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 22:9] + node _T = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_1 = cat(w0v[2], _T) @[Cat.scala 29:58] + node _T_2 = cat(w0v[3], _T_1) @[Cat.scala 29:58] + node _T_3 = cat(w0v[4], _T_2) @[Cat.scala 29:58] + node _T_4 = cat(w0v[5], _T_3) @[Cat.scala 29:58] + node _T_5 = cat(w0v[6], _T_4) @[Cat.scala 29:58] + node _T_6 = cat(w0v[7], _T_5) @[Cat.scala 29:58] + node _T_7 = cat(w0v[8], _T_6) @[Cat.scala 29:58] + node _T_8 = cat(w0v[9], _T_7) @[Cat.scala 29:58] + node _T_9 = cat(w0v[10], _T_8) @[Cat.scala 29:58] + node _T_10 = cat(w0v[11], _T_9) @[Cat.scala 29:58] + node _T_11 = cat(w0v[12], _T_10) @[Cat.scala 29:58] + node _T_12 = cat(w0v[13], _T_11) @[Cat.scala 29:58] + node _T_13 = cat(w0v[14], _T_12) @[Cat.scala 29:58] + node _T_14 = cat(w0v[15], _T_13) @[Cat.scala 29:58] + node _T_15 = cat(w0v[16], _T_14) @[Cat.scala 29:58] + node _T_16 = cat(w0v[17], _T_15) @[Cat.scala 29:58] + node _T_17 = cat(w0v[18], _T_16) @[Cat.scala 29:58] + node _T_18 = cat(w0v[19], _T_17) @[Cat.scala 29:58] + node _T_19 = cat(w0v[20], _T_18) @[Cat.scala 29:58] + node _T_20 = cat(w0v[21], _T_19) @[Cat.scala 29:58] + node _T_21 = cat(w0v[22], _T_20) @[Cat.scala 29:58] + node _T_22 = cat(w0v[23], _T_21) @[Cat.scala 29:58] + node _T_23 = cat(w0v[24], _T_22) @[Cat.scala 29:58] + node _T_24 = cat(w0v[25], _T_23) @[Cat.scala 29:58] + node _T_25 = cat(w0v[26], _T_24) @[Cat.scala 29:58] + node _T_26 = cat(w0v[27], _T_25) @[Cat.scala 29:58] + node _T_27 = cat(w0v[28], _T_26) @[Cat.scala 29:58] + node _T_28 = cat(w0v[29], _T_27) @[Cat.scala 29:58] + node _T_29 = cat(w0v[30], _T_28) @[Cat.scala 29:58] + node _T_30 = cat(w0v[31], _T_29) @[Cat.scala 29:58] + node _T_31 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_32 = cat(w1v[2], _T_31) @[Cat.scala 29:58] + node _T_33 = cat(w1v[3], _T_32) @[Cat.scala 29:58] + node _T_34 = cat(w1v[4], _T_33) @[Cat.scala 29:58] + node _T_35 = cat(w1v[5], _T_34) @[Cat.scala 29:58] + node _T_36 = cat(w1v[6], _T_35) @[Cat.scala 29:58] + node _T_37 = cat(w1v[7], _T_36) @[Cat.scala 29:58] + node _T_38 = cat(w1v[8], _T_37) @[Cat.scala 29:58] + node _T_39 = cat(w1v[9], _T_38) @[Cat.scala 29:58] + node _T_40 = cat(w1v[10], _T_39) @[Cat.scala 29:58] + node _T_41 = cat(w1v[11], _T_40) @[Cat.scala 29:58] + node _T_42 = cat(w1v[12], _T_41) @[Cat.scala 29:58] + node _T_43 = cat(w1v[13], _T_42) @[Cat.scala 29:58] + node _T_44 = cat(w1v[14], _T_43) @[Cat.scala 29:58] + node _T_45 = cat(w1v[15], _T_44) @[Cat.scala 29:58] + node _T_46 = cat(w1v[16], _T_45) @[Cat.scala 29:58] + node _T_47 = cat(w1v[17], _T_46) @[Cat.scala 29:58] + node _T_48 = cat(w1v[18], _T_47) @[Cat.scala 29:58] + node _T_49 = cat(w1v[19], _T_48) @[Cat.scala 29:58] + node _T_50 = cat(w1v[20], _T_49) @[Cat.scala 29:58] + node _T_51 = cat(w1v[21], _T_50) @[Cat.scala 29:58] + node _T_52 = cat(w1v[22], _T_51) @[Cat.scala 29:58] + node _T_53 = cat(w1v[23], _T_52) @[Cat.scala 29:58] + node _T_54 = cat(w1v[24], _T_53) @[Cat.scala 29:58] + node _T_55 = cat(w1v[25], _T_54) @[Cat.scala 29:58] + node _T_56 = cat(w1v[26], _T_55) @[Cat.scala 29:58] + node _T_57 = cat(w1v[27], _T_56) @[Cat.scala 29:58] + node _T_58 = cat(w1v[28], _T_57) @[Cat.scala 29:58] + node _T_59 = cat(w1v[29], _T_58) @[Cat.scala 29:58] + node _T_60 = cat(w1v[30], _T_59) @[Cat.scala 29:58] + node _T_61 = cat(w1v[31], _T_60) @[Cat.scala 29:58] + node _T_62 = or(_T_30, _T_61) @[el2_dec_gpr_ctl.scala 23:51] + node _T_63 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_64 = cat(w2v[2], _T_63) @[Cat.scala 29:58] + node _T_65 = cat(w2v[3], _T_64) @[Cat.scala 29:58] + node _T_66 = cat(w2v[4], _T_65) @[Cat.scala 29:58] + node _T_67 = cat(w2v[5], _T_66) @[Cat.scala 29:58] + node _T_68 = cat(w2v[6], _T_67) @[Cat.scala 29:58] + node _T_69 = cat(w2v[7], _T_68) @[Cat.scala 29:58] + node _T_70 = cat(w2v[8], _T_69) @[Cat.scala 29:58] + node _T_71 = cat(w2v[9], _T_70) @[Cat.scala 29:58] + node _T_72 = cat(w2v[10], _T_71) @[Cat.scala 29:58] + node _T_73 = cat(w2v[11], _T_72) @[Cat.scala 29:58] + node _T_74 = cat(w2v[12], _T_73) @[Cat.scala 29:58] + node _T_75 = cat(w2v[13], _T_74) @[Cat.scala 29:58] + node _T_76 = cat(w2v[14], _T_75) @[Cat.scala 29:58] + node _T_77 = cat(w2v[15], _T_76) @[Cat.scala 29:58] + node _T_78 = cat(w2v[16], _T_77) @[Cat.scala 29:58] + node _T_79 = cat(w2v[17], _T_78) @[Cat.scala 29:58] + node _T_80 = cat(w2v[18], _T_79) @[Cat.scala 29:58] + node _T_81 = cat(w2v[19], _T_80) @[Cat.scala 29:58] + node _T_82 = cat(w2v[20], _T_81) @[Cat.scala 29:58] + node _T_83 = cat(w2v[21], _T_82) @[Cat.scala 29:58] + node _T_84 = cat(w2v[22], _T_83) @[Cat.scala 29:58] + node _T_85 = cat(w2v[23], _T_84) @[Cat.scala 29:58] + node _T_86 = cat(w2v[24], _T_85) @[Cat.scala 29:58] + node _T_87 = cat(w2v[25], _T_86) @[Cat.scala 29:58] + node _T_88 = cat(w2v[26], _T_87) @[Cat.scala 29:58] + node _T_89 = cat(w2v[27], _T_88) @[Cat.scala 29:58] + node _T_90 = cat(w2v[28], _T_89) @[Cat.scala 29:58] + node _T_91 = cat(w2v[29], _T_90) @[Cat.scala 29:58] + node _T_92 = cat(w2v[30], _T_91) @[Cat.scala 29:58] + node _T_93 = cat(w2v[31], _T_92) @[Cat.scala 29:58] + node _T_94 = or(_T_62, _T_93) @[el2_dec_gpr_ctl.scala 23:89] + gpr_wr_en <= _T_94 @[el2_dec_gpr_ctl.scala 23:12] + node _T_95 = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_96 = and(io.wen0, _T_95) @[el2_dec_gpr_ctl.scala 26:28] + w0v[1] <= _T_96 @[el2_dec_gpr_ctl.scala 26:16] + node _T_97 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_98 = and(io.wen1, _T_97) @[el2_dec_gpr_ctl.scala 27:28] + w1v[1] <= _T_98 @[el2_dec_gpr_ctl.scala 27:16] + node _T_99 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_100 = and(io.wen2, _T_99) @[el2_dec_gpr_ctl.scala 28:28] + w2v[1] <= _T_100 @[el2_dec_gpr_ctl.scala 28:16] + node _T_101 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_103 = and(_T_102, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_104 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_106 = and(_T_105, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_107 = or(_T_103, _T_106) @[el2_dec_gpr_ctl.scala 29:47] + node _T_108 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_110 = and(_T_109, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_111 = or(_T_107, _T_110) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[1] <= _T_111 @[el2_dec_gpr_ctl.scala 29:16] + node _T_112 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_113 = and(io.wen0, _T_112) @[el2_dec_gpr_ctl.scala 26:28] + w0v[2] <= _T_113 @[el2_dec_gpr_ctl.scala 26:16] + node _T_114 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_115 = and(io.wen1, _T_114) @[el2_dec_gpr_ctl.scala 27:28] + w1v[2] <= _T_115 @[el2_dec_gpr_ctl.scala 27:16] + node _T_116 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_117 = and(io.wen2, _T_116) @[el2_dec_gpr_ctl.scala 28:28] + w2v[2] <= _T_117 @[el2_dec_gpr_ctl.scala 28:16] + node _T_118 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_119 = mux(_T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_120 = and(_T_119, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_121 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_122 = mux(_T_121, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_123 = and(_T_122, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_124 = or(_T_120, _T_123) @[el2_dec_gpr_ctl.scala 29:47] + node _T_125 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_128 = or(_T_124, _T_127) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[2] <= _T_128 @[el2_dec_gpr_ctl.scala 29:16] + node _T_129 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_130 = and(io.wen0, _T_129) @[el2_dec_gpr_ctl.scala 26:28] + w0v[3] <= _T_130 @[el2_dec_gpr_ctl.scala 26:16] + node _T_131 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_132 = and(io.wen1, _T_131) @[el2_dec_gpr_ctl.scala 27:28] + w1v[3] <= _T_132 @[el2_dec_gpr_ctl.scala 27:16] + node _T_133 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_134 = and(io.wen2, _T_133) @[el2_dec_gpr_ctl.scala 28:28] + w2v[3] <= _T_134 @[el2_dec_gpr_ctl.scala 28:16] + node _T_135 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_136 = mux(_T_135, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_137 = and(_T_136, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_138 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_139 = mux(_T_138, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_140 = and(_T_139, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_141 = or(_T_137, _T_140) @[el2_dec_gpr_ctl.scala 29:47] + node _T_142 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(_T_143, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_145 = or(_T_141, _T_144) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[3] <= _T_145 @[el2_dec_gpr_ctl.scala 29:16] + node _T_146 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_147 = and(io.wen0, _T_146) @[el2_dec_gpr_ctl.scala 26:28] + w0v[4] <= _T_147 @[el2_dec_gpr_ctl.scala 26:16] + node _T_148 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_149 = and(io.wen1, _T_148) @[el2_dec_gpr_ctl.scala 27:28] + w1v[4] <= _T_149 @[el2_dec_gpr_ctl.scala 27:16] + node _T_150 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_151 = and(io.wen2, _T_150) @[el2_dec_gpr_ctl.scala 28:28] + w2v[4] <= _T_151 @[el2_dec_gpr_ctl.scala 28:16] + node _T_152 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_153 = mux(_T_152, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_154 = and(_T_153, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_155 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_156 = mux(_T_155, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_157 = and(_T_156, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_158 = or(_T_154, _T_157) @[el2_dec_gpr_ctl.scala 29:47] + node _T_159 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_161 = and(_T_160, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_162 = or(_T_158, _T_161) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[4] <= _T_162 @[el2_dec_gpr_ctl.scala 29:16] + node _T_163 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_164 = and(io.wen0, _T_163) @[el2_dec_gpr_ctl.scala 26:28] + w0v[5] <= _T_164 @[el2_dec_gpr_ctl.scala 26:16] + node _T_165 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_166 = and(io.wen1, _T_165) @[el2_dec_gpr_ctl.scala 27:28] + w1v[5] <= _T_166 @[el2_dec_gpr_ctl.scala 27:16] + node _T_167 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_168 = and(io.wen2, _T_167) @[el2_dec_gpr_ctl.scala 28:28] + w2v[5] <= _T_168 @[el2_dec_gpr_ctl.scala 28:16] + node _T_169 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_171 = and(_T_170, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_172 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(_T_173, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_175 = or(_T_171, _T_174) @[el2_dec_gpr_ctl.scala 29:47] + node _T_176 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_178 = and(_T_177, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_179 = or(_T_175, _T_178) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[5] <= _T_179 @[el2_dec_gpr_ctl.scala 29:16] + node _T_180 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_181 = and(io.wen0, _T_180) @[el2_dec_gpr_ctl.scala 26:28] + w0v[6] <= _T_181 @[el2_dec_gpr_ctl.scala 26:16] + node _T_182 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_183 = and(io.wen1, _T_182) @[el2_dec_gpr_ctl.scala 27:28] + w1v[6] <= _T_183 @[el2_dec_gpr_ctl.scala 27:16] + node _T_184 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_185 = and(io.wen2, _T_184) @[el2_dec_gpr_ctl.scala 28:28] + w2v[6] <= _T_185 @[el2_dec_gpr_ctl.scala 28:16] + node _T_186 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_187 = mux(_T_186, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_188 = and(_T_187, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_189 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_191 = and(_T_190, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_192 = or(_T_188, _T_191) @[el2_dec_gpr_ctl.scala 29:47] + node _T_193 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_196 = or(_T_192, _T_195) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[6] <= _T_196 @[el2_dec_gpr_ctl.scala 29:16] + node _T_197 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_198 = and(io.wen0, _T_197) @[el2_dec_gpr_ctl.scala 26:28] + w0v[7] <= _T_198 @[el2_dec_gpr_ctl.scala 26:16] + node _T_199 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_200 = and(io.wen1, _T_199) @[el2_dec_gpr_ctl.scala 27:28] + w1v[7] <= _T_200 @[el2_dec_gpr_ctl.scala 27:16] + node _T_201 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_202 = and(io.wen2, _T_201) @[el2_dec_gpr_ctl.scala 28:28] + w2v[7] <= _T_202 @[el2_dec_gpr_ctl.scala 28:16] + node _T_203 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_204 = mux(_T_203, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_205 = and(_T_204, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_206 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_208 = and(_T_207, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_209 = or(_T_205, _T_208) @[el2_dec_gpr_ctl.scala 29:47] + node _T_210 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_212 = and(_T_211, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_213 = or(_T_209, _T_212) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[7] <= _T_213 @[el2_dec_gpr_ctl.scala 29:16] + node _T_214 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_215 = and(io.wen0, _T_214) @[el2_dec_gpr_ctl.scala 26:28] + w0v[8] <= _T_215 @[el2_dec_gpr_ctl.scala 26:16] + node _T_216 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_217 = and(io.wen1, _T_216) @[el2_dec_gpr_ctl.scala 27:28] + w1v[8] <= _T_217 @[el2_dec_gpr_ctl.scala 27:16] + node _T_218 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_219 = and(io.wen2, _T_218) @[el2_dec_gpr_ctl.scala 28:28] + w2v[8] <= _T_219 @[el2_dec_gpr_ctl.scala 28:16] + node _T_220 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_222 = and(_T_221, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_223 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = and(_T_224, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_226 = or(_T_222, _T_225) @[el2_dec_gpr_ctl.scala 29:47] + node _T_227 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_230 = or(_T_226, _T_229) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[8] <= _T_230 @[el2_dec_gpr_ctl.scala 29:16] + node _T_231 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_232 = and(io.wen0, _T_231) @[el2_dec_gpr_ctl.scala 26:28] + w0v[9] <= _T_232 @[el2_dec_gpr_ctl.scala 26:16] + node _T_233 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_234 = and(io.wen1, _T_233) @[el2_dec_gpr_ctl.scala 27:28] + w1v[9] <= _T_234 @[el2_dec_gpr_ctl.scala 27:16] + node _T_235 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_236 = and(io.wen2, _T_235) @[el2_dec_gpr_ctl.scala 28:28] + w2v[9] <= _T_236 @[el2_dec_gpr_ctl.scala 28:16] + node _T_237 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_239 = and(_T_238, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_240 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_242 = and(_T_241, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_243 = or(_T_239, _T_242) @[el2_dec_gpr_ctl.scala 29:47] + node _T_244 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_246 = and(_T_245, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_247 = or(_T_243, _T_246) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[9] <= _T_247 @[el2_dec_gpr_ctl.scala 29:16] + node _T_248 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_249 = and(io.wen0, _T_248) @[el2_dec_gpr_ctl.scala 26:28] + w0v[10] <= _T_249 @[el2_dec_gpr_ctl.scala 26:16] + node _T_250 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_251 = and(io.wen1, _T_250) @[el2_dec_gpr_ctl.scala 27:28] + w1v[10] <= _T_251 @[el2_dec_gpr_ctl.scala 27:16] + node _T_252 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_253 = and(io.wen2, _T_252) @[el2_dec_gpr_ctl.scala 28:28] + w2v[10] <= _T_253 @[el2_dec_gpr_ctl.scala 28:16] + node _T_254 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_256 = and(_T_255, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_257 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_258 = mux(_T_257, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_259 = and(_T_258, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_260 = or(_T_256, _T_259) @[el2_dec_gpr_ctl.scala 29:47] + node _T_261 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_263 = and(_T_262, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_264 = or(_T_260, _T_263) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[10] <= _T_264 @[el2_dec_gpr_ctl.scala 29:16] + node _T_265 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_266 = and(io.wen0, _T_265) @[el2_dec_gpr_ctl.scala 26:28] + w0v[11] <= _T_266 @[el2_dec_gpr_ctl.scala 26:16] + node _T_267 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_268 = and(io.wen1, _T_267) @[el2_dec_gpr_ctl.scala 27:28] + w1v[11] <= _T_268 @[el2_dec_gpr_ctl.scala 27:16] + node _T_269 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_270 = and(io.wen2, _T_269) @[el2_dec_gpr_ctl.scala 28:28] + w2v[11] <= _T_270 @[el2_dec_gpr_ctl.scala 28:16] + node _T_271 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_273 = and(_T_272, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_274 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = and(_T_275, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_277 = or(_T_273, _T_276) @[el2_dec_gpr_ctl.scala 29:47] + node _T_278 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_281 = or(_T_277, _T_280) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[11] <= _T_281 @[el2_dec_gpr_ctl.scala 29:16] + node _T_282 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_283 = and(io.wen0, _T_282) @[el2_dec_gpr_ctl.scala 26:28] + w0v[12] <= _T_283 @[el2_dec_gpr_ctl.scala 26:16] + node _T_284 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_285 = and(io.wen1, _T_284) @[el2_dec_gpr_ctl.scala 27:28] + w1v[12] <= _T_285 @[el2_dec_gpr_ctl.scala 27:16] + node _T_286 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_287 = and(io.wen2, _T_286) @[el2_dec_gpr_ctl.scala 28:28] + w2v[12] <= _T_287 @[el2_dec_gpr_ctl.scala 28:16] + node _T_288 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_291 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_293 = and(_T_292, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_294 = or(_T_290, _T_293) @[el2_dec_gpr_ctl.scala 29:47] + node _T_295 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_297 = and(_T_296, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_298 = or(_T_294, _T_297) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[12] <= _T_298 @[el2_dec_gpr_ctl.scala 29:16] + node _T_299 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_300 = and(io.wen0, _T_299) @[el2_dec_gpr_ctl.scala 26:28] + w0v[13] <= _T_300 @[el2_dec_gpr_ctl.scala 26:16] + node _T_301 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_302 = and(io.wen1, _T_301) @[el2_dec_gpr_ctl.scala 27:28] + w1v[13] <= _T_302 @[el2_dec_gpr_ctl.scala 27:16] + node _T_303 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_304 = and(io.wen2, _T_303) @[el2_dec_gpr_ctl.scala 28:28] + w2v[13] <= _T_304 @[el2_dec_gpr_ctl.scala 28:16] + node _T_305 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_307 = and(_T_306, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_308 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_309 = mux(_T_308, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_310 = and(_T_309, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_311 = or(_T_307, _T_310) @[el2_dec_gpr_ctl.scala 29:47] + node _T_312 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_314 = and(_T_313, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_315 = or(_T_311, _T_314) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[13] <= _T_315 @[el2_dec_gpr_ctl.scala 29:16] + node _T_316 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_317 = and(io.wen0, _T_316) @[el2_dec_gpr_ctl.scala 26:28] + w0v[14] <= _T_317 @[el2_dec_gpr_ctl.scala 26:16] + node _T_318 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_319 = and(io.wen1, _T_318) @[el2_dec_gpr_ctl.scala 27:28] + w1v[14] <= _T_319 @[el2_dec_gpr_ctl.scala 27:16] + node _T_320 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_321 = and(io.wen2, _T_320) @[el2_dec_gpr_ctl.scala 28:28] + w2v[14] <= _T_321 @[el2_dec_gpr_ctl.scala 28:16] + node _T_322 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_323 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_324 = and(_T_323, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_325 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_326 = mux(_T_325, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_327 = and(_T_326, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_328 = or(_T_324, _T_327) @[el2_dec_gpr_ctl.scala 29:47] + node _T_329 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_331 = and(_T_330, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_332 = or(_T_328, _T_331) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[14] <= _T_332 @[el2_dec_gpr_ctl.scala 29:16] + node _T_333 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_334 = and(io.wen0, _T_333) @[el2_dec_gpr_ctl.scala 26:28] + w0v[15] <= _T_334 @[el2_dec_gpr_ctl.scala 26:16] + node _T_335 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_336 = and(io.wen1, _T_335) @[el2_dec_gpr_ctl.scala 27:28] + w1v[15] <= _T_336 @[el2_dec_gpr_ctl.scala 27:16] + node _T_337 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_338 = and(io.wen2, _T_337) @[el2_dec_gpr_ctl.scala 28:28] + w2v[15] <= _T_338 @[el2_dec_gpr_ctl.scala 28:16] + node _T_339 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_340 = mux(_T_339, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_341 = and(_T_340, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_342 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_343 = mux(_T_342, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_344 = and(_T_343, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_345 = or(_T_341, _T_344) @[el2_dec_gpr_ctl.scala 29:47] + node _T_346 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_348 = and(_T_347, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_349 = or(_T_345, _T_348) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[15] <= _T_349 @[el2_dec_gpr_ctl.scala 29:16] + node _T_350 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_351 = and(io.wen0, _T_350) @[el2_dec_gpr_ctl.scala 26:28] + w0v[16] <= _T_351 @[el2_dec_gpr_ctl.scala 26:16] + node _T_352 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_353 = and(io.wen1, _T_352) @[el2_dec_gpr_ctl.scala 27:28] + w1v[16] <= _T_353 @[el2_dec_gpr_ctl.scala 27:16] + node _T_354 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_355 = and(io.wen2, _T_354) @[el2_dec_gpr_ctl.scala 28:28] + w2v[16] <= _T_355 @[el2_dec_gpr_ctl.scala 28:16] + node _T_356 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_357 = mux(_T_356, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_358 = and(_T_357, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_359 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_360 = mux(_T_359, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_361 = and(_T_360, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_362 = or(_T_358, _T_361) @[el2_dec_gpr_ctl.scala 29:47] + node _T_363 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_366 = or(_T_362, _T_365) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[16] <= _T_366 @[el2_dec_gpr_ctl.scala 29:16] + node _T_367 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_368 = and(io.wen0, _T_367) @[el2_dec_gpr_ctl.scala 26:28] + w0v[17] <= _T_368 @[el2_dec_gpr_ctl.scala 26:16] + node _T_369 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_370 = and(io.wen1, _T_369) @[el2_dec_gpr_ctl.scala 27:28] + w1v[17] <= _T_370 @[el2_dec_gpr_ctl.scala 27:16] + node _T_371 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_372 = and(io.wen2, _T_371) @[el2_dec_gpr_ctl.scala 28:28] + w2v[17] <= _T_372 @[el2_dec_gpr_ctl.scala 28:16] + node _T_373 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_374 = mux(_T_373, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_375 = and(_T_374, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_376 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_377 = mux(_T_376, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_378 = and(_T_377, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_379 = or(_T_375, _T_378) @[el2_dec_gpr_ctl.scala 29:47] + node _T_380 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_382 = and(_T_381, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_383 = or(_T_379, _T_382) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[17] <= _T_383 @[el2_dec_gpr_ctl.scala 29:16] + node _T_384 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_385 = and(io.wen0, _T_384) @[el2_dec_gpr_ctl.scala 26:28] + w0v[18] <= _T_385 @[el2_dec_gpr_ctl.scala 26:16] + node _T_386 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_387 = and(io.wen1, _T_386) @[el2_dec_gpr_ctl.scala 27:28] + w1v[18] <= _T_387 @[el2_dec_gpr_ctl.scala 27:16] + node _T_388 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_389 = and(io.wen2, _T_388) @[el2_dec_gpr_ctl.scala 28:28] + w2v[18] <= _T_389 @[el2_dec_gpr_ctl.scala 28:16] + node _T_390 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_391 = mux(_T_390, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_392 = and(_T_391, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_393 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_394 = mux(_T_393, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_395 = and(_T_394, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_396 = or(_T_392, _T_395) @[el2_dec_gpr_ctl.scala 29:47] + node _T_397 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_399 = and(_T_398, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_400 = or(_T_396, _T_399) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[18] <= _T_400 @[el2_dec_gpr_ctl.scala 29:16] + node _T_401 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_402 = and(io.wen0, _T_401) @[el2_dec_gpr_ctl.scala 26:28] + w0v[19] <= _T_402 @[el2_dec_gpr_ctl.scala 26:16] + node _T_403 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_404 = and(io.wen1, _T_403) @[el2_dec_gpr_ctl.scala 27:28] + w1v[19] <= _T_404 @[el2_dec_gpr_ctl.scala 27:16] + node _T_405 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_406 = and(io.wen2, _T_405) @[el2_dec_gpr_ctl.scala 28:28] + w2v[19] <= _T_406 @[el2_dec_gpr_ctl.scala 28:16] + node _T_407 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_409 = and(_T_408, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_410 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_411 = mux(_T_410, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_412 = and(_T_411, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_413 = or(_T_409, _T_412) @[el2_dec_gpr_ctl.scala 29:47] + node _T_414 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_417 = or(_T_413, _T_416) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[19] <= _T_417 @[el2_dec_gpr_ctl.scala 29:16] + node _T_418 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_419 = and(io.wen0, _T_418) @[el2_dec_gpr_ctl.scala 26:28] + w0v[20] <= _T_419 @[el2_dec_gpr_ctl.scala 26:16] + node _T_420 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_421 = and(io.wen1, _T_420) @[el2_dec_gpr_ctl.scala 27:28] + w1v[20] <= _T_421 @[el2_dec_gpr_ctl.scala 27:16] + node _T_422 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_423 = and(io.wen2, _T_422) @[el2_dec_gpr_ctl.scala 28:28] + w2v[20] <= _T_423 @[el2_dec_gpr_ctl.scala 28:16] + node _T_424 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_426 = and(_T_425, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_427 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_428 = mux(_T_427, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_429 = and(_T_428, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_430 = or(_T_426, _T_429) @[el2_dec_gpr_ctl.scala 29:47] + node _T_431 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_433 = and(_T_432, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_434 = or(_T_430, _T_433) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[20] <= _T_434 @[el2_dec_gpr_ctl.scala 29:16] + node _T_435 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_436 = and(io.wen0, _T_435) @[el2_dec_gpr_ctl.scala 26:28] + w0v[21] <= _T_436 @[el2_dec_gpr_ctl.scala 26:16] + node _T_437 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_438 = and(io.wen1, _T_437) @[el2_dec_gpr_ctl.scala 27:28] + w1v[21] <= _T_438 @[el2_dec_gpr_ctl.scala 27:16] + node _T_439 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_440 = and(io.wen2, _T_439) @[el2_dec_gpr_ctl.scala 28:28] + w2v[21] <= _T_440 @[el2_dec_gpr_ctl.scala 28:16] + node _T_441 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_442 = mux(_T_441, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_443 = and(_T_442, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_444 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_446 = and(_T_445, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_447 = or(_T_443, _T_446) @[el2_dec_gpr_ctl.scala 29:47] + node _T_448 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_451 = or(_T_447, _T_450) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[21] <= _T_451 @[el2_dec_gpr_ctl.scala 29:16] + node _T_452 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_453 = and(io.wen0, _T_452) @[el2_dec_gpr_ctl.scala 26:28] + w0v[22] <= _T_453 @[el2_dec_gpr_ctl.scala 26:16] + node _T_454 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_455 = and(io.wen1, _T_454) @[el2_dec_gpr_ctl.scala 27:28] + w1v[22] <= _T_455 @[el2_dec_gpr_ctl.scala 27:16] + node _T_456 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_457 = and(io.wen2, _T_456) @[el2_dec_gpr_ctl.scala 28:28] + w2v[22] <= _T_457 @[el2_dec_gpr_ctl.scala 28:16] + node _T_458 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(_T_459, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_461 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_462 = mux(_T_461, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_463 = and(_T_462, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_464 = or(_T_460, _T_463) @[el2_dec_gpr_ctl.scala 29:47] + node _T_465 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_467 = and(_T_466, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_468 = or(_T_464, _T_467) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[22] <= _T_468 @[el2_dec_gpr_ctl.scala 29:16] + node _T_469 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_470 = and(io.wen0, _T_469) @[el2_dec_gpr_ctl.scala 26:28] + w0v[23] <= _T_470 @[el2_dec_gpr_ctl.scala 26:16] + node _T_471 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_472 = and(io.wen1, _T_471) @[el2_dec_gpr_ctl.scala 27:28] + w1v[23] <= _T_472 @[el2_dec_gpr_ctl.scala 27:16] + node _T_473 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_474 = and(io.wen2, _T_473) @[el2_dec_gpr_ctl.scala 28:28] + w2v[23] <= _T_474 @[el2_dec_gpr_ctl.scala 28:16] + node _T_475 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(_T_476, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_478 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_480 = and(_T_479, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_481 = or(_T_477, _T_480) @[el2_dec_gpr_ctl.scala 29:47] + node _T_482 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_484 = and(_T_483, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_485 = or(_T_481, _T_484) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[23] <= _T_485 @[el2_dec_gpr_ctl.scala 29:16] + node _T_486 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_487 = and(io.wen0, _T_486) @[el2_dec_gpr_ctl.scala 26:28] + w0v[24] <= _T_487 @[el2_dec_gpr_ctl.scala 26:16] + node _T_488 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_489 = and(io.wen1, _T_488) @[el2_dec_gpr_ctl.scala 27:28] + w1v[24] <= _T_489 @[el2_dec_gpr_ctl.scala 27:16] + node _T_490 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_491 = and(io.wen2, _T_490) @[el2_dec_gpr_ctl.scala 28:28] + w2v[24] <= _T_491 @[el2_dec_gpr_ctl.scala 28:16] + node _T_492 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_493 = mux(_T_492, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_494 = and(_T_493, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_495 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_496 = mux(_T_495, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_497 = and(_T_496, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_498 = or(_T_494, _T_497) @[el2_dec_gpr_ctl.scala 29:47] + node _T_499 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_501 = and(_T_500, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_502 = or(_T_498, _T_501) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[24] <= _T_502 @[el2_dec_gpr_ctl.scala 29:16] + node _T_503 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_504 = and(io.wen0, _T_503) @[el2_dec_gpr_ctl.scala 26:28] + w0v[25] <= _T_504 @[el2_dec_gpr_ctl.scala 26:16] + node _T_505 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_506 = and(io.wen1, _T_505) @[el2_dec_gpr_ctl.scala 27:28] + w1v[25] <= _T_506 @[el2_dec_gpr_ctl.scala 27:16] + node _T_507 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_508 = and(io.wen2, _T_507) @[el2_dec_gpr_ctl.scala 28:28] + w2v[25] <= _T_508 @[el2_dec_gpr_ctl.scala 28:16] + node _T_509 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_510 = mux(_T_509, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_511 = and(_T_510, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_512 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_513 = mux(_T_512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_514 = and(_T_513, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_515 = or(_T_511, _T_514) @[el2_dec_gpr_ctl.scala 29:47] + node _T_516 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(_T_517, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_519 = or(_T_515, _T_518) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[25] <= _T_519 @[el2_dec_gpr_ctl.scala 29:16] + node _T_520 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_521 = and(io.wen0, _T_520) @[el2_dec_gpr_ctl.scala 26:28] + w0v[26] <= _T_521 @[el2_dec_gpr_ctl.scala 26:16] + node _T_522 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_523 = and(io.wen1, _T_522) @[el2_dec_gpr_ctl.scala 27:28] + w1v[26] <= _T_523 @[el2_dec_gpr_ctl.scala 27:16] + node _T_524 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_525 = and(io.wen2, _T_524) @[el2_dec_gpr_ctl.scala 28:28] + w2v[26] <= _T_525 @[el2_dec_gpr_ctl.scala 28:16] + node _T_526 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(_T_527, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_529 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_531 = and(_T_530, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_532 = or(_T_528, _T_531) @[el2_dec_gpr_ctl.scala 29:47] + node _T_533 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_534 = mux(_T_533, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_535 = and(_T_534, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_536 = or(_T_532, _T_535) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[26] <= _T_536 @[el2_dec_gpr_ctl.scala 29:16] + node _T_537 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_538 = and(io.wen0, _T_537) @[el2_dec_gpr_ctl.scala 26:28] + w0v[27] <= _T_538 @[el2_dec_gpr_ctl.scala 26:16] + node _T_539 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_540 = and(io.wen1, _T_539) @[el2_dec_gpr_ctl.scala 27:28] + w1v[27] <= _T_540 @[el2_dec_gpr_ctl.scala 27:16] + node _T_541 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_542 = and(io.wen2, _T_541) @[el2_dec_gpr_ctl.scala 28:28] + w2v[27] <= _T_542 @[el2_dec_gpr_ctl.scala 28:16] + node _T_543 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_545 = and(_T_544, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_546 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_548 = and(_T_547, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_549 = or(_T_545, _T_548) @[el2_dec_gpr_ctl.scala 29:47] + node _T_550 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_552 = and(_T_551, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_553 = or(_T_549, _T_552) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[27] <= _T_553 @[el2_dec_gpr_ctl.scala 29:16] + node _T_554 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_555 = and(io.wen0, _T_554) @[el2_dec_gpr_ctl.scala 26:28] + w0v[28] <= _T_555 @[el2_dec_gpr_ctl.scala 26:16] + node _T_556 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_557 = and(io.wen1, _T_556) @[el2_dec_gpr_ctl.scala 27:28] + w1v[28] <= _T_557 @[el2_dec_gpr_ctl.scala 27:16] + node _T_558 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_559 = and(io.wen2, _T_558) @[el2_dec_gpr_ctl.scala 28:28] + w2v[28] <= _T_559 @[el2_dec_gpr_ctl.scala 28:16] + node _T_560 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_562 = and(_T_561, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_563 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_564 = mux(_T_563, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_565 = and(_T_564, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_566 = or(_T_562, _T_565) @[el2_dec_gpr_ctl.scala 29:47] + node _T_567 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_569 = and(_T_568, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_570 = or(_T_566, _T_569) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[28] <= _T_570 @[el2_dec_gpr_ctl.scala 29:16] + node _T_571 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_572 = and(io.wen0, _T_571) @[el2_dec_gpr_ctl.scala 26:28] + w0v[29] <= _T_572 @[el2_dec_gpr_ctl.scala 26:16] + node _T_573 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_574 = and(io.wen1, _T_573) @[el2_dec_gpr_ctl.scala 27:28] + w1v[29] <= _T_574 @[el2_dec_gpr_ctl.scala 27:16] + node _T_575 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_576 = and(io.wen2, _T_575) @[el2_dec_gpr_ctl.scala 28:28] + w2v[29] <= _T_576 @[el2_dec_gpr_ctl.scala 28:16] + node _T_577 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_579 = and(_T_578, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_580 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_582 = and(_T_581, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_583 = or(_T_579, _T_582) @[el2_dec_gpr_ctl.scala 29:47] + node _T_584 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_585 = mux(_T_584, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_586 = and(_T_585, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_587 = or(_T_583, _T_586) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[29] <= _T_587 @[el2_dec_gpr_ctl.scala 29:16] + node _T_588 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_589 = and(io.wen0, _T_588) @[el2_dec_gpr_ctl.scala 26:28] + w0v[30] <= _T_589 @[el2_dec_gpr_ctl.scala 26:16] + node _T_590 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_591 = and(io.wen1, _T_590) @[el2_dec_gpr_ctl.scala 27:28] + w1v[30] <= _T_591 @[el2_dec_gpr_ctl.scala 27:16] + node _T_592 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_593 = and(io.wen2, _T_592) @[el2_dec_gpr_ctl.scala 28:28] + w2v[30] <= _T_593 @[el2_dec_gpr_ctl.scala 28:16] + node _T_594 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_595 = mux(_T_594, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_596 = and(_T_595, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_597 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_600 = or(_T_596, _T_599) @[el2_dec_gpr_ctl.scala 29:47] + node _T_601 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_602 = mux(_T_601, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_603 = and(_T_602, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_604 = or(_T_600, _T_603) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[30] <= _T_604 @[el2_dec_gpr_ctl.scala 29:16] + node _T_605 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_606 = and(io.wen0, _T_605) @[el2_dec_gpr_ctl.scala 26:28] + w0v[31] <= _T_606 @[el2_dec_gpr_ctl.scala 26:16] + node _T_607 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_608 = and(io.wen1, _T_607) @[el2_dec_gpr_ctl.scala 27:28] + w1v[31] <= _T_608 @[el2_dec_gpr_ctl.scala 27:16] + node _T_609 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_610 = and(io.wen2, _T_609) @[el2_dec_gpr_ctl.scala 28:28] + w2v[31] <= _T_610 @[el2_dec_gpr_ctl.scala 28:16] + node _T_611 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_612 = mux(_T_611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_613 = and(_T_612, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_614 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_615 = mux(_T_614, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_616 = and(_T_615, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_617 = or(_T_613, _T_616) @[el2_dec_gpr_ctl.scala 29:47] + node _T_618 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_620 = and(_T_619, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_621 = or(_T_617, _T_620) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[31] <= _T_621 @[el2_dec_gpr_ctl.scala 29:16] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr of rvclkhdr_20 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_622 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_623 <= gpr_in[1] @[el2_lib.scala 491:16] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 33:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_1 of rvclkhdr_21 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_624 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_625 <= gpr_in[2] @[el2_lib.scala 491:16] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 33:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_2 of rvclkhdr_22 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_626 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_627 <= gpr_in[3] @[el2_lib.scala 491:16] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 33:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_3 of rvclkhdr_23 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_628 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_629 <= gpr_in[4] @[el2_lib.scala 491:16] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 33:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_4 of rvclkhdr_24 @[el2_lib.scala 485:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_4.io.en <= _T_630 @[el2_lib.scala 488:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_631 <= gpr_in[5] @[el2_lib.scala 491:16] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 33:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_5 of rvclkhdr_25 @[el2_lib.scala 485:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_5.io.en <= _T_632 @[el2_lib.scala 488:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_633 <= gpr_in[6] @[el2_lib.scala 491:16] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 33:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_6 of rvclkhdr_26 @[el2_lib.scala 485:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_6.io.en <= _T_634 @[el2_lib.scala 488:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_635 <= gpr_in[7] @[el2_lib.scala 491:16] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 33:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_7 of rvclkhdr_27 @[el2_lib.scala 485:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_7.io.en <= _T_636 @[el2_lib.scala 488:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_637 <= gpr_in[8] @[el2_lib.scala 491:16] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 33:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_8 of rvclkhdr_28 @[el2_lib.scala 485:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_8.io.en <= _T_638 @[el2_lib.scala 488:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_639 <= gpr_in[9] @[el2_lib.scala 491:16] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 33:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_9 of rvclkhdr_29 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_640 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_641 <= gpr_in[10] @[el2_lib.scala 491:16] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 33:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_10 of rvclkhdr_30 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_642 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_643 <= gpr_in[11] @[el2_lib.scala 491:16] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 33:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_11 of rvclkhdr_31 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_644 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_645 <= gpr_in[12] @[el2_lib.scala 491:16] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 33:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_12 of rvclkhdr_32 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_646 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_647 <= gpr_in[13] @[el2_lib.scala 491:16] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 33:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_13 of rvclkhdr_33 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_648 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_649 <= gpr_in[14] @[el2_lib.scala 491:16] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 33:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_14 of rvclkhdr_34 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_650 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_651 <= gpr_in[15] @[el2_lib.scala 491:16] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 33:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_15 of rvclkhdr_35 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_652 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_653 <= gpr_in[16] @[el2_lib.scala 491:16] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 33:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_16 of rvclkhdr_36 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_654 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_655 <= gpr_in[17] @[el2_lib.scala 491:16] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 33:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_17 of rvclkhdr_37 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_656 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_657 <= gpr_in[18] @[el2_lib.scala 491:16] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 33:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_18 of rvclkhdr_38 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_658 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_659 <= gpr_in[19] @[el2_lib.scala 491:16] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 33:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_19 of rvclkhdr_39 @[el2_lib.scala 485:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_19.io.en <= _T_660 @[el2_lib.scala 488:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_661 <= gpr_in[20] @[el2_lib.scala 491:16] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 33:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_20 of rvclkhdr_40 @[el2_lib.scala 485:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_20.io.en <= _T_662 @[el2_lib.scala 488:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_663 <= gpr_in[21] @[el2_lib.scala 491:16] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 33:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_21 of rvclkhdr_41 @[el2_lib.scala 485:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_21.io.en <= _T_664 @[el2_lib.scala 488:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_665 <= gpr_in[22] @[el2_lib.scala 491:16] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 33:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_22 of rvclkhdr_42 @[el2_lib.scala 485:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_22.io.en <= _T_666 @[el2_lib.scala 488:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_667 <= gpr_in[23] @[el2_lib.scala 491:16] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 33:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_23 of rvclkhdr_43 @[el2_lib.scala 485:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_23.io.en <= _T_668 @[el2_lib.scala 488:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_669 <= gpr_in[24] @[el2_lib.scala 491:16] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 33:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_24 of rvclkhdr_44 @[el2_lib.scala 485:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_24.io.en <= _T_670 @[el2_lib.scala 488:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_671 <= gpr_in[25] @[el2_lib.scala 491:16] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 33:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_25 of rvclkhdr_45 @[el2_lib.scala 485:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_25.io.en <= _T_672 @[el2_lib.scala 488:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_673 <= gpr_in[26] @[el2_lib.scala 491:16] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 33:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_26 of rvclkhdr_46 @[el2_lib.scala 485:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_26.io.en <= _T_674 @[el2_lib.scala 488:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_675 <= gpr_in[27] @[el2_lib.scala 491:16] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 33:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_27 of rvclkhdr_47 @[el2_lib.scala 485:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_27.io.en <= _T_676 @[el2_lib.scala 488:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_677 <= gpr_in[28] @[el2_lib.scala 491:16] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 33:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_28 of rvclkhdr_48 @[el2_lib.scala 485:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_28.io.en <= _T_678 @[el2_lib.scala 488:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_679 <= gpr_in[29] @[el2_lib.scala 491:16] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 33:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_29 of rvclkhdr_49 @[el2_lib.scala 485:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_29.io.en <= _T_680 @[el2_lib.scala 488:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_681 <= gpr_in[30] @[el2_lib.scala 491:16] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 33:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_30 of rvclkhdr_50 @[el2_lib.scala 485:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_30.io.en <= _T_682 @[el2_lib.scala 488:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_683 <= gpr_in[31] @[el2_lib.scala 491:16] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 33:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72] + node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72] + node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72] + node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72] + node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72] + node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72] + node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72] + node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72] + node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72] + node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72] + node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72] + node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72] + node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72] + node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72] + node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72] + node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72] + node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72] + node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72] + node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72] + node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72] + node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72] + node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72] + node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72] + node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72] + node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] + wire _T_807 : UInt<32> @[Mux.scala 27:72] + _T_807 <= _T_806 @[Mux.scala 27:72] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 36:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72] + node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72] + node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72] + node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72] + node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72] + node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72] + node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72] + node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72] + node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72] + node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72] + node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72] + node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72] + node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72] + node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72] + node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72] + node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72] + node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72] + node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72] + node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72] + node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] + wire _T_931 : UInt<32> @[Mux.scala 27:72] + _T_931 <= _T_930 @[Mux.scala 27:72] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 37:9] + + extmodule TEC_RV_ICG_51 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_51 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_51 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_52 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_52 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_52 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_53 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_53 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_53 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_54 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_54 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_54 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_timer_ctl : + input clock : Clock + input reset : Reset + output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} + + wire mitctl1 : UInt<4> @[el2_dec_tlu_ctl.scala 2745:19] + wire mitctl0 : UInt<3> @[el2_dec_tlu_ctl.scala 2746:19] + wire mitb1 : UInt<32> @[el2_dec_tlu_ctl.scala 2747:19] + wire mitb0 : UInt<32> @[el2_dec_tlu_ctl.scala 2748:19] + wire mitcnt1 : UInt<32> @[el2_dec_tlu_ctl.scala 2749:19] + wire mitcnt0 : UInt<32> @[el2_dec_tlu_ctl.scala 2750:19] + node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] + node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] + io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] + io.dec_timer_t1_pulse <= mit1_match_ns @[el2_dec_tlu_ctl.scala 2756:25] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[el2_dec_tlu_ctl.scala 2763:66] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[el2_dec_tlu_ctl.scala 2763:43] + node _T_1 = bits(mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2765:31] + node _T_2 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2765:50] + node _T_3 = bits(mitctl0, 2, 2) @[el2_dec_tlu_ctl.scala 2765:79] + node _T_4 = or(_T_2, _T_3) @[el2_dec_tlu_ctl.scala 2765:70] + node _T_5 = and(_T_1, _T_4) @[el2_dec_tlu_ctl.scala 2765:47] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2765:106] + node _T_7 = bits(mitctl0, 1, 1) @[el2_dec_tlu_ctl.scala 2765:141] + node _T_8 = or(_T_6, _T_7) @[el2_dec_tlu_ctl.scala 2765:132] + node _T_9 = and(_T_5, _T_8) @[el2_dec_tlu_ctl.scala 2765:103] + node _T_10 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2765:167] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[el2_dec_tlu_ctl.scala 2765:165] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2766:29] + node mitcnt0_inc = tail(_T_11, 1) @[el2_dec_tlu_ctl.scala 2766:29] + node _T_12 = bits(mit0_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2767:38] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:60] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:77] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:94] + inst rvclkhdr of rvclkhdr_51 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_17 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_18 <= mitcnt0_ns @[el2_lib.scala 491:16] + mitcnt0 <= _T_18 @[el2_dec_tlu_ctl.scala 2768:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[el2_dec_tlu_ctl.scala 2775:66] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[el2_dec_tlu_ctl.scala 2775:43] + node _T_20 = bits(mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2777:31] + node _T_21 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2777:50] + node _T_22 = bits(mitctl1, 2, 2) @[el2_dec_tlu_ctl.scala 2777:79] + node _T_23 = or(_T_21, _T_22) @[el2_dec_tlu_ctl.scala 2777:70] + node _T_24 = and(_T_20, _T_23) @[el2_dec_tlu_ctl.scala 2777:47] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2777:106] + node _T_26 = bits(mitctl1, 1, 1) @[el2_dec_tlu_ctl.scala 2777:141] + node _T_27 = or(_T_25, _T_26) @[el2_dec_tlu_ctl.scala 2777:132] + node _T_28 = and(_T_24, _T_27) @[el2_dec_tlu_ctl.scala 2777:103] + node _T_29 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2777:167] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[el2_dec_tlu_ctl.scala 2777:165] + node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_31 = bits(mitctl1, 3, 3) @[el2_dec_tlu_ctl.scala 2780:62] + node _T_32 = not(_T_31) @[el2_dec_tlu_ctl.scala 2780:54] + node _T_33 = or(_T_32, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2780:66] + node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] + node _T_35 = add(mitcnt1, _T_34) @[el2_dec_tlu_ctl.scala 2780:29] + node mitcnt1_inc = tail(_T_35, 1) @[el2_dec_tlu_ctl.scala 2780:29] + node _T_36 = bits(mit1_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2781:39] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2781:69] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[el2_dec_tlu_ctl.scala 2781:55] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[el2_dec_tlu_ctl.scala 2781:24] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[el2_dec_tlu_ctl.scala 2782:52] + node _T_40 = or(_T_39, mit1_match_ns) @[el2_dec_tlu_ctl.scala 2782:69] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_tlu_ctl.scala 2782:86] + inst rvclkhdr_1 of rvclkhdr_52 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_42 <= mitcnt1_ns @[el2_lib.scala 491:16] + mitcnt1 <= _T_42 @[el2_dec_tlu_ctl.scala 2782:17] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[el2_dec_tlu_ctl.scala 2789:64] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[el2_dec_tlu_ctl.scala 2789:41] + node _T_44 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2790:30] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2790:63] + inst rvclkhdr_2 of rvclkhdr_53 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mitb0_b <= _T_44 @[el2_lib.scala 491:16] + node _T_46 = not(mitb0_b) @[el2_dec_tlu_ctl.scala 2791:14] + mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:24] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] + inst rvclkhdr_3 of rvclkhdr_54 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mitb1_b <= _T_48 @[el2_lib.scala 491:16] + node _T_50 = not(mitb1_b) @[el2_dec_tlu_ctl.scala 2800:12] + mitb1 <= _T_50 @[el2_dec_tlu_ctl.scala 2800:9] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[el2_dec_tlu_ctl.scala 2811:66] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[el2_dec_tlu_ctl.scala 2811:43] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2812:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[el2_dec_tlu_ctl.scala 2812:72] + node _T_54 = bits(mitctl0, 2, 0) @[el2_dec_tlu_ctl.scala 2812:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[el2_dec_tlu_ctl.scala 2812:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2814:35] + node mitctl0_0_b_ns = not(_T_55) @[el2_dec_tlu_ctl.scala 2814:24] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2815:54] + mitctl0_0_b <= mitctl0_0_b_ns @[el2_dec_tlu_ctl.scala 2815:54] + node _T_56 = bits(mitctl0_ns, 2, 1) @[el2_dec_tlu_ctl.scala 2816:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2816:67] + _T_57 <= _T_56 @[el2_dec_tlu_ctl.scala 2816:67] + node _T_58 = not(mitctl0_0_b) @[el2_dec_tlu_ctl.scala 2816:90] + node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] + mitctl0 <= _T_59 @[el2_dec_tlu_ctl.scala 2816:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[el2_dec_tlu_ctl.scala 2826:65] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[el2_dec_tlu_ctl.scala 2826:43] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2827:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2827:71] + node _T_63 = bits(mitctl1, 3, 0) @[el2_dec_tlu_ctl.scala 2827:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[el2_dec_tlu_ctl.scala 2827:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2828:34] + node mitctl1_0_b_ns = not(_T_64) @[el2_dec_tlu_ctl.scala 2828:23] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2829:49] + mitctl1_0_b <= mitctl1_0_b_ns @[el2_dec_tlu_ctl.scala 2829:49] + node _T_65 = bits(mitctl1_ns, 3, 1) @[el2_dec_tlu_ctl.scala 2830:57] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2830:46] + _T_66 <= _T_65 @[el2_dec_tlu_ctl.scala 2830:46] + node _T_67 = not(mitctl1_0_b) @[el2_dec_tlu_ctl.scala 2830:69] + node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] + mitctl1 <= _T_68 @[el2_dec_tlu_ctl.scala 2830:10] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[el2_dec_tlu_ctl.scala 2832:43] + node _T_70 = or(_T_69, io.csr_mitb1) @[el2_dec_tlu_ctl.scala 2832:60] + node _T_71 = or(_T_70, io.csr_mitb0) @[el2_dec_tlu_ctl.scala 2832:75] + node _T_72 = or(_T_71, io.csr_mitctl0) @[el2_dec_tlu_ctl.scala 2832:90] + node _T_73 = or(_T_72, io.csr_mitctl1) @[el2_dec_tlu_ctl.scala 2832:107] + io.dec_timer_read_d <= _T_73 @[el2_dec_tlu_ctl.scala 2832:25] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[el2_dec_tlu_ctl.scala 2834:20] + node _T_75 = bits(mitcnt0, 31, 0) @[el2_dec_tlu_ctl.scala 2834:39] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[el2_dec_tlu_ctl.scala 2835:20] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[el2_dec_tlu_ctl.scala 2836:18] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[el2_dec_tlu_ctl.scala 2837:18] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2838:20] + node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] + node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2839:20] + node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] + node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72] + node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72] + node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72] + node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72] + node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] + wire _T_96 : UInt<32> @[Mux.scala 27:72] + _T_96 <= _T_95 @[Mux.scala 27:72] + io.dec_timer_rddata_d <= _T_96 @[el2_dec_tlu_ctl.scala 2833:33] + + extmodule TEC_RV_ICG_55 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_55 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_55 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_56 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_56 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_56 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_57 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_57 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_57 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_58 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_58 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_58 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_59 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_59 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_59 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_60 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_60 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_60 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_61 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_61 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_61 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_62 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_62 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_62 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_63 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_63 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_63 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_64 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_64 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_64 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_65 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_65 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_65 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_66 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_66 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_66 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_67 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_67 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_67 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_68 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_68 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_68 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_69 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_69 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_69 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_70 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_70 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_70 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_71 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_71 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_71 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_72 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_72 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_72 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_73 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_73 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_73 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_74 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_74 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_74 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_75 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_75 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_75 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_76 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_76 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_76 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_77 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_77 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_77 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_78 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_78 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_78 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_79 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_79 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_79 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_80 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_80 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_80 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_81 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_81 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_81 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_82 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_82 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_82 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_83 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_83 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_83 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_84 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_84 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_84 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_85 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_85 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_85 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_86 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_86 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_86 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_87 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_87 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_87 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_88 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_88 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_88 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_89 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_89 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_89 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_90 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_90 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_90 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_91 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_91 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_91 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_92 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_92 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_92 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_93 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_93 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_93 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module csr_tlu : + input clock : Clock + input reset : Reset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + + wire miccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1454:41] + wire mice_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1455:41] + wire mdccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1456:41] + wire pc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 1457:41] + wire mpmc_b_ns : UInt<1> @[el2_dec_tlu_ctl.scala 1458:41] + wire mpmc_b : UInt<1> @[el2_dec_tlu_ctl.scala 1459:41] + wire wr_mcycleh_r : UInt<1> + wr_mcycleh_r <= UInt<1>("h00") + wire mcycleh : UInt<32> + mcycleh <= UInt<1>("h00") + wire minstretl_inc : UInt<33> + minstretl_inc <= UInt<1>("h00") + wire wr_minstreth_r : UInt<1> + wr_minstreth_r <= UInt<1>("h00") + wire minstretl : UInt<32> + minstretl <= UInt<1>("h00") + wire minstreth_inc : UInt<32> + minstreth_inc <= UInt<1>("h00") + wire minstreth : UInt<32> + minstreth <= UInt<1>("h00") + wire mfdc_ns : UInt<15> + mfdc_ns <= UInt<1>("h00") + wire mfdc_int : UInt<15> + mfdc_int <= UInt<1>("h00") + wire mhpmc6_incr : UInt<64> + mhpmc6_incr <= UInt<1>("h00") + wire mhpmc5_incr : UInt<64> + mhpmc5_incr <= UInt<1>("h00") + wire mhpmc4_incr : UInt<64> + mhpmc4_incr <= UInt<1>("h00") + wire perfcnt_halted : UInt<1> + perfcnt_halted <= UInt<1>("h00") + wire mhpmc3_incr : UInt<64> + mhpmc3_incr <= UInt<1>("h00") + wire mhpme_vec : UInt<10>[4] @[el2_dec_tlu_ctl.scala 1474:41] + wire mtdata2_t : UInt<32>[4] @[el2_dec_tlu_ctl.scala 1475:65] + wire wr_meicpct_r : UInt<1> + wr_meicpct_r <= UInt<1>("h00") + wire force_halt_ctr_f : UInt<32> + force_halt_ctr_f <= UInt<1>("h00") + wire mdccmect_inc : UInt<27> + mdccmect_inc <= UInt<1>("h00") + wire miccmect_inc : UInt<27> + miccmect_inc <= UInt<1>("h00") + wire fw_halted : UInt<1> + fw_halted <= UInt<1>("h00") + wire micect_inc : UInt<27> + micect_inc <= UInt<1>("h00") + wire mdseac_en : UInt<1> + mdseac_en <= UInt<1>("h00") + wire mie : UInt<6> + mie <= UInt<1>("h00") + wire mcyclel : UInt<32> + mcyclel <= UInt<1>("h00") + wire mscratch : UInt<32> + mscratch <= UInt<1>("h00") + wire mcause : UInt<32> + mcause <= UInt<1>("h00") + wire mscause : UInt<4> + mscause <= UInt<1>("h00") + wire mtval : UInt<32> + mtval <= UInt<1>("h00") + wire meicurpl : UInt<4> + meicurpl <= UInt<1>("h00") + wire meicidpl : UInt<4> + meicidpl <= UInt<1>("h00") + wire meipt : UInt<4> + meipt <= UInt<1>("h00") + wire mfdc : UInt<19> + mfdc <= UInt<1>("h00") + wire mtsel : UInt<2> + mtsel <= UInt<1>("h00") + wire micect : UInt<32> + micect <= UInt<1>("h00") + wire miccmect : UInt<32> + miccmect <= UInt<1>("h00") + wire mdccmect : UInt<32> + mdccmect <= UInt<1>("h00") + wire mhpmc3h : UInt<32> + mhpmc3h <= UInt<1>("h00") + wire mhpmc3 : UInt<32> + mhpmc3 <= UInt<1>("h00") + wire mhpmc4h : UInt<32> + mhpmc4h <= UInt<1>("h00") + wire mhpmc4 : UInt<32> + mhpmc4 <= UInt<1>("h00") + wire mhpmc5h : UInt<32> + mhpmc5h <= UInt<1>("h00") + wire mhpmc5 : UInt<32> + mhpmc5 <= UInt<1>("h00") + wire mhpmc6h : UInt<32> + mhpmc6h <= UInt<1>("h00") + wire mhpmc6 : UInt<32> + mhpmc6 <= UInt<1>("h00") + wire mhpme3 : UInt<10> + mhpme3 <= UInt<1>("h00") + wire mhpme4 : UInt<10> + mhpme4 <= UInt<1>("h00") + wire mhpme5 : UInt<10> + mhpme5 <= UInt<1>("h00") + wire mhpme6 : UInt<10> + mhpme6 <= UInt<1>("h00") + wire mfdht : UInt<6> + mfdht <= UInt<1>("h00") + wire mfdhs : UInt<2> + mfdhs <= UInt<1>("h00") + wire mcountinhibit : UInt<7> + mcountinhibit <= UInt<1>("h00") + wire mpmc : UInt<1> + mpmc <= UInt<1>("h00") + wire dicad1 : UInt<32> + dicad1 <= UInt<1>("h00") + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:46] + node _T_1 = and(io.dec_csr_wen_r, _T) @[el2_dec_tlu_ctl.scala 1530:44] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:69] + node _T_3 = and(_T_1, _T_2) @[el2_dec_tlu_ctl.scala 1530:67] + io.dec_csr_wen_r_mod <= _T_3 @[el2_dec_tlu_ctl.scala 1530:24] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1531:65] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[el2_dec_tlu_ctl.scala 1531:72] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[el2_dec_tlu_ctl.scala 1531:43] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1534:29] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[el2_dec_tlu_ctl.scala 1534:40] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:6] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1537:20] + node _T_9 = bits(_T_8, 0, 0) @[el2_dec_tlu_ctl.scala 1537:45] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_11 = bits(_T_10, 0, 0) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_12 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1538:19] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 1538:44] + node _T_14 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1538:77] + node _T_15 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1539:18] + node _T_16 = and(io.mret_r, _T_15) @[el2_dec_tlu_ctl.scala 1539:16] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 1539:42] + node _T_18 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1539:71] + node _T_19 = cat(UInt<1>("h01"), _T_18) @[Cat.scala 29:58] + node _T_20 = bits(set_mie_pmu_fw_halt, 0, 0) @[el2_dec_tlu_ctl.scala 1540:27] + node _T_21 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1540:51] + node _T_22 = cat(_T_21, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_23 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1541:21] + node _T_24 = and(wr_mstatus_r, _T_23) @[el2_dec_tlu_ctl.scala 1541:19] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 1541:45] + node _T_26 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1541:78] + node _T_27 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1541:102] + node _T_28 = cat(_T_26, _T_27) @[Cat.scala 29:58] + node _T_29 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:6] + node _T_30 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:22] + node _T_31 = and(_T_29, _T_30) @[el2_dec_tlu_ctl.scala 1542:20] + node _T_32 = eq(io.mret_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:47] + node _T_33 = and(_T_31, _T_32) @[el2_dec_tlu_ctl.scala 1542:45] + node _T_34 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:60] + node _T_35 = and(_T_33, _T_34) @[el2_dec_tlu_ctl.scala 1542:58] + node _T_36 = bits(_T_35, 0, 0) @[el2_dec_tlu_ctl.scala 1542:82] + node _T_37 = mux(_T_9, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_39 = mux(_T_17, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_20, _T_22, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_25, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_36, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = or(_T_37, _T_38) @[Mux.scala 27:72] + node _T_44 = or(_T_43, _T_39) @[Mux.scala 27:72] + node _T_45 = or(_T_44, _T_40) @[Mux.scala 27:72] + node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72] + wire mstatus_ns : UInt<2> @[Mux.scala 27:72] + mstatus_ns <= _T_47 @[Mux.scala 27:72] + node _T_48 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_49 = bits(_T_48, 0, 0) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_50 = not(io.dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 1545:51] + node _T_51 = bits(io.dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 1545:91] + node _T_52 = or(_T_50, _T_51) @[el2_dec_tlu_ctl.scala 1545:82] + node _T_53 = and(_T_49, _T_52) @[el2_dec_tlu_ctl.scala 1545:48] + io.mstatus_mie_ns <= _T_53 @[el2_dec_tlu_ctl.scala 1545:21] + reg _T_54 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1547:12] + _T_54 <= mstatus_ns @[el2_dec_tlu_ctl.scala 1547:12] + io.mstatus <= _T_54 @[el2_dec_tlu_ctl.scala 1546:14] + node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1556:63] + node _T_56 = eq(_T_55, UInt<12>("h0305")) @[el2_dec_tlu_ctl.scala 1556:70] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_56) @[el2_dec_tlu_ctl.scala 1556:41] + node _T_57 = bits(io.dec_csr_wrdata_r, 31, 2) @[el2_dec_tlu_ctl.scala 1557:41] + node _T_58 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1557:69] + node mtvec_ns = cat(_T_57, _T_58) @[Cat.scala 29:58] + node _T_59 = bits(wr_mtvec_r, 0, 0) @[el2_dec_tlu_ctl.scala 1558:43] + inst rvclkhdr of rvclkhdr_59 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_59 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_60 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_60 <= mtvec_ns @[el2_lib.scala 491:16] + io.mtvec <= _T_60 @[el2_dec_tlu_ctl.scala 1558:12] + node _T_61 = or(mdccme_ce_req, miccme_ce_req) @[el2_dec_tlu_ctl.scala 1570:31] + node ce_int = or(_T_61, mice_ce_req) @[el2_dec_tlu_ctl.scala 1570:47] + node _T_62 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, io.soft_int_sync) @[Cat.scala 29:58] + node _T_64 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, io.dec_timer_t1_pulse) @[Cat.scala 29:58] + node mip_ns = cat(_T_65, _T_63) @[Cat.scala 29:58] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1574:12] + _T_66 <= mip_ns @[el2_dec_tlu_ctl.scala 1574:12] + io.mip <= _T_66 @[el2_dec_tlu_ctl.scala 1573:10] + node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1586:61] + node _T_68 = eq(_T_67, UInt<12>("h0304")) @[el2_dec_tlu_ctl.scala 1586:68] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[el2_dec_tlu_ctl.scala 1586:39] + node _T_69 = bits(wr_mie_r, 0, 0) @[el2_dec_tlu_ctl.scala 1587:29] + node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[el2_dec_tlu_ctl.scala 1587:60] + node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1587:89] + node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1587:114] + node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1587:138] + node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58] + node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58] + node _T_77 = mux(_T_69, _T_76, mie) @[el2_dec_tlu_ctl.scala 1587:19] + io.mie_ns <= _T_77 @[el2_dec_tlu_ctl.scala 1587:13] + reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1589:12] + _T_78 <= io.mie_ns @[el2_dec_tlu_ctl.scala 1589:12] + mie <= _T_78 @[el2_dec_tlu_ctl.scala 1588:7] + node _T_79 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1596:64] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[el2_dec_tlu_ctl.scala 1596:55] + node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1598:65] + node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[el2_dec_tlu_ctl.scala 1598:72] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[el2_dec_tlu_ctl.scala 1598:43] + node _T_82 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1600:81] + node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[el2_dec_tlu_ctl.scala 1600:72] + node _T_84 = or(kill_ebreak_count_r, _T_83) @[el2_dec_tlu_ctl.scala 1600:47] + node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 1600:95] + node _T_86 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 1600:137] + node _T_87 = or(_T_85, _T_86) @[el2_dec_tlu_ctl.scala 1600:122] + node mcyclel_cout_in = not(_T_87) @[el2_dec_tlu_ctl.scala 1600:25] + wire mcyclel_inc : UInt<33> + mcyclel_inc <= UInt<1>("h00") + node _T_88 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] + node _T_89 = add(mcyclel, _T_88) @[el2_dec_tlu_ctl.scala 1604:26] + node _T_90 = tail(_T_89, 1) @[el2_dec_tlu_ctl.scala 1604:26] + mcyclel_inc <= _T_90 @[el2_dec_tlu_ctl.scala 1604:15] + node _T_91 = bits(wr_mcyclel_r, 0, 0) @[el2_dec_tlu_ctl.scala 1605:37] + node mcyclel_ns = mux(_T_91, io.dec_csr_wrdata_r, mcyclel_inc) @[el2_dec_tlu_ctl.scala 1605:23] + node _T_92 = bits(mcyclel_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1606:33] + node mcyclel_cout = bits(_T_92, 0, 0) @[el2_dec_tlu_ctl.scala 1606:38] + node _T_93 = or(wr_mcyclel_r, mcyclel_cout_in) @[el2_dec_tlu_ctl.scala 1607:47] + node _T_94 = bits(_T_93, 0, 0) @[el2_dec_tlu_ctl.scala 1607:73] + inst rvclkhdr_1 of rvclkhdr_60 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_94 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_95 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_95 <= mcyclel_ns @[el2_lib.scala 491:16] + mcyclel <= _T_95 @[el2_dec_tlu_ctl.scala 1607:11] + node _T_96 = eq(wr_mcycleh_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1608:72] + node _T_97 = and(mcyclel_cout, _T_96) @[el2_dec_tlu_ctl.scala 1608:70] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1608:55] + mcyclel_cout_f <= _T_97 @[el2_dec_tlu_ctl.scala 1608:55] + node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1614:62] + node _T_99 = eq(_T_98, UInt<12>("h0b80")) @[el2_dec_tlu_ctl.scala 1614:69] + node _T_100 = and(io.dec_csr_wen_r_mod, _T_99) @[el2_dec_tlu_ctl.scala 1614:40] + wr_mcycleh_r <= _T_100 @[el2_dec_tlu_ctl.scala 1614:16] + node _T_101 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] + node _T_102 = add(mcycleh, _T_101) @[el2_dec_tlu_ctl.scala 1616:29] + node mcycleh_inc = tail(_T_102, 1) @[el2_dec_tlu_ctl.scala 1616:29] + node _T_103 = bits(wr_mcycleh_r, 0, 0) @[el2_dec_tlu_ctl.scala 1617:37] + node mcycleh_ns = mux(_T_103, io.dec_csr_wrdata_r, mcycleh_inc) @[el2_dec_tlu_ctl.scala 1617:23] + node _T_104 = or(wr_mcycleh_r, mcyclel_cout_f) @[el2_dec_tlu_ctl.scala 1619:47] + node _T_105 = bits(_T_104, 0, 0) @[el2_dec_tlu_ctl.scala 1619:65] + inst rvclkhdr_2 of rvclkhdr_61 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_105 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_106 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_106 <= mcycleh_ns @[el2_lib.scala 491:16] + mcycleh <= _T_106 @[el2_dec_tlu_ctl.scala 1619:11] + node _T_107 = or(io.ebreak_r, io.ecall_r) @[el2_dec_tlu_ctl.scala 1633:73] + node _T_108 = or(_T_107, io.ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 1633:86] + node _T_109 = or(_T_108, io.illegal_r) @[el2_dec_tlu_ctl.scala 1633:114] + node _T_110 = bits(mcountinhibit, 2, 2) @[el2_dec_tlu_ctl.scala 1633:144] + node _T_111 = or(_T_109, _T_110) @[el2_dec_tlu_ctl.scala 1633:129] + node _T_112 = bits(_T_111, 0, 0) @[el2_dec_tlu_ctl.scala 1633:149] + node _T_113 = not(_T_112) @[el2_dec_tlu_ctl.scala 1633:59] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_113) @[el2_dec_tlu_ctl.scala 1633:57] + node _T_114 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1635:67] + node _T_115 = eq(_T_114, UInt<12>("h0b02")) @[el2_dec_tlu_ctl.scala 1635:74] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_115) @[el2_dec_tlu_ctl.scala 1635:45] + node _T_116 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] + node _T_117 = add(minstretl, _T_116) @[el2_dec_tlu_ctl.scala 1637:30] + node _T_118 = tail(_T_117, 1) @[el2_dec_tlu_ctl.scala 1637:30] + minstretl_inc <= _T_118 @[el2_dec_tlu_ctl.scala 1637:17] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1638:37] + node _T_119 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[el2_dec_tlu_ctl.scala 1639:53] + node minstret_enable = bits(_T_119, 0, 0) @[el2_dec_tlu_ctl.scala 1639:71] + node _T_120 = bits(wr_minstretl_r, 0, 0) @[el2_dec_tlu_ctl.scala 1641:41] + node minstretl_ns = mux(_T_120, io.dec_csr_wrdata_r, minstretl_inc) @[el2_dec_tlu_ctl.scala 1641:25] + node _T_121 = bits(minstret_enable, 0, 0) @[el2_dec_tlu_ctl.scala 1642:52] + inst rvclkhdr_3 of rvclkhdr_62 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_121 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_122 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_122 <= minstretl_ns @[el2_lib.scala 491:16] + minstretl <= _T_122 @[el2_dec_tlu_ctl.scala 1642:13] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1643:57] + minstret_enable_f <= minstret_enable @[el2_dec_tlu_ctl.scala 1643:57] + node _T_123 = not(wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1644:76] + node _T_124 = and(minstretl_cout, _T_123) @[el2_dec_tlu_ctl.scala 1644:74] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1644:57] + minstretl_cout_f <= _T_124 @[el2_dec_tlu_ctl.scala 1644:57] + node _T_125 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1652:65] + node _T_126 = eq(_T_125, UInt<12>("h0b82")) @[el2_dec_tlu_ctl.scala 1652:72] + node _T_127 = and(io.dec_csr_wen_r_mod, _T_126) @[el2_dec_tlu_ctl.scala 1652:43] + node _T_128 = bits(_T_127, 0, 0) @[el2_dec_tlu_ctl.scala 1652:88] + wr_minstreth_r <= _T_128 @[el2_dec_tlu_ctl.scala 1652:18] + node _T_129 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] + node _T_130 = add(minstreth, _T_129) @[el2_dec_tlu_ctl.scala 1655:30] + node _T_131 = tail(_T_130, 1) @[el2_dec_tlu_ctl.scala 1655:30] + minstreth_inc <= _T_131 @[el2_dec_tlu_ctl.scala 1655:17] + node _T_132 = bits(wr_minstreth_r, 0, 0) @[el2_dec_tlu_ctl.scala 1656:42] + node minstreth_ns = mux(_T_132, io.dec_csr_wrdata_r, minstreth_inc) @[el2_dec_tlu_ctl.scala 1656:26] + node _T_133 = or(minstret_enable_f, wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1658:56] + node _T_134 = bits(_T_133, 0, 0) @[el2_dec_tlu_ctl.scala 1658:74] + inst rvclkhdr_4 of rvclkhdr_63 @[el2_lib.scala 485:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_4.io.en <= _T_134 @[el2_lib.scala 488:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_135 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_135 <= minstreth_ns @[el2_lib.scala 491:16] + minstreth <= _T_135 @[el2_dec_tlu_ctl.scala 1658:13] + node _T_136 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1666:66] + node _T_137 = eq(_T_136, UInt<12>("h0340")) @[el2_dec_tlu_ctl.scala 1666:73] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_137) @[el2_dec_tlu_ctl.scala 1666:44] + node _T_138 = bits(wr_mscratch_r, 0, 0) @[el2_dec_tlu_ctl.scala 1668:56] + inst rvclkhdr_5 of rvclkhdr_64 @[el2_lib.scala 485:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_5.io.en <= _T_138 @[el2_lib.scala 488:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_139 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_139 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mscratch <= _T_139 @[el2_dec_tlu_ctl.scala 1668:12] + node _T_140 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:23] + node _T_141 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:48] + node _T_142 = and(_T_140, _T_141) @[el2_dec_tlu_ctl.scala 1677:46] + node sel_exu_npc_r = and(_T_142, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1677:73] + node _T_143 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:25] + node _T_144 = and(_T_143, io.tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 1678:48] + node _T_145 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:76] + node sel_flush_npc_r = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 1678:74] + node _T_146 = eq(sel_exu_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:24] + node _T_147 = eq(sel_flush_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:41] + node sel_hold_npc_r = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 1679:39] + node _T_148 = bits(sel_exu_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1682:19] + node _T_149 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1683:6] + node _T_150 = and(_T_149, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1683:28] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_tlu_ctl.scala 1683:48] + node _T_152 = bits(sel_flush_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1684:21] + node _T_153 = bits(sel_hold_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1685:20] + node _T_154 = mux(_T_148, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_155 = mux(_T_151, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_156 = mux(_T_152, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_157 = mux(_T_153, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_158 = or(_T_154, _T_155) @[Mux.scala 27:72] + node _T_159 = or(_T_158, _T_156) @[Mux.scala 27:72] + node _T_160 = or(_T_159, _T_157) @[Mux.scala 27:72] + wire _T_161 : UInt<31> @[Mux.scala 27:72] + _T_161 <= _T_160 @[Mux.scala 27:72] + io.npc_r <= _T_161 @[el2_dec_tlu_ctl.scala 1681:12] + node _T_162 = or(sel_exu_npc_r, sel_flush_npc_r) @[el2_dec_tlu_ctl.scala 1687:49] + node _T_163 = or(_T_162, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1687:67] + node _T_164 = bits(_T_163, 0, 0) @[el2_dec_tlu_ctl.scala 1687:87] + inst rvclkhdr_6 of rvclkhdr_65 @[el2_lib.scala 485:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_6.io.en <= _T_164 @[el2_lib.scala 488:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_165 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_165 <= io.npc_r @[el2_lib.scala 491:16] + io.npc_r_d1 <= _T_165 @[el2_dec_tlu_ctl.scala 1687:15] + node _T_166 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1690:22] + node _T_167 = and(_T_166, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1690:45] + node pc0_valid_r = bits(_T_167, 0, 0) @[el2_dec_tlu_ctl.scala 1690:70] + node _T_168 = not(pc0_valid_r) @[el2_dec_tlu_ctl.scala 1694:5] + node _T_169 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_170 = mux(_T_168, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_171 = or(_T_169, _T_170) @[Mux.scala 27:72] + wire pc_r : UInt<31> @[Mux.scala 27:72] + pc_r <= _T_171 @[Mux.scala 27:72] + inst rvclkhdr_7 of rvclkhdr_66 @[el2_lib.scala 485:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 488:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_172 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_172 <= pc_r @[el2_lib.scala 491:16] + pc_r_d1 <= _T_172 @[el2_dec_tlu_ctl.scala 1696:11] + node _T_173 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1698:62] + node _T_174 = eq(_T_173, UInt<12>("h0341")) @[el2_dec_tlu_ctl.scala 1698:69] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_174) @[el2_dec_tlu_ctl.scala 1698:40] + node _T_175 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1701:30] + node _T_176 = or(_T_175, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1701:51] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_tlu_ctl.scala 1701:83] + node _T_178 = bits(io.interrupt_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1702:28] + node _T_179 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1703:18] + node _T_180 = and(wr_mepc_r, _T_179) @[el2_dec_tlu_ctl.scala 1703:16] + node _T_181 = bits(_T_180, 0, 0) @[el2_dec_tlu_ctl.scala 1703:42] + node _T_182 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 1703:107] + node _T_183 = eq(wr_mepc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:6] + node _T_184 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:19] + node _T_185 = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 1704:17] + node _T_186 = bits(_T_185, 0, 0) @[el2_dec_tlu_ctl.scala 1704:43] + node _T_187 = mux(_T_177, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = mux(_T_178, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_189 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_186, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = or(_T_187, _T_188) @[Mux.scala 27:72] + node _T_192 = or(_T_191, _T_189) @[Mux.scala 27:72] + node _T_193 = or(_T_192, _T_190) @[Mux.scala 27:72] + wire mepc_ns : UInt<31> @[Mux.scala 27:72] + mepc_ns <= _T_193 @[Mux.scala 27:72] + reg _T_194 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1706:48] + _T_194 <= mepc_ns @[el2_dec_tlu_ctl.scala 1706:48] + io.mepc <= _T_194 @[el2_dec_tlu_ctl.scala 1706:11] + node _T_195 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1713:64] + node _T_196 = eq(_T_195, UInt<12>("h0342")) @[el2_dec_tlu_ctl.scala 1713:71] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_196) @[el2_dec_tlu_ctl.scala 1713:42] + node _T_197 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1714:52] + node mcause_sel_nmi_store = and(_T_197, io.nmi_lsu_store_type) @[el2_dec_tlu_ctl.scala 1714:66] + node _T_198 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1715:51] + node mcause_sel_nmi_load = and(_T_198, io.nmi_lsu_load_type) @[el2_dec_tlu_ctl.scala 1715:65] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1716:50] + node _T_200 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1716:83] + node mcause_sel_nmi_ext = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 1716:64] + node _T_201 = andr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1722:52] + node _T_202 = bits(io.lsu_fir_error, 1, 1) @[el2_dec_tlu_ctl.scala 1722:75] + node _T_203 = bits(io.lsu_fir_error, 0, 0) @[el2_dec_tlu_ctl.scala 1722:98] + node _T_204 = not(_T_203) @[el2_dec_tlu_ctl.scala 1722:81] + node _T_205 = and(_T_202, _T_204) @[el2_dec_tlu_ctl.scala 1722:79] + node mcause_fir_error_type = cat(_T_201, _T_205) @[Cat.scala 29:58] + node _T_206 = bits(mcause_sel_nmi_store, 0, 0) @[el2_dec_tlu_ctl.scala 1725:26] + node _T_207 = bits(mcause_sel_nmi_load, 0, 0) @[el2_dec_tlu_ctl.scala 1726:25] + node _T_208 = bits(mcause_sel_nmi_ext, 0, 0) @[el2_dec_tlu_ctl.scala 1727:24] + node _T_209 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] + node _T_210 = cat(_T_209, mcause_fir_error_type) @[Cat.scala 29:58] + node _T_211 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1728:30] + node _T_212 = and(io.exc_or_int_valid_r, _T_211) @[el2_dec_tlu_ctl.scala 1728:28] + node _T_213 = bits(_T_212, 0, 0) @[el2_dec_tlu_ctl.scala 1728:44] + node _T_214 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] + node _T_215 = cat(_T_214, io.exc_cause_r) @[Cat.scala 29:58] + node _T_216 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1729:20] + node _T_217 = and(wr_mcause_r, _T_216) @[el2_dec_tlu_ctl.scala 1729:18] + node _T_218 = bits(_T_217, 0, 0) @[el2_dec_tlu_ctl.scala 1729:44] + node _T_219 = not(wr_mcause_r) @[el2_dec_tlu_ctl.scala 1730:6] + node _T_220 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1730:21] + node _T_221 = and(_T_219, _T_220) @[el2_dec_tlu_ctl.scala 1730:19] + node _T_222 = bits(_T_221, 0, 0) @[el2_dec_tlu_ctl.scala 1730:45] + node _T_223 = mux(_T_206, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_224 = mux(_T_207, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_225 = mux(_T_208, _T_210, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = mux(_T_218, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_228 = mux(_T_222, mcause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = or(_T_223, _T_224) @[Mux.scala 27:72] + node _T_230 = or(_T_229, _T_225) @[Mux.scala 27:72] + node _T_231 = or(_T_230, _T_226) @[Mux.scala 27:72] + node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72] + node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72] + wire mcause_ns : UInt<32> @[Mux.scala 27:72] + mcause_ns <= _T_233 @[Mux.scala 27:72] + reg _T_234 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1732:47] + _T_234 <= mcause_ns @[el2_dec_tlu_ctl.scala 1732:47] + mcause <= _T_234 @[el2_dec_tlu_ctl.scala 1732:10] + node _T_235 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1739:65] + node _T_236 = eq(_T_235, UInt<12>("h07ff")) @[el2_dec_tlu_ctl.scala 1739:72] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_236) @[el2_dec_tlu_ctl.scala 1739:43] + node _T_237 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 1741:57] + node _T_238 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] + node ifu_mscause = mux(_T_237, UInt<4>("h09"), _T_238) @[el2_dec_tlu_ctl.scala 1741:25] + node _T_239 = bits(io.lsu_i0_exc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1744:21] + node _T_240 = bits(io.i0_trigger_hit_r, 0, 0) @[el2_dec_tlu_ctl.scala 1745:25] + node _T_241 = bits(io.ebreak_r, 0, 0) @[el2_dec_tlu_ctl.scala 1746:17] + node _T_242 = bits(io.inst_acc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1747:19] + node _T_243 = mux(_T_239, io.lsu_error_pkt_r.mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_240, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_241, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = mux(_T_242, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_247 = or(_T_243, _T_244) @[Mux.scala 27:72] + node _T_248 = or(_T_247, _T_245) @[Mux.scala 27:72] + node _T_249 = or(_T_248, _T_246) @[Mux.scala 27:72] + wire mscause_type : UInt<4> @[Mux.scala 27:72] + mscause_type <= _T_249 @[Mux.scala 27:72] + node _T_250 = bits(io.exc_or_int_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1751:29] + node _T_251 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1752:21] + node _T_252 = and(wr_mscause_r, _T_251) @[el2_dec_tlu_ctl.scala 1752:19] + node _T_253 = bits(_T_252, 0, 0) @[el2_dec_tlu_ctl.scala 1752:45] + node _T_254 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 1752:84] + node _T_255 = eq(wr_mscause_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:6] + node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:22] + node _T_257 = and(_T_255, _T_256) @[el2_dec_tlu_ctl.scala 1753:20] + node _T_258 = bits(_T_257, 0, 0) @[el2_dec_tlu_ctl.scala 1753:46] + node _T_259 = mux(_T_250, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72] + wire mscause_ns : UInt<4> @[Mux.scala 27:72] + mscause_ns <= _T_263 @[Mux.scala 27:72] + reg _T_264 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1755:48] + _T_264 <= mscause_ns @[el2_dec_tlu_ctl.scala 1755:48] + mscause <= _T_264 @[el2_dec_tlu_ctl.scala 1755:11] + node _T_265 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1762:63] + node _T_266 = eq(_T_265, UInt<12>("h0343")) @[el2_dec_tlu_ctl.scala 1762:70] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_266) @[el2_dec_tlu_ctl.scala 1762:41] + node _T_267 = not(io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1763:84] + node _T_268 = and(io.inst_acc_r, _T_267) @[el2_dec_tlu_ctl.scala 1763:82] + node _T_269 = or(io.ebreak_r, _T_268) @[el2_dec_tlu_ctl.scala 1763:65] + node _T_270 = or(_T_269, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1763:107] + node _T_271 = and(io.exc_or_int_valid_r, _T_270) @[el2_dec_tlu_ctl.scala 1763:50] + node _T_272 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1763:141] + node mtval_capture_pc_r = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 1763:139] + node _T_273 = and(io.inst_acc_r, io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1764:73] + node _T_274 = and(io.exc_or_int_valid_r, _T_273) @[el2_dec_tlu_ctl.scala 1764:56] + node _T_275 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1764:99] + node mtval_capture_pc_plus2_r = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 1764:97] + node _T_276 = and(io.exc_or_int_valid_r, io.illegal_r) @[el2_dec_tlu_ctl.scala 1765:52] + node _T_277 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1765:69] + node mtval_capture_inst_r = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 1765:67] + node _T_278 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1766:51] + node _T_279 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1766:74] + node mtval_capture_lsu_r = and(_T_278, _T_279) @[el2_dec_tlu_ctl.scala 1766:72] + node _T_280 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1767:47] + node _T_281 = and(io.exc_or_int_valid_r, _T_280) @[el2_dec_tlu_ctl.scala 1767:45] + node _T_282 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1767:69] + node _T_283 = and(_T_281, _T_282) @[el2_dec_tlu_ctl.scala 1767:67] + node _T_284 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1767:93] + node _T_285 = and(_T_283, _T_284) @[el2_dec_tlu_ctl.scala 1767:91] + node _T_286 = not(io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1767:116] + node mtval_clear_r = and(_T_285, _T_286) @[el2_dec_tlu_ctl.scala 1767:114] + node _T_287 = bits(mtval_capture_pc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1771:26] + node _T_288 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_289 = bits(mtval_capture_pc_plus2_r, 0, 0) @[el2_dec_tlu_ctl.scala 1772:32] + node _T_290 = add(pc_r, UInt<31>("h01")) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_291 = tail(_T_290, 1) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = bits(mtval_capture_inst_r, 0, 0) @[el2_dec_tlu_ctl.scala 1773:28] + node _T_294 = bits(mtval_capture_lsu_r, 0, 0) @[el2_dec_tlu_ctl.scala 1774:27] + node _T_295 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1775:19] + node _T_296 = and(wr_mtval_r, _T_295) @[el2_dec_tlu_ctl.scala 1775:17] + node _T_297 = bits(_T_296, 0, 0) @[el2_dec_tlu_ctl.scala 1775:49] + node _T_298 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1776:6] + node _T_299 = not(wr_mtval_r) @[el2_dec_tlu_ctl.scala 1776:21] + node _T_300 = and(_T_298, _T_299) @[el2_dec_tlu_ctl.scala 1776:19] + node _T_301 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1776:35] + node _T_302 = and(_T_300, _T_301) @[el2_dec_tlu_ctl.scala 1776:33] + node _T_303 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1776:57] + node _T_304 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 1776:55] + node _T_305 = not(mtval_clear_r) @[el2_dec_tlu_ctl.scala 1776:81] + node _T_306 = and(_T_304, _T_305) @[el2_dec_tlu_ctl.scala 1776:79] + node _T_307 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1776:98] + node _T_308 = and(_T_306, _T_307) @[el2_dec_tlu_ctl.scala 1776:96] + node _T_309 = bits(_T_308, 0, 0) @[el2_dec_tlu_ctl.scala 1776:120] + node _T_310 = mux(_T_287, _T_288, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_311 = mux(_T_289, _T_292, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_312 = mux(_T_293, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_313 = mux(_T_294, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_314 = mux(_T_297, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_315 = mux(_T_309, mtval, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_316 = or(_T_310, _T_311) @[Mux.scala 27:72] + node _T_317 = or(_T_316, _T_312) @[Mux.scala 27:72] + node _T_318 = or(_T_317, _T_313) @[Mux.scala 27:72] + node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72] + node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72] + wire mtval_ns : UInt<32> @[Mux.scala 27:72] + mtval_ns <= _T_320 @[Mux.scala 27:72] + reg _T_321 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1778:47] + _T_321 <= mtval_ns @[el2_dec_tlu_ctl.scala 1778:47] + mtval <= _T_321 @[el2_dec_tlu_ctl.scala 1778:9] + node _T_322 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1793:62] + node _T_323 = eq(_T_322, UInt<12>("h07f8")) @[el2_dec_tlu_ctl.scala 1793:69] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_323) @[el2_dec_tlu_ctl.scala 1793:40] + node _T_324 = bits(io.dec_csr_wrdata_r, 8, 0) @[el2_dec_tlu_ctl.scala 1795:40] + node _T_325 = bits(wr_mcgc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1795:56] + inst rvclkhdr_8 of rvclkhdr_67 @[el2_lib.scala 485:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_8.io.en <= _T_325 @[el2_lib.scala 488:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mcgc <= _T_324 @[el2_lib.scala 491:16] + node _T_326 = bits(mcgc, 8, 8) @[el2_dec_tlu_ctl.scala 1797:39] + io.dec_tlu_misc_clk_override <= _T_326 @[el2_dec_tlu_ctl.scala 1797:32] + node _T_327 = bits(mcgc, 7, 7) @[el2_dec_tlu_ctl.scala 1798:39] + io.dec_tlu_dec_clk_override <= _T_327 @[el2_dec_tlu_ctl.scala 1798:32] + node _T_328 = bits(mcgc, 5, 5) @[el2_dec_tlu_ctl.scala 1799:39] + io.dec_tlu_ifu_clk_override <= _T_328 @[el2_dec_tlu_ctl.scala 1799:32] + node _T_329 = bits(mcgc, 4, 4) @[el2_dec_tlu_ctl.scala 1800:39] + io.dec_tlu_lsu_clk_override <= _T_329 @[el2_dec_tlu_ctl.scala 1800:32] + node _T_330 = bits(mcgc, 3, 3) @[el2_dec_tlu_ctl.scala 1801:39] + io.dec_tlu_bus_clk_override <= _T_330 @[el2_dec_tlu_ctl.scala 1801:32] + node _T_331 = bits(mcgc, 2, 2) @[el2_dec_tlu_ctl.scala 1802:39] + io.dec_tlu_pic_clk_override <= _T_331 @[el2_dec_tlu_ctl.scala 1802:32] + node _T_332 = bits(mcgc, 1, 1) @[el2_dec_tlu_ctl.scala 1803:39] + io.dec_tlu_dccm_clk_override <= _T_332 @[el2_dec_tlu_ctl.scala 1803:32] + node _T_333 = bits(mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 1804:39] + io.dec_tlu_icm_clk_override <= _T_333 @[el2_dec_tlu_ctl.scala 1804:32] + node _T_334 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1823:62] + node _T_335 = eq(_T_334, UInt<12>("h07f9")) @[el2_dec_tlu_ctl.scala 1823:69] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_335) @[el2_dec_tlu_ctl.scala 1823:40] + node _T_336 = bits(wr_mfdc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1827:40] + inst rvclkhdr_9 of rvclkhdr_68 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_336 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_337 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_337 <= mfdc_ns @[el2_lib.scala 491:16] + mfdc_int <= _T_337 @[el2_dec_tlu_ctl.scala 1827:12] + node _T_338 = bits(io.dec_csr_wrdata_r, 18, 16) @[el2_dec_tlu_ctl.scala 1832:40] + node _T_339 = not(_T_338) @[el2_dec_tlu_ctl.scala 1832:20] + node _T_340 = bits(io.dec_csr_wrdata_r, 11, 7) @[el2_dec_tlu_ctl.scala 1832:67] + node _T_341 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1832:95] + node _T_342 = not(_T_341) @[el2_dec_tlu_ctl.scala 1832:75] + node _T_343 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1832:119] + node _T_344 = cat(_T_342, _T_343) @[Cat.scala 29:58] + node _T_345 = cat(_T_339, _T_340) @[Cat.scala 29:58] + node _T_346 = cat(_T_345, _T_344) @[Cat.scala 29:58] + mfdc_ns <= _T_346 @[el2_dec_tlu_ctl.scala 1832:13] + node _T_347 = bits(mfdc_int, 14, 12) @[el2_dec_tlu_ctl.scala 1833:29] + node _T_348 = not(_T_347) @[el2_dec_tlu_ctl.scala 1833:20] + node _T_349 = bits(mfdc_int, 11, 7) @[el2_dec_tlu_ctl.scala 1833:55] + node _T_350 = bits(mfdc_int, 6, 6) @[el2_dec_tlu_ctl.scala 1833:72] + node _T_351 = not(_T_350) @[el2_dec_tlu_ctl.scala 1833:63] + node _T_352 = bits(mfdc_int, 5, 0) @[el2_dec_tlu_ctl.scala 1833:85] + node _T_353 = cat(_T_351, _T_352) @[Cat.scala 29:58] + node _T_354 = cat(_T_348, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_355 = cat(_T_354, _T_349) @[Cat.scala 29:58] + node _T_356 = cat(_T_355, _T_353) @[Cat.scala 29:58] + mfdc <= _T_356 @[el2_dec_tlu_ctl.scala 1833:13] + node _T_357 = bits(mfdc, 18, 16) @[el2_dec_tlu_ctl.scala 1841:47] + io.dec_tlu_dma_qos_prty <= _T_357 @[el2_dec_tlu_ctl.scala 1841:40] + node _T_358 = bits(mfdc, 11, 11) @[el2_dec_tlu_ctl.scala 1842:47] + io.dec_tlu_external_ldfwd_disable <= _T_358 @[el2_dec_tlu_ctl.scala 1842:40] + node _T_359 = bits(mfdc, 8, 8) @[el2_dec_tlu_ctl.scala 1843:47] + io.dec_tlu_core_ecc_disable <= _T_359 @[el2_dec_tlu_ctl.scala 1843:40] + node _T_360 = bits(mfdc, 6, 6) @[el2_dec_tlu_ctl.scala 1844:47] + io.dec_tlu_sideeffect_posted_disable <= _T_360 @[el2_dec_tlu_ctl.scala 1844:40] + node _T_361 = bits(mfdc, 3, 3) @[el2_dec_tlu_ctl.scala 1845:47] + io.dec_tlu_bpred_disable <= _T_361 @[el2_dec_tlu_ctl.scala 1845:40] + node _T_362 = bits(mfdc, 2, 2) @[el2_dec_tlu_ctl.scala 1846:47] + io.dec_tlu_wb_coalescing_disable <= _T_362 @[el2_dec_tlu_ctl.scala 1846:40] + node _T_363 = bits(mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 1847:47] + io.dec_tlu_pipelining_disable <= _T_363 @[el2_dec_tlu_ctl.scala 1847:40] + node _T_364 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1856:71] + node _T_365 = eq(_T_364, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 1856:78] + node _T_366 = and(io.dec_csr_wen_r_mod, _T_365) @[el2_dec_tlu_ctl.scala 1856:49] + node _T_367 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1856:90] + node _T_368 = and(_T_366, _T_367) @[el2_dec_tlu_ctl.scala 1856:88] + node _T_369 = not(io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 1856:114] + node _T_370 = and(_T_368, _T_369) @[el2_dec_tlu_ctl.scala 1856:112] + io.dec_tlu_wr_pause_r <= _T_370 @[el2_dec_tlu_ctl.scala 1856:25] + node _T_371 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1863:62] + node _T_372 = eq(_T_371, UInt<12>("h07c0")) @[el2_dec_tlu_ctl.scala 1863:69] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_372) @[el2_dec_tlu_ctl.scala 1863:40] + node _T_373 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:40] + node _T_374 = bits(io.dec_csr_wrdata_r, 30, 30) @[el2_dec_tlu_ctl.scala 1866:65] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:92] + node _T_376 = not(_T_375) @[el2_dec_tlu_ctl.scala 1866:72] + node _T_377 = and(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 1866:70] + node _T_378 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:24] + node _T_379 = bits(io.dec_csr_wrdata_r, 28, 28) @[el2_dec_tlu_ctl.scala 1867:49] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:76] + node _T_381 = not(_T_380) @[el2_dec_tlu_ctl.scala 1867:56] + node _T_382 = and(_T_379, _T_381) @[el2_dec_tlu_ctl.scala 1867:54] + node _T_383 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:24] + node _T_384 = bits(io.dec_csr_wrdata_r, 26, 26) @[el2_dec_tlu_ctl.scala 1868:49] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:76] + node _T_386 = not(_T_385) @[el2_dec_tlu_ctl.scala 1868:56] + node _T_387 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 1868:54] + node _T_388 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:24] + node _T_389 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 1869:49] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:76] + node _T_391 = not(_T_390) @[el2_dec_tlu_ctl.scala 1869:56] + node _T_392 = and(_T_389, _T_391) @[el2_dec_tlu_ctl.scala 1869:54] + node _T_393 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:24] + node _T_394 = bits(io.dec_csr_wrdata_r, 22, 22) @[el2_dec_tlu_ctl.scala 1870:49] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:76] + node _T_396 = not(_T_395) @[el2_dec_tlu_ctl.scala 1870:56] + node _T_397 = and(_T_394, _T_396) @[el2_dec_tlu_ctl.scala 1870:54] + node _T_398 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:24] + node _T_399 = bits(io.dec_csr_wrdata_r, 20, 20) @[el2_dec_tlu_ctl.scala 1871:49] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:76] + node _T_401 = not(_T_400) @[el2_dec_tlu_ctl.scala 1871:56] + node _T_402 = and(_T_399, _T_401) @[el2_dec_tlu_ctl.scala 1871:54] + node _T_403 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:24] + node _T_404 = bits(io.dec_csr_wrdata_r, 18, 18) @[el2_dec_tlu_ctl.scala 1872:49] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:76] + node _T_406 = not(_T_405) @[el2_dec_tlu_ctl.scala 1872:56] + node _T_407 = and(_T_404, _T_406) @[el2_dec_tlu_ctl.scala 1872:54] + node _T_408 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:24] + node _T_409 = bits(io.dec_csr_wrdata_r, 16, 16) @[el2_dec_tlu_ctl.scala 1873:49] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:76] + node _T_411 = not(_T_410) @[el2_dec_tlu_ctl.scala 1873:56] + node _T_412 = and(_T_409, _T_411) @[el2_dec_tlu_ctl.scala 1873:54] + node _T_413 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:24] + node _T_414 = bits(io.dec_csr_wrdata_r, 14, 14) @[el2_dec_tlu_ctl.scala 1874:49] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:76] + node _T_416 = not(_T_415) @[el2_dec_tlu_ctl.scala 1874:56] + node _T_417 = and(_T_414, _T_416) @[el2_dec_tlu_ctl.scala 1874:54] + node _T_418 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:24] + node _T_419 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 1875:49] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:76] + node _T_421 = not(_T_420) @[el2_dec_tlu_ctl.scala 1875:56] + node _T_422 = and(_T_419, _T_421) @[el2_dec_tlu_ctl.scala 1875:54] + node _T_423 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:24] + node _T_424 = bits(io.dec_csr_wrdata_r, 10, 10) @[el2_dec_tlu_ctl.scala 1876:49] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:76] + node _T_426 = not(_T_425) @[el2_dec_tlu_ctl.scala 1876:56] + node _T_427 = and(_T_424, _T_426) @[el2_dec_tlu_ctl.scala 1876:54] + node _T_428 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:24] + node _T_429 = bits(io.dec_csr_wrdata_r, 8, 8) @[el2_dec_tlu_ctl.scala 1877:49] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:76] + node _T_431 = not(_T_430) @[el2_dec_tlu_ctl.scala 1877:56] + node _T_432 = and(_T_429, _T_431) @[el2_dec_tlu_ctl.scala 1877:53] + node _T_433 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:24] + node _T_434 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1878:49] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:76] + node _T_436 = not(_T_435) @[el2_dec_tlu_ctl.scala 1878:56] + node _T_437 = and(_T_434, _T_436) @[el2_dec_tlu_ctl.scala 1878:53] + node _T_438 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:24] + node _T_439 = bits(io.dec_csr_wrdata_r, 4, 4) @[el2_dec_tlu_ctl.scala 1879:49] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:76] + node _T_441 = not(_T_440) @[el2_dec_tlu_ctl.scala 1879:56] + node _T_442 = and(_T_439, _T_441) @[el2_dec_tlu_ctl.scala 1879:53] + node _T_443 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:24] + node _T_444 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 1880:49] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:76] + node _T_446 = not(_T_445) @[el2_dec_tlu_ctl.scala 1880:56] + node _T_447 = and(_T_444, _T_446) @[el2_dec_tlu_ctl.scala 1880:53] + node _T_448 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:24] + node _T_449 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1881:49] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:76] + node _T_451 = not(_T_450) @[el2_dec_tlu_ctl.scala 1881:56] + node _T_452 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 1881:53] + node _T_453 = cat(_T_448, _T_452) @[Cat.scala 29:58] + node _T_454 = cat(_T_443, _T_447) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_453) @[Cat.scala 29:58] + node _T_456 = cat(_T_438, _T_442) @[Cat.scala 29:58] + node _T_457 = cat(_T_433, _T_437) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_456) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_455) @[Cat.scala 29:58] + node _T_460 = cat(_T_428, _T_432) @[Cat.scala 29:58] + node _T_461 = cat(_T_423, _T_427) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_418, _T_422) @[Cat.scala 29:58] + node _T_464 = cat(_T_413, _T_417) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_459) @[Cat.scala 29:58] + node _T_468 = cat(_T_408, _T_412) @[Cat.scala 29:58] + node _T_469 = cat(_T_403, _T_407) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_468) @[Cat.scala 29:58] + node _T_471 = cat(_T_398, _T_402) @[Cat.scala 29:58] + node _T_472 = cat(_T_393, _T_397) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_471) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_470) @[Cat.scala 29:58] + node _T_475 = cat(_T_388, _T_392) @[Cat.scala 29:58] + node _T_476 = cat(_T_383, _T_387) @[Cat.scala 29:58] + node _T_477 = cat(_T_476, _T_475) @[Cat.scala 29:58] + node _T_478 = cat(_T_378, _T_382) @[Cat.scala 29:58] + node _T_479 = cat(_T_373, _T_377) @[Cat.scala 29:58] + node _T_480 = cat(_T_479, _T_478) @[Cat.scala 29:58] + node _T_481 = cat(_T_480, _T_477) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_474) @[Cat.scala 29:58] + node mrac_in = cat(_T_482, _T_467) @[Cat.scala 29:58] + node _T_483 = bits(wr_mrac_r, 0, 0) @[el2_dec_tlu_ctl.scala 1884:39] + inst rvclkhdr_10 of rvclkhdr_69 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_483 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mrac <= mrac_in @[el2_lib.scala 491:16] + io.dec_tlu_mrac_ff <= mrac @[el2_dec_tlu_ctl.scala 1886:22] + node _T_484 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1894:63] + node _T_485 = eq(_T_484, UInt<12>("h0bc0")) @[el2_dec_tlu_ctl.scala 1894:70] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_485) @[el2_dec_tlu_ctl.scala 1894:41] + node _T_486 = not(wr_mdeau_r) @[el2_dec_tlu_ctl.scala 1904:60] + node _T_487 = and(io.mdseac_locked_f, _T_486) @[el2_dec_tlu_ctl.scala 1904:58] + node _T_488 = or(mdseac_en, _T_487) @[el2_dec_tlu_ctl.scala 1904:36] + io.mdseac_locked_ns <= _T_488 @[el2_dec_tlu_ctl.scala 1904:23] + node _T_489 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 1906:50] + node _T_490 = not(io.nmi_int_detected_f) @[el2_dec_tlu_ctl.scala 1906:87] + node _T_491 = and(_T_489, _T_490) @[el2_dec_tlu_ctl.scala 1906:85] + node _T_492 = not(io.mdseac_locked_f) @[el2_dec_tlu_ctl.scala 1906:112] + node _T_493 = and(_T_491, _T_492) @[el2_dec_tlu_ctl.scala 1906:110] + mdseac_en <= _T_493 @[el2_dec_tlu_ctl.scala 1906:13] + node _T_494 = bits(mdseac_en, 0, 0) @[el2_dec_tlu_ctl.scala 1908:65] + inst rvclkhdr_11 of rvclkhdr_70 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_494 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mdseac <= io.lsu_imprecise_error_addr_any @[el2_lib.scala 491:16] + node _T_495 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1917:62] + node _T_496 = eq(_T_495, UInt<12>("h07c6")) @[el2_dec_tlu_ctl.scala 1917:69] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_496) @[el2_dec_tlu_ctl.scala 1917:40] + node _T_497 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1921:52] + node _T_498 = and(wr_mpmc_r, _T_497) @[el2_dec_tlu_ctl.scala 1921:31] + node _T_499 = not(io.internal_dbg_halt_mode_f2) @[el2_dec_tlu_ctl.scala 1921:58] + node _T_500 = and(_T_498, _T_499) @[el2_dec_tlu_ctl.scala 1921:56] + node _T_501 = not(io.ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 1921:90] + node _T_502 = and(_T_500, _T_501) @[el2_dec_tlu_ctl.scala 1921:88] + io.fw_halt_req <= _T_502 @[el2_dec_tlu_ctl.scala 1921:18] + node _T_503 = or(io.fw_halt_req, fw_halted) @[el2_dec_tlu_ctl.scala 1923:38] + node _T_504 = not(set_mie_pmu_fw_halt) @[el2_dec_tlu_ctl.scala 1923:53] + node fw_halted_ns = and(_T_503, _T_504) @[el2_dec_tlu_ctl.scala 1923:51] + node _T_505 = bits(wr_mpmc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1924:30] + node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1924:58] + node _T_507 = not(_T_506) @[el2_dec_tlu_ctl.scala 1924:38] + node _T_508 = not(mpmc) @[el2_dec_tlu_ctl.scala 1924:63] + node _T_509 = mux(_T_505, _T_507, _T_508) @[el2_dec_tlu_ctl.scala 1924:19] + mpmc_b_ns <= _T_509 @[el2_dec_tlu_ctl.scala 1924:13] + reg _T_510 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1926:45] + _T_510 <= mpmc_b_ns @[el2_dec_tlu_ctl.scala 1926:45] + mpmc_b <= _T_510 @[el2_dec_tlu_ctl.scala 1926:10] + reg _T_511 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1927:46] + _T_511 <= fw_halted_ns @[el2_dec_tlu_ctl.scala 1927:46] + fw_halted <= _T_511 @[el2_dec_tlu_ctl.scala 1927:13] + node _T_512 = not(mpmc_b) @[el2_dec_tlu_ctl.scala 1929:11] + mpmc <= _T_512 @[el2_dec_tlu_ctl.scala 1929:8] + node _T_513 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:41] + node _T_514 = gt(_T_513, UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 1938:49] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:93] + node csr_sat = mux(_T_514, UInt<5>("h01a"), _T_515) @[el2_dec_tlu_ctl.scala 1938:20] + node _T_516 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1940:64] + node _T_517 = eq(_T_516, UInt<12>("h07f0")) @[el2_dec_tlu_ctl.scala 1940:71] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_517) @[el2_dec_tlu_ctl.scala 1940:42] + node _T_518 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_519 = add(micect, _T_518) @[el2_dec_tlu_ctl.scala 1941:24] + node _T_520 = tail(_T_519, 1) @[el2_dec_tlu_ctl.scala 1941:24] + micect_inc <= _T_520 @[el2_dec_tlu_ctl.scala 1941:14] + node _T_521 = bits(wr_micect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1942:36] + node _T_522 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1942:76] + node _T_523 = cat(csr_sat, _T_522) @[Cat.scala 29:58] + node _T_524 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1942:96] + node _T_525 = cat(_T_524, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_521, _T_523, _T_525) @[el2_dec_tlu_ctl.scala 1942:23] + node _T_526 = or(wr_micect_r, io.ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 1944:43] + node _T_527 = bits(_T_526, 0, 0) @[el2_dec_tlu_ctl.scala 1944:62] + inst rvclkhdr_12 of rvclkhdr_71 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_527 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_528 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_528 <= micect_ns @[el2_lib.scala 491:16] + micect <= _T_528 @[el2_dec_tlu_ctl.scala 1944:10] + node _T_529 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1946:48] + node _T_530 = dshl(UInt<32>("h0ffffffff"), _T_529) @[el2_dec_tlu_ctl.scala 1946:39] + node _T_531 = orr(_T_530) @[el2_dec_tlu_ctl.scala 1946:57] + node _T_532 = bits(micect, 26, 0) @[el2_dec_tlu_ctl.scala 1946:83] + node _T_533 = cat(UInt<5>("h00"), _T_532) @[Cat.scala 29:58] + node _T_534 = and(_T_531, _T_533) @[el2_dec_tlu_ctl.scala 1946:61] + mice_ce_req <= _T_534 @[el2_dec_tlu_ctl.scala 1946:15] + node _T_535 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1955:70] + node _T_536 = eq(_T_535, UInt<12>("h07f1")) @[el2_dec_tlu_ctl.scala 1955:77] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_536) @[el2_dec_tlu_ctl.scala 1955:48] + node _T_537 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1956:27] + node _T_538 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1956:71] + node _T_539 = cat(UInt<26>("h00"), _T_538) @[Cat.scala 29:58] + node _T_540 = add(_T_537, _T_539) @[el2_dec_tlu_ctl.scala 1956:34] + node _T_541 = tail(_T_540, 1) @[el2_dec_tlu_ctl.scala 1956:34] + miccmect_inc <= _T_541 @[el2_dec_tlu_ctl.scala 1956:16] + node _T_542 = bits(wr_miccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1957:46] + node _T_543 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1957:86] + node _T_544 = cat(csr_sat, _T_543) @[Cat.scala 29:58] + node _T_545 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1957:108] + node _T_546 = cat(_T_545, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_542, _T_544, _T_546) @[el2_dec_tlu_ctl.scala 1957:31] + node _T_547 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 1959:49] + node _T_548 = or(_T_547, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1959:70] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 1959:94] + inst rvclkhdr_13 of rvclkhdr_72 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_549 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_550 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_550 <= miccmect_ns @[el2_lib.scala 491:16] + miccmect <= _T_550 @[el2_dec_tlu_ctl.scala 1959:12] + node _T_551 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1960:53] + node _T_552 = dshl(UInt<32>("h0ffffffff"), _T_551) @[el2_dec_tlu_ctl.scala 1960:42] + node _T_553 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1960:86] + node _T_554 = cat(UInt<5>("h00"), _T_553) @[Cat.scala 29:58] + node _T_555 = and(_T_552, _T_554) @[el2_dec_tlu_ctl.scala 1960:62] + node _T_556 = orr(_T_555) @[el2_dec_tlu_ctl.scala 1960:95] + miccme_ce_req <= _T_556 @[el2_dec_tlu_ctl.scala 1960:17] + node _T_557 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1969:70] + node _T_558 = eq(_T_557, UInt<12>("h07f2")) @[el2_dec_tlu_ctl.scala 1969:77] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_558) @[el2_dec_tlu_ctl.scala 1969:48] + node _T_559 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1970:27] + node _T_560 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_561 = add(_T_559, _T_560) @[el2_dec_tlu_ctl.scala 1970:34] + node _T_562 = tail(_T_561, 1) @[el2_dec_tlu_ctl.scala 1970:34] + mdccmect_inc <= _T_562 @[el2_dec_tlu_ctl.scala 1970:16] + node _T_563 = bits(wr_mdccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1971:46] + node _T_564 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1971:86] + node _T_565 = cat(csr_sat, _T_564) @[Cat.scala 29:58] + node _T_566 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1971:108] + node _T_567 = cat(_T_566, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_563, _T_565, _T_567) @[el2_dec_tlu_ctl.scala 1971:31] + node _T_568 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[el2_dec_tlu_ctl.scala 1973:50] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 1973:82] + inst rvclkhdr_14 of rvclkhdr_73 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_569 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_570 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_570 <= mdccmect_ns @[el2_lib.scala 491:16] + mdccmect <= _T_570 @[el2_dec_tlu_ctl.scala 1973:12] + node _T_571 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1975:53] + node _T_572 = dshl(UInt<32>("h0ffffffff"), _T_571) @[el2_dec_tlu_ctl.scala 1975:42] + node _T_573 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1975:86] + node _T_574 = cat(UInt<5>("h00"), _T_573) @[Cat.scala 29:58] + node _T_575 = and(_T_572, _T_574) @[el2_dec_tlu_ctl.scala 1975:62] + node _T_576 = orr(_T_575) @[el2_dec_tlu_ctl.scala 1975:95] + mdccme_ce_req <= _T_576 @[el2_dec_tlu_ctl.scala 1975:17] + node _T_577 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1985:63] + node _T_578 = eq(_T_577, UInt<12>("h07ce")) @[el2_dec_tlu_ctl.scala 1985:70] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_578) @[el2_dec_tlu_ctl.scala 1985:41] + node _T_579 = bits(wr_mfdht_r, 0, 0) @[el2_dec_tlu_ctl.scala 1987:33] + node _T_580 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1987:60] + node mfdht_ns = mux(_T_579, _T_580, mfdht) @[el2_dec_tlu_ctl.scala 1987:21] + reg _T_581 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1989:44] + _T_581 <= mfdht_ns @[el2_dec_tlu_ctl.scala 1989:44] + mfdht <= _T_581 @[el2_dec_tlu_ctl.scala 1989:9] + node _T_582 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1998:63] + node _T_583 = eq(_T_582, UInt<12>("h07cf")) @[el2_dec_tlu_ctl.scala 1998:70] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_583) @[el2_dec_tlu_ctl.scala 1998:41] + node _T_584 = bits(wr_mfdhs_r, 0, 0) @[el2_dec_tlu_ctl.scala 2000:33] + node _T_585 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2000:61] + node _T_586 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2001:30] + node _T_587 = and(io.dbg_tlu_halted, _T_586) @[el2_dec_tlu_ctl.scala 2001:28] + node _T_588 = bits(_T_587, 0, 0) @[el2_dec_tlu_ctl.scala 2001:52] + node _T_589 = not(io.lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 2001:65] + node _T_590 = not(io.ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 2001:85] + node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] + node _T_592 = mux(_T_588, _T_591, mfdhs) @[el2_dec_tlu_ctl.scala 2001:8] + node mfdhs_ns = mux(_T_584, _T_585, _T_592) @[el2_dec_tlu_ctl.scala 2000:21] + node _T_593 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2003:72] + node _T_594 = bits(_T_593, 0, 0) @[el2_dec_tlu_ctl.scala 2003:93] + reg _T_595 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_594 : @[Reg.scala 28:19] + _T_595 <= mfdhs_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdhs <= _T_595 @[el2_dec_tlu_ctl.scala 2003:9] + node _T_596 = bits(io.debug_halt_req_f, 0, 0) @[el2_dec_tlu_ctl.scala 2005:48] + node _T_597 = add(force_halt_ctr_f, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_598 = tail(_T_597, 1) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_599 = bits(io.dbg_tlu_halted_f, 0, 0) @[el2_dec_tlu_ctl.scala 2006:29] + node _T_600 = mux(_T_599, UInt<32>("h00"), force_halt_ctr_f) @[el2_dec_tlu_ctl.scala 2006:8] + node force_halt_ctr = mux(_T_596, _T_598, _T_600) @[el2_dec_tlu_ctl.scala 2005:27] + node _T_601 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2008:82] + reg _T_602 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_601 : @[Reg.scala 28:19] + _T_602 <= force_halt_ctr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + force_halt_ctr_f <= _T_602 @[el2_dec_tlu_ctl.scala 2008:20] + node _T_603 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2010:25] + node _T_604 = bits(mfdht, 5, 1) @[el2_dec_tlu_ctl.scala 2010:80] + node _T_605 = dshl(UInt<32>("h0ffffffff"), _T_604) @[el2_dec_tlu_ctl.scala 2010:72] + node _T_606 = and(force_halt_ctr_f, _T_605) @[el2_dec_tlu_ctl.scala 2010:49] + node _T_607 = orr(_T_606) @[el2_dec_tlu_ctl.scala 2010:88] + node _T_608 = and(_T_603, _T_607) @[el2_dec_tlu_ctl.scala 2010:29] + io.force_halt <= _T_608 @[el2_dec_tlu_ctl.scala 2010:17] + node _T_609 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2018:63] + node _T_610 = eq(_T_609, UInt<12>("h0bc8")) @[el2_dec_tlu_ctl.scala 2018:70] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_610) @[el2_dec_tlu_ctl.scala 2018:41] + node _T_611 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2020:41] + node _T_612 = bits(wr_meivt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2020:60] + inst rvclkhdr_15 of rvclkhdr_74 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_612 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + meivt <= _T_611 @[el2_lib.scala 491:16] + node _T_613 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2032:50] + inst rvclkhdr_16 of rvclkhdr_75 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_613 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + meihap <= io.pic_claimid @[el2_lib.scala 491:16] + node _T_614 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, UInt<2>("h00")) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_615 @[el2_dec_tlu_ctl.scala 2033:21] + node _T_616 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2042:66] + node _T_617 = eq(_T_616, UInt<12>("h0bcc")) @[el2_dec_tlu_ctl.scala 2042:73] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_617) @[el2_dec_tlu_ctl.scala 2042:44] + node _T_618 = bits(wr_meicurpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2043:39] + node _T_619 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2043:66] + node meicurpl_ns = mux(_T_618, _T_619, meicurpl) @[el2_dec_tlu_ctl.scala 2043:24] + reg _T_620 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2045:47] + _T_620 <= meicurpl_ns @[el2_dec_tlu_ctl.scala 2045:47] + meicurpl <= _T_620 @[el2_dec_tlu_ctl.scala 2045:12] + io.dec_tlu_meicurpl <= meicurpl @[el2_dec_tlu_ctl.scala 2047:23] + node _T_621 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2057:67] + node _T_622 = eq(_T_621, UInt<12>("h0bcb")) @[el2_dec_tlu_ctl.scala 2057:74] + node _T_623 = and(io.dec_csr_wen_r_mod, _T_622) @[el2_dec_tlu_ctl.scala 2057:45] + node wr_meicidpl_r = or(_T_623, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2057:89] + node _T_624 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2059:38] + node _T_625 = bits(wr_meicidpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2060:23] + node _T_626 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2060:50] + node _T_627 = mux(_T_625, _T_626, meicidpl) @[el2_dec_tlu_ctl.scala 2060:8] + node meicidpl_ns = mux(_T_624, io.pic_pl, _T_627) @[el2_dec_tlu_ctl.scala 2059:24] + reg _T_628 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2062:45] + _T_628 <= meicidpl_ns @[el2_dec_tlu_ctl.scala 2062:45] + meicidpl <= _T_628 @[el2_dec_tlu_ctl.scala 2062:12] + node _T_629 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2069:63] + node _T_630 = eq(_T_629, UInt<12>("h0bca")) @[el2_dec_tlu_ctl.scala 2069:70] + node _T_631 = and(io.dec_csr_wen_r_mod, _T_630) @[el2_dec_tlu_ctl.scala 2069:41] + node _T_632 = or(_T_631, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2069:84] + wr_meicpct_r <= _T_632 @[el2_dec_tlu_ctl.scala 2069:16] + node _T_633 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2078:63] + node _T_634 = eq(_T_633, UInt<12>("h0bc9")) @[el2_dec_tlu_ctl.scala 2078:70] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_634) @[el2_dec_tlu_ctl.scala 2078:41] + node _T_635 = bits(wr_meipt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2079:33] + node _T_636 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2079:60] + node meipt_ns = mux(_T_635, _T_636, meipt) @[el2_dec_tlu_ctl.scala 2079:21] + reg _T_637 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2081:44] + _T_637 <= meipt_ns @[el2_dec_tlu_ctl.scala 2081:44] + meipt <= _T_637 @[el2_dec_tlu_ctl.scala 2081:9] + io.dec_tlu_meipt <= meipt @[el2_dec_tlu_ctl.scala 2083:20] + node _T_638 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 2109:90] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_638) @[el2_dec_tlu_ctl.scala 2109:67] + node _T_639 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2112:35] + node _T_640 = and(io.dcsr_single_step_done_f, _T_639) @[el2_dec_tlu_ctl.scala 2112:33] + node _T_641 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2112:67] + node _T_642 = and(_T_640, _T_641) @[el2_dec_tlu_ctl.scala 2112:65] + node _T_643 = not(io.debug_halt_req) @[el2_dec_tlu_ctl.scala 2112:102] + node _T_644 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2112:100] + node _T_645 = bits(_T_644, 0, 0) @[el2_dec_tlu_ctl.scala 2112:122] + node _T_646 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2113:26] + node _T_647 = and(io.debug_halt_req, _T_646) @[el2_dec_tlu_ctl.scala 2113:24] + node _T_648 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2113:58] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 2113:56] + node _T_650 = bits(_T_649, 0, 0) @[el2_dec_tlu_ctl.scala 2113:92] + node _T_651 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2114:37] + node _T_652 = and(io.ebreak_to_debug_mode_r_d1, _T_651) @[el2_dec_tlu_ctl.scala 2114:35] + node _T_653 = bits(_T_652, 0, 0) @[el2_dec_tlu_ctl.scala 2114:71] + node _T_654 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[el2_dec_tlu_ctl.scala 2115:39] + node _T_655 = mux(_T_645, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_656 = mux(_T_650, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_653, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = or(_T_655, _T_656) @[Mux.scala 27:72] + node _T_660 = or(_T_659, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + wire dcsr_cause : UInt<3> @[Mux.scala 27:72] + dcsr_cause <= _T_661 @[Mux.scala 27:72] + node _T_662 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2117:47] + node _T_663 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2117:92] + node _T_664 = eq(_T_663, UInt<12>("h07b0")) @[el2_dec_tlu_ctl.scala 2117:99] + node wr_dcsr_r = and(_T_662, _T_664) @[el2_dec_tlu_ctl.scala 2117:70] + node _T_665 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2123:70] + node _T_666 = eq(_T_665, UInt<3>("h03")) @[el2_dec_tlu_ctl.scala 2123:76] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_666) @[el2_dec_tlu_ctl.scala 2123:60] + node _T_667 = not(io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2124:60] + node _T_668 = or(_T_667, dcsr_cause_upgradeable) @[el2_dec_tlu_ctl.scala 2124:79] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_668) @[el2_dec_tlu_ctl.scala 2124:57] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[el2_dec_tlu_ctl.scala 2126:49] + node _T_669 = bits(enter_debug_halt_req_le, 0, 0) @[el2_dec_tlu_ctl.scala 2127:45] + node _T_670 = bits(io.dcsr, 15, 9) @[el2_dec_tlu_ctl.scala 2127:65] + node _T_671 = bits(io.dcsr, 5, 2) @[el2_dec_tlu_ctl.scala 2127:92] + node _T_672 = cat(_T_671, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_673 = cat(_T_670, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 29:58] + node _T_675 = bits(wr_dcsr_r, 0, 0) @[el2_dec_tlu_ctl.scala 2128:19] + node _T_676 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 2128:50] + node _T_677 = bits(io.dec_csr_wrdata_r, 11, 10) @[el2_dec_tlu_ctl.scala 2128:85] + node _T_678 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2128:111] + node _T_679 = bits(io.dcsr, 3, 3) @[el2_dec_tlu_ctl.scala 2128:155] + node _T_680 = or(nmi_in_debug_mode, _T_679) @[el2_dec_tlu_ctl.scala 2128:146] + node _T_681 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2128:179] + node _T_682 = cat(_T_681, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_683 = cat(UInt<2>("h00"), _T_680) @[Cat.scala 29:58] + node _T_684 = cat(_T_683, _T_682) @[Cat.scala 29:58] + node _T_685 = cat(UInt<1>("h00"), _T_678) @[Cat.scala 29:58] + node _T_686 = cat(_T_676, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_677) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_685) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_684) @[Cat.scala 29:58] + node _T_690 = bits(io.dcsr, 15, 4) @[el2_dec_tlu_ctl.scala 2128:212] + node _T_691 = bits(io.dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 2128:246] + node _T_692 = cat(_T_691, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_693 = cat(_T_690, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58] + node _T_695 = mux(_T_675, _T_689, _T_694) @[el2_dec_tlu_ctl.scala 2128:8] + node dcsr_ns = mux(_T_669, _T_674, _T_695) @[el2_dec_tlu_ctl.scala 2127:20] + node _T_696 = or(enter_debug_halt_req_le, wr_dcsr_r) @[el2_dec_tlu_ctl.scala 2130:55] + node _T_697 = or(_T_696, io.internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 2130:67] + node _T_698 = or(_T_697, io.take_nmi) @[el2_dec_tlu_ctl.scala 2130:95] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_tlu_ctl.scala 2130:110] + inst rvclkhdr_17 of rvclkhdr_76 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_699 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_700 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_700 <= dcsr_ns @[el2_lib.scala 491:16] + io.dcsr <= _T_700 @[el2_dec_tlu_ctl.scala 2130:11] + node _T_701 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2138:46] + node _T_702 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2138:91] + node _T_703 = eq(_T_702, UInt<12>("h07b1")) @[el2_dec_tlu_ctl.scala 2138:98] + node wr_dpc_r = and(_T_701, _T_703) @[el2_dec_tlu_ctl.scala 2138:69] + node _T_704 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2139:45] + node _T_705 = and(io.dbg_tlu_halted, _T_704) @[el2_dec_tlu_ctl.scala 2139:43] + node _T_706 = not(io.request_debug_mode_done) @[el2_dec_tlu_ctl.scala 2139:68] + node dpc_capture_npc = and(_T_705, _T_706) @[el2_dec_tlu_ctl.scala 2139:66] + node _T_707 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2143:6] + node _T_708 = not(dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2143:24] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 2143:22] + node _T_710 = and(_T_709, wr_dpc_r) @[el2_dec_tlu_ctl.scala 2143:41] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_tlu_ctl.scala 2143:53] + node _T_712 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 2143:82] + node _T_713 = bits(io.request_debug_mode_r, 0, 0) @[el2_dec_tlu_ctl.scala 2144:22] + node _T_714 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2145:6] + node _T_715 = and(_T_714, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2145:22] + node _T_716 = bits(_T_715, 0, 0) @[el2_dec_tlu_ctl.scala 2145:41] + node _T_717 = mux(_T_711, _T_712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_718 = mux(_T_713, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_716, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = or(_T_717, _T_718) @[Mux.scala 27:72] + node _T_721 = or(_T_720, _T_719) @[Mux.scala 27:72] + wire dpc_ns : UInt<31> @[Mux.scala 27:72] + dpc_ns <= _T_721 @[Mux.scala 27:72] + node _T_722 = or(wr_dpc_r, io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2147:37] + node _T_723 = or(_T_722, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2147:54] + node _T_724 = bits(_T_723, 0, 0) @[el2_dec_tlu_ctl.scala 2147:73] + inst rvclkhdr_18 of rvclkhdr_77 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_724 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_725 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_725 <= dpc_ns @[el2_lib.scala 491:16] + io.dpc <= _T_725 @[el2_dec_tlu_ctl.scala 2147:10] + node _T_726 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 2161:44] + node _T_727 = bits(io.dec_csr_wrdata_r, 21, 20) @[el2_dec_tlu_ctl.scala 2161:69] + node _T_728 = bits(io.dec_csr_wrdata_r, 16, 3) @[el2_dec_tlu_ctl.scala 2161:97] + node _T_729 = cat(_T_726, _T_727) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_729, _T_728) @[Cat.scala 29:58] + node _T_730 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2162:51] + node _T_731 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2162:96] + node _T_732 = eq(_T_731, UInt<12>("h07c8")) @[el2_dec_tlu_ctl.scala 2162:103] + node wr_dicawics_r = and(_T_730, _T_732) @[el2_dec_tlu_ctl.scala 2162:74] + node _T_733 = bits(wr_dicawics_r, 0, 0) @[el2_dec_tlu_ctl.scala 2164:51] + inst rvclkhdr_19 of rvclkhdr_78 @[el2_lib.scala 485:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_19.io.en <= _T_733 @[el2_lib.scala 488:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicawics <= dicawics_ns @[el2_lib.scala 491:16] + node _T_734 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2180:49] + node _T_735 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2180:94] + node _T_736 = eq(_T_735, UInt<12>("h07c9")) @[el2_dec_tlu_ctl.scala 2180:101] + node wr_dicad0_r = and(_T_734, _T_736) @[el2_dec_tlu_ctl.scala 2180:72] + node _T_737 = bits(wr_dicad0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2181:35] + node dicad0_ns = mux(_T_737, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[el2_dec_tlu_ctl.scala 2181:22] + node _T_738 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2183:47] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_tlu_ctl.scala 2183:80] + inst rvclkhdr_20 of rvclkhdr_79 @[el2_lib.scala 485:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_20.io.en <= _T_739 @[el2_lib.scala 488:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicad0 <= dicad0_ns @[el2_lib.scala 491:16] + node _T_740 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2193:50] + node _T_741 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2193:95] + node _T_742 = eq(_T_741, UInt<12>("h07cc")) @[el2_dec_tlu_ctl.scala 2193:102] + node wr_dicad0h_r = and(_T_740, _T_742) @[el2_dec_tlu_ctl.scala 2193:73] + node _T_743 = bits(wr_dicad0h_r, 0, 0) @[el2_dec_tlu_ctl.scala 2195:37] + node _T_744 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[el2_dec_tlu_ctl.scala 2195:89] + node dicad0h_ns = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[el2_dec_tlu_ctl.scala 2195:23] + node _T_745 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2197:49] + node _T_746 = bits(_T_745, 0, 0) @[el2_dec_tlu_ctl.scala 2197:82] + inst rvclkhdr_21 of rvclkhdr_80 @[el2_lib.scala 485:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_21.io.en <= _T_746 @[el2_lib.scala 488:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicad0h <= dicad0h_ns @[el2_lib.scala 491:16] + wire _T_747 : UInt<7> + _T_747 <= UInt<1>("h00") + node _T_748 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2205:51] + node _T_749 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2205:96] + node _T_750 = eq(_T_749, UInt<12>("h07ca")) @[el2_dec_tlu_ctl.scala 2205:103] + node _T_751 = and(_T_748, _T_750) @[el2_dec_tlu_ctl.scala 2205:74] + node _T_752 = bits(_T_751, 0, 0) @[el2_dec_tlu_ctl.scala 2207:37] + node _T_753 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[el2_dec_tlu_ctl.scala 2207:89] + node _T_754 = mux(_T_752, io.dec_csr_wrdata_r, _T_753) @[el2_dec_tlu_ctl.scala 2207:24] + node _T_755 = or(_T_751, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2209:81] + node _T_756 = bits(_T_755, 0, 0) @[el2_dec_tlu_ctl.scala 2209:114] + reg _T_757 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_756 : @[Reg.scala 28:19] + _T_757 <= _T_754 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_747 <= _T_757 @[el2_dec_tlu_ctl.scala 2209:16] + node _T_758 = cat(UInt<25>("h00"), _T_747) @[Cat.scala 29:58] + dicad1 <= _T_758 @[el2_dec_tlu_ctl.scala 2210:12] + node _T_759 = bits(dicad1, 6, 0) @[el2_dec_tlu_ctl.scala 2232:78] + node _T_760 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2232:92] + node _T_761 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2232:106] + node _T_762 = cat(_T_759, _T_760) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_761) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_763 @[el2_dec_tlu_ctl.scala 2232:65] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[el2_dec_tlu_ctl.scala 2235:42] + node _T_764 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 2237:53] + node _T_765 = and(_T_764, io.dec_i0_decode_d) @[el2_dec_tlu_ctl.scala 2237:76] + node _T_766 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 2237:99] + node _T_767 = and(_T_765, _T_766) @[el2_dec_tlu_ctl.scala 2237:97] + node _T_768 = bits(io.dec_csr_rdaddr_d, 11, 0) @[el2_dec_tlu_ctl.scala 2237:143] + node _T_769 = eq(_T_768, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2237:150] + node icache_rd_valid = and(_T_767, _T_769) @[el2_dec_tlu_ctl.scala 2237:121] + node _T_770 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2238:53] + node _T_771 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2238:98] + node _T_772 = eq(_T_771, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2238:105] + node icache_wr_valid = and(_T_770, _T_772) @[el2_dec_tlu_ctl.scala 2238:76] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2240:59] + icache_rd_valid_f <= icache_rd_valid @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2241:59] + icache_wr_valid_f <= icache_wr_valid @[el2_dec_tlu_ctl.scala 2241:59] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[el2_dec_tlu_ctl.scala 2243:42] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[el2_dec_tlu_ctl.scala 2244:42] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2252:63] + node _T_774 = eq(_T_773, UInt<12>("h07a0")) @[el2_dec_tlu_ctl.scala 2252:70] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_774) @[el2_dec_tlu_ctl.scala 2252:41] + node _T_775 = bits(wr_mtsel_r, 0, 0) @[el2_dec_tlu_ctl.scala 2253:33] + node _T_776 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2253:60] + node mtsel_ns = mux(_T_775, _T_776, mtsel) @[el2_dec_tlu_ctl.scala 2253:21] + reg _T_777 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2255:44] + _T_777 <= mtsel_ns @[el2_dec_tlu_ctl.scala 2255:44] + mtsel <= _T_777 @[el2_dec_tlu_ctl.scala 2255:9] + node _T_778 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2290:39] + node _T_779 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2290:65] + node _T_780 = not(_T_779) @[el2_dec_tlu_ctl.scala 2290:45] + node tdata_load = and(_T_778, _T_780) @[el2_dec_tlu_ctl.scala 2290:43] + node _T_781 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2292:41] + node _T_782 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2292:67] + node _T_783 = not(_T_782) @[el2_dec_tlu_ctl.scala 2292:47] + node tdata_opcode = and(_T_781, _T_783) @[el2_dec_tlu_ctl.scala 2292:45] + node _T_784 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2294:42] + node _T_785 = and(_T_784, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2294:47] + node _T_786 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 2294:91] + node tdata_action = and(_T_785, _T_786) @[el2_dec_tlu_ctl.scala 2294:70] + node _T_787 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2296:48] + node _T_788 = and(_T_787, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2296:53] + node _T_789 = bits(io.dec_csr_wrdata_r, 20, 19) @[el2_dec_tlu_ctl.scala 2296:95] + node _T_790 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 2296:137] + node _T_791 = bits(io.dec_csr_wrdata_r, 7, 6) @[el2_dec_tlu_ctl.scala 2297:24] + node _T_792 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 2297:64] + node _T_793 = cat(_T_792, tdata_load) @[Cat.scala 29:58] + node _T_794 = cat(_T_791, tdata_opcode) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, _T_793) @[Cat.scala 29:58] + node _T_796 = cat(tdata_action, _T_790) @[Cat.scala 29:58] + node _T_797 = cat(_T_788, _T_789) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, _T_796) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_798, _T_795) @[Cat.scala 29:58] + node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_802 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_803 = and(_T_801, _T_802) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_804 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_805 = not(_T_804) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_807 = and(_T_803, _T_806) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_811 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_813 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_814 = not(_T_813) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_816 = and(_T_812, _T_815) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_820 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_821 = and(_T_819, _T_820) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_822 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_823 = not(_T_822) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_825 = and(_T_821, _T_824) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_826 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_827 = eq(_T_826, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_828 = and(io.dec_csr_wen_r_mod, _T_827) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_829 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_830 = and(_T_828, _T_829) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_831 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_832 = not(_T_831) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_833 = or(_T_832, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_834 = and(_T_830, _T_833) @[el2_dec_tlu_ctl.scala 2300:136] + wire wr_mtdata1_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[0] <= _T_807 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[1] <= _T_816 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[2] <= _T_825 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[3] <= _T_834 @[el2_dec_tlu_ctl.scala 2300:43] + node _T_835 = bits(wr_mtdata1_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_836 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_837 = bits(io.update_hit_bit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_838 = bits(io.mtdata1_t[0], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_839 = or(_T_837, _T_838) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_840 = bits(io.mtdata1_t[0], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] + node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] + node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_844 = bits(wr_mtdata1_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_845 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_846 = bits(io.update_hit_bit_r, 1, 1) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_847 = bits(io.mtdata1_t[1], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_848 = or(_T_846, _T_847) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_849 = bits(io.mtdata1_t[1], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] + node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] + node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_853 = bits(wr_mtdata1_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_854 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_855 = bits(io.update_hit_bit_r, 2, 2) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_856 = bits(io.mtdata1_t[2], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_857 = or(_T_855, _T_856) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_858 = bits(io.mtdata1_t[2], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] + node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] + node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_862 = bits(wr_mtdata1_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_863 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_864 = bits(io.update_hit_bit_r, 3, 3) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_865 = bits(io.mtdata1_t[3], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_866 = or(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_867 = bits(io.mtdata1_t[3], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_868 = cat(_T_863, _T_866) @[Cat.scala 29:58] + node _T_869 = cat(_T_868, _T_867) @[Cat.scala 29:58] + node _T_870 = mux(_T_862, tdata_wrdata_r, _T_869) @[el2_dec_tlu_ctl.scala 2301:50] + wire mtdata1_t_ns : UInt<10>[4] @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[0] <= _T_843 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[1] <= _T_852 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[2] <= _T_861 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[3] <= _T_870 @[el2_dec_tlu_ctl.scala 2301:41] + reg _T_871 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_871 <= mtdata1_t_ns[0] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[0] <= _T_871 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_872 <= mtdata1_t_ns[1] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[1] <= _T_872 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_873 <= mtdata1_t_ns[2] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[2] <= _T_873 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_874 <= mtdata1_t_ns[3] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[3] <= _T_874 @[el2_dec_tlu_ctl.scala 2303:41] + node _T_875 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_876 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_877 = bits(io.mtdata1_t[0], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_878 = bits(io.mtdata1_t[0], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_879 = bits(io.mtdata1_t[0], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_880 = bits(io.mtdata1_t[0], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_881 = cat(UInt<3>("h00"), _T_880) @[Cat.scala 29:58] + node _T_882 = cat(_T_878, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_883 = cat(_T_882, _T_879) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_881) @[Cat.scala 29:58] + node _T_885 = cat(_T_877, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_886 = cat(UInt<4>("h02"), _T_876) @[Cat.scala 29:58] + node _T_887 = cat(_T_886, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, _T_885) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_884) @[Cat.scala 29:58] + node _T_890 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_891 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_892 = bits(io.mtdata1_t[1], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_893 = bits(io.mtdata1_t[1], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_894 = bits(io.mtdata1_t[1], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_895 = bits(io.mtdata1_t[1], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_896 = cat(UInt<3>("h00"), _T_895) @[Cat.scala 29:58] + node _T_897 = cat(_T_893, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, _T_894) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_896) @[Cat.scala 29:58] + node _T_900 = cat(_T_892, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_901 = cat(UInt<4>("h02"), _T_891) @[Cat.scala 29:58] + node _T_902 = cat(_T_901, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, _T_900) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_899) @[Cat.scala 29:58] + node _T_905 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_906 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_907 = bits(io.mtdata1_t[2], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_908 = bits(io.mtdata1_t[2], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_909 = bits(io.mtdata1_t[2], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_910 = bits(io.mtdata1_t[2], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_911 = cat(UInt<3>("h00"), _T_910) @[Cat.scala 29:58] + node _T_912 = cat(_T_908, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_913 = cat(_T_912, _T_909) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_911) @[Cat.scala 29:58] + node _T_915 = cat(_T_907, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_916 = cat(UInt<4>("h02"), _T_906) @[Cat.scala 29:58] + node _T_917 = cat(_T_916, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, _T_915) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_914) @[Cat.scala 29:58] + node _T_920 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_921 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_922 = bits(io.mtdata1_t[3], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_923 = bits(io.mtdata1_t[3], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_924 = bits(io.mtdata1_t[3], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_925 = bits(io.mtdata1_t[3], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_926 = cat(UInt<3>("h00"), _T_925) @[Cat.scala 29:58] + node _T_927 = cat(_T_923, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_928 = cat(_T_927, _T_924) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_926) @[Cat.scala 29:58] + node _T_930 = cat(_T_922, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_931 = cat(UInt<4>("h02"), _T_921) @[Cat.scala 29:58] + node _T_932 = cat(_T_931, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_930) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_929) @[Cat.scala 29:58] + node _T_935 = mux(_T_875, _T_889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_936 = mux(_T_890, _T_904, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_905, _T_919, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_920, _T_934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = or(_T_935, _T_936) @[Mux.scala 27:72] + node _T_940 = or(_T_939, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] + node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[0].match_ <= _T_943 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[0].load <= _T_945 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_946 = bits(io.mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[0].execute <= _T_946 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_947 = bits(io.mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[1].match_ <= _T_949 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[1].load <= _T_951 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_952 = bits(io.mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[1].execute <= _T_952 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_953 = bits(io.mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[2].match_ <= _T_955 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[2].load <= _T_957 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_958 = bits(io.mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[2].execute <= _T_958 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_959 = bits(io.mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[3].match_ <= _T_961 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[3].load <= _T_963 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_964 = bits(io.mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[3].execute <= _T_964 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_965 = bits(io.mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[3].m <= _T_965 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_969 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_970 = and(_T_968, _T_969) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_971 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_972 = not(_T_971) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_974 = and(_T_970, _T_973) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_978 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_979 = and(_T_977, _T_978) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_980 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_981 = not(_T_980) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_983 = and(_T_979, _T_982) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_987 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_988 = and(_T_986, _T_987) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_989 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_990 = not(_T_989) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_992 = and(_T_988, _T_991) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_993 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_994 = eq(_T_993, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_995 = and(io.dec_csr_wen_r_mod, _T_994) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_996 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_997 = and(_T_995, _T_996) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_998 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_999 = not(_T_998) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_1000 = or(_T_999, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_1001 = and(_T_997, _T_1000) @[el2_dec_tlu_ctl.scala 2320:135] + wire wr_mtdata2_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[0] <= _T_974 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[1] <= _T_983 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[2] <= _T_992 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[3] <= _T_1001 @[el2_dec_tlu_ctl.scala 2320:43] + node _T_1002 = bits(wr_mtdata2_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_22 of rvclkhdr_81 @[el2_lib.scala 485:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_22.io.en <= _T_1002 @[el2_lib.scala 488:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1003 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1003 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[0] <= _T_1003 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1004 = bits(wr_mtdata2_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_23 of rvclkhdr_82 @[el2_lib.scala 485:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_23.io.en <= _T_1004 @[el2_lib.scala 488:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1005 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1005 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[1] <= _T_1005 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1006 = bits(wr_mtdata2_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_24 of rvclkhdr_83 @[el2_lib.scala 485:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_24.io.en <= _T_1006 @[el2_lib.scala 488:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1007 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1007 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[2] <= _T_1007 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1008 = bits(wr_mtdata2_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_25 of rvclkhdr_84 @[el2_lib.scala 485:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_25.io.en <= _T_1008 @[el2_lib.scala 488:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1009 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1009 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[3] <= _T_1009 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1010 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1011 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1012 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1013 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1014 = mux(_T_1010, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1015 = mux(_T_1011, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = or(_T_1014, _T_1015) @[Mux.scala 27:72] + node _T_1019 = or(_T_1018, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1020 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[el2_dec_tlu_ctl.scala 2326:53] + mhpme_vec[0] <= mhpme3 @[el2_dec_tlu_ctl.scala 2336:16] + mhpme_vec[1] <= mhpme4 @[el2_dec_tlu_ctl.scala 2337:16] + mhpme_vec[2] <= mhpme5 @[el2_dec_tlu_ctl.scala 2338:16] + mhpme_vec[3] <= mhpme6 @[el2_dec_tlu_ctl.scala 2339:16] + node _T_1021 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1022 = mux(_T_1021, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1022) @[el2_dec_tlu_ctl.scala 2345:60] + wire mhpmc_inc_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2346:25] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2347:28] + node _T_1023 = bits(mcountinhibit, 3, 3) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1024 = not(_T_1023) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1025 = eq(mhpme_vec[0], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1026 = bits(_T_1025, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1027 = eq(mhpme_vec[0], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1028 = bits(_T_1027, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1030 = bits(_T_1029, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1031 = eq(mhpme_vec[0], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1032 = bits(_T_1031, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1033 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1034 = and(io.tlu_i0_commit_cmt, _T_1033) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1035 = eq(mhpme_vec[0], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1036 = bits(_T_1035, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1037 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1038 = and(io.tlu_i0_commit_cmt, _T_1037) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1039 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1040 = and(_T_1038, _T_1039) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1041 = eq(mhpme_vec[0], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1042 = bits(_T_1041, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1043 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1044 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1045 = and(_T_1043, _T_1044) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1046 = eq(mhpme_vec[0], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1047 = bits(_T_1046, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1048 = eq(mhpme_vec[0], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1049 = bits(_T_1048, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1050 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1051 = bits(_T_1050, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1052 = eq(mhpme_vec[0], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1053 = bits(_T_1052, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1056 = bits(_T_1055, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1057 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1058 = eq(mhpme_vec[0], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1059 = bits(_T_1058, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1060 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1062 = bits(_T_1061, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1065 = bits(_T_1064, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1067 = eq(mhpme_vec[0], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1068 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1067) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1069 = bits(_T_1068, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1070 = and(_T_1066, _T_1069) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1072 = and(_T_1070, _T_1071) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1074 = and(_T_1072, _T_1073) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1076 = bits(_T_1075, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1079 = bits(_T_1078, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1082 = bits(_T_1081, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1085 = bits(_T_1084, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1088 = bits(_T_1087, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1091 = bits(_T_1090, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1094 = bits(_T_1093, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1097 = bits(_T_1096, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1100 = bits(_T_1099, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1103 = bits(_T_1102, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1106 = or(_T_1104, _T_1105) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1108 = bits(_T_1107, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1111 = bits(_T_1110, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1114 = bits(_T_1113, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1117 = bits(_T_1116, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1119 = bits(_T_1118, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1121 = bits(_T_1120, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1123 = bits(_T_1122, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1125 = bits(_T_1124, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1127 = bits(_T_1126, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1129 = bits(_T_1128, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1131 = bits(_T_1130, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1135 = bits(_T_1134, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1139 = bits(_T_1138, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1141 = bits(_T_1140, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1143 = bits(_T_1142, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1147 = bits(_T_1146, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1149 = bits(_T_1148, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1151 = bits(_T_1150, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1153 = bits(_T_1152, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1155 = bits(_T_1154, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1157 = bits(_T_1156, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1159 = bits(_T_1158, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1161 = bits(_T_1160, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1163 = bits(_T_1162, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1164 = not(_T_1163) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1166 = bits(_T_1165, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1168 = bits(_T_1167, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1169 = not(_T_1168) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1170 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1171 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1172 = and(_T_1170, _T_1171) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1173 = and(_T_1169, _T_1172) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1175 = bits(_T_1174, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1178 = bits(_T_1177, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1181 = bits(_T_1180, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1184 = bits(_T_1183, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1186 = bits(_T_1185, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1188 = bits(_T_1187, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1190 = bits(_T_1189, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1192 = bits(_T_1191, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1193 = mux(_T_1026, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1028, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, _T_1034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1036, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1042, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1047, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1056, _T_1057, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1059, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1062, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1065, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1166, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1195) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1196) @[Mux.scala 27:72] + node _T_1252 = or(_T_1251, _T_1197) @[Mux.scala 27:72] + node _T_1253 = or(_T_1252, _T_1198) @[Mux.scala 27:72] + node _T_1254 = or(_T_1253, _T_1199) @[Mux.scala 27:72] + node _T_1255 = or(_T_1254, _T_1200) @[Mux.scala 27:72] + node _T_1256 = or(_T_1255, _T_1201) @[Mux.scala 27:72] + node _T_1257 = or(_T_1256, _T_1202) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1203) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1204) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1205) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1206) @[Mux.scala 27:72] + node _T_1262 = or(_T_1261, _T_1207) @[Mux.scala 27:72] + node _T_1263 = or(_T_1262, _T_1208) @[Mux.scala 27:72] + node _T_1264 = or(_T_1263, _T_1209) @[Mux.scala 27:72] + node _T_1265 = or(_T_1264, _T_1210) @[Mux.scala 27:72] + node _T_1266 = or(_T_1265, _T_1211) @[Mux.scala 27:72] + node _T_1267 = or(_T_1266, _T_1212) @[Mux.scala 27:72] + node _T_1268 = or(_T_1267, _T_1213) @[Mux.scala 27:72] + node _T_1269 = or(_T_1268, _T_1214) @[Mux.scala 27:72] + node _T_1270 = or(_T_1269, _T_1215) @[Mux.scala 27:72] + node _T_1271 = or(_T_1270, _T_1216) @[Mux.scala 27:72] + node _T_1272 = or(_T_1271, _T_1217) @[Mux.scala 27:72] + node _T_1273 = or(_T_1272, _T_1218) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1219) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1220) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1221) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1222) @[Mux.scala 27:72] + node _T_1278 = or(_T_1277, _T_1223) @[Mux.scala 27:72] + node _T_1279 = or(_T_1278, _T_1224) @[Mux.scala 27:72] + node _T_1280 = or(_T_1279, _T_1225) @[Mux.scala 27:72] + node _T_1281 = or(_T_1280, _T_1226) @[Mux.scala 27:72] + node _T_1282 = or(_T_1281, _T_1227) @[Mux.scala 27:72] + node _T_1283 = or(_T_1282, _T_1228) @[Mux.scala 27:72] + node _T_1284 = or(_T_1283, _T_1229) @[Mux.scala 27:72] + node _T_1285 = or(_T_1284, _T_1230) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1231) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1232) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1233) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1234) @[Mux.scala 27:72] + node _T_1290 = or(_T_1289, _T_1235) @[Mux.scala 27:72] + node _T_1291 = or(_T_1290, _T_1236) @[Mux.scala 27:72] + node _T_1292 = or(_T_1291, _T_1237) @[Mux.scala 27:72] + node _T_1293 = or(_T_1292, _T_1238) @[Mux.scala 27:72] + node _T_1294 = or(_T_1293, _T_1239) @[Mux.scala 27:72] + node _T_1295 = or(_T_1294, _T_1240) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1241) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1242) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1243) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1244) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1245) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1246) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1247) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1248) @[Mux.scala 27:72] + wire _T_1304 : UInt<6> @[Mux.scala 27:72] + _T_1304 <= _T_1303 @[Mux.scala 27:72] + node _T_1305 = and(_T_1024, _T_1304) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[0] <= _T_1305 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1306 = bits(mcountinhibit, 4, 4) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1307 = not(_T_1306) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1308 = eq(mhpme_vec[1], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1309 = bits(_T_1308, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1310 = eq(mhpme_vec[1], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1311 = bits(_T_1310, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1313 = bits(_T_1312, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1314 = eq(mhpme_vec[1], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1315 = bits(_T_1314, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1316 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1317 = and(io.tlu_i0_commit_cmt, _T_1316) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1318 = eq(mhpme_vec[1], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1319 = bits(_T_1318, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1320 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1321 = and(io.tlu_i0_commit_cmt, _T_1320) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1322 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1323 = and(_T_1321, _T_1322) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1324 = eq(mhpme_vec[1], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1325 = bits(_T_1324, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1326 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1327 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1328 = and(_T_1326, _T_1327) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1329 = eq(mhpme_vec[1], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1330 = bits(_T_1329, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1331 = eq(mhpme_vec[1], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1332 = bits(_T_1331, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1333 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1334 = bits(_T_1333, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1335 = eq(mhpme_vec[1], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1336 = bits(_T_1335, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1339 = bits(_T_1338, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1340 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1342 = bits(_T_1341, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1345 = bits(_T_1344, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1348 = bits(_T_1347, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1351 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1350) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1352 = bits(_T_1351, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1353 = and(_T_1349, _T_1352) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1355 = and(_T_1353, _T_1354) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1357 = and(_T_1355, _T_1356) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1359 = bits(_T_1358, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1362 = bits(_T_1361, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1365 = bits(_T_1364, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1368 = bits(_T_1367, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1371 = bits(_T_1370, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1377 = bits(_T_1376, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1380 = bits(_T_1379, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1383 = bits(_T_1382, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1386 = bits(_T_1385, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1389 = or(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1391 = bits(_T_1390, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1394 = bits(_T_1393, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1397 = bits(_T_1396, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1400 = bits(_T_1399, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1402 = bits(_T_1401, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1404 = bits(_T_1403, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1406 = bits(_T_1405, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1408 = bits(_T_1407, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1410 = bits(_T_1409, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1412 = bits(_T_1411, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1414 = bits(_T_1413, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1418 = bits(_T_1417, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1422 = bits(_T_1421, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1424 = bits(_T_1423, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1426 = bits(_T_1425, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1430 = bits(_T_1429, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1432 = bits(_T_1431, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1434 = bits(_T_1433, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1436 = bits(_T_1435, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1438 = bits(_T_1437, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1440 = bits(_T_1439, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1442 = bits(_T_1441, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1444 = bits(_T_1443, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1446 = bits(_T_1445, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1447 = not(_T_1446) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1449 = bits(_T_1448, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1451 = bits(_T_1450, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1452 = not(_T_1451) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1453 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1454 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1455 = and(_T_1453, _T_1454) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1456 = and(_T_1452, _T_1455) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1457 = eq(mhpme_vec[1], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1458 = bits(_T_1457, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1459 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1460 = eq(mhpme_vec[1], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1461 = bits(_T_1460, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1462 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1463 = eq(mhpme_vec[1], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1465 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1467 = bits(_T_1466, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1469 = bits(_T_1468, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1471 = bits(_T_1470, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1473 = bits(_T_1472, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1475 = bits(_T_1474, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1476 = mux(_T_1309, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1311, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1319, _T_1323, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1325, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1330, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1348, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1449, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1458, _T_1459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1461, _T_1462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1464, _T_1465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1467, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1469, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1471, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1473, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1475, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = or(_T_1476, _T_1477) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1478) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1479) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1480) @[Mux.scala 27:72] + node _T_1536 = or(_T_1535, _T_1481) @[Mux.scala 27:72] + node _T_1537 = or(_T_1536, _T_1482) @[Mux.scala 27:72] + node _T_1538 = or(_T_1537, _T_1483) @[Mux.scala 27:72] + node _T_1539 = or(_T_1538, _T_1484) @[Mux.scala 27:72] + node _T_1540 = or(_T_1539, _T_1485) @[Mux.scala 27:72] + node _T_1541 = or(_T_1540, _T_1486) @[Mux.scala 27:72] + node _T_1542 = or(_T_1541, _T_1487) @[Mux.scala 27:72] + node _T_1543 = or(_T_1542, _T_1488) @[Mux.scala 27:72] + node _T_1544 = or(_T_1543, _T_1489) @[Mux.scala 27:72] + node _T_1545 = or(_T_1544, _T_1490) @[Mux.scala 27:72] + node _T_1546 = or(_T_1545, _T_1491) @[Mux.scala 27:72] + node _T_1547 = or(_T_1546, _T_1492) @[Mux.scala 27:72] + node _T_1548 = or(_T_1547, _T_1493) @[Mux.scala 27:72] + node _T_1549 = or(_T_1548, _T_1494) @[Mux.scala 27:72] + node _T_1550 = or(_T_1549, _T_1495) @[Mux.scala 27:72] + node _T_1551 = or(_T_1550, _T_1496) @[Mux.scala 27:72] + node _T_1552 = or(_T_1551, _T_1497) @[Mux.scala 27:72] + node _T_1553 = or(_T_1552, _T_1498) @[Mux.scala 27:72] + node _T_1554 = or(_T_1553, _T_1499) @[Mux.scala 27:72] + node _T_1555 = or(_T_1554, _T_1500) @[Mux.scala 27:72] + node _T_1556 = or(_T_1555, _T_1501) @[Mux.scala 27:72] + node _T_1557 = or(_T_1556, _T_1502) @[Mux.scala 27:72] + node _T_1558 = or(_T_1557, _T_1503) @[Mux.scala 27:72] + node _T_1559 = or(_T_1558, _T_1504) @[Mux.scala 27:72] + node _T_1560 = or(_T_1559, _T_1505) @[Mux.scala 27:72] + node _T_1561 = or(_T_1560, _T_1506) @[Mux.scala 27:72] + node _T_1562 = or(_T_1561, _T_1507) @[Mux.scala 27:72] + node _T_1563 = or(_T_1562, _T_1508) @[Mux.scala 27:72] + node _T_1564 = or(_T_1563, _T_1509) @[Mux.scala 27:72] + node _T_1565 = or(_T_1564, _T_1510) @[Mux.scala 27:72] + node _T_1566 = or(_T_1565, _T_1511) @[Mux.scala 27:72] + node _T_1567 = or(_T_1566, _T_1512) @[Mux.scala 27:72] + node _T_1568 = or(_T_1567, _T_1513) @[Mux.scala 27:72] + node _T_1569 = or(_T_1568, _T_1514) @[Mux.scala 27:72] + node _T_1570 = or(_T_1569, _T_1515) @[Mux.scala 27:72] + node _T_1571 = or(_T_1570, _T_1516) @[Mux.scala 27:72] + node _T_1572 = or(_T_1571, _T_1517) @[Mux.scala 27:72] + node _T_1573 = or(_T_1572, _T_1518) @[Mux.scala 27:72] + node _T_1574 = or(_T_1573, _T_1519) @[Mux.scala 27:72] + node _T_1575 = or(_T_1574, _T_1520) @[Mux.scala 27:72] + node _T_1576 = or(_T_1575, _T_1521) @[Mux.scala 27:72] + node _T_1577 = or(_T_1576, _T_1522) @[Mux.scala 27:72] + node _T_1578 = or(_T_1577, _T_1523) @[Mux.scala 27:72] + node _T_1579 = or(_T_1578, _T_1524) @[Mux.scala 27:72] + node _T_1580 = or(_T_1579, _T_1525) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1526) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1527) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1528) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1529) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1530) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1531) @[Mux.scala 27:72] + wire _T_1587 : UInt<6> @[Mux.scala 27:72] + _T_1587 <= _T_1586 @[Mux.scala 27:72] + node _T_1588 = and(_T_1307, _T_1587) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[1] <= _T_1588 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1589 = bits(mcountinhibit, 5, 5) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1590 = not(_T_1589) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1591 = eq(mhpme_vec[2], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1592 = bits(_T_1591, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1593 = eq(mhpme_vec[2], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1594 = bits(_T_1593, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1595 = eq(mhpme_vec[2], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1596 = bits(_T_1595, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1597 = eq(mhpme_vec[2], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1598 = bits(_T_1597, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1599 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1600 = and(io.tlu_i0_commit_cmt, _T_1599) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1602 = bits(_T_1601, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1603 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1605 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1606 = and(_T_1604, _T_1605) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1607 = eq(mhpme_vec[2], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1608 = bits(_T_1607, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1609 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1610 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1611 = and(_T_1609, _T_1610) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1612 = eq(mhpme_vec[2], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1613 = bits(_T_1612, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1614 = eq(mhpme_vec[2], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1615 = bits(_T_1614, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1616 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1617 = bits(_T_1616, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1619 = bits(_T_1618, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1622 = bits(_T_1621, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1623 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1625 = bits(_T_1624, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1628 = bits(_T_1627, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1631 = bits(_T_1630, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1634 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1633) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1635 = bits(_T_1634, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1636 = and(_T_1632, _T_1635) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1638 = and(_T_1636, _T_1637) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1639 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1640 = and(_T_1638, _T_1639) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1641 = eq(mhpme_vec[2], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1642 = bits(_T_1641, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1644 = eq(mhpme_vec[2], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1645 = bits(_T_1644, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1647 = eq(mhpme_vec[2], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1648 = bits(_T_1647, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1650 = eq(mhpme_vec[2], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1651 = bits(_T_1650, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1653 = eq(mhpme_vec[2], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1654 = bits(_T_1653, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1656 = eq(mhpme_vec[2], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1657 = bits(_T_1656, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1659 = eq(mhpme_vec[2], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1660 = bits(_T_1659, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1662 = eq(mhpme_vec[2], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1663 = bits(_T_1662, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1665 = eq(mhpme_vec[2], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1666 = bits(_T_1665, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1667 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1668 = eq(mhpme_vec[2], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1669 = bits(_T_1668, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1670 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1672 = or(_T_1670, _T_1671) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1673 = eq(mhpme_vec[2], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1674 = bits(_T_1673, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1675 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1677 = bits(_T_1676, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1678 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1680 = bits(_T_1679, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1681 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1682 = eq(mhpme_vec[2], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1683 = bits(_T_1682, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1685 = bits(_T_1684, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1687 = bits(_T_1686, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1688 = eq(mhpme_vec[2], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1689 = bits(_T_1688, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1691 = bits(_T_1690, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1693 = bits(_T_1692, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1695 = bits(_T_1694, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1697 = bits(_T_1696, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1698 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1699 = or(_T_1698, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1700 = eq(mhpme_vec[2], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1701 = bits(_T_1700, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1702 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1703 = or(_T_1702, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1704 = eq(mhpme_vec[2], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1705 = bits(_T_1704, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1707 = bits(_T_1706, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1709 = bits(_T_1708, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1710 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1711 = and(_T_1710, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1713 = bits(_T_1712, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1715 = bits(_T_1714, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1717 = bits(_T_1716, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1719 = bits(_T_1718, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1721 = bits(_T_1720, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1723 = bits(_T_1722, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1725 = bits(_T_1724, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1727 = bits(_T_1726, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1728 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1729 = bits(_T_1728, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1730 = not(_T_1729) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1731 = eq(mhpme_vec[2], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1732 = bits(_T_1731, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1733 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1734 = bits(_T_1733, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1735 = not(_T_1734) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1736 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1737 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1738 = and(_T_1736, _T_1737) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1739 = and(_T_1735, _T_1738) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1740 = eq(mhpme_vec[2], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1741 = bits(_T_1740, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1742 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1744 = bits(_T_1743, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1745 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1747 = bits(_T_1746, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1750 = bits(_T_1749, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1752 = bits(_T_1751, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1754 = bits(_T_1753, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1756 = bits(_T_1755, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1758 = bits(_T_1757, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1759 = mux(_T_1592, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1594, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1596, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1598, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1602, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1608, _T_1611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1613, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1615, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1617, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1631, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1660, _T_1661, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1669, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1674, _T_1675, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1680, _T_1681, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1683, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1685, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1687, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1689, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1691, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1693, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1695, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1697, _T_1699, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1705, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1707, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1709, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1713, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1715, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1717, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1719, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1721, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1723, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1725, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1727, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1732, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1750, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1752, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1754, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1756, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1758, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = or(_T_1759, _T_1760) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1761) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1762) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1763) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1764) @[Mux.scala 27:72] + node _T_1820 = or(_T_1819, _T_1765) @[Mux.scala 27:72] + node _T_1821 = or(_T_1820, _T_1766) @[Mux.scala 27:72] + node _T_1822 = or(_T_1821, _T_1767) @[Mux.scala 27:72] + node _T_1823 = or(_T_1822, _T_1768) @[Mux.scala 27:72] + node _T_1824 = or(_T_1823, _T_1769) @[Mux.scala 27:72] + node _T_1825 = or(_T_1824, _T_1770) @[Mux.scala 27:72] + node _T_1826 = or(_T_1825, _T_1771) @[Mux.scala 27:72] + node _T_1827 = or(_T_1826, _T_1772) @[Mux.scala 27:72] + node _T_1828 = or(_T_1827, _T_1773) @[Mux.scala 27:72] + node _T_1829 = or(_T_1828, _T_1774) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1775) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1776) @[Mux.scala 27:72] + node _T_1832 = or(_T_1831, _T_1777) @[Mux.scala 27:72] + node _T_1833 = or(_T_1832, _T_1778) @[Mux.scala 27:72] + node _T_1834 = or(_T_1833, _T_1779) @[Mux.scala 27:72] + node _T_1835 = or(_T_1834, _T_1780) @[Mux.scala 27:72] + node _T_1836 = or(_T_1835, _T_1781) @[Mux.scala 27:72] + node _T_1837 = or(_T_1836, _T_1782) @[Mux.scala 27:72] + node _T_1838 = or(_T_1837, _T_1783) @[Mux.scala 27:72] + node _T_1839 = or(_T_1838, _T_1784) @[Mux.scala 27:72] + node _T_1840 = or(_T_1839, _T_1785) @[Mux.scala 27:72] + node _T_1841 = or(_T_1840, _T_1786) @[Mux.scala 27:72] + node _T_1842 = or(_T_1841, _T_1787) @[Mux.scala 27:72] + node _T_1843 = or(_T_1842, _T_1788) @[Mux.scala 27:72] + node _T_1844 = or(_T_1843, _T_1789) @[Mux.scala 27:72] + node _T_1845 = or(_T_1844, _T_1790) @[Mux.scala 27:72] + node _T_1846 = or(_T_1845, _T_1791) @[Mux.scala 27:72] + node _T_1847 = or(_T_1846, _T_1792) @[Mux.scala 27:72] + node _T_1848 = or(_T_1847, _T_1793) @[Mux.scala 27:72] + node _T_1849 = or(_T_1848, _T_1794) @[Mux.scala 27:72] + node _T_1850 = or(_T_1849, _T_1795) @[Mux.scala 27:72] + node _T_1851 = or(_T_1850, _T_1796) @[Mux.scala 27:72] + node _T_1852 = or(_T_1851, _T_1797) @[Mux.scala 27:72] + node _T_1853 = or(_T_1852, _T_1798) @[Mux.scala 27:72] + node _T_1854 = or(_T_1853, _T_1799) @[Mux.scala 27:72] + node _T_1855 = or(_T_1854, _T_1800) @[Mux.scala 27:72] + node _T_1856 = or(_T_1855, _T_1801) @[Mux.scala 27:72] + node _T_1857 = or(_T_1856, _T_1802) @[Mux.scala 27:72] + node _T_1858 = or(_T_1857, _T_1803) @[Mux.scala 27:72] + node _T_1859 = or(_T_1858, _T_1804) @[Mux.scala 27:72] + node _T_1860 = or(_T_1859, _T_1805) @[Mux.scala 27:72] + node _T_1861 = or(_T_1860, _T_1806) @[Mux.scala 27:72] + node _T_1862 = or(_T_1861, _T_1807) @[Mux.scala 27:72] + node _T_1863 = or(_T_1862, _T_1808) @[Mux.scala 27:72] + node _T_1864 = or(_T_1863, _T_1809) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1810) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1811) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1812) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1813) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1814) @[Mux.scala 27:72] + wire _T_1870 : UInt<6> @[Mux.scala 27:72] + _T_1870 <= _T_1869 @[Mux.scala 27:72] + node _T_1871 = and(_T_1590, _T_1870) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[2] <= _T_1871 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1872 = bits(mcountinhibit, 6, 6) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1873 = not(_T_1872) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1874 = eq(mhpme_vec[3], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1875 = bits(_T_1874, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1876 = eq(mhpme_vec[3], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1877 = bits(_T_1876, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1878 = eq(mhpme_vec[3], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1879 = bits(_T_1878, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1880 = eq(mhpme_vec[3], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1881 = bits(_T_1880, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1882 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1885 = bits(_T_1884, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1886 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1888 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1889 = and(_T_1887, _T_1888) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1890 = eq(mhpme_vec[3], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1891 = bits(_T_1890, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1892 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1893 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1894 = and(_T_1892, _T_1893) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1896 = bits(_T_1895, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1897 = eq(mhpme_vec[3], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1898 = bits(_T_1897, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1899 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1900 = bits(_T_1899, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1902 = bits(_T_1901, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1905 = bits(_T_1904, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1906 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1908 = bits(_T_1907, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1910 = eq(mhpme_vec[3], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1911 = bits(_T_1910, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1912 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1914 = bits(_T_1913, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1917 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1916) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1918 = bits(_T_1917, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1919 = and(_T_1915, _T_1918) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1921 = and(_T_1919, _T_1920) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1922 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1923 = and(_T_1921, _T_1922) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1924 = eq(mhpme_vec[3], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1925 = bits(_T_1924, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1927 = eq(mhpme_vec[3], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1928 = bits(_T_1927, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1931 = bits(_T_1930, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1934 = bits(_T_1933, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1937 = bits(_T_1936, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1940 = bits(_T_1939, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1943 = bits(_T_1942, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1946 = bits(_T_1945, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1949 = bits(_T_1948, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1952 = bits(_T_1951, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1954 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1955 = or(_T_1953, _T_1954) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1956 = eq(mhpme_vec[3], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1957 = bits(_T_1956, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1958 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1960 = bits(_T_1959, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1961 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1963 = bits(_T_1962, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1964 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1966 = bits(_T_1965, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1968 = bits(_T_1967, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1970 = bits(_T_1969, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1972 = bits(_T_1971, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1974 = bits(_T_1973, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1976 = bits(_T_1975, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1978 = bits(_T_1977, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1980 = bits(_T_1979, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1981 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1982 = or(_T_1981, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1984 = bits(_T_1983, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1985 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1986 = or(_T_1985, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1987 = eq(mhpme_vec[3], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1988 = bits(_T_1987, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1990 = bits(_T_1989, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1992 = bits(_T_1991, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1993 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1994 = and(_T_1993, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1996 = bits(_T_1995, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1998 = bits(_T_1997, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_2000 = bits(_T_1999, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_2002 = bits(_T_2001, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_2004 = bits(_T_2003, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_2006 = bits(_T_2005, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_2008 = bits(_T_2007, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_2010 = bits(_T_2009, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_2011 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2012 = bits(_T_2011, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2013 = not(_T_2012) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_2014 = eq(mhpme_vec[3], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_2015 = bits(_T_2014, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_2016 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2017 = bits(_T_2016, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2018 = not(_T_2017) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_2019 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_2020 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_2021 = and(_T_2019, _T_2020) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_2022 = and(_T_2018, _T_2021) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_2023 = eq(mhpme_vec[3], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_2024 = bits(_T_2023, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_2025 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_2027 = bits(_T_2026, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_2028 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_2030 = bits(_T_2029, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_2033 = bits(_T_2032, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_2035 = bits(_T_2034, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_2037 = bits(_T_2036, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_2039 = bits(_T_2038, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_2041 = bits(_T_2040, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_2042 = mux(_T_1875, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1877, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1879, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1881, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1885, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1891, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1896, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1898, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1900, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1914, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1952, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1966, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1968, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1970, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1972, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1974, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1976, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1978, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1980, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1988, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1990, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1992, _T_1994, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1996, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1998, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2000, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2002, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2004, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2006, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2008, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2010, _T_2013, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2015, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2033, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2035, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2037, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2039, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2041, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = or(_T_2042, _T_2043) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2044) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2045) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2046) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2047) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2048) @[Mux.scala 27:72] + node _T_2104 = or(_T_2103, _T_2049) @[Mux.scala 27:72] + node _T_2105 = or(_T_2104, _T_2050) @[Mux.scala 27:72] + node _T_2106 = or(_T_2105, _T_2051) @[Mux.scala 27:72] + node _T_2107 = or(_T_2106, _T_2052) @[Mux.scala 27:72] + node _T_2108 = or(_T_2107, _T_2053) @[Mux.scala 27:72] + node _T_2109 = or(_T_2108, _T_2054) @[Mux.scala 27:72] + node _T_2110 = or(_T_2109, _T_2055) @[Mux.scala 27:72] + node _T_2111 = or(_T_2110, _T_2056) @[Mux.scala 27:72] + node _T_2112 = or(_T_2111, _T_2057) @[Mux.scala 27:72] + node _T_2113 = or(_T_2112, _T_2058) @[Mux.scala 27:72] + node _T_2114 = or(_T_2113, _T_2059) @[Mux.scala 27:72] + node _T_2115 = or(_T_2114, _T_2060) @[Mux.scala 27:72] + node _T_2116 = or(_T_2115, _T_2061) @[Mux.scala 27:72] + node _T_2117 = or(_T_2116, _T_2062) @[Mux.scala 27:72] + node _T_2118 = or(_T_2117, _T_2063) @[Mux.scala 27:72] + node _T_2119 = or(_T_2118, _T_2064) @[Mux.scala 27:72] + node _T_2120 = or(_T_2119, _T_2065) @[Mux.scala 27:72] + node _T_2121 = or(_T_2120, _T_2066) @[Mux.scala 27:72] + node _T_2122 = or(_T_2121, _T_2067) @[Mux.scala 27:72] + node _T_2123 = or(_T_2122, _T_2068) @[Mux.scala 27:72] + node _T_2124 = or(_T_2123, _T_2069) @[Mux.scala 27:72] + node _T_2125 = or(_T_2124, _T_2070) @[Mux.scala 27:72] + node _T_2126 = or(_T_2125, _T_2071) @[Mux.scala 27:72] + node _T_2127 = or(_T_2126, _T_2072) @[Mux.scala 27:72] + node _T_2128 = or(_T_2127, _T_2073) @[Mux.scala 27:72] + node _T_2129 = or(_T_2128, _T_2074) @[Mux.scala 27:72] + node _T_2130 = or(_T_2129, _T_2075) @[Mux.scala 27:72] + node _T_2131 = or(_T_2130, _T_2076) @[Mux.scala 27:72] + node _T_2132 = or(_T_2131, _T_2077) @[Mux.scala 27:72] + node _T_2133 = or(_T_2132, _T_2078) @[Mux.scala 27:72] + node _T_2134 = or(_T_2133, _T_2079) @[Mux.scala 27:72] + node _T_2135 = or(_T_2134, _T_2080) @[Mux.scala 27:72] + node _T_2136 = or(_T_2135, _T_2081) @[Mux.scala 27:72] + node _T_2137 = or(_T_2136, _T_2082) @[Mux.scala 27:72] + node _T_2138 = or(_T_2137, _T_2083) @[Mux.scala 27:72] + node _T_2139 = or(_T_2138, _T_2084) @[Mux.scala 27:72] + node _T_2140 = or(_T_2139, _T_2085) @[Mux.scala 27:72] + node _T_2141 = or(_T_2140, _T_2086) @[Mux.scala 27:72] + node _T_2142 = or(_T_2141, _T_2087) @[Mux.scala 27:72] + node _T_2143 = or(_T_2142, _T_2088) @[Mux.scala 27:72] + node _T_2144 = or(_T_2143, _T_2089) @[Mux.scala 27:72] + node _T_2145 = or(_T_2144, _T_2090) @[Mux.scala 27:72] + node _T_2146 = or(_T_2145, _T_2091) @[Mux.scala 27:72] + node _T_2147 = or(_T_2146, _T_2092) @[Mux.scala 27:72] + node _T_2148 = or(_T_2147, _T_2093) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2094) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2095) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2096) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2097) @[Mux.scala 27:72] + wire _T_2153 : UInt<6> @[Mux.scala 27:72] + _T_2153 <= _T_2152 @[Mux.scala 27:72] + node _T_2154 = and(_T_1873, _T_2153) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[3] <= _T_2154 @[el2_dec_tlu_ctl.scala 2351:20] + reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2413:54] + _T_2155 <= mhpmc_inc_r[0] @[el2_dec_tlu_ctl.scala 2413:54] + mhpmc_inc_r_d1[0] <= _T_2155 @[el2_dec_tlu_ctl.scala 2413:21] + reg _T_2156 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2414:54] + _T_2156 <= mhpmc_inc_r[1] @[el2_dec_tlu_ctl.scala 2414:54] + mhpmc_inc_r_d1[1] <= _T_2156 @[el2_dec_tlu_ctl.scala 2414:21] + reg _T_2157 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2415:54] + _T_2157 <= mhpmc_inc_r[2] @[el2_dec_tlu_ctl.scala 2415:54] + mhpmc_inc_r_d1[2] <= _T_2157 @[el2_dec_tlu_ctl.scala 2415:21] + reg _T_2158 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2416:54] + _T_2158 <= mhpmc_inc_r[3] @[el2_dec_tlu_ctl.scala 2416:54] + mhpmc_inc_r_d1[3] <= _T_2158 @[el2_dec_tlu_ctl.scala 2416:21] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2417:57] + perfcnt_halted_d1 <= perfcnt_halted @[el2_dec_tlu_ctl.scala 2417:57] + node _T_2159 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2420:54] + node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[el2_dec_tlu_ctl.scala 2420:45] + node _T_2161 = or(_T_2160, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2420:68] + perfcnt_halted <= _T_2161 @[el2_dec_tlu_ctl.scala 2420:18] + node _T_2162 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2421:71] + node _T_2163 = and(io.dec_tlu_dbg_halted, _T_2162) @[el2_dec_tlu_ctl.scala 2421:62] + node _T_2164 = not(_T_2163) @[el2_dec_tlu_ctl.scala 2421:38] + node _T_2165 = bits(_T_2164, 0, 0) @[Bitwise.scala 72:15] + node _T_2166 = mux(_T_2165, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2167 = bits(mhpme_vec[3], 9, 9) @[el2_dec_tlu_ctl.scala 2421:105] + node _T_2168 = bits(mhpme_vec[2], 9, 9) @[el2_dec_tlu_ctl.scala 2421:121] + node _T_2169 = bits(mhpme_vec[1], 9, 9) @[el2_dec_tlu_ctl.scala 2421:137] + node _T_2170 = bits(mhpme_vec[0], 9, 9) @[el2_dec_tlu_ctl.scala 2421:153] + node _T_2171 = cat(_T_2169, _T_2170) @[Cat.scala 29:58] + node _T_2172 = cat(_T_2167, _T_2168) @[Cat.scala 29:58] + node _T_2173 = cat(_T_2172, _T_2171) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2166, _T_2173) @[el2_dec_tlu_ctl.scala 2421:87] + node _T_2174 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2423:89] + node _T_2175 = not(_T_2174) @[el2_dec_tlu_ctl.scala 2423:68] + node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[el2_dec_tlu_ctl.scala 2423:66] + node _T_2177 = not(_T_2176) @[el2_dec_tlu_ctl.scala 2423:46] + node _T_2178 = and(mhpmc_inc_r_d1[0], _T_2177) @[el2_dec_tlu_ctl.scala 2423:44] + io.dec_tlu_perfcnt0 <= _T_2178 @[el2_dec_tlu_ctl.scala 2423:23] + node _T_2179 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2424:89] + node _T_2180 = not(_T_2179) @[el2_dec_tlu_ctl.scala 2424:68] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[el2_dec_tlu_ctl.scala 2424:66] + node _T_2182 = not(_T_2181) @[el2_dec_tlu_ctl.scala 2424:46] + node _T_2183 = and(mhpmc_inc_r_d1[1], _T_2182) @[el2_dec_tlu_ctl.scala 2424:44] + io.dec_tlu_perfcnt1 <= _T_2183 @[el2_dec_tlu_ctl.scala 2424:23] + node _T_2184 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2425:89] + node _T_2185 = not(_T_2184) @[el2_dec_tlu_ctl.scala 2425:68] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[el2_dec_tlu_ctl.scala 2425:66] + node _T_2187 = not(_T_2186) @[el2_dec_tlu_ctl.scala 2425:46] + node _T_2188 = and(mhpmc_inc_r_d1[2], _T_2187) @[el2_dec_tlu_ctl.scala 2425:44] + io.dec_tlu_perfcnt2 <= _T_2188 @[el2_dec_tlu_ctl.scala 2425:23] + node _T_2189 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2426:89] + node _T_2190 = not(_T_2189) @[el2_dec_tlu_ctl.scala 2426:68] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[el2_dec_tlu_ctl.scala 2426:66] + node _T_2192 = not(_T_2191) @[el2_dec_tlu_ctl.scala 2426:46] + node _T_2193 = and(mhpmc_inc_r_d1[3], _T_2192) @[el2_dec_tlu_ctl.scala 2426:44] + io.dec_tlu_perfcnt3 <= _T_2193 @[el2_dec_tlu_ctl.scala 2426:23] + node _T_2194 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2432:66] + node _T_2195 = eq(_T_2194, UInt<12>("h0b03")) @[el2_dec_tlu_ctl.scala 2432:73] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2195) @[el2_dec_tlu_ctl.scala 2432:44] + node _T_2196 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2433:24] + node _T_2197 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2433:62] + node _T_2198 = or(_T_2196, _T_2197) @[el2_dec_tlu_ctl.scala 2433:40] + node _T_2199 = orr(mhpmc_inc_r[0]) @[el2_dec_tlu_ctl.scala 2433:87] + node mhpmc3_wr_en1 = and(_T_2198, _T_2199) @[el2_dec_tlu_ctl.scala 2433:67] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2434:37] + node _T_2200 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2437:29] + node _T_2201 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2437:42] + node _T_2202 = cat(_T_2200, _T_2201) @[Cat.scala 29:58] + node _T_2203 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2204 = add(_T_2202, _T_2203) @[el2_dec_tlu_ctl.scala 2437:50] + node _T_2205 = tail(_T_2204, 1) @[el2_dec_tlu_ctl.scala 2437:50] + mhpmc3_incr <= _T_2205 @[el2_dec_tlu_ctl.scala 2437:15] + node _T_2206 = bits(mhpmc3_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2438:37] + node _T_2207 = bits(mhpmc3_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2438:77] + node mhpmc3_ns = mux(_T_2206, io.dec_csr_wrdata_r, _T_2207) @[el2_dec_tlu_ctl.scala 2438:22] + node _T_2208 = bits(mhpmc3_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2440:43] + inst rvclkhdr_26 of rvclkhdr_85 @[el2_lib.scala 485:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_26.io.en <= _T_2208 @[el2_lib.scala 488:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2209 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2209 <= mhpmc3_ns @[el2_lib.scala 491:16] + mhpmc3 <= _T_2209 @[el2_dec_tlu_ctl.scala 2440:10] + node _T_2210 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2442:67] + node _T_2211 = eq(_T_2210, UInt<12>("h0b83")) @[el2_dec_tlu_ctl.scala 2442:74] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2211) @[el2_dec_tlu_ctl.scala 2442:45] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2443:39] + node _T_2212 = bits(mhpmc3h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2444:39] + node _T_2213 = bits(mhpmc3_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2444:79] + node mhpmc3h_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[el2_dec_tlu_ctl.scala 2444:23] + node _T_2214 = bits(mhpmc3h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2446:47] + inst rvclkhdr_27 of rvclkhdr_86 @[el2_lib.scala 485:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_27.io.en <= _T_2214 @[el2_lib.scala 488:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2215 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2215 <= mhpmc3h_ns @[el2_lib.scala 491:16] + mhpmc3h <= _T_2215 @[el2_dec_tlu_ctl.scala 2446:11] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2451:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b04")) @[el2_dec_tlu_ctl.scala 2451:73] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[el2_dec_tlu_ctl.scala 2451:44] + node _T_2218 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2452:24] + node _T_2219 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2452:62] + node _T_2220 = or(_T_2218, _T_2219) @[el2_dec_tlu_ctl.scala 2452:40] + node _T_2221 = orr(mhpmc_inc_r[1]) @[el2_dec_tlu_ctl.scala 2452:87] + node mhpmc4_wr_en1 = and(_T_2220, _T_2221) @[el2_dec_tlu_ctl.scala 2452:67] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2453:37] + node _T_2222 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2457:29] + node _T_2223 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2457:42] + node _T_2224 = cat(_T_2222, _T_2223) @[Cat.scala 29:58] + node _T_2225 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2226 = add(_T_2224, _T_2225) @[el2_dec_tlu_ctl.scala 2457:50] + node _T_2227 = tail(_T_2226, 1) @[el2_dec_tlu_ctl.scala 2457:50] + mhpmc4_incr <= _T_2227 @[el2_dec_tlu_ctl.scala 2457:15] + node _T_2228 = bits(mhpmc4_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2458:37] + node _T_2229 = bits(io.dec_csr_wrdata_r, 31, 0) @[el2_dec_tlu_ctl.scala 2458:64] + node _T_2230 = bits(mhpmc4_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2458:83] + node mhpmc4_ns = mux(_T_2228, _T_2229, _T_2230) @[el2_dec_tlu_ctl.scala 2458:22] + node _T_2231 = bits(mhpmc4_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2459:44] + inst rvclkhdr_28 of rvclkhdr_87 @[el2_lib.scala 485:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_28.io.en <= _T_2231 @[el2_lib.scala 488:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2232 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2232 <= mhpmc4_ns @[el2_lib.scala 491:16] + mhpmc4 <= _T_2232 @[el2_dec_tlu_ctl.scala 2459:10] + node _T_2233 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2461:67] + node _T_2234 = eq(_T_2233, UInt<12>("h0b84")) @[el2_dec_tlu_ctl.scala 2461:74] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2234) @[el2_dec_tlu_ctl.scala 2461:45] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2462:39] + node _T_2235 = bits(mhpmc4h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2463:39] + node _T_2236 = bits(mhpmc4_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2463:79] + node mhpmc4h_ns = mux(_T_2235, io.dec_csr_wrdata_r, _T_2236) @[el2_dec_tlu_ctl.scala 2463:23] + node _T_2237 = bits(mhpmc4h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2464:47] + inst rvclkhdr_29 of rvclkhdr_88 @[el2_lib.scala 485:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_29.io.en <= _T_2237 @[el2_lib.scala 488:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2238 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2238 <= mhpmc4h_ns @[el2_lib.scala 491:16] + mhpmc4h <= _T_2238 @[el2_dec_tlu_ctl.scala 2464:11] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2470:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b05")) @[el2_dec_tlu_ctl.scala 2470:73] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[el2_dec_tlu_ctl.scala 2470:44] + node _T_2241 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2471:24] + node _T_2242 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2471:62] + node _T_2243 = or(_T_2241, _T_2242) @[el2_dec_tlu_ctl.scala 2471:40] + node _T_2244 = orr(mhpmc_inc_r[2]) @[el2_dec_tlu_ctl.scala 2471:87] + node mhpmc5_wr_en1 = and(_T_2243, _T_2244) @[el2_dec_tlu_ctl.scala 2471:67] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2472:37] + node _T_2245 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2474:29] + node _T_2246 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2474:42] + node _T_2247 = cat(_T_2245, _T_2246) @[Cat.scala 29:58] + node _T_2248 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2249 = add(_T_2247, _T_2248) @[el2_dec_tlu_ctl.scala 2474:50] + node _T_2250 = tail(_T_2249, 1) @[el2_dec_tlu_ctl.scala 2474:50] + mhpmc5_incr <= _T_2250 @[el2_dec_tlu_ctl.scala 2474:15] + node _T_2251 = bits(mhpmc5_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2475:37] + node _T_2252 = bits(mhpmc5_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2475:77] + node mhpmc5_ns = mux(_T_2251, io.dec_csr_wrdata_r, _T_2252) @[el2_dec_tlu_ctl.scala 2475:22] + node _T_2253 = bits(mhpmc5_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2477:44] + inst rvclkhdr_30 of rvclkhdr_89 @[el2_lib.scala 485:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_30.io.en <= _T_2253 @[el2_lib.scala 488:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2254 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2254 <= mhpmc5_ns @[el2_lib.scala 491:16] + mhpmc5 <= _T_2254 @[el2_dec_tlu_ctl.scala 2477:10] + node _T_2255 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2479:67] + node _T_2256 = eq(_T_2255, UInt<12>("h0b85")) @[el2_dec_tlu_ctl.scala 2479:74] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2256) @[el2_dec_tlu_ctl.scala 2479:45] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2480:39] + node _T_2257 = bits(mhpmc5h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2481:39] + node _T_2258 = bits(mhpmc5_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2481:79] + node mhpmc5h_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[el2_dec_tlu_ctl.scala 2481:23] + node _T_2259 = bits(mhpmc5h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2483:47] + inst rvclkhdr_31 of rvclkhdr_90 @[el2_lib.scala 485:23] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_31.io.en <= _T_2259 @[el2_lib.scala 488:17] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2260 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2260 <= mhpmc5h_ns @[el2_lib.scala 491:16] + mhpmc5h <= _T_2260 @[el2_dec_tlu_ctl.scala 2483:11] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2488:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b06")) @[el2_dec_tlu_ctl.scala 2488:73] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[el2_dec_tlu_ctl.scala 2488:44] + node _T_2263 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2489:24] + node _T_2264 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2489:62] + node _T_2265 = or(_T_2263, _T_2264) @[el2_dec_tlu_ctl.scala 2489:40] + node _T_2266 = orr(mhpmc_inc_r[3]) @[el2_dec_tlu_ctl.scala 2489:87] + node mhpmc6_wr_en1 = and(_T_2265, _T_2266) @[el2_dec_tlu_ctl.scala 2489:67] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2490:37] + node _T_2267 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2492:29] + node _T_2268 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2492:42] + node _T_2269 = cat(_T_2267, _T_2268) @[Cat.scala 29:58] + node _T_2270 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2271 = add(_T_2269, _T_2270) @[el2_dec_tlu_ctl.scala 2492:50] + node _T_2272 = tail(_T_2271, 1) @[el2_dec_tlu_ctl.scala 2492:50] + mhpmc6_incr <= _T_2272 @[el2_dec_tlu_ctl.scala 2492:15] + node _T_2273 = bits(mhpmc6_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2493:37] + node _T_2274 = bits(mhpmc6_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2493:77] + node mhpmc6_ns = mux(_T_2273, io.dec_csr_wrdata_r, _T_2274) @[el2_dec_tlu_ctl.scala 2493:22] + node _T_2275 = bits(mhpmc6_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2495:44] + inst rvclkhdr_32 of rvclkhdr_91 @[el2_lib.scala 485:23] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_32.io.en <= _T_2275 @[el2_lib.scala 488:17] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2276 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2276 <= mhpmc6_ns @[el2_lib.scala 491:16] + mhpmc6 <= _T_2276 @[el2_dec_tlu_ctl.scala 2495:10] + node _T_2277 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2497:67] + node _T_2278 = eq(_T_2277, UInt<12>("h0b86")) @[el2_dec_tlu_ctl.scala 2497:74] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2278) @[el2_dec_tlu_ctl.scala 2497:45] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2498:39] + node _T_2279 = bits(mhpmc6h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2499:39] + node _T_2280 = bits(mhpmc6_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2499:79] + node mhpmc6h_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[el2_dec_tlu_ctl.scala 2499:23] + node _T_2281 = bits(mhpmc6h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2501:47] + inst rvclkhdr_33 of rvclkhdr_92 @[el2_lib.scala 485:23] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_33.io.en <= _T_2281 @[el2_lib.scala 488:17] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2282 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2282 <= mhpmc6h_ns @[el2_lib.scala 491:16] + mhpmc6h <= _T_2282 @[el2_dec_tlu_ctl.scala 2501:11] + node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:51] + node _T_2284 = gt(_T_2283, UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2508:57] + node _T_2285 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2508:94] + node _T_2286 = orr(_T_2285) @[el2_dec_tlu_ctl.scala 2508:103] + node _T_2287 = or(_T_2284, _T_2286) @[el2_dec_tlu_ctl.scala 2508:72] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:142] + node event_saturate_r = mux(_T_2287, UInt<10>("h0204"), _T_2288) @[el2_dec_tlu_ctl.scala 2508:29] + node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2510:64] + node _T_2290 = eq(_T_2289, UInt<12>("h0323")) @[el2_dec_tlu_ctl.scala 2510:71] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2290) @[el2_dec_tlu_ctl.scala 2510:42] + node _T_2291 = bits(wr_mhpme3_r, 0, 0) @[el2_dec_tlu_ctl.scala 2512:81] + reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2291 : @[Reg.scala 28:19] + _T_2292 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme3 <= _T_2292 @[el2_dec_tlu_ctl.scala 2512:10] + node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2517:64] + node _T_2294 = eq(_T_2293, UInt<12>("h0324")) @[el2_dec_tlu_ctl.scala 2517:71] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2294) @[el2_dec_tlu_ctl.scala 2517:42] + node _T_2295 = bits(wr_mhpme4_r, 0, 0) @[el2_dec_tlu_ctl.scala 2518:81] + reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2295 : @[Reg.scala 28:19] + _T_2296 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme4 <= _T_2296 @[el2_dec_tlu_ctl.scala 2518:10] + node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2524:64] + node _T_2298 = eq(_T_2297, UInt<12>("h0325")) @[el2_dec_tlu_ctl.scala 2524:71] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2298) @[el2_dec_tlu_ctl.scala 2524:42] + node _T_2299 = bits(wr_mhpme5_r, 0, 0) @[el2_dec_tlu_ctl.scala 2525:81] + reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2299 : @[Reg.scala 28:19] + _T_2300 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme5 <= _T_2300 @[el2_dec_tlu_ctl.scala 2525:10] + node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2531:64] + node _T_2302 = eq(_T_2301, UInt<12>("h0326")) @[el2_dec_tlu_ctl.scala 2531:71] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2302) @[el2_dec_tlu_ctl.scala 2531:42] + node _T_2303 = bits(wr_mhpme6_r, 0, 0) @[el2_dec_tlu_ctl.scala 2532:81] + reg _T_2304 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2303 : @[Reg.scala 28:19] + _T_2304 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme6 <= _T_2304 @[el2_dec_tlu_ctl.scala 2532:10] + node _T_2305 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2548:71] + node _T_2306 = eq(_T_2305, UInt<12>("h0320")) @[el2_dec_tlu_ctl.scala 2548:78] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2306) @[el2_dec_tlu_ctl.scala 2548:49] + node _T_2307 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2550:55] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_2307 + node _T_2308 = bits(mcountinhibit, 1, 1) @[el2_dec_tlu_ctl.scala 2551:55] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_2308 + node _T_2309 = bits(mcountinhibit, 6, 2) @[el2_dec_tlu_ctl.scala 2552:56] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_2309 + node _T_2310 = bits(io.dec_csr_wrdata_r, 6, 2) @[el2_dec_tlu_ctl.scala 2553:75] + node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2553:104] + reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2311 : @[Reg.scala 28:19] + _T_2312 <= _T_2310 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount6_2 <= _T_2312 @[el2_dec_tlu_ctl.scala 2553:18] + node _T_2313 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:73] + node _T_2314 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:100] + reg _T_2315 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2314 : @[Reg.scala 28:19] + _T_2315 <= _T_2313 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_2315 @[el2_dec_tlu_ctl.scala 2555:16] + node _T_2316 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2317 = cat(_T_2316, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2317 @[el2_dec_tlu_ctl.scala 2556:17] + node _T_2318 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:52] + node _T_2319 = or(_T_2318, io.interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:79] + node _T_2320 = or(_T_2319, io.dec_tlu_i0_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:105] + node _T_2321 = or(_T_2320, io.dec_tlu_i0_exc_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:131] + node _T_2322 = or(_T_2321, io.dec_tlu_int_valid_wb1) @[el2_dec_tlu_ctl.scala 2564:33] + node _T_2323 = or(_T_2322, io.clk_override) @[el2_dec_tlu_ctl.scala 2564:60] + node _T_2324 = bits(_T_2323, 0, 0) @[el2_dec_tlu_ctl.scala 2564:79] + inst rvclkhdr_34 of rvclkhdr_93 @[el2_lib.scala 474:22] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_34.io.en <= _T_2324 @[el2_lib.scala 476:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2566:63] + _T_2325 <= io.i0_valid_wb @[el2_dec_tlu_ctl.scala 2566:63] + io.dec_tlu_i0_valid_wb1 <= _T_2325 @[el2_dec_tlu_ctl.scala 2566:31] + node _T_2326 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[el2_dec_tlu_ctl.scala 2567:92] + node _T_2327 = not(io.trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 2567:138] + node _T_2328 = and(io.trigger_hit_r_d1, _T_2327) @[el2_dec_tlu_ctl.scala 2567:136] + node _T_2329 = or(_T_2326, _T_2328) @[el2_dec_tlu_ctl.scala 2567:113] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2567:63] + _T_2330 <= _T_2329 @[el2_dec_tlu_ctl.scala 2567:63] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2330 @[el2_dec_tlu_ctl.scala 2567:31] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2568:63] + _T_2331 <= io.exc_cause_wb @[el2_dec_tlu_ctl.scala 2568:63] + io.dec_tlu_exc_cause_wb1 <= _T_2331 @[el2_dec_tlu_ctl.scala 2568:31] + reg _T_2332 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2569:63] + _T_2332 <= io.interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 2569:63] + io.dec_tlu_int_valid_wb1 <= _T_2332 @[el2_dec_tlu_ctl.scala 2569:31] + io.dec_tlu_mtval_wb1 <= mtval @[el2_dec_tlu_ctl.scala 2571:25] + node _T_2333 = bits(io.csr_pkt.csr_misa, 0, 0) @[el2_dec_tlu_ctl.scala 2577:25] + node _T_2334 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[el2_dec_tlu_ctl.scala 2578:30] + node _T_2335 = bits(io.csr_pkt.csr_marchid, 0, 0) @[el2_dec_tlu_ctl.scala 2579:28] + node _T_2336 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[el2_dec_tlu_ctl.scala 2580:27] + node _T_2337 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[el2_dec_tlu_ctl.scala 2581:28] + node _T_2338 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2339 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:28] + node _T_2340 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 2582:91] + node _T_2341 = bits(io.mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:116] + node _T_2342 = cat(UInt<3>("h00"), _T_2341) @[Cat.scala 29:58] + node _T_2343 = cat(_T_2342, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2344 = cat(UInt<3>("h00"), _T_2340) @[Cat.scala 29:58] + node _T_2345 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2346 = cat(_T_2345, _T_2344) @[Cat.scala 29:58] + node _T_2347 = cat(_T_2346, _T_2343) @[Cat.scala 29:58] + node _T_2348 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:26] + node _T_2349 = bits(io.mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 2583:58] + node _T_2350 = bits(io.mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:84] + node _T_2351 = cat(_T_2349, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:24] + node _T_2354 = bits(io.mip, 5, 3) @[el2_dec_tlu_ctl.scala 2584:66] + node _T_2355 = bits(io.mip, 2, 2) @[el2_dec_tlu_ctl.scala 2584:90] + node _T_2356 = bits(io.mip, 1, 1) @[el2_dec_tlu_ctl.scala 2584:111] + node _T_2357 = bits(io.mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:132] + node _T_2358 = cat(_T_2357, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2359 = cat(_T_2356, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, _T_2358) @[Cat.scala 29:58] + node _T_2361 = cat(_T_2355, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2362 = cat(UInt<1>("h00"), _T_2354) @[Cat.scala 29:58] + node _T_2363 = cat(_T_2362, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2363, _T_2361) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2360) @[Cat.scala 29:58] + node _T_2366 = bits(io.csr_pkt.csr_mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:24] + node _T_2367 = bits(mie, 5, 3) @[el2_dec_tlu_ctl.scala 2585:63] + node _T_2368 = bits(mie, 2, 2) @[el2_dec_tlu_ctl.scala 2585:84] + node _T_2369 = bits(mie, 1, 1) @[el2_dec_tlu_ctl.scala 2585:102] + node _T_2370 = bits(mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:120] + node _T_2371 = cat(_T_2370, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2369, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, _T_2371) @[Cat.scala 29:58] + node _T_2374 = cat(_T_2368, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2375 = cat(UInt<1>("h00"), _T_2367) @[Cat.scala 29:58] + node _T_2376 = cat(_T_2375, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2376, _T_2374) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2373) @[Cat.scala 29:58] + node _T_2379 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[el2_dec_tlu_ctl.scala 2586:28] + node _T_2380 = bits(mcyclel, 31, 0) @[el2_dec_tlu_ctl.scala 2586:53] + node _T_2381 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[el2_dec_tlu_ctl.scala 2587:28] + node _T_2382 = bits(mcycleh_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2587:57] + node _T_2383 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[el2_dec_tlu_ctl.scala 2588:30] + node _T_2384 = bits(minstretl, 31, 0) @[el2_dec_tlu_ctl.scala 2588:60] + node _T_2385 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[el2_dec_tlu_ctl.scala 2589:30] + node _T_2386 = bits(minstreth_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2589:60] + node _T_2387 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[el2_dec_tlu_ctl.scala 2590:29] + node _T_2388 = bits(mscratch, 31, 0) @[el2_dec_tlu_ctl.scala 2590:54] + node _T_2389 = bits(io.csr_pkt.csr_mepc, 0, 0) @[el2_dec_tlu_ctl.scala 2591:25] + node _T_2390 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2391 = bits(io.csr_pkt.csr_mcause, 0, 0) @[el2_dec_tlu_ctl.scala 2592:27] + node _T_2392 = bits(mcause, 31, 0) @[el2_dec_tlu_ctl.scala 2592:52] + node _T_2393 = bits(io.csr_pkt.csr_mscause, 0, 0) @[el2_dec_tlu_ctl.scala 2593:28] + node _T_2394 = bits(mscause, 3, 0) @[el2_dec_tlu_ctl.scala 2593:68] + node _T_2395 = cat(UInt<28>("h00"), _T_2394) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mtval, 0, 0) @[el2_dec_tlu_ctl.scala 2594:26] + node _T_2397 = bits(mtval, 31, 0) @[el2_dec_tlu_ctl.scala 2594:51] + node _T_2398 = bits(io.csr_pkt.csr_mrac, 0, 0) @[el2_dec_tlu_ctl.scala 2595:25] + node _T_2399 = bits(mrac, 31, 0) @[el2_dec_tlu_ctl.scala 2595:50] + node _T_2400 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[el2_dec_tlu_ctl.scala 2596:27] + node _T_2401 = bits(mdseac, 31, 0) @[el2_dec_tlu_ctl.scala 2596:52] + node _T_2402 = bits(io.csr_pkt.csr_meivt, 0, 0) @[el2_dec_tlu_ctl.scala 2597:26] + node _T_2403 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2404 = bits(io.csr_pkt.csr_meihap, 0, 0) @[el2_dec_tlu_ctl.scala 2598:27] + node _T_2405 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2406 = cat(_T_2405, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2407 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[el2_dec_tlu_ctl.scala 2599:29] + node _T_2408 = bits(meicurpl, 3, 0) @[el2_dec_tlu_ctl.scala 2599:69] + node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[el2_dec_tlu_ctl.scala 2600:29] + node _T_2411 = bits(meicidpl, 3, 0) @[el2_dec_tlu_ctl.scala 2600:69] + node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meipt, 0, 0) @[el2_dec_tlu_ctl.scala 2601:26] + node _T_2414 = bits(meipt, 3, 0) @[el2_dec_tlu_ctl.scala 2601:66] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 2602:25] + node _T_2417 = bits(mcgc, 8, 0) @[el2_dec_tlu_ctl.scala 2602:65] + node _T_2418 = cat(UInt<23>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 2603:25] + node _T_2420 = bits(mfdc, 18, 0) @[el2_dec_tlu_ctl.scala 2603:65] + node _T_2421 = cat(UInt<13>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[el2_dec_tlu_ctl.scala 2604:25] + node _T_2423 = bits(io.dcsr, 15, 2) @[el2_dec_tlu_ctl.scala 2604:73] + node _T_2424 = cat(UInt<16>("h04000"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = cat(_T_2424, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2426 = bits(io.csr_pkt.csr_dpc, 0, 0) @[el2_dec_tlu_ctl.scala 2605:24] + node _T_2427 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[el2_dec_tlu_ctl.scala 2606:27] + node _T_2429 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2606:52] + node _T_2430 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[el2_dec_tlu_ctl.scala 2607:28] + node _T_2431 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2607:53] + node _T_2432 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[el2_dec_tlu_ctl.scala 2608:27] + node _T_2433 = bits(dicad1, 31, 0) @[el2_dec_tlu_ctl.scala 2608:52] + node _T_2434 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[el2_dec_tlu_ctl.scala 2609:29] + node _T_2435 = bits(dicawics, 16, 16) @[el2_dec_tlu_ctl.scala 2609:68] + node _T_2436 = bits(dicawics, 15, 14) @[el2_dec_tlu_ctl.scala 2609:92] + node _T_2437 = bits(dicawics, 13, 0) @[el2_dec_tlu_ctl.scala 2609:119] + node _T_2438 = cat(UInt<3>("h00"), _T_2437) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2440 = cat(UInt<2>("h00"), _T_2436) @[Cat.scala 29:58] + node _T_2441 = cat(UInt<7>("h00"), _T_2435) @[Cat.scala 29:58] + node _T_2442 = cat(_T_2441, _T_2440) @[Cat.scala 29:58] + node _T_2443 = cat(_T_2442, _T_2439) @[Cat.scala 29:58] + node _T_2444 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[el2_dec_tlu_ctl.scala 2610:26] + node _T_2445 = bits(mtsel, 1, 0) @[el2_dec_tlu_ctl.scala 2610:66] + node _T_2446 = cat(UInt<30>("h00"), _T_2445) @[Cat.scala 29:58] + node _T_2447 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[el2_dec_tlu_ctl.scala 2611:28] + node _T_2448 = bits(mtdata1_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2611:62] + node _T_2449 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[el2_dec_tlu_ctl.scala 2612:28] + node _T_2450 = bits(mtdata2_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2612:62] + node _T_2451 = bits(io.csr_pkt.csr_micect, 0, 0) @[el2_dec_tlu_ctl.scala 2613:27] + node _T_2452 = bits(micect, 31, 0) @[el2_dec_tlu_ctl.scala 2613:52] + node _T_2453 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2614:29] + node _T_2454 = bits(miccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2614:54] + node _T_2455 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2615:29] + node _T_2456 = bits(mdccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2615:54] + node _T_2457 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[el2_dec_tlu_ctl.scala 2616:27] + node _T_2458 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2616:52] + node _T_2459 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[el2_dec_tlu_ctl.scala 2617:27] + node _T_2460 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2617:52] + node _T_2461 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[el2_dec_tlu_ctl.scala 2618:27] + node _T_2462 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2618:52] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[el2_dec_tlu_ctl.scala 2619:27] + node _T_2464 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2619:52] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[el2_dec_tlu_ctl.scala 2620:28] + node _T_2466 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2620:53] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[el2_dec_tlu_ctl.scala 2621:28] + node _T_2468 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2621:53] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[el2_dec_tlu_ctl.scala 2622:28] + node _T_2470 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2622:53] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[el2_dec_tlu_ctl.scala 2623:28] + node _T_2472 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2623:53] + node _T_2473 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2624:26] + node _T_2474 = bits(mfdht, 5, 0) @[el2_dec_tlu_ctl.scala 2624:66] + node _T_2475 = cat(UInt<26>("h00"), _T_2474) @[Cat.scala 29:58] + node _T_2476 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[el2_dec_tlu_ctl.scala 2625:26] + node _T_2477 = bits(mfdhs, 1, 0) @[el2_dec_tlu_ctl.scala 2625:66] + node _T_2478 = cat(UInt<30>("h00"), _T_2477) @[Cat.scala 29:58] + node _T_2479 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[el2_dec_tlu_ctl.scala 2626:27] + node _T_2480 = bits(mhpme3, 9, 0) @[el2_dec_tlu_ctl.scala 2626:67] + node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[el2_dec_tlu_ctl.scala 2627:27] + node _T_2483 = bits(mhpme4, 9, 0) @[el2_dec_tlu_ctl.scala 2627:67] + node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[el2_dec_tlu_ctl.scala 2628:27] + node _T_2486 = bits(mhpme5, 9, 0) @[el2_dec_tlu_ctl.scala 2628:66] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[el2_dec_tlu_ctl.scala 2629:27] + node _T_2489 = bits(mhpme6, 9, 0) @[el2_dec_tlu_ctl.scala 2629:66] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2630:34] + node _T_2492 = bits(mcountinhibit, 6, 0) @[el2_dec_tlu_ctl.scala 2630:74] + node _T_2493 = cat(UInt<25>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[el2_dec_tlu_ctl.scala 2631:25] + node _T_2495 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2496 = cat(_T_2495, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2497 = bits(io.dec_timer_read_d, 0, 0) @[el2_dec_tlu_ctl.scala 2632:25] + node _T_2498 = bits(io.dec_timer_rddata_d, 31, 0) @[el2_dec_tlu_ctl.scala 2632:64] + node _T_2499 = mux(_T_2333, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2334, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2335, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2336, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2337, _T_2338, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2339, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2348, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2353, _T_2365, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2366, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2393, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2400, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2422, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2430, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2434, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2444, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2497, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = or(_T_2499, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] + node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] + node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] + node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72] + node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72] + node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72] + node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72] + node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72] + node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72] + node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72] + node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72] + node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72] + node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72] + node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72] + node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72] + node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72] + node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72] + node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72] + node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72] + node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72] + node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72] + node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72] + node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72] + node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72] + node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72] + node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72] + node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72] + node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72] + node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72] + node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72] + node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72] + node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72] + node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72] + node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72] + node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72] + node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72] + node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72] + node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72] + node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72] + node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72] + node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] + node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] + node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] + node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + wire _T_2610 : UInt @[Mux.scala 27:72] + _T_2610 <= _T_2609 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2610 @[el2_dec_tlu_ctl.scala 2576:22] + + module el2_dec_decode_csr_read : + input clock : Clock + input reset : Reset + output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1 = eq(_T, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_9 = and(_T_1, _T_3) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_10 = and(_T_9, _T_5) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_11 = and(_T_10, _T_7) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_12 = and(_T_11, _T_8) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_misa <= _T_12 @[el2_dec_tlu_ctl.scala 2650:49] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_19 = and(_T_13, _T_15) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_20 = and(_T_19, _T_17) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_21 = and(_T_20, _T_18) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mvendorid <= _T_21 @[el2_dec_tlu_ctl.scala 2651:49] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_28 = and(_T_22, _T_24) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_29 = and(_T_28, _T_25) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_30 = and(_T_29, _T_27) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_marchid <= _T_30 @[el2_dec_tlu_ctl.scala 2652:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_36 = and(_T_31, _T_33) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_37 = and(_T_36, _T_34) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_38 = and(_T_37, _T_35) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mimpid <= _T_38 @[el2_dec_tlu_ctl.scala 2653:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_43 = and(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_44 = and(_T_43, _T_42) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhartid <= _T_44 @[el2_dec_tlu_ctl.scala 2654:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_55 = and(_T_46, _T_48) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_56 = and(_T_55, _T_50) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_57 = and(_T_56, _T_52) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_58 = and(_T_57, _T_54) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mstatus <= _T_58 @[el2_dec_tlu_ctl.scala 2655:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_67 = and(_T_60, _T_62) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_68 = and(_T_67, _T_64) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_69 = and(_T_68, _T_65) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_70 = and(_T_69, _T_66) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtvec <= _T_70 @[el2_dec_tlu_ctl.scala 2656:49] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_75 = and(_T_72, _T_73) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_76 = and(_T_75, _T_74) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mip <= _T_76 @[el2_dec_tlu_ctl.scala 2657:57] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_86 = and(_T_78, _T_80) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_87 = and(_T_86, _T_82) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_88 = and(_T_87, _T_83) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_89 = and(_T_88, _T_85) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mie <= _T_89 @[el2_dec_tlu_ctl.scala 2658:57] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_101 = and(_T_90, _T_92) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_102 = and(_T_101, _T_94) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_103 = and(_T_102, _T_96) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_104 = and(_T_103, _T_98) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_105 = and(_T_104, _T_100) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcyclel <= _T_105 @[el2_dec_tlu_ctl.scala 2659:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_119 = and(_T_106, _T_108) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_120 = and(_T_119, _T_110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_121 = and(_T_120, _T_112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_122 = and(_T_121, _T_114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_123 = and(_T_122, _T_116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_124 = and(_T_123, _T_118) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcycleh <= _T_124 @[el2_dec_tlu_ctl.scala 2660:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_138 = and(_T_126, _T_128) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_139 = and(_T_138, _T_130) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_140 = and(_T_139, _T_132) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_141 = and(_T_140, _T_134) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_142 = and(_T_141, _T_135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_143 = and(_T_142, _T_137) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstretl <= _T_143 @[el2_dec_tlu_ctl.scala 2661:49] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_156 = and(_T_145, _T_146) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_157 = and(_T_156, _T_148) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_158 = and(_T_157, _T_150) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_159 = and(_T_158, _T_152) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_160 = and(_T_159, _T_153) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_161 = and(_T_160, _T_155) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstreth <= _T_161 @[el2_dec_tlu_ctl.scala 2662:49] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_171 = and(_T_163, _T_164) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_172 = and(_T_171, _T_166) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_173 = and(_T_172, _T_168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_174 = and(_T_173, _T_170) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscratch <= _T_174 @[el2_dec_tlu_ctl.scala 2663:49] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_181 = and(_T_176, _T_177) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_182 = and(_T_181, _T_179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_183 = and(_T_182, _T_180) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mepc <= _T_183 @[el2_dec_tlu_ctl.scala 2664:49] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_190 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_191 = and(_T_190, _T_187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_192 = and(_T_191, _T_189) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcause <= _T_192 @[el2_dec_tlu_ctl.scala 2665:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_196 = and(_T_193, _T_194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_197 = and(_T_196, _T_195) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscause <= _T_197 @[el2_dec_tlu_ctl.scala 2666:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_203 = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_204 = and(_T_203, _T_201) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_205 = and(_T_204, _T_202) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtval <= _T_205 @[el2_dec_tlu_ctl.scala 2667:49] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_217 = and(_T_207, _T_208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_218 = and(_T_217, _T_210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_219 = and(_T_218, _T_212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_220 = and(_T_219, _T_214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_221 = and(_T_220, _T_216) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mrac <= _T_221 @[el2_dec_tlu_ctl.scala 2668:49] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_230 = and(_T_222, _T_224) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_231 = and(_T_230, _T_226) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_232 = and(_T_231, _T_227) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_233 = and(_T_232, _T_229) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dmst <= _T_233 @[el2_dec_tlu_ctl.scala 2669:49] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_240 = and(_T_234, _T_235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_241 = and(_T_240, _T_237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_242 = and(_T_241, _T_239) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdseac <= _T_242 @[el2_dec_tlu_ctl.scala 2670:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_246 = and(_T_243, _T_244) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_247 = and(_T_246, _T_245) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meihap <= _T_247 @[el2_dec_tlu_ctl.scala 2671:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_258 = and(_T_249, _T_250) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_259 = and(_T_258, _T_251) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_260 = and(_T_259, _T_253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_261 = and(_T_260, _T_255) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_262 = and(_T_261, _T_257) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meivt <= _T_262 @[el2_dec_tlu_ctl.scala 2672:49] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_268 = and(_T_263, _T_264) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_269 = and(_T_268, _T_266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_270 = and(_T_269, _T_267) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meipt <= _T_270 @[el2_dec_tlu_ctl.scala 2673:49] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_274 = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_275 = and(_T_274, _T_273) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicurpl <= _T_275 @[el2_dec_tlu_ctl.scala 2674:49] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_280 = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_281 = and(_T_280, _T_278) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_282 = and(_T_281, _T_279) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicidpl <= _T_282 @[el2_dec_tlu_ctl.scala 2675:49] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_290 = and(_T_283, _T_285) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_291 = and(_T_290, _T_286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_292 = and(_T_291, _T_287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_293 = and(_T_292, _T_289) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dcsr <= _T_293 @[el2_dec_tlu_ctl.scala 2676:49] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_299 = and(_T_294, _T_295) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_300 = and(_T_299, _T_296) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_301 = and(_T_300, _T_298) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcgc <= _T_301 @[el2_dec_tlu_ctl.scala 2677:49] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_308 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_309 = and(_T_308, _T_304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_310 = and(_T_309, _T_306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_311 = and(_T_310, _T_307) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdc <= _T_311 @[el2_dec_tlu_ctl.scala 2678:49] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_318 = and(_T_312, _T_314) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_319 = and(_T_318, _T_315) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_320 = and(_T_319, _T_316) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_321 = and(_T_320, _T_317) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dpc <= _T_321 @[el2_dec_tlu_ctl.scala 2679:57] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_330 = and(_T_322, _T_323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_331 = and(_T_330, _T_325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_332 = and(_T_331, _T_327) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_333 = and(_T_332, _T_329) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtsel <= _T_333 @[el2_dec_tlu_ctl.scala 2680:49] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_340 = and(_T_334, _T_336) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_341 = and(_T_340, _T_338) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_342 = and(_T_341, _T_339) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata1 <= _T_342 @[el2_dec_tlu_ctl.scala 2681:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_348 = and(_T_343, _T_344) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_349 = and(_T_348, _T_346) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_350 = and(_T_349, _T_347) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata2 <= _T_350 @[el2_dec_tlu_ctl.scala 2682:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_361 = and(_T_351, _T_353) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_362 = and(_T_361, _T_355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_363 = and(_T_362, _T_357) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_364 = and(_T_363, _T_359) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_365 = and(_T_364, _T_360) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[el2_dec_tlu_ctl.scala 2683:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_378 = and(_T_366, _T_368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_379 = and(_T_378, _T_370) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_380 = and(_T_379, _T_372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_381 = and(_T_380, _T_373) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_382 = and(_T_381, _T_375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_383 = and(_T_382, _T_377) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[el2_dec_tlu_ctl.scala 2684:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_394 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_395 = and(_T_394, _T_388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_396 = and(_T_395, _T_390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_397 = and(_T_396, _T_392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_398 = and(_T_397, _T_393) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[el2_dec_tlu_ctl.scala 2685:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_411 = and(_T_400, _T_402) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_412 = and(_T_411, _T_404) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_413 = and(_T_412, _T_406) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_414 = and(_T_413, _T_407) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_415 = and(_T_414, _T_408) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_416 = and(_T_415, _T_410) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[el2_dec_tlu_ctl.scala 2686:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_426 = and(_T_417, _T_419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_427 = and(_T_426, _T_421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_428 = and(_T_427, _T_423) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_429 = and(_T_428, _T_424) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_430 = and(_T_429, _T_425) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[el2_dec_tlu_ctl.scala 2687:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_443 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_444 = and(_T_443, _T_435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_445 = and(_T_444, _T_437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_446 = and(_T_445, _T_438) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_447 = and(_T_446, _T_440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_448 = and(_T_447, _T_442) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[el2_dec_tlu_ctl.scala 2688:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_458 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_459 = and(_T_458, _T_453) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_460 = and(_T_459, _T_454) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_461 = and(_T_460, _T_456) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_462 = and(_T_461, _T_457) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[el2_dec_tlu_ctl.scala 2689:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_474 = and(_T_463, _T_465) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_475 = and(_T_474, _T_467) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_476 = and(_T_475, _T_469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_477 = and(_T_476, _T_470) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_478 = and(_T_477, _T_471) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_479 = and(_T_478, _T_473) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[el2_dec_tlu_ctl.scala 2690:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_490 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_491 = and(_T_490, _T_484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_492 = and(_T_491, _T_486) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_493 = and(_T_492, _T_488) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_494 = and(_T_493, _T_489) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme3 <= _T_494 @[el2_dec_tlu_ctl.scala 2691:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_505 = and(_T_495, _T_497) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_506 = and(_T_505, _T_499) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_507 = and(_T_506, _T_500) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_508 = and(_T_507, _T_502) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_509 = and(_T_508, _T_504) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme4 <= _T_509 @[el2_dec_tlu_ctl.scala 2692:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_519 = and(_T_510, _T_512) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_520 = and(_T_519, _T_514) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_521 = and(_T_520, _T_515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_522 = and(_T_521, _T_517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_523 = and(_T_522, _T_518) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme5 <= _T_523 @[el2_dec_tlu_ctl.scala 2693:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_533 = and(_T_524, _T_526) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_534 = and(_T_533, _T_528) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_535 = and(_T_534, _T_529) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_536 = and(_T_535, _T_530) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_537 = and(_T_536, _T_532) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme6 <= _T_537 @[el2_dec_tlu_ctl.scala 2694:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_549 = and(_T_539, _T_540) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_550 = and(_T_549, _T_542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_551 = and(_T_550, _T_544) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_552 = and(_T_551, _T_546) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_553 = and(_T_552, _T_548) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[el2_dec_tlu_ctl.scala 2695:41] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_562 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_563 = and(_T_562, _T_557) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_564 = and(_T_563, _T_559) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_565 = and(_T_564, _T_561) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl0 <= _T_565 @[el2_dec_tlu_ctl.scala 2696:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_572 = and(_T_566, _T_568) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_573 = and(_T_572, _T_569) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_574 = and(_T_573, _T_570) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_575 = and(_T_574, _T_571) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl1 <= _T_575 @[el2_dec_tlu_ctl.scala 2697:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_583 = and(_T_576, _T_578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_584 = and(_T_583, _T_579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_585 = and(_T_584, _T_581) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_586 = and(_T_585, _T_582) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb0 <= _T_586 @[el2_dec_tlu_ctl.scala 2698:49] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_593 = and(_T_587, _T_588) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_594 = and(_T_593, _T_589) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_595 = and(_T_594, _T_590) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_596 = and(_T_595, _T_592) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb1 <= _T_596 @[el2_dec_tlu_ctl.scala 2699:49] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_605 = and(_T_597, _T_599) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_606 = and(_T_605, _T_600) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_607 = and(_T_606, _T_602) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_608 = and(_T_607, _T_604) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[el2_dec_tlu_ctl.scala 2700:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_614 = and(_T_609, _T_610) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_615 = and(_T_614, _T_612) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_616 = and(_T_615, _T_613) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[el2_dec_tlu_ctl.scala 2701:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_624 = and(_T_617, _T_619) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_625 = and(_T_624, _T_621) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_626 = and(_T_625, _T_622) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_627 = and(_T_626, _T_623) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mpmc <= _T_627 @[el2_dec_tlu_ctl.scala 2702:49] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_637 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_638 = and(_T_637, _T_631) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_639 = and(_T_638, _T_633) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_640 = and(_T_639, _T_635) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_641 = and(_T_640, _T_636) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcpc <= _T_641 @[el2_dec_tlu_ctl.scala 2703:49] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_647 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_648 = and(_T_647, _T_644) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_649 = and(_T_648, _T_646) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicpct <= _T_649 @[el2_dec_tlu_ctl.scala 2704:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_656 = and(_T_651, _T_652) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_657 = and(_T_656, _T_653) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_658 = and(_T_657, _T_655) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdeau <= _T_658 @[el2_dec_tlu_ctl.scala 2705:49] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_667 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_668 = and(_T_667, _T_662) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_669 = and(_T_668, _T_664) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_670 = and(_T_669, _T_666) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_micect <= _T_670 @[el2_dec_tlu_ctl.scala 2706:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_676 = and(_T_671, _T_672) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_677 = and(_T_676, _T_674) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_678 = and(_T_677, _T_675) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_miccmect <= _T_678 @[el2_dec_tlu_ctl.scala 2707:49] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_684 = and(_T_679, _T_680) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_685 = and(_T_684, _T_681) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_686 = and(_T_685, _T_683) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdccmect <= _T_686 @[el2_dec_tlu_ctl.scala 2708:49] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_693 = and(_T_687, _T_688) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_694 = and(_T_693, _T_689) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_695 = and(_T_694, _T_690) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_696 = and(_T_695, _T_692) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdht <= _T_696 @[el2_dec_tlu_ctl.scala 2709:49] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_702 = and(_T_697, _T_699) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_703 = and(_T_702, _T_700) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_704 = and(_T_703, _T_701) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdhs <= _T_704 @[el2_dec_tlu_ctl.scala 2710:49] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_716 = and(_T_706, _T_708) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_717 = and(_T_716, _T_709) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_718 = and(_T_717, _T_711) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_719 = and(_T_718, _T_713) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_720 = and(_T_719, _T_715) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicawics <= _T_720 @[el2_dec_tlu_ctl.scala 2711:49] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_726 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_727 = and(_T_726, _T_723) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_728 = and(_T_727, _T_725) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0h <= _T_728 @[el2_dec_tlu_ctl.scala 2712:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_736 = and(_T_729, _T_731) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_737 = and(_T_736, _T_732) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_738 = and(_T_737, _T_734) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_739 = and(_T_738, _T_735) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0 <= _T_739 @[el2_dec_tlu_ctl.scala 2713:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_747 = and(_T_740, _T_741) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_748 = and(_T_747, _T_743) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_749 = and(_T_748, _T_744) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_750 = and(_T_749, _T_746) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad1 <= _T_750 @[el2_dec_tlu_ctl.scala 2714:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_757 = and(_T_751, _T_752) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_758 = and(_T_757, _T_754) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_759 = and(_T_758, _T_755) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_760 = and(_T_759, _T_756) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicago <= _T_760 @[el2_dec_tlu_ctl.scala 2715:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_767 = and(_T_761, _T_762) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_768 = and(_T_767, _T_763) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_769 = and(_T_768, _T_765) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_770 = and(_T_769, _T_766) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_782 = and(_T_772, _T_773) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_783 = and(_T_782, _T_775) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_784 = and(_T_783, _T_777) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_785 = and(_T_784, _T_779) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_786 = and(_T_785, _T_781) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_787 = or(_T_770, _T_786) @[el2_dec_tlu_ctl.scala 2716:73] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_799 = and(_T_789, _T_791) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_800 = and(_T_799, _T_793) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_801 = and(_T_800, _T_795) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_802 = and(_T_801, _T_797) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_803 = and(_T_802, _T_798) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_804 = or(_T_787, _T_803) @[el2_dec_tlu_ctl.scala 2716:113] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_813 = and(_T_805, _T_807) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_814 = and(_T_813, _T_809) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_815 = and(_T_814, _T_810) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_816 = and(_T_815, _T_812) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_817 = or(_T_804, _T_816) @[el2_dec_tlu_ctl.scala 2716:147] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_826 = and(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_827 = and(_T_826, _T_822) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_828 = and(_T_827, _T_823) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_829 = and(_T_828, _T_825) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_830 = or(_T_817, _T_829) @[el2_dec_tlu_ctl.scala 2717:41] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_841 = and(_T_831, _T_833) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_842 = and(_T_841, _T_835) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_843 = and(_T_842, _T_837) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_844 = and(_T_843, _T_839) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_845 = and(_T_844, _T_840) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_846 = or(_T_830, _T_845) @[el2_dec_tlu_ctl.scala 2717:81] + io.csr_pkt.presync <= _T_846 @[el2_dec_tlu_ctl.scala 2716:26] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_853 = and(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_854 = and(_T_853, _T_849) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_855 = and(_T_854, _T_851) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_856 = and(_T_855, _T_852) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_865 = and(_T_858, _T_860) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_866 = and(_T_865, _T_862) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_867 = and(_T_866, _T_863) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_868 = and(_T_867, _T_864) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_869 = or(_T_856, _T_868) @[el2_dec_tlu_ctl.scala 2718:73] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_876 = and(_T_871, _T_872) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_877 = and(_T_876, _T_874) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_878 = and(_T_877, _T_875) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_879 = or(_T_869, _T_878) @[el2_dec_tlu_ctl.scala 2718:113] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_886 = and(_T_880, _T_882) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_887 = and(_T_886, _T_884) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_888 = and(_T_887, _T_885) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_889 = or(_T_879, _T_888) @[el2_dec_tlu_ctl.scala 2718:154] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_904 = and(_T_891, _T_893) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_905 = and(_T_904, _T_895) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_906 = and(_T_905, _T_897) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_907 = and(_T_906, _T_899) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_908 = and(_T_907, _T_901) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_909 = and(_T_908, _T_903) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_910 = or(_T_889, _T_909) @[el2_dec_tlu_ctl.scala 2719:41] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_921 = and(_T_912, _T_913) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_922 = and(_T_921, _T_914) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_923 = and(_T_922, _T_916) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_924 = and(_T_923, _T_918) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_925 = and(_T_924, _T_920) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_926 = or(_T_910, _T_925) @[el2_dec_tlu_ctl.scala 2719:81] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_935 = and(_T_927, _T_929) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_936 = and(_T_935, _T_931) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_937 = and(_T_936, _T_933) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_938 = and(_T_937, _T_934) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_939 = or(_T_926, _T_938) @[el2_dec_tlu_ctl.scala 2719:114] + io.csr_pkt.postsync <= _T_939 @[el2_dec_tlu_ctl.scala 2718:24] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_955 = and(_T_941, _T_942) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_956 = and(_T_955, _T_943) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_957 = and(_T_956, _T_944) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_958 = and(_T_957, _T_945) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_959 = and(_T_958, _T_946) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_960 = and(_T_959, _T_947) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_961 = and(_T_960, _T_949) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_962 = and(_T_961, _T_951) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_963 = and(_T_962, _T_952) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_964 = and(_T_963, _T_954) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_983 = and(_T_966, _T_968) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_984 = and(_T_983, _T_969) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_985 = and(_T_984, _T_970) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_986 = and(_T_985, _T_972) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_987 = and(_T_986, _T_974) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_988 = and(_T_987, _T_976) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_989 = and(_T_988, _T_978) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_990 = and(_T_989, _T_980) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_991 = and(_T_990, _T_982) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_992 = or(_T_964, _T_991) @[el2_dec_tlu_ctl.scala 2721:73] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1008 = and(_T_994, _T_996) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1009 = and(_T_1008, _T_997) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1010 = and(_T_1009, _T_998) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1011 = and(_T_1010, _T_1000) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1012 = and(_T_1011, _T_1002) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1013 = and(_T_1012, _T_1003) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1014 = and(_T_1013, _T_1005) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1015 = and(_T_1014, _T_1007) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1016 = or(_T_992, _T_1015) @[el2_dec_tlu_ctl.scala 2721:121] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1032 = and(_T_1017, _T_1018) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1033 = and(_T_1032, _T_1019) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1034 = and(_T_1033, _T_1020) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1035 = and(_T_1034, _T_1021) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1036 = and(_T_1035, _T_1023) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1037 = and(_T_1036, _T_1025) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1038 = and(_T_1037, _T_1027) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1039 = and(_T_1038, _T_1029) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1040 = and(_T_1039, _T_1031) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1041 = or(_T_1016, _T_1040) @[el2_dec_tlu_ctl.scala 2722:57] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1053 = and(_T_1042, _T_1044) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1054 = and(_T_1053, _T_1045) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1055 = and(_T_1054, _T_1046) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1056 = and(_T_1055, _T_1048) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1057 = and(_T_1056, _T_1050) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1058 = and(_T_1057, _T_1052) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1059 = or(_T_1041, _T_1058) @[el2_dec_tlu_ctl.scala 2722:105] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1073 = and(_T_1061, _T_1062) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1074 = and(_T_1073, _T_1063) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1075 = and(_T_1074, _T_1064) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1076 = and(_T_1075, _T_1065) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1077 = and(_T_1076, _T_1066) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1078 = and(_T_1077, _T_1067) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1079 = and(_T_1078, _T_1068) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1080 = and(_T_1079, _T_1069) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1081 = and(_T_1080, _T_1070) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1082 = and(_T_1081, _T_1071) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1083 = and(_T_1082, _T_1072) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1084 = or(_T_1059, _T_1083) @[el2_dec_tlu_ctl.scala 2723:65] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1098 = and(_T_1086, _T_1087) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1099 = and(_T_1098, _T_1088) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1100 = and(_T_1099, _T_1089) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1101 = and(_T_1100, _T_1090) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1102 = and(_T_1101, _T_1091) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1103 = and(_T_1102, _T_1092) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1104 = and(_T_1103, _T_1093) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1105 = and(_T_1104, _T_1095) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1106 = and(_T_1105, _T_1097) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1107 = or(_T_1084, _T_1106) @[el2_dec_tlu_ctl.scala 2723:113] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1123 = and(_T_1108, _T_1109) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1124 = and(_T_1123, _T_1110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1125 = and(_T_1124, _T_1112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1126 = and(_T_1125, _T_1114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1127 = and(_T_1126, _T_1116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1128 = and(_T_1127, _T_1117) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1129 = and(_T_1128, _T_1119) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1130 = and(_T_1129, _T_1121) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1131 = and(_T_1130, _T_1122) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1132 = or(_T_1107, _T_1131) @[el2_dec_tlu_ctl.scala 2724:57] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1148 = and(_T_1134, _T_1135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1149 = and(_T_1148, _T_1136) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1150 = and(_T_1149, _T_1137) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1151 = and(_T_1150, _T_1138) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1152 = and(_T_1151, _T_1140) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1153 = and(_T_1152, _T_1141) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1154 = and(_T_1153, _T_1143) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1155 = and(_T_1154, _T_1145) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1156 = and(_T_1155, _T_1147) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1157 = or(_T_1132, _T_1156) @[el2_dec_tlu_ctl.scala 2724:113] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1170 = and(_T_1159, _T_1161) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1171 = and(_T_1170, _T_1162) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1172 = and(_T_1171, _T_1163) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1173 = and(_T_1172, _T_1165) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1174 = and(_T_1173, _T_1167) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1175 = and(_T_1174, _T_1168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1176 = and(_T_1175, _T_1169) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1177 = or(_T_1157, _T_1176) @[el2_dec_tlu_ctl.scala 2725:57] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1195 = and(_T_1178, _T_1179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1196 = and(_T_1195, _T_1180) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1197 = and(_T_1196, _T_1182) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1198 = and(_T_1197, _T_1184) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1199 = and(_T_1198, _T_1186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1200 = and(_T_1199, _T_1187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1201 = and(_T_1200, _T_1189) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1202 = and(_T_1201, _T_1190) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1203 = and(_T_1202, _T_1192) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1204 = and(_T_1203, _T_1194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1205 = or(_T_1177, _T_1204) @[el2_dec_tlu_ctl.scala 2725:113] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1219 = and(_T_1207, _T_1208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1220 = and(_T_1219, _T_1209) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1221 = and(_T_1220, _T_1210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1222 = and(_T_1221, _T_1211) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1223 = and(_T_1222, _T_1212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1224 = and(_T_1223, _T_1214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1225 = and(_T_1224, _T_1216) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1226 = and(_T_1225, _T_1217) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1227 = and(_T_1226, _T_1218) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1228 = or(_T_1205, _T_1227) @[el2_dec_tlu_ctl.scala 2726:57] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1242 = and(_T_1230, _T_1231) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1243 = and(_T_1242, _T_1232) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1244 = and(_T_1243, _T_1233) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1245 = and(_T_1244, _T_1234) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1246 = and(_T_1245, _T_1235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1247 = and(_T_1246, _T_1237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1248 = and(_T_1247, _T_1238) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1249 = and(_T_1248, _T_1240) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1250 = and(_T_1249, _T_1241) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1251 = or(_T_1228, _T_1250) @[el2_dec_tlu_ctl.scala 2726:113] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1267 = and(_T_1252, _T_1253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1268 = and(_T_1267, _T_1254) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1269 = and(_T_1268, _T_1256) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1270 = and(_T_1269, _T_1258) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1271 = and(_T_1270, _T_1260) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1272 = and(_T_1271, _T_1261) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1273 = and(_T_1272, _T_1263) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1274 = and(_T_1273, _T_1265) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1275 = and(_T_1274, _T_1266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1276 = or(_T_1251, _T_1275) @[el2_dec_tlu_ctl.scala 2727:57] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1290 = and(_T_1278, _T_1280) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1291 = and(_T_1290, _T_1281) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1292 = and(_T_1291, _T_1282) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1293 = and(_T_1292, _T_1284) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1294 = and(_T_1293, _T_1286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1295 = and(_T_1294, _T_1287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1296 = and(_T_1295, _T_1288) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1297 = and(_T_1296, _T_1289) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1298 = or(_T_1276, _T_1297) @[el2_dec_tlu_ctl.scala 2727:113] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1312 = and(_T_1299, _T_1301) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1313 = and(_T_1312, _T_1302) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1314 = and(_T_1313, _T_1303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1315 = and(_T_1314, _T_1304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1316 = and(_T_1315, _T_1306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1317 = and(_T_1316, _T_1308) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1318 = and(_T_1317, _T_1309) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1319 = and(_T_1318, _T_1311) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1320 = or(_T_1298, _T_1319) @[el2_dec_tlu_ctl.scala 2728:65] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1336 = and(_T_1321, _T_1323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1337 = and(_T_1336, _T_1324) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1338 = and(_T_1337, _T_1325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1339 = and(_T_1338, _T_1326) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1340 = and(_T_1339, _T_1328) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1341 = and(_T_1340, _T_1330) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1342 = and(_T_1341, _T_1331) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1343 = and(_T_1342, _T_1333) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1344 = and(_T_1343, _T_1335) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1345 = or(_T_1320, _T_1344) @[el2_dec_tlu_ctl.scala 2728:121] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1356 = and(_T_1346, _T_1348) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1357 = and(_T_1356, _T_1349) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1358 = and(_T_1357, _T_1350) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1359 = and(_T_1358, _T_1352) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1360 = and(_T_1359, _T_1354) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1361 = and(_T_1360, _T_1355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1362 = or(_T_1345, _T_1361) @[el2_dec_tlu_ctl.scala 2729:57] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1376 = and(_T_1364, _T_1365) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1377 = and(_T_1376, _T_1366) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1378 = and(_T_1377, _T_1367) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1379 = and(_T_1378, _T_1368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1380 = and(_T_1379, _T_1369) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1381 = and(_T_1380, _T_1371) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1382 = and(_T_1381, _T_1372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1383 = and(_T_1382, _T_1374) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1384 = and(_T_1383, _T_1375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1385 = or(_T_1362, _T_1384) @[el2_dec_tlu_ctl.scala 2729:113] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1399 = and(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1400 = and(_T_1399, _T_1389) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1401 = and(_T_1400, _T_1390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1402 = and(_T_1401, _T_1391) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1403 = and(_T_1402, _T_1392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1404 = and(_T_1403, _T_1394) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1405 = and(_T_1404, _T_1396) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1406 = and(_T_1405, _T_1398) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1407 = or(_T_1385, _T_1406) @[el2_dec_tlu_ctl.scala 2730:57] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1422 = and(_T_1409, _T_1410) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1423 = and(_T_1422, _T_1411) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1424 = and(_T_1423, _T_1412) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1425 = and(_T_1424, _T_1413) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1426 = and(_T_1425, _T_1414) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1427 = and(_T_1426, _T_1416) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1428 = and(_T_1427, _T_1418) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1429 = and(_T_1428, _T_1419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1430 = and(_T_1429, _T_1421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1431 = or(_T_1407, _T_1430) @[el2_dec_tlu_ctl.scala 2730:113] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1449 = and(_T_1433, _T_1434) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1450 = and(_T_1449, _T_1435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1451 = and(_T_1450, _T_1436) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1452 = and(_T_1451, _T_1437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1453 = and(_T_1452, _T_1439) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1454 = and(_T_1453, _T_1440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1455 = and(_T_1454, _T_1442) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1456 = and(_T_1455, _T_1444) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1457 = and(_T_1456, _T_1446) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1458 = and(_T_1457, _T_1448) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1459 = or(_T_1431, _T_1458) @[el2_dec_tlu_ctl.scala 2731:57] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1470 = and(_T_1460, _T_1462) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1471 = and(_T_1470, _T_1463) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1472 = and(_T_1471, _T_1464) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1473 = and(_T_1472, _T_1466) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1474 = and(_T_1473, _T_1468) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1475 = and(_T_1474, _T_1469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1476 = or(_T_1459, _T_1475) @[el2_dec_tlu_ctl.scala 2731:105] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1494 = and(_T_1478, _T_1480) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1495 = and(_T_1494, _T_1481) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1496 = and(_T_1495, _T_1482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1497 = and(_T_1496, _T_1484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1498 = and(_T_1497, _T_1485) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1499 = and(_T_1498, _T_1487) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1500 = and(_T_1499, _T_1489) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1501 = and(_T_1500, _T_1491) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1502 = and(_T_1501, _T_1493) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1503 = or(_T_1476, _T_1502) @[el2_dec_tlu_ctl.scala 2732:65] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1522 = and(_T_1505, _T_1507) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1523 = and(_T_1522, _T_1508) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1524 = and(_T_1523, _T_1509) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1525 = and(_T_1524, _T_1511) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1526 = and(_T_1525, _T_1513) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1527 = and(_T_1526, _T_1515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1528 = and(_T_1527, _T_1517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1529 = and(_T_1528, _T_1519) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1530 = and(_T_1529, _T_1521) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1531 = or(_T_1503, _T_1530) @[el2_dec_tlu_ctl.scala 2732:113] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1544 = and(_T_1533, _T_1535) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1545 = and(_T_1544, _T_1536) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1546 = and(_T_1545, _T_1537) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1547 = and(_T_1546, _T_1539) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1548 = and(_T_1547, _T_1541) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1549 = and(_T_1548, _T_1542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1550 = and(_T_1549, _T_1543) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1551 = or(_T_1531, _T_1550) @[el2_dec_tlu_ctl.scala 2733:57] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1562 = and(_T_1552, _T_1554) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1563 = and(_T_1562, _T_1555) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1564 = and(_T_1563, _T_1556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1565 = and(_T_1564, _T_1558) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1566 = and(_T_1565, _T_1560) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1567 = and(_T_1566, _T_1561) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1568 = or(_T_1551, _T_1567) @[el2_dec_tlu_ctl.scala 2733:113] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1581 = and(_T_1570, _T_1572) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1582 = and(_T_1581, _T_1573) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1583 = and(_T_1582, _T_1574) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1584 = and(_T_1583, _T_1576) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1585 = and(_T_1584, _T_1578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1586 = and(_T_1585, _T_1579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1587 = and(_T_1586, _T_1580) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1588 = or(_T_1568, _T_1587) @[el2_dec_tlu_ctl.scala 2734:65] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1599 = and(_T_1589, _T_1591) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1600 = and(_T_1599, _T_1592) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1601 = and(_T_1600, _T_1593) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1602 = and(_T_1601, _T_1595) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1603 = and(_T_1602, _T_1597) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1604 = and(_T_1603, _T_1598) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1605 = or(_T_1588, _T_1604) @[el2_dec_tlu_ctl.scala 2734:121] + io.csr_pkt.legal <= _T_1605 @[el2_dec_tlu_ctl.scala 2721:20] + + module el2_dec_tlu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + + wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] + wire pause_expired_wb : UInt<1> @[el2_dec_tlu_ctl.scala 237:54] + wire take_nmi_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 238:62] + wire exc_or_int_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 239:54] + wire interrupt_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 240:54] + wire tlu_flush_lower_r : UInt<1> @[el2_dec_tlu_ctl.scala 241:54] + wire synchronous_flush_r : UInt<1> @[el2_dec_tlu_ctl.scala 242:62] + wire interrupt_valid_r : UInt<1> @[el2_dec_tlu_ctl.scala 243:54] + wire take_nmi : UInt<1> @[el2_dec_tlu_ctl.scala 244:62] + wire take_reset : UInt<1> @[el2_dec_tlu_ctl.scala 245:70] + wire take_int_timer1_int : UInt<1> @[el2_dec_tlu_ctl.scala 246:62] + wire take_int_timer0_int : UInt<1> @[el2_dec_tlu_ctl.scala 247:62] + wire take_timer_int : UInt<1> @[el2_dec_tlu_ctl.scala 248:62] + wire take_soft_int : UInt<1> @[el2_dec_tlu_ctl.scala 249:62] + wire take_ce_int : UInt<1> @[el2_dec_tlu_ctl.scala 250:70] + wire take_ext_int_start : UInt<1> @[el2_dec_tlu_ctl.scala 251:62] + wire ext_int_freeze : UInt<1> @[el2_dec_tlu_ctl.scala 252:62] + wire ext_int_freeze_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 253:62] + wire take_ext_int_start_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 254:54] + wire take_ext_int_start_d2 : UInt<1> @[el2_dec_tlu_ctl.scala 255:54] + wire take_ext_int_start_d3 : UInt<1> @[el2_dec_tlu_ctl.scala 256:54] + wire fast_int_meicpct : UInt<1> @[el2_dec_tlu_ctl.scala 257:54] + wire ignore_ext_int_due_to_lsu_stall : UInt<1> @[el2_dec_tlu_ctl.scala 258:44] + wire take_ext_int : UInt<1> @[el2_dec_tlu_ctl.scala 259:62] + wire internal_dbg_halt_timers : UInt<1> @[el2_dec_tlu_ctl.scala 260:46] + wire int_timer1_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 261:62] + wire int_timer0_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 262:62] + wire mhwakeup_ready : UInt<1> @[el2_dec_tlu_ctl.scala 263:62] + wire ext_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 264:54] + wire ce_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 265:54] + wire soft_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 266:54] + wire timer_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 267:54] + wire ebreak_to_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 268:54] + wire ebreak_to_debug_mode_r : UInt<1> @[el2_dec_tlu_ctl.scala 269:54] + wire inst_acc_r : UInt<1> @[el2_dec_tlu_ctl.scala 270:70] + wire inst_acc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 271:62] + wire iccm_sbecc_r : UInt<1> @[el2_dec_tlu_ctl.scala 272:62] + wire ic_perr_r : UInt<1> @[el2_dec_tlu_ctl.scala 273:62] + wire fence_i_r : UInt<1> @[el2_dec_tlu_ctl.scala 274:62] + wire ebreak_r : UInt<1> @[el2_dec_tlu_ctl.scala 275:62] + wire ecall_r : UInt<1> @[el2_dec_tlu_ctl.scala 276:62] + wire illegal_r : UInt<1> @[el2_dec_tlu_ctl.scala 277:62] + wire mret_r : UInt<1> @[el2_dec_tlu_ctl.scala 278:62] + wire iccm_repair_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 279:54] + wire rfpc_i0_r : UInt<1> @[el2_dec_tlu_ctl.scala 280:70] + wire tlu_i0_kill_writeb_r : UInt<1> @[el2_dec_tlu_ctl.scala 281:54] + wire lsu_exc_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 282:62] + wire lsu_i0_exc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 283:54] + wire mdseac_locked_f : UInt<1> @[el2_dec_tlu_ctl.scala 284:62] + wire i_cpu_run_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 285:54] + wire cpu_run_ack : UInt<1> @[el2_dec_tlu_ctl.scala 286:70] + wire cpu_halt_status : UInt<1> @[el2_dec_tlu_ctl.scala 287:62] + wire cpu_halt_ack : UInt<1> @[el2_dec_tlu_ctl.scala 288:62] + wire pmu_fw_tlu_halted : UInt<1> @[el2_dec_tlu_ctl.scala 289:54] + wire internal_pmu_fw_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 290:46] + wire pmu_fw_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 291:62] + wire pmu_fw_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 292:62] + wire pmu_fw_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 293:54] + wire int_timer0_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 294:54] + wire int_timer1_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 295:54] + wire trigger_hit_dmode_r : UInt<1> @[el2_dec_tlu_ctl.scala 296:54] + wire i0_trigger_hit_r : UInt<1> @[el2_dec_tlu_ctl.scala 297:54] + wire pause_expired_r : UInt<1> @[el2_dec_tlu_ctl.scala 298:62] + wire dec_tlu_pmu_fw_halted : UInt<1> @[el2_dec_tlu_ctl.scala 299:54] + wire dec_tlu_flush_noredir_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 300:54] + wire halt_taken_f : UInt<1> @[el2_dec_tlu_ctl.scala 301:62] + wire lsu_idle_any_f : UInt<1> @[el2_dec_tlu_ctl.scala 302:62] + wire ifu_miss_state_idle_f : UInt<1> @[el2_dec_tlu_ctl.scala 303:54] + wire dbg_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 304:54] + wire debug_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 305:54] + wire debug_resume_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 306:62] + wire trigger_hit_dmode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 307:54] + wire dcsr_single_step_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 308:54] + wire debug_halt_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 309:54] + wire request_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 310:54] + wire request_debug_mode_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 311:46] + wire dcsr_single_step_running_f : UInt<1> @[el2_dec_tlu_ctl.scala 312:54] + wire dec_tlu_flush_pause_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 313:46] + wire dbg_halt_req_held : UInt<1> @[el2_dec_tlu_ctl.scala 314:54] + wire debug_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 315:62] + wire internal_dbg_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 316:54] + wire core_empty : UInt<1> @[el2_dec_tlu_ctl.scala 317:70] + wire dbg_halt_req_final : UInt<1> @[el2_dec_tlu_ctl.scala 318:62] + wire debug_brkpt_status_ns : UInt<1> @[el2_dec_tlu_ctl.scala 319:54] + wire mpc_debug_halt_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 320:54] + wire mpc_debug_run_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 321:54] + wire mpc_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 322:62] + wire mpc_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 323:54] + wire dbg_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 324:62] + wire dbg_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 325:54] + wire dbg_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 326:54] + wire mpc_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 327:54] + wire nmi_int_detected : UInt<1> @[el2_dec_tlu_ctl.scala 328:54] + wire nmi_lsu_load_type : UInt<1> @[el2_dec_tlu_ctl.scala 329:62] + wire nmi_lsu_store_type : UInt<1> @[el2_dec_tlu_ctl.scala 330:62] + wire reset_delayed : UInt<1> @[el2_dec_tlu_ctl.scala 331:62] + wire debug_mode_status : UInt<1> @[el2_dec_tlu_ctl.scala 332:46] + wire e5_valid : UInt<1> @[el2_dec_tlu_ctl.scala 333:62] + wire ic_perr_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 334:62] + wire iccm_sbecc_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 335:62] + wire npc_r : UInt<31> @[el2_dec_tlu_ctl.scala 337:41] + wire npc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 338:41] + wire mie_ns : UInt<6> @[el2_dec_tlu_ctl.scala 339:41] + wire mepc : UInt<31> @[el2_dec_tlu_ctl.scala 340:41] + wire mdseac_locked_ns : UInt<1> @[el2_dec_tlu_ctl.scala 341:41] + wire force_halt : UInt<1> @[el2_dec_tlu_ctl.scala 342:57] + wire dpc : UInt<31> @[el2_dec_tlu_ctl.scala 343:41] + wire mstatus_mie_ns : UInt<1> @[el2_dec_tlu_ctl.scala 344:41] + wire dec_csr_wen_r_mod : UInt<1> @[el2_dec_tlu_ctl.scala 345:41] + wire fw_halt_req : UInt<1> @[el2_dec_tlu_ctl.scala 346:41] + wire mstatus : UInt<2> @[el2_dec_tlu_ctl.scala 347:41] + wire dcsr : UInt<16> @[el2_dec_tlu_ctl.scala 348:41] + wire mtvec : UInt<31> @[el2_dec_tlu_ctl.scala 349:41] + wire mip : UInt<6> @[el2_dec_tlu_ctl.scala 350:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> @[el2_dec_tlu_ctl.scala 352:41] + node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] + node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] + dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] + inst int_timers of el2_dec_timer_ctl @[el2_dec_tlu_ctl.scala 355:24] + int_timers.clock <= clock + int_timers.reset <= reset + int_timers.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 356:57] + int_timers.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 357:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 358:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 359:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 360:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 361:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 362:49] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 363:49] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 364:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 365:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 366:49] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 367:49] + int_timers.io.dec_pause_state <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 368:41] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 369:41] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[el2_dec_tlu_ctl.scala 370:41] + node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] + node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] + node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 174:81] + _T_8 <= _T_7 @[el2_lib.scala 174:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 174:58] + syncro_ff <= _T_8 @[el2_lib.scala 174:58] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[el2_dec_tlu_ctl.scala 382:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[el2_dec_tlu_ctl.scala 383:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[el2_dec_tlu_ctl.scala 384:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[el2_dec_tlu_ctl.scala 385:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[el2_dec_tlu_ctl.scala 386:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[el2_dec_tlu_ctl.scala 387:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[el2_dec_tlu_ctl.scala 388:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 391:52] + node _T_10 = bits(_T_9, 0, 0) @[el2_dec_tlu_ctl.scala 391:68] + inst rvclkhdr of rvclkhdr_55 @[el2_lib.scala 474:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr.io.en <= _T_10 @[el2_lib.scala 476:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node _T_11 = or(io.lsu_error_pkt_r.exc_valid, lsu_exc_valid_r_d1) @[el2_dec_tlu_ctl.scala 392:65] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 392:86] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 392:102] + inst rvclkhdr_1 of rvclkhdr_56 @[el2_lib.scala 474:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 476:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[el2_dec_tlu_ctl.scala 395:29] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 396:49] + node _T_15 = or(_T_14, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 396:68] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 396:88] + node _T_17 = or(_T_16, reset_delayed) @[el2_dec_tlu_ctl.scala 396:111] + node _T_18 = or(_T_17, pause_expired_r) @[el2_dec_tlu_ctl.scala 396:127] + node _T_19 = or(_T_18, pause_expired_wb) @[el2_dec_tlu_ctl.scala 396:145] + node _T_20 = or(_T_19, ic_perr_r) @[el2_dec_tlu_ctl.scala 396:164] + node _T_21 = or(_T_20, ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 396:176] + node _T_22 = or(_T_21, iccm_sbecc_r) @[el2_dec_tlu_ctl.scala 396:191] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 396:206] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 396:224] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 398:43] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 398:59] + inst rvclkhdr_2 of rvclkhdr_57 @[el2_lib.scala 474:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 476:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[el2_dec_tlu_ctl.scala 399:47] + node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 399:65] + inst rvclkhdr_3 of rvclkhdr_58 @[el2_lib.scala 474:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 476:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 401:72] + iccm_repair_state_d1 <= iccm_repair_state_ns @[el2_dec_tlu_ctl.scala 401:72] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 402:81] + _T_28 <= ic_perr_r @[el2_dec_tlu_ctl.scala 402:81] + ic_perr_r_d1 <= _T_28 @[el2_dec_tlu_ctl.scala 402:49] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 403:89] + _T_29 <= iccm_sbecc_r @[el2_dec_tlu_ctl.scala 403:89] + iccm_sbecc_r_d1 <= _T_29 @[el2_dec_tlu_ctl.scala 403:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 404:89] + _T_30 <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 404:89] + e5_valid <= _T_30 @[el2_dec_tlu_ctl.scala 404:57] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 405:73] + _T_31 <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 405:73] + debug_mode_status <= _T_31 @[el2_dec_tlu_ctl.scala 405:41] + reg lsu_pmu_load_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 406:72] + lsu_pmu_load_external_r <= io.lsu_pmu_load_external_m @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 407:64] + lsu_pmu_store_external_r <= io.lsu_pmu_store_external_m @[el2_dec_tlu_ctl.scala 407:64] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 408:72] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 408:72] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 409:65] + _T_32 <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 409:65] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[el2_dec_tlu_ctl.scala 409:33] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 410:64] + internal_dbg_halt_mode_f2 <= debug_mode_status @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 411:73] + _T_33 <= force_halt @[el2_dec_tlu_ctl.scala 411:73] + io.dec_tlu_force_halt <= _T_33 @[el2_dec_tlu_ctl.scala 411:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 415:33] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 416:80] + reset_detect <= UInt<1>("h01") @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 417:80] + reset_detected <= reset_detect @[el2_dec_tlu_ctl.scala 417:80] + node _T_34 = xor(reset_detect, reset_detected) @[el2_dec_tlu_ctl.scala 418:64] + reset_delayed <= _T_34 @[el2_dec_tlu_ctl.scala 418:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 420:64] + nmi_int_delayed <= nmi_int_sync @[el2_dec_tlu_ctl.scala 420:64] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 421:72] + nmi_int_detected_f <= nmi_int_detected @[el2_dec_tlu_ctl.scala 421:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 422:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 423:64] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 423:64] + node _T_35 = not(mdseac_locked_f) @[el2_dec_tlu_ctl.scala 427:26] + node _T_36 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 427:78] + node nmi_lsu_detected = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 427:43] + node _T_37 = not(nmi_int_delayed) @[el2_dec_tlu_ctl.scala 429:39] + node _T_38 = and(nmi_int_sync, _T_37) @[el2_dec_tlu_ctl.scala 429:37] + node _T_39 = or(_T_38, nmi_lsu_detected) @[el2_dec_tlu_ctl.scala 429:57] + node _T_40 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:100] + node _T_41 = and(nmi_int_detected_f, _T_40) @[el2_dec_tlu_ctl.scala 429:98] + node _T_42 = or(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 429:76] + node _T_43 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 429:159] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[el2_dec_tlu_ctl.scala 429:140] + node _T_45 = or(_T_42, _T_44) @[el2_dec_tlu_ctl.scala 429:116] + nmi_int_detected <= _T_45 @[el2_dec_tlu_ctl.scala 429:20] + node _T_46 = and(nmi_lsu_detected, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 431:42] + node _T_47 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:101] + node _T_48 = and(nmi_int_detected_f, _T_47) @[el2_dec_tlu_ctl.scala 431:99] + node _T_49 = not(_T_48) @[el2_dec_tlu_ctl.scala 431:78] + node _T_50 = and(_T_46, _T_49) @[el2_dec_tlu_ctl.scala 431:76] + node _T_51 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:143] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[el2_dec_tlu_ctl.scala 431:141] + node _T_53 = or(_T_50, _T_52) @[el2_dec_tlu_ctl.scala 431:118] + nmi_lsu_load_type <= _T_53 @[el2_dec_tlu_ctl.scala 431:21] + node _T_54 = and(nmi_lsu_detected, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 432:43] + node _T_55 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:103] + node _T_56 = and(nmi_int_detected_f, _T_55) @[el2_dec_tlu_ctl.scala 432:101] + node _T_57 = not(_T_56) @[el2_dec_tlu_ctl.scala 432:80] + node _T_58 = and(_T_54, _T_57) @[el2_dec_tlu_ctl.scala 432:78] + node _T_59 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:146] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[el2_dec_tlu_ctl.scala 432:144] + node _T_61 = or(_T_58, _T_60) @[el2_dec_tlu_ctl.scala 432:120] + nmi_lsu_store_type <= _T_61 @[el2_dec_tlu_ctl.scala 432:22] + node _T_62 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 439:63] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[el2_dec_tlu_ctl.scala 439:61] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 440:64] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 441:64] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[el2_dec_tlu_ctl.scala 441:64] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 442:81] + _T_63 <= mpc_halt_state_ns @[el2_dec_tlu_ctl.scala 442:81] + mpc_halt_state_f <= _T_63 @[el2_dec_tlu_ctl.scala 442:49] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 443:80] + mpc_run_state_f <= mpc_run_state_ns @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 444:72] + debug_brkpt_status_f <= debug_brkpt_status_ns @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 445:72] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 446:80] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[el2_dec_tlu_ctl.scala 446:80] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 447:81] + _T_64 <= dbg_halt_state_ns @[el2_dec_tlu_ctl.scala 447:81] + dbg_halt_state_f <= _T_64 @[el2_dec_tlu_ctl.scala 447:49] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 448:80] + dbg_run_state_f <= dbg_run_state_ns @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 449:73] + _T_65 <= dec_tlu_mpc_halted_only_ns @[el2_dec_tlu_ctl.scala 449:73] + io.dec_tlu_mpc_halted_only <= _T_65 @[el2_dec_tlu_ctl.scala 449:41] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[el2_dec_tlu_ctl.scala 453:65] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[el2_dec_tlu_ctl.scala 453:63] + node _T_67 = not(mpc_debug_run_req_sync_f) @[el2_dec_tlu_ctl.scala 454:64] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[el2_dec_tlu_ctl.scala 454:62] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[el2_dec_tlu_ctl.scala 456:42] + node _T_69 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 456:93] + node _T_70 = and(reset_delayed, _T_69) @[el2_dec_tlu_ctl.scala 456:91] + node _T_71 = or(_T_68, _T_70) @[el2_dec_tlu_ctl.scala 456:74] + node _T_72 = not(mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 456:119] + node _T_73 = and(_T_71, _T_72) @[el2_dec_tlu_ctl.scala 456:117] + mpc_halt_state_ns <= _T_73 @[el2_dec_tlu_ctl.scala 456:21] + node _T_74 = not(mpc_debug_run_ack_f) @[el2_dec_tlu_ctl.scala 457:74] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[el2_dec_tlu_ctl.scala 457:72] + node _T_76 = or(mpc_run_state_f, _T_75) @[el2_dec_tlu_ctl.scala 457:40] + node _T_77 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 457:127] + node _T_78 = and(debug_mode_status, _T_77) @[el2_dec_tlu_ctl.scala 457:125] + node _T_79 = and(_T_76, _T_78) @[el2_dec_tlu_ctl.scala 457:97] + mpc_run_state_ns <= _T_79 @[el2_dec_tlu_ctl.scala 457:20] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 459:64] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 459:90] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 459:115] + node _T_83 = or(dbg_halt_state_f, _T_82) @[el2_dec_tlu_ctl.scala 459:42] + node _T_84 = not(io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 459:147] + node _T_85 = and(_T_83, _T_84) @[el2_dec_tlu_ctl.scala 459:145] + dbg_halt_state_ns <= _T_85 @[el2_dec_tlu_ctl.scala 459:21] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 460:40] + node _T_87 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 460:91] + node _T_88 = and(debug_mode_status, _T_87) @[el2_dec_tlu_ctl.scala 460:89] + node _T_89 = and(_T_86, _T_88) @[el2_dec_tlu_ctl.scala 460:61] + dbg_run_state_ns <= _T_89 @[el2_dec_tlu_ctl.scala 460:20] + node _T_90 = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 463:33] + node _T_91 = and(_T_90, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 463:51] + dec_tlu_mpc_halted_only_ns <= _T_91 @[el2_dec_tlu_ctl.scala 463:30] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 466:53] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[el2_dec_tlu_ctl.scala 467:47] + node _T_93 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 467:99] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[el2_dec_tlu_ctl.scala 467:97] + node _T_95 = and(_T_92, _T_94) @[el2_dec_tlu_ctl.scala 467:71] + debug_brkpt_status_ns <= _T_95 @[el2_dec_tlu_ctl.scala 467:25] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[el2_dec_tlu_ctl.scala 470:45] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 470:72] + node _T_98 = and(_T_97, core_empty) @[el2_dec_tlu_ctl.scala 470:98] + mpc_debug_halt_ack_ns <= _T_98 @[el2_dec_tlu_ctl.scala 470:25] + node _T_99 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 471:53] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[el2_dec_tlu_ctl.scala 471:51] + node _T_101 = not(mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 471:74] + node _T_102 = and(_T_100, _T_101) @[el2_dec_tlu_ctl.scala 471:72] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 471:123] + node _T_104 = or(_T_102, _T_103) @[el2_dec_tlu_ctl.scala 471:100] + mpc_debug_run_ack_ns <= _T_104 @[el2_dec_tlu_ctl.scala 471:24] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[el2_dec_tlu_ctl.scala 474:25] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[el2_dec_tlu_ctl.scala 475:25] + io.debug_brkpt_status <= debug_brkpt_status_f @[el2_dec_tlu_ctl.scala 476:25] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 479:47] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 479:68] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 480:42] + node _T_107 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 480:65] + node _T_108 = and(_T_106, _T_107) @[el2_dec_tlu_ctl.scala 480:63] + dbg_halt_req_final <= _T_108 @[el2_dec_tlu_ctl.scala 480:22] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 483:44] + node _T_110 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 483:89] + node _T_111 = and(reset_delayed, _T_110) @[el2_dec_tlu_ctl.scala 483:87] + node _T_112 = or(_T_109, _T_111) @[el2_dec_tlu_ctl.scala 483:70] + node _T_113 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 483:115] + node _T_114 = and(_T_112, _T_113) @[el2_dec_tlu_ctl.scala 483:113] + node _T_115 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 483:143] + node debug_halt_req = and(_T_114, _T_115) @[el2_dec_tlu_ctl.scala 483:141] + node _T_116 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 485:26] + node _T_117 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:69] + node _T_118 = and(mpc_run_state_ns, _T_117) @[el2_dec_tlu_ctl.scala 485:67] + node _T_119 = not(mpc_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:111] + node _T_120 = and(dbg_run_state_ns, _T_119) @[el2_dec_tlu_ctl.scala 485:109] + node _T_121 = or(_T_118, _T_120) @[el2_dec_tlu_ctl.scala 485:89] + node debug_resume_req = and(_T_116, _T_121) @[el2_dec_tlu_ctl.scala 485:46] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 490:37] + node _T_123 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 490:60] + node _T_124 = and(_T_122, _T_123) @[el2_dec_tlu_ctl.scala 490:58] + node _T_125 = not(mret_r) @[el2_dec_tlu_ctl.scala 490:83] + node _T_126 = and(_T_124, _T_125) @[el2_dec_tlu_ctl.scala 490:81] + node _T_127 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 490:93] + node _T_128 = and(_T_126, _T_127) @[el2_dec_tlu_ctl.scala 490:91] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[el2_dec_tlu_ctl.scala 490:109] + node _T_130 = and(_T_128, _T_129) @[el2_dec_tlu_ctl.scala 490:107] + node _T_131 = not(take_reset) @[el2_dec_tlu_ctl.scala 490:139] + node take_halt = and(_T_130, _T_131) @[el2_dec_tlu_ctl.scala 490:137] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[el2_dec_tlu_ctl.scala 493:50] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[el2_dec_tlu_ctl.scala 493:48] + node _T_134 = not(take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 493:78] + node _T_135 = and(_T_133, _T_134) @[el2_dec_tlu_ctl.scala 493:76] + node _T_136 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:120] + node _T_137 = and(halt_taken_f, _T_136) @[el2_dec_tlu_ctl.scala 493:118] + node _T_138 = not(pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:140] + node _T_139 = and(_T_137, _T_138) @[el2_dec_tlu_ctl.scala 493:138] + node _T_140 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 493:163] + node _T_141 = and(_T_139, _T_140) @[el2_dec_tlu_ctl.scala 493:161] + node halt_taken = or(_T_135, _T_141) @[el2_dec_tlu_ctl.scala 493:102] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 497:47] + node _T_143 = and(_T_142, io.ifu_miss_state_idle) @[el2_dec_tlu_ctl.scala 497:64] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 497:89] + node _T_145 = not(debug_halt_req) @[el2_dec_tlu_ctl.scala 497:115] + node _T_146 = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 497:113] + node _T_147 = not(debug_halt_req_d1) @[el2_dec_tlu_ctl.scala 497:133] + node _T_148 = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 497:131] + node _T_149 = not(io.dec_div_active) @[el2_dec_tlu_ctl.scala 497:154] + node _T_150 = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 497:152] + node _T_151 = or(force_halt, _T_150) @[el2_dec_tlu_ctl.scala 497:28] + core_empty <= _T_151 @[el2_dec_tlu_ctl.scala 497:14] + node _T_152 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 503:31] + node _T_153 = and(_T_152, debug_halt_req) @[el2_dec_tlu_ctl.scala 503:57] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 503:75] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 503:101] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 503:126] + node _T_156 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 506:105] + node _T_157 = not(_T_156) @[el2_dec_tlu_ctl.scala 506:100] + node _T_158 = and(debug_resume_req_f, _T_157) @[el2_dec_tlu_ctl.scala 506:98] + node _T_159 = not(_T_158) @[el2_dec_tlu_ctl.scala 506:77] + node _T_160 = and(debug_mode_status, _T_159) @[el2_dec_tlu_ctl.scala 506:75] + node _T_161 = or(debug_halt_req_ns, _T_160) @[el2_dec_tlu_ctl.scala 506:47] + internal_dbg_halt_mode <= _T_161 @[el2_dec_tlu_ctl.scala 506:26] + node _T_162 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 508:61] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[el2_dec_tlu_ctl.scala 508:59] + node _T_163 = and(debug_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 513:42] + node _T_164 = and(_T_163, halt_taken) @[el2_dec_tlu_ctl.scala 513:55] + node _T_165 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 513:91] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[el2_dec_tlu_ctl.scala 513:89] + node dbg_tlu_halted = or(_T_164, _T_166) @[el2_dec_tlu_ctl.scala 513:69] + node _T_167 = not(dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 514:67] + node _T_168 = and(debug_halt_req_f, _T_167) @[el2_dec_tlu_ctl.scala 514:65] + node _T_169 = or(enter_debug_halt_req, _T_168) @[el2_dec_tlu_ctl.scala 514:45] + debug_halt_req_ns <= _T_169 @[el2_dec_tlu_ctl.scala 514:21] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 515:43] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[el2_dec_tlu_ctl.scala 515:62] + node _T_171 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 517:55] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[el2_dec_tlu_ctl.scala 517:53] + node _T_173 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 517:84] + node _T_174 = and(_T_172, _T_173) @[el2_dec_tlu_ctl.scala 517:78] + node _T_175 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 517:98] + node dcsr_single_step_done = and(_T_174, _T_175) @[el2_dec_tlu_ctl.scala 517:96] + node _T_176 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 519:60] + node _T_177 = and(debug_resume_req_f, _T_176) @[el2_dec_tlu_ctl.scala 519:54] + node _T_178 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 519:105] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[el2_dec_tlu_ctl.scala 519:103] + node dcsr_single_step_running = or(_T_177, _T_179) @[el2_dec_tlu_ctl.scala 519:73] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 521:47] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 524:51] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 524:106] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[el2_dec_tlu_ctl.scala 524:104] + node request_debug_mode_r = or(_T_180, _T_182) @[el2_dec_tlu_ctl.scala 524:77] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[el2_dec_tlu_ctl.scala 526:58] + node _T_184 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 526:89] + node request_debug_mode_done = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 526:87] + reg _T_185 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 529:73] + _T_185 <= io.dec_tlu_flush_noredir_r @[el2_dec_tlu_ctl.scala 529:73] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[el2_dec_tlu_ctl.scala 529:41] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 530:81] + _T_186 <= halt_taken @[el2_dec_tlu_ctl.scala 530:81] + halt_taken_f <= _T_186 @[el2_dec_tlu_ctl.scala 530:49] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 531:89] + _T_187 <= io.lsu_idle_any @[el2_dec_tlu_ctl.scala 531:89] + lsu_idle_any_f <= _T_187 @[el2_dec_tlu_ctl.scala 531:57] + reg _T_188 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 532:73] + _T_188 <= io.ifu_miss_state_idle @[el2_dec_tlu_ctl.scala 532:73] + ifu_miss_state_idle_f <= _T_188 @[el2_dec_tlu_ctl.scala 532:41] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 533:81] + _T_189 <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 533:81] + dbg_tlu_halted_f <= _T_189 @[el2_dec_tlu_ctl.scala 533:49] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 534:73] + _T_190 <= resume_ack_ns @[el2_dec_tlu_ctl.scala 534:73] + io.dec_tlu_resume_ack <= _T_190 @[el2_dec_tlu_ctl.scala 534:41] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 535:81] + _T_191 <= debug_halt_req_ns @[el2_dec_tlu_ctl.scala 535:81] + debug_halt_req_f <= _T_191 @[el2_dec_tlu_ctl.scala 535:49] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 536:81] + _T_192 <= debug_resume_req @[el2_dec_tlu_ctl.scala 536:81] + debug_resume_req_f <= _T_192 @[el2_dec_tlu_ctl.scala 536:49] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 537:81] + _T_193 <= trigger_hit_dmode_r @[el2_dec_tlu_ctl.scala 537:81] + trigger_hit_dmode_r_d1 <= _T_193 @[el2_dec_tlu_ctl.scala 537:49] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 538:81] + _T_194 <= dcsr_single_step_done @[el2_dec_tlu_ctl.scala 538:81] + dcsr_single_step_done_f <= _T_194 @[el2_dec_tlu_ctl.scala 538:49] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 539:81] + _T_195 <= debug_halt_req @[el2_dec_tlu_ctl.scala 539:81] + debug_halt_req_d1 <= _T_195 @[el2_dec_tlu_ctl.scala 539:49] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 540:73] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 540:73] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 541:73] + dec_pause_state_f <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 541:73] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 542:81] + _T_196 <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 542:81] + request_debug_mode_r_d1 <= _T_196 @[el2_dec_tlu_ctl.scala 542:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 543:73] + _T_197 <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 543:73] + request_debug_mode_done_f <= _T_197 @[el2_dec_tlu_ctl.scala 543:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 544:73] + _T_198 <= dcsr_single_step_running @[el2_dec_tlu_ctl.scala 544:73] + dcsr_single_step_running_f <= _T_198 @[el2_dec_tlu_ctl.scala 544:41] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 545:73] + _T_199 <= io.dec_tlu_flush_pause_r @[el2_dec_tlu_ctl.scala 545:73] + dec_tlu_flush_pause_r_d1 <= _T_199 @[el2_dec_tlu_ctl.scala 545:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 546:81] + _T_200 <= dbg_halt_req_held_ns @[el2_dec_tlu_ctl.scala 546:81] + dbg_halt_req_held <= _T_200 @[el2_dec_tlu_ctl.scala 546:49] + io.dec_tlu_debug_stall <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 549:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 550:41] + io.dec_tlu_debug_mode <= debug_mode_status @[el2_dec_tlu_ctl.scala 551:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[el2_dec_tlu_ctl.scala 552:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 555:56] + node _T_202 = or(take_halt, _T_201) @[el2_dec_tlu_ctl.scala 555:43] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[el2_dec_tlu_ctl.scala 555:82] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 555:129] + node _T_205 = or(_T_203, _T_204) @[el2_dec_tlu_ctl.scala 555:109] + node _T_206 = or(_T_205, take_ext_int_start) @[el2_dec_tlu_ctl.scala 555:152] + io.dec_tlu_flush_noredir_r <= _T_206 @[el2_dec_tlu_ctl.scala 555:30] + io.dec_tlu_flush_extint <= take_ext_int_start @[el2_dec_tlu_ctl.scala 557:27] + node _T_207 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 560:55] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[el2_dec_tlu_ctl.scala 560:53] + node _T_209 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 560:76] + node _T_210 = and(_T_208, _T_209) @[el2_dec_tlu_ctl.scala 560:74] + io.dec_tlu_flush_pause_r <= _T_210 @[el2_dec_tlu_ctl.scala 560:28] + node _T_211 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 562:22] + node _T_212 = and(_T_211, dec_pause_state_f) @[el2_dec_tlu_ctl.scala 562:42] + node _T_213 = or(ext_int_ready, ce_int_ready) @[el2_dec_tlu_ctl.scala 562:80] + node _T_214 = or(_T_213, timer_int_ready) @[el2_dec_tlu_ctl.scala 562:95] + node _T_215 = or(_T_214, soft_int_ready) @[el2_dec_tlu_ctl.scala 562:113] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 562:130] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 562:154] + node _T_218 = or(_T_217, nmi_int_detected) @[el2_dec_tlu_ctl.scala 562:178] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 562:197] + node _T_220 = not(_T_219) @[el2_dec_tlu_ctl.scala 562:64] + node _T_221 = and(_T_212, _T_220) @[el2_dec_tlu_ctl.scala 562:62] + node _T_222 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 562:220] + node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 562:218] + node _T_224 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 562:244] + node _T_225 = and(_T_223, _T_224) @[el2_dec_tlu_ctl.scala 562:242] + node _T_226 = not(pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 562:264] + node _T_227 = and(_T_225, _T_226) @[el2_dec_tlu_ctl.scala 562:262] + node _T_228 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 562:285] + node _T_229 = and(_T_227, _T_228) @[el2_dec_tlu_ctl.scala 562:283] + pause_expired_r <= _T_229 @[el2_dec_tlu_ctl.scala 562:19] + node _T_230 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 564:66] + node _T_231 = and(io.dec_tlu_flush_lower_r, _T_230) @[el2_dec_tlu_ctl.scala 564:60] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 564:103] + node _T_233 = and(_T_231, _T_232) @[el2_dec_tlu_ctl.scala 564:78] + node _T_234 = not(io.dec_tlu_flush_noredir_r) @[el2_dec_tlu_ctl.scala 564:133] + node _T_235 = and(_T_233, _T_234) @[el2_dec_tlu_ctl.scala 564:131] + io.dec_tlu_flush_leak_one_r <= _T_235 @[el2_dec_tlu_ctl.scala 564:31] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 565:70] + node _T_237 = and(io.dec_tlu_flush_lower_r, _T_236) @[el2_dec_tlu_ctl.scala 565:54] + io.dec_tlu_flush_err_r <= _T_237 @[el2_dec_tlu_ctl.scala 565:26] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[el2_dec_tlu_ctl.scala 568:23] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[el2_dec_tlu_ctl.scala 569:36] + io.dec_dbg_cmd_fail <= _T_238 @[el2_dec_tlu_ctl.scala 569:23] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 582:42] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 582:69] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 582:96] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 582:123] + node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] + node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] + node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 583:44] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 583:71] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 583:98] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 583:125] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] + node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 584:44] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 584:71] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 584:98] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 584:125] + node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] + node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] + node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 587:45] + node _T_258 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:71] + node _T_259 = or(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 587:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 587:100] + node _T_261 = and(_T_259, _T_260) @[el2_dec_tlu_ctl.scala 587:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 587:133] + node _T_263 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:159] + node _T_264 = or(_T_262, _T_263) @[el2_dec_tlu_ctl.scala 587:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 587:188] + node _T_266 = and(_T_264, _T_265) @[el2_dec_tlu_ctl.scala 587:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 587:222] + node _T_268 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:248] + node _T_269 = or(_T_267, _T_268) @[el2_dec_tlu_ctl.scala 587:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 587:277] + node _T_271 = and(_T_269, _T_270) @[el2_dec_tlu_ctl.scala 587:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 587:311] + node _T_273 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:337] + node _T_274 = or(_T_272, _T_273) @[el2_dec_tlu_ctl.scala 587:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 587:366] + node _T_276 = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 587:352] + node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] + node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] + node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] + node _T_279 = and(trigger_execute, trigger_data) @[el2_dec_tlu_ctl.scala 590:56] + node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_282 = and(_T_279, _T_281) @[el2_dec_tlu_ctl.scala 590:71] + node _T_283 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 590:128] + node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] + node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_286 = or(_T_282, _T_285) @[el2_dec_tlu_ctl.scala 590:97] + node i0_iside_trigger_has_pri_r = not(_T_286) @[el2_dec_tlu_ctl.scala 590:37] + node _T_287 = and(trigger_store, trigger_data) @[el2_dec_tlu_ctl.scala 593:50] + node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_287, _T_289) @[el2_dec_tlu_ctl.scala 593:65] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[el2_dec_tlu_ctl.scala 593:34] + node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[el2_dec_tlu_ctl.scala 598:83] + node _T_294 = and(_T_292, _T_293) @[el2_dec_tlu_ctl.scala 598:52] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:89] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:118] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[el2_dec_tlu_ctl.scala 598:145] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 600:57] + node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_300 = not(_T_299) @[el2_dec_tlu_ctl.scala 600:22] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[el2_dec_tlu_ctl.scala 600:83] + node _T_301 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:52] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:72] + node _T_303 = not(_T_302) @[el2_dec_tlu_ctl.scala 603:59] + node _T_304 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:102] + node _T_305 = or(_T_303, _T_304) @[el2_dec_tlu_ctl.scala 603:88] + node _T_306 = and(_T_301, _T_305) @[el2_dec_tlu_ctl.scala 603:56] + node _T_307 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:120] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:140] + node _T_309 = not(_T_308) @[el2_dec_tlu_ctl.scala 603:127] + node _T_310 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:170] + node _T_311 = or(_T_309, _T_310) @[el2_dec_tlu_ctl.scala 603:156] + node _T_312 = and(_T_307, _T_311) @[el2_dec_tlu_ctl.scala 603:124] + node _T_313 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:188] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:208] + node _T_315 = not(_T_314) @[el2_dec_tlu_ctl.scala 603:195] + node _T_316 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:238] + node _T_317 = or(_T_315, _T_316) @[el2_dec_tlu_ctl.scala 603:224] + node _T_318 = and(_T_313, _T_317) @[el2_dec_tlu_ctl.scala 603:192] + node _T_319 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:256] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:276] + node _T_321 = not(_T_320) @[el2_dec_tlu_ctl.scala 603:263] + node _T_322 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:306] + node _T_323 = or(_T_321, _T_322) @[el2_dec_tlu_ctl.scala 603:292] + node _T_324 = and(_T_319, _T_323) @[el2_dec_tlu_ctl.scala 603:260] + node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] + node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] + node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 606:56] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[el2_dec_tlu_ctl.scala 608:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 612:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 612:75] + node _T_329 = and(_T_327, _T_328) @[el2_dec_tlu_ctl.scala 612:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 612:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 612:135] + node _T_332 = and(_T_330, _T_331) @[el2_dec_tlu_ctl.scala 612:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 612:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 612:195] + node _T_335 = and(_T_333, _T_334) @[el2_dec_tlu_ctl.scala 612:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 612:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 612:255] + node _T_338 = and(_T_336, _T_337) @[el2_dec_tlu_ctl.scala 612:241] + node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] + node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] + node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] + node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] + node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 615:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[el2_dec_tlu_ctl.scala 618:56] + node i0_trigger_action_r = orr(_T_343) @[el2_dec_tlu_ctl.scala 618:74] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[el2_dec_tlu_ctl.scala 620:44] + trigger_hit_dmode_r <= _T_344 @[el2_dec_tlu_ctl.scala 620:23] + node _T_345 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 622:54] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[el2_dec_tlu_ctl.scala 622:52] + node _T_346 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 649:56] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[el2_dec_tlu_ctl.scala 649:54] + node _T_348 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 649:81] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[el2_dec_tlu_ctl.scala 649:79] + node _T_349 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 650:54] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[el2_dec_tlu_ctl.scala 650:52] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 650:77] + node _T_352 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 650:101] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[el2_dec_tlu_ctl.scala 650:99] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 652:80] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[el2_dec_tlu_ctl.scala 652:80] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 653:72] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[el2_dec_tlu_ctl.scala 653:72] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 654:73] + _T_353 <= cpu_halt_status @[el2_dec_tlu_ctl.scala 654:73] + io.o_cpu_halt_status <= _T_353 @[el2_dec_tlu_ctl.scala 654:41] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 655:81] + _T_354 <= cpu_halt_ack @[el2_dec_tlu_ctl.scala 655:81] + io.o_cpu_halt_ack <= _T_354 @[el2_dec_tlu_ctl.scala 655:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 656:81] + _T_355 <= cpu_run_ack @[el2_dec_tlu_ctl.scala 656:81] + io.o_cpu_run_ack <= _T_355 @[el2_dec_tlu_ctl.scala 656:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 657:66] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[el2_dec_tlu_ctl.scala 657:66] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 658:73] + _T_356 <= pmu_fw_halt_req_ns @[el2_dec_tlu_ctl.scala 658:73] + pmu_fw_halt_req_f <= _T_356 @[el2_dec_tlu_ctl.scala 658:41] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 659:73] + _T_357 <= pmu_fw_tlu_halted @[el2_dec_tlu_ctl.scala 659:73] + pmu_fw_tlu_halted_f <= _T_357 @[el2_dec_tlu_ctl.scala 659:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 660:65] + _T_358 <= int_timer0_int_hold @[el2_dec_tlu_ctl.scala 660:65] + int_timer0_int_hold_f <= _T_358 @[el2_dec_tlu_ctl.scala 660:33] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 661:65] + _T_359 <= int_timer1_int_hold @[el2_dec_tlu_ctl.scala 661:65] + int_timer1_int_hold_f <= _T_359 @[el2_dec_tlu_ctl.scala 661:33] + node _T_360 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 665:51] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[el2_dec_tlu_ctl.scala 665:49] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[el2_dec_tlu_ctl.scala 666:47] + node _T_361 = not(pmu_fw_tlu_halted) @[el2_dec_tlu_ctl.scala 667:71] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[el2_dec_tlu_ctl.scala 667:69] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[el2_dec_tlu_ctl.scala 667:48] + node _T_364 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 667:94] + node _T_365 = and(_T_363, _T_364) @[el2_dec_tlu_ctl.scala 667:92] + pmu_fw_halt_req_ns <= _T_365 @[el2_dec_tlu_ctl.scala 667:22] + node _T_366 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 668:84] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[el2_dec_tlu_ctl.scala 668:82] + node _T_368 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 668:104] + node _T_369 = and(_T_367, _T_368) @[el2_dec_tlu_ctl.scala 668:102] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[el2_dec_tlu_ctl.scala 668:51] + internal_pmu_fw_halt_mode <= _T_370 @[el2_dec_tlu_ctl.scala 668:29] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 671:44] + node _T_372 = and(_T_371, halt_taken) @[el2_dec_tlu_ctl.scala 671:57] + node _T_373 = not(enter_debug_halt_req) @[el2_dec_tlu_ctl.scala 671:72] + node _T_374 = and(_T_372, _T_373) @[el2_dec_tlu_ctl.scala 671:70] + node _T_375 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:120] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[el2_dec_tlu_ctl.scala 671:118] + node _T_377 = or(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 671:95] + node _T_378 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 671:142] + node _T_379 = and(_T_377, _T_378) @[el2_dec_tlu_ctl.scala 671:140] + pmu_fw_tlu_halted <= _T_379 @[el2_dec_tlu_ctl.scala 671:21] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 673:37] + cpu_halt_ack <= _T_380 @[el2_dec_tlu_ctl.scala 673:16] + node _T_381 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:45] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[el2_dec_tlu_ctl.scala 674:43] + node _T_383 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:90] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[el2_dec_tlu_ctl.scala 674:88] + node _T_385 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 674:110] + node _T_386 = and(_T_384, _T_385) @[el2_dec_tlu_ctl.scala 674:108] + node _T_387 = or(_T_382, _T_386) @[el2_dec_tlu_ctl.scala 674:64] + cpu_halt_status <= _T_387 @[el2_dec_tlu_ctl.scala 674:19] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:40] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:87] + node _T_390 = or(_T_388, _T_389) @[el2_dec_tlu_ctl.scala 675:67] + cpu_run_ack <= _T_390 @[el2_dec_tlu_ctl.scala 675:15] + io.o_debug_mode_status <= debug_mode_status @[el2_dec_tlu_ctl.scala 677:26] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[el2_dec_tlu_ctl.scala 680:65] + node _T_392 = or(_T_391, soft_int_ready) @[el2_dec_tlu_ctl.scala 680:83] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 680:100] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 680:124] + node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[el2_dec_tlu_ctl.scala 680:163] + node _T_396 = or(_T_394, _T_395) @[el2_dec_tlu_ctl.scala 680:148] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[el2_dec_tlu_ctl.scala 680:182] + node _T_398 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 680:207] + node _T_399 = and(_T_397, _T_398) @[el2_dec_tlu_ctl.scala 680:205] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[el2_dec_tlu_ctl.scala 680:44] + i_cpu_run_req_d1 <= _T_400 @[el2_dec_tlu_ctl.scala 680:20] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 686:89] + _T_401 <= mdseac_locked_ns @[el2_dec_tlu_ctl.scala 686:89] + mdseac_locked_f <= _T_401 @[el2_dec_tlu_ctl.scala 686:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 687:64] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[el2_dec_tlu_ctl.scala 687:64] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 689:60] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.exc_valid, _T_402) @[el2_dec_tlu_ctl.scala 689:58] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 690:20] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[el2_dec_tlu_ctl.scala 691:39] + node _T_404 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 691:63] + node _T_405 = and(_T_403, _T_404) @[el2_dec_tlu_ctl.scala 691:61] + node _T_406 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 691:83] + node lsu_exc_valid_r = and(_T_405, _T_406) @[el2_dec_tlu_ctl.scala 691:81] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 693:74] + _T_407 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 693:74] + lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] + node _T_408 = not(io.lsu_error_pkt_r.exc_type) @[el2_dec_tlu_ctl.scala 695:39] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.exc_type) @[el2_dec_tlu_ctl.scala 696:37] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.inst_type) @[el2_dec_tlu_ctl.scala 697:37] + node _T_409 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 701:48] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[el2_dec_tlu_ctl.scala 701:46] + node _T_411 = not(io.lsu_error_pkt_r.inst_type) @[el2_dec_tlu_ctl.scala 701:69] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.single_ecc_error) @[el2_dec_tlu_ctl.scala 701:99] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[el2_dec_tlu_ctl.scala 701:66] + node _T_413 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 704:51] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[el2_dec_tlu_ctl.scala 704:49] + node _T_415 = not(lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 704:64] + node _T_416 = and(_T_414, _T_415) @[el2_dec_tlu_ctl.scala 704:62] + node _T_417 = not(inst_acc_r) @[el2_dec_tlu_ctl.scala 704:81] + node _T_418 = and(_T_416, _T_417) @[el2_dec_tlu_ctl.scala 704:78] + node _T_419 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 704:95] + node _T_420 = and(_T_418, _T_419) @[el2_dec_tlu_ctl.scala 704:93] + node _T_421 = not(request_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 704:120] + node _T_422 = and(_T_420, _T_421) @[el2_dec_tlu_ctl.scala 704:118] + node _T_423 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 704:147] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[el2_dec_tlu_ctl.scala 704:145] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 707:37] + node _T_425 = or(_T_424, inst_acc_r) @[el2_dec_tlu_ctl.scala 707:52] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 707:78] + node _T_427 = or(_T_425, _T_426) @[el2_dec_tlu_ctl.scala 707:65] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 707:103] + tlu_i0_kill_writeb_r <= _T_428 @[el2_dec_tlu_ctl.scala 707:24] + io.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 708:28] + node _T_429 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 713:43] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[el2_dec_tlu_ctl.scala 713:41] + node _T_431 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 713:89] + node _T_432 = and(_T_430, _T_431) @[el2_dec_tlu_ctl.scala 713:65] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 713:137] + node _T_434 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 713:158] + node _T_435 = and(_T_433, _T_434) @[el2_dec_tlu_ctl.scala 713:156] + node _T_436 = or(_T_432, _T_435) @[el2_dec_tlu_ctl.scala 713:120] + node _T_437 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 713:182] + node _T_438 = and(_T_436, _T_437) @[el2_dec_tlu_ctl.scala 713:179] + node _T_439 = not(lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 713:203] + node _T_440 = and(_T_438, _T_439) @[el2_dec_tlu_ctl.scala 713:200] + rfpc_i0_r <= _T_440 @[el2_dec_tlu_ctl.scala 713:13] + node _T_441 = not(io.dec_tlu_flush_lower_r) @[el2_dec_tlu_ctl.scala 716:69] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[el2_dec_tlu_ctl.scala 716:67] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[el2_dec_tlu_ctl.scala 716:43] + iccm_repair_state_ns <= _T_443 @[el2_dec_tlu_ctl.scala 716:24] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[el2_dec_tlu_ctl.scala 722:51] + node _T_445 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 722:87] + node _T_446 = or(_T_445, mret_r) @[el2_dec_tlu_ctl.scala 722:97] + node _T_447 = or(_T_446, take_reset) @[el2_dec_tlu_ctl.scala 722:106] + node _T_448 = or(_T_447, illegal_r) @[el2_dec_tlu_ctl.scala 722:119] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 722:175] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[el2_dec_tlu_ctl.scala 722:152] + node _T_451 = or(_T_448, _T_450) @[el2_dec_tlu_ctl.scala 722:131] + node _T_452 = not(_T_451) @[el2_dec_tlu_ctl.scala 722:76] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[el2_dec_tlu_ctl.scala 722:74] + node _T_453 = and(io.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 725:50] + node _T_454 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 725:76] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[el2_dec_tlu_ctl.scala 725:74] + node _T_455 = and(io.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 726:62] + node _T_456 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 726:88] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[el2_dec_tlu_ctl.scala 726:86] + node _T_457 = and(io.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 727:46] + node _T_458 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 727:72] + node _T_459 = and(_T_457, _T_458) @[el2_dec_tlu_ctl.scala 727:70] + node _T_460 = not(io.exu_i0_br_mp_r) @[el2_dec_tlu_ctl.scala 727:97] + node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] + node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] + io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49] + io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41] + io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] + io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49] + io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] + node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] + node _T_466 = and(_T_464, _T_465) @[el2_dec_tlu_ctl.scala 738:88] + node _T_467 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 738:115] + node _T_468 = not(_T_467) @[el2_dec_tlu_ctl.scala 738:110] + node _T_469 = and(_T_466, _T_468) @[el2_dec_tlu_ctl.scala 738:108] + node _T_470 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 738:132] + node _T_471 = and(_T_469, _T_470) @[el2_dec_tlu_ctl.scala 738:130] + ebreak_r <= _T_471 @[el2_dec_tlu_ctl.scala 738:13] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 739:51] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 739:64] + node _T_474 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 739:90] + node _T_475 = and(_T_473, _T_474) @[el2_dec_tlu_ctl.scala 739:88] + node _T_476 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 739:110] + node _T_477 = and(_T_475, _T_476) @[el2_dec_tlu_ctl.scala 739:108] + ecall_r <= _T_477 @[el2_dec_tlu_ctl.scala 739:13] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[el2_dec_tlu_ctl.scala 740:17] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 740:46] + node _T_480 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 740:72] + node _T_481 = and(_T_479, _T_480) @[el2_dec_tlu_ctl.scala 740:70] + node _T_482 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 740:92] + node _T_483 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 740:90] + illegal_r <= _T_483 @[el2_dec_tlu_ctl.scala 740:13] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 741:51] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 741:64] + node _T_486 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 741:90] + node _T_487 = and(_T_485, _T_486) @[el2_dec_tlu_ctl.scala 741:88] + node _T_488 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 741:110] + node _T_489 = and(_T_487, _T_488) @[el2_dec_tlu_ctl.scala 741:108] + mret_r <= _T_489 @[el2_dec_tlu_ctl.scala 741:13] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 743:49] + node _T_491 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 743:75] + node _T_492 = and(_T_490, _T_491) @[el2_dec_tlu_ctl.scala 743:73] + node _T_493 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 743:96] + node _T_494 = and(_T_492, _T_493) @[el2_dec_tlu_ctl.scala 743:94] + fence_i_r <= _T_494 @[el2_dec_tlu_ctl.scala 743:16] + node _T_495 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 744:44] + node _T_496 = and(io.ifu_ic_error_start, _T_495) @[el2_dec_tlu_ctl.scala 744:42] + node _T_497 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 744:66] + node _T_498 = or(_T_497, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 744:92] + node _T_499 = and(_T_496, _T_498) @[el2_dec_tlu_ctl.scala 744:63] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 744:122] + node _T_501 = and(_T_499, _T_500) @[el2_dec_tlu_ctl.scala 744:120] + ic_perr_r <= _T_501 @[el2_dec_tlu_ctl.scala 744:16] + node _T_502 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 745:52] + node _T_503 = and(io.ifu_iccm_rd_ecc_single_err, _T_502) @[el2_dec_tlu_ctl.scala 745:50] + node _T_504 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 745:74] + node _T_505 = or(_T_504, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 745:100] + node _T_506 = and(_T_503, _T_505) @[el2_dec_tlu_ctl.scala 745:71] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 745:130] + node _T_508 = and(_T_506, _T_507) @[el2_dec_tlu_ctl.scala 745:128] + iccm_sbecc_r <= _T_508 @[el2_dec_tlu_ctl.scala 745:16] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 746:48] + inst_acc_r_raw <= _T_509 @[el2_dec_tlu_ctl.scala 746:19] + node _T_510 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 747:34] + node _T_511 = and(inst_acc_r_raw, _T_510) @[el2_dec_tlu_ctl.scala 747:32] + node _T_512 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 747:47] + node _T_513 = and(_T_511, _T_512) @[el2_dec_tlu_ctl.scala 747:45] + inst_acc_r <= _T_513 @[el2_dec_tlu_ctl.scala 747:14] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 750:63] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 750:76] + node _T_516 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 750:102] + node _T_517 = and(_T_515, _T_516) @[el2_dec_tlu_ctl.scala 750:100] + node _T_518 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 750:126] + node _T_519 = and(_T_517, _T_518) @[el2_dec_tlu_ctl.scala 750:120] + node _T_520 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 750:143] + node _T_521 = and(_T_519, _T_520) @[el2_dec_tlu_ctl.scala 750:141] + ebreak_to_debug_mode_r <= _T_521 @[el2_dec_tlu_ctl.scala 750:26] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 752:58] + _T_522 <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 752:58] + ebreak_to_debug_mode_r_d1 <= _T_522 @[el2_dec_tlu_ctl.scala 752:28] + io.dec_tlu_fence_i_r <= fence_i_r @[el2_dec_tlu_ctl.scala 753:24] + node _T_523 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 766:40] + node _T_524 = or(_T_523, illegal_r) @[el2_dec_tlu_ctl.scala 766:50] + node _T_525 = or(_T_524, inst_acc_r) @[el2_dec_tlu_ctl.scala 766:62] + node _T_526 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 766:78] + node _T_527 = and(_T_525, _T_526) @[el2_dec_tlu_ctl.scala 766:76] + node _T_528 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 766:91] + node i0_exception_valid_r = and(_T_527, _T_528) @[el2_dec_tlu_ctl.scala 766:89] + node _T_529 = not(take_nmi) @[el2_dec_tlu_ctl.scala 775:21] + node _T_530 = and(take_ext_int, _T_529) @[el2_dec_tlu_ctl.scala 775:19] + node _T_531 = bits(_T_530, 0, 0) @[el2_dec_tlu_ctl.scala 775:32] + node _T_532 = not(take_nmi) @[el2_dec_tlu_ctl.scala 776:23] + node _T_533 = and(take_timer_int, _T_532) @[el2_dec_tlu_ctl.scala 776:21] + node _T_534 = bits(_T_533, 0, 0) @[el2_dec_tlu_ctl.scala 776:34] + node _T_535 = not(take_nmi) @[el2_dec_tlu_ctl.scala 777:22] + node _T_536 = and(take_soft_int, _T_535) @[el2_dec_tlu_ctl.scala 777:20] + node _T_537 = bits(_T_536, 0, 0) @[el2_dec_tlu_ctl.scala 777:33] + node _T_538 = not(take_nmi) @[el2_dec_tlu_ctl.scala 778:28] + node _T_539 = and(take_int_timer0_int, _T_538) @[el2_dec_tlu_ctl.scala 778:26] + node _T_540 = bits(_T_539, 0, 0) @[el2_dec_tlu_ctl.scala 778:39] + node _T_541 = not(take_nmi) @[el2_dec_tlu_ctl.scala 779:28] + node _T_542 = and(take_int_timer1_int, _T_541) @[el2_dec_tlu_ctl.scala 779:26] + node _T_543 = bits(_T_542, 0, 0) @[el2_dec_tlu_ctl.scala 779:39] + node _T_544 = not(take_nmi) @[el2_dec_tlu_ctl.scala 780:20] + node _T_545 = and(take_ce_int, _T_544) @[el2_dec_tlu_ctl.scala 780:18] + node _T_546 = bits(_T_545, 0, 0) @[el2_dec_tlu_ctl.scala 780:31] + node _T_547 = not(take_nmi) @[el2_dec_tlu_ctl.scala 781:18] + node _T_548 = and(illegal_r, _T_547) @[el2_dec_tlu_ctl.scala 781:16] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 781:29] + node _T_550 = not(take_nmi) @[el2_dec_tlu_ctl.scala 782:17] + node _T_551 = and(ecall_r, _T_550) @[el2_dec_tlu_ctl.scala 782:15] + node _T_552 = bits(_T_551, 0, 0) @[el2_dec_tlu_ctl.scala 782:28] + node _T_553 = not(take_nmi) @[el2_dec_tlu_ctl.scala 783:20] + node _T_554 = and(inst_acc_r, _T_553) @[el2_dec_tlu_ctl.scala 783:18] + node _T_555 = bits(_T_554, 0, 0) @[el2_dec_tlu_ctl.scala 783:31] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 784:16] + node _T_557 = not(take_nmi) @[el2_dec_tlu_ctl.scala 784:38] + node _T_558 = and(_T_556, _T_557) @[el2_dec_tlu_ctl.scala 784:36] + node _T_559 = bits(_T_558, 0, 0) @[el2_dec_tlu_ctl.scala 784:49] + node _T_560 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 785:21] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[el2_dec_tlu_ctl.scala 785:19] + node _T_562 = not(take_nmi) @[el2_dec_tlu_ctl.scala 785:37] + node _T_563 = and(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 785:35] + node _T_564 = bits(_T_563, 0, 0) @[el2_dec_tlu_ctl.scala 785:48] + node _T_565 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 786:22] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[el2_dec_tlu_ctl.scala 786:20] + node _T_567 = not(take_nmi) @[el2_dec_tlu_ctl.scala 786:38] + node _T_568 = and(_T_566, _T_567) @[el2_dec_tlu_ctl.scala 786:36] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 786:49] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 787:19] + node _T_571 = not(take_nmi) @[el2_dec_tlu_ctl.scala 787:36] + node _T_572 = and(_T_570, _T_571) @[el2_dec_tlu_ctl.scala 787:34] + node _T_573 = bits(_T_572, 0, 0) @[el2_dec_tlu_ctl.scala 787:47] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 788:20] + node _T_575 = not(take_nmi) @[el2_dec_tlu_ctl.scala 788:37] + node _T_576 = and(_T_574, _T_575) @[el2_dec_tlu_ctl.scala 788:35] + node _T_577 = bits(_T_576, 0, 0) @[el2_dec_tlu_ctl.scala 788:48] + node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72] + node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72] + node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72] + node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72] + node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72] + node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72] + node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72] + node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72] + node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72] + node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72] + node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72] + node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72] + node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] + wire exc_cause_r : UInt<5> @[Mux.scala 27:72] + exc_cause_r <= _T_604 @[Mux.scala 27:72] + node _T_605 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 799:23] + node _T_606 = and(_T_605, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 799:48] + node _T_607 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 799:70] + node _T_608 = and(_T_606, _T_607) @[el2_dec_tlu_ctl.scala 799:65] + node _T_609 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 799:91] + node _T_610 = and(_T_608, _T_609) @[el2_dec_tlu_ctl.scala 799:83] + mhwakeup_ready <= _T_610 @[el2_dec_tlu_ctl.scala 799:19] + node _T_611 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 800:22] + node _T_612 = and(_T_611, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 800:47] + node _T_613 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 800:69] + node _T_614 = and(_T_612, _T_613) @[el2_dec_tlu_ctl.scala 800:64] + node _T_615 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 800:90] + node _T_616 = and(_T_614, _T_615) @[el2_dec_tlu_ctl.scala 800:82] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[el2_dec_tlu_ctl.scala 800:103] + node _T_618 = and(_T_616, _T_617) @[el2_dec_tlu_ctl.scala 800:101] + ext_int_ready <= _T_618 @[el2_dec_tlu_ctl.scala 800:19] + node _T_619 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 801:22] + node _T_620 = and(_T_619, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 801:47] + node _T_621 = bits(mip, 5, 5) @[el2_dec_tlu_ctl.scala 801:69] + node _T_622 = and(_T_620, _T_621) @[el2_dec_tlu_ctl.scala 801:64] + node _T_623 = bits(mie_ns, 5, 5) @[el2_dec_tlu_ctl.scala 801:90] + node _T_624 = and(_T_622, _T_623) @[el2_dec_tlu_ctl.scala 801:82] + ce_int_ready <= _T_624 @[el2_dec_tlu_ctl.scala 801:19] + node _T_625 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 802:22] + node _T_626 = and(_T_625, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 802:47] + node _T_627 = bits(mip, 0, 0) @[el2_dec_tlu_ctl.scala 802:69] + node _T_628 = and(_T_626, _T_627) @[el2_dec_tlu_ctl.scala 802:64] + node _T_629 = bits(mie_ns, 0, 0) @[el2_dec_tlu_ctl.scala 802:90] + node _T_630 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 802:82] + soft_int_ready <= _T_630 @[el2_dec_tlu_ctl.scala 802:19] + node _T_631 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 803:22] + node _T_632 = and(_T_631, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 803:47] + node _T_633 = bits(mip, 1, 1) @[el2_dec_tlu_ctl.scala 803:69] + node _T_634 = and(_T_632, _T_633) @[el2_dec_tlu_ctl.scala 803:64] + node _T_635 = bits(mie_ns, 1, 1) @[el2_dec_tlu_ctl.scala 803:90] + node _T_636 = and(_T_634, _T_635) @[el2_dec_tlu_ctl.scala 803:82] + timer_int_ready <= _T_636 @[el2_dec_tlu_ctl.scala 803:19] + node _T_637 = bits(mie_ns, 4, 4) @[el2_dec_tlu_ctl.scala 806:56] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[el2_dec_tlu_ctl.scala 806:48] + node _T_638 = bits(mip, 4, 4) @[el2_dec_tlu_ctl.scala 807:33] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 807:46] + node _T_639 = bits(mie_ns, 3, 3) @[el2_dec_tlu_ctl.scala 808:56] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[el2_dec_tlu_ctl.scala 808:48] + node _T_640 = bits(mip, 3, 3) @[el2_dec_tlu_ctl.scala 809:33] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 809:46] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 813:51] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 813:73] + node int_timer_stalled = or(_T_642, mret_r) @[el2_dec_tlu_ctl.scala 813:97] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 815:71] + node _T_644 = and(int_timer0_int_ready, _T_643) @[el2_dec_tlu_ctl.scala 815:48] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 815:120] + node _T_646 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 815:146] + node _T_647 = and(_T_645, _T_646) @[el2_dec_tlu_ctl.scala 815:144] + node _T_648 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 815:167] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 815:165] + node _T_650 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 815:189] + node _T_651 = and(_T_649, _T_650) @[el2_dec_tlu_ctl.scala 815:187] + node _T_652 = or(_T_644, _T_651) @[el2_dec_tlu_ctl.scala 815:93] + int_timer0_int_hold <= _T_652 @[el2_dec_tlu_ctl.scala 815:23] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 816:71] + node _T_654 = and(int_timer1_int_ready, _T_653) @[el2_dec_tlu_ctl.scala 816:48] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 816:120] + node _T_656 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 816:146] + node _T_657 = and(_T_655, _T_656) @[el2_dec_tlu_ctl.scala 816:144] + node _T_658 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 816:167] + node _T_659 = and(_T_657, _T_658) @[el2_dec_tlu_ctl.scala 816:165] + node _T_660 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 816:189] + node _T_661 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 816:187] + node _T_662 = or(_T_654, _T_661) @[el2_dec_tlu_ctl.scala 816:93] + int_timer1_int_hold <= _T_662 @[el2_dec_tlu_ctl.scala 816:23] + node _T_663 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 818:58] + node _T_664 = and(debug_mode_status, _T_663) @[el2_dec_tlu_ctl.scala 818:56] + internal_dbg_halt_timers <= _T_664 @[el2_dec_tlu_ctl.scala 818:28] + node _T_665 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 820:54] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 820:80] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[el2_dec_tlu_ctl.scala 820:51] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 820:106] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 820:134] + node _T_670 = or(_T_669, take_nmi) @[el2_dec_tlu_ctl.scala 820:154] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 820:165] + node _T_672 = or(_T_671, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 820:190] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 820:213] + node _T_674 = or(_T_673, mret_r) @[el2_dec_tlu_ctl.scala 820:237] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 820:246] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 824:58] + _T_675 <= take_ext_int_start @[el2_dec_tlu_ctl.scala 824:58] + take_ext_int_start_d1 <= _T_675 @[el2_dec_tlu_ctl.scala 824:26] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 825:58] + _T_676 <= take_ext_int_start_d1 @[el2_dec_tlu_ctl.scala 825:58] + take_ext_int_start_d2 <= _T_676 @[el2_dec_tlu_ctl.scala 825:26] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 826:58] + _T_677 <= take_ext_int_start_d2 @[el2_dec_tlu_ctl.scala 826:58] + take_ext_int_start_d3 <= _T_677 @[el2_dec_tlu_ctl.scala 826:26] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 827:58] + _T_678 <= ext_int_freeze @[el2_dec_tlu_ctl.scala 827:58] + ext_int_freeze_d1 <= _T_678 @[el2_dec_tlu_ctl.scala 827:26] + node _T_679 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 828:43] + node _T_680 = and(ext_int_ready, _T_679) @[el2_dec_tlu_ctl.scala 828:41] + take_ext_int_start <= _T_680 @[el2_dec_tlu_ctl.scala 828:24] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 830:42] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[el2_dec_tlu_ctl.scala 830:66] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[el2_dec_tlu_ctl.scala 830:90] + ext_int_freeze <= _T_683 @[el2_dec_tlu_ctl.scala 830:20] + node _T_684 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 831:63] + node _T_685 = not(_T_684) @[el2_dec_tlu_ctl.scala 831:45] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[el2_dec_tlu_ctl.scala 831:43] + take_ext_int <= _T_686 @[el2_dec_tlu_ctl.scala 831:18] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 832:45] + fast_int_meicpct <= _T_687 @[el2_dec_tlu_ctl.scala 832:22] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[el2_dec_tlu_ctl.scala 833:37] + node _T_688 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 846:34] + node _T_689 = and(ce_int_ready, _T_688) @[el2_dec_tlu_ctl.scala 846:32] + node _T_690 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 846:51] + node _T_691 = and(_T_689, _T_690) @[el2_dec_tlu_ctl.scala 846:49] + take_ce_int <= _T_691 @[el2_dec_tlu_ctl.scala 846:16] + node _T_692 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 847:37] + node _T_693 = and(soft_int_ready, _T_692) @[el2_dec_tlu_ctl.scala 847:35] + node _T_694 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 847:54] + node _T_695 = and(_T_693, _T_694) @[el2_dec_tlu_ctl.scala 847:52] + node _T_696 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 847:70] + node _T_697 = and(_T_695, _T_696) @[el2_dec_tlu_ctl.scala 847:68] + take_soft_int <= _T_697 @[el2_dec_tlu_ctl.scala 847:17] + node _T_698 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 848:39] + node _T_699 = and(timer_int_ready, _T_698) @[el2_dec_tlu_ctl.scala 848:37] + node _T_700 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 848:57] + node _T_701 = and(_T_699, _T_700) @[el2_dec_tlu_ctl.scala 848:55] + node _T_702 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 848:74] + node _T_703 = and(_T_701, _T_702) @[el2_dec_tlu_ctl.scala 848:72] + node _T_704 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 848:90] + node _T_705 = and(_T_703, _T_704) @[el2_dec_tlu_ctl.scala 848:88] + take_timer_int <= _T_705 @[el2_dec_tlu_ctl.scala 848:18] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 849:48] + node _T_707 = and(_T_706, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 849:73] + node _T_708 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 849:101] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 849:99] + node _T_710 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 849:128] + node _T_711 = and(_T_709, _T_710) @[el2_dec_tlu_ctl.scala 849:126] + node _T_712 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 849:147] + node _T_713 = and(_T_711, _T_712) @[el2_dec_tlu_ctl.scala 849:145] + node _T_714 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 849:165] + node _T_715 = and(_T_713, _T_714) @[el2_dec_tlu_ctl.scala 849:163] + node _T_716 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 849:182] + node _T_717 = and(_T_715, _T_716) @[el2_dec_tlu_ctl.scala 849:180] + node _T_718 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 849:198] + node _T_719 = and(_T_717, _T_718) @[el2_dec_tlu_ctl.scala 849:196] + take_int_timer0_int <= _T_719 @[el2_dec_tlu_ctl.scala 849:23] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 850:48] + node _T_721 = and(_T_720, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 850:73] + node _T_722 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 850:101] + node _T_723 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 850:99] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 850:151] + node _T_725 = not(_T_724) @[el2_dec_tlu_ctl.scala 850:128] + node _T_726 = and(_T_723, _T_725) @[el2_dec_tlu_ctl.scala 850:126] + node _T_727 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 850:178] + node _T_728 = and(_T_726, _T_727) @[el2_dec_tlu_ctl.scala 850:176] + node _T_729 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 850:197] + node _T_730 = and(_T_728, _T_729) @[el2_dec_tlu_ctl.scala 850:195] + node _T_731 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 850:215] + node _T_732 = and(_T_730, _T_731) @[el2_dec_tlu_ctl.scala 850:213] + node _T_733 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 850:232] + node _T_734 = and(_T_732, _T_733) @[el2_dec_tlu_ctl.scala 850:230] + node _T_735 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 850:248] + node _T_736 = and(_T_734, _T_735) @[el2_dec_tlu_ctl.scala 850:246] + take_int_timer1_int <= _T_736 @[el2_dec_tlu_ctl.scala 850:23] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 851:31] + take_reset <= _T_737 @[el2_dec_tlu_ctl.scala 851:14] + node _T_738 = not(internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 852:34] + node _T_739 = and(nmi_int_detected, _T_738) @[el2_dec_tlu_ctl.scala 852:32] + node _T_740 = not(internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 852:64] + node _T_741 = bits(dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 852:124] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[el2_dec_tlu_ctl.scala 852:118] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 852:140] + node _T_744 = and(_T_742, _T_743) @[el2_dec_tlu_ctl.scala 852:138] + node _T_745 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 852:165] + node _T_746 = and(_T_744, _T_745) @[el2_dec_tlu_ctl.scala 852:163] + node _T_747 = or(_T_740, _T_746) @[el2_dec_tlu_ctl.scala 852:88] + node _T_748 = and(_T_739, _T_747) @[el2_dec_tlu_ctl.scala 852:61] + node _T_749 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 852:194] + node _T_750 = and(_T_748, _T_749) @[el2_dec_tlu_ctl.scala 852:192] + node _T_751 = not(mret_r) @[el2_dec_tlu_ctl.scala 852:217] + node _T_752 = and(_T_750, _T_751) @[el2_dec_tlu_ctl.scala 852:215] + node _T_753 = not(take_reset) @[el2_dec_tlu_ctl.scala 852:227] + node _T_754 = and(_T_752, _T_753) @[el2_dec_tlu_ctl.scala 852:225] + node _T_755 = not(ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 852:241] + node _T_756 = and(_T_754, _T_755) @[el2_dec_tlu_ctl.scala 852:239] + node _T_757 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 852:268] + node _T_758 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 852:331] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[el2_dec_tlu_ctl.scala 852:312] + node _T_760 = or(_T_757, _T_759) @[el2_dec_tlu_ctl.scala 852:287] + node _T_761 = and(_T_756, _T_760) @[el2_dec_tlu_ctl.scala 852:265] + take_nmi <= _T_761 @[el2_dec_tlu_ctl.scala 852:12] + node _T_762 = or(take_ext_int, take_timer_int) @[el2_dec_tlu_ctl.scala 855:37] + node _T_763 = or(_T_762, take_soft_int) @[el2_dec_tlu_ctl.scala 855:54] + node _T_764 = or(_T_763, take_nmi) @[el2_dec_tlu_ctl.scala 855:70] + node _T_765 = or(_T_764, take_ce_int) @[el2_dec_tlu_ctl.scala 855:81] + node _T_766 = or(_T_765, take_int_timer0_int) @[el2_dec_tlu_ctl.scala 855:95] + node _T_767 = or(_T_766, take_int_timer1_int) @[el2_dec_tlu_ctl.scala 855:117] + interrupt_valid_r <= _T_767 @[el2_dec_tlu_ctl.scala 855:21] + node _T_768 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 860:33] + node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_772 = add(_T_769, _T_771) @[el2_dec_tlu_ctl.scala 860:50] + node vectored_path = tail(_T_772, 1) @[el2_dec_tlu_ctl.scala 860:50] + node _T_773 = bits(take_nmi, 0, 0) @[el2_dec_tlu_ctl.scala 861:37] + node _T_774 = bits(mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 861:66] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 861:70] + node _T_776 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 861:103] + node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[el2_dec_tlu_ctl.scala 861:60] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[el2_dec_tlu_ctl.scala 861:27] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[el2_dec_tlu_ctl.scala 862:35] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 862:47] + node _T_781 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 862:95] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[el2_dec_tlu_ctl.scala 862:93] + node _T_783 = or(_T_780, _T_782) @[el2_dec_tlu_ctl.scala 862:73] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 862:130] + node _T_785 = and(rfpc_i0_r, _T_784) @[el2_dec_tlu_ctl.scala 862:128] + node sel_npc_r = or(_T_783, _T_785) @[el2_dec_tlu_ctl.scala 862:115] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 863:42] + node sel_npc_resume = or(_T_786, pause_expired_r) @[el2_dec_tlu_ctl.scala 863:65] + node _T_787 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 864:64] + node _T_788 = not(_T_787) @[el2_dec_tlu_ctl.scala 864:46] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[el2_dec_tlu_ctl.scala 864:44] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[el2_dec_tlu_ctl.scala 865:48] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 865:60] + node _T_791 = or(_T_790, fence_i_r) @[el2_dec_tlu_ctl.scala 865:78] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 865:90] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 865:107] + node _T_794 = or(_T_793, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 865:134] + node _T_795 = or(_T_794, sel_npc_resume) @[el2_dec_tlu_ctl.scala 865:156] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[el2_dec_tlu_ctl.scala 865:174] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 865:200] + synchronous_flush_r <= _T_797 @[el2_dec_tlu_ctl.scala 865:24] + node _T_798 = or(interrupt_valid_r, mret_r) @[el2_dec_tlu_ctl.scala 866:42] + node _T_799 = or(_T_798, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 866:51] + node _T_800 = or(_T_799, take_halt) @[el2_dec_tlu_ctl.scala 866:73] + node _T_801 = or(_T_800, take_reset) @[el2_dec_tlu_ctl.scala 866:85] + node _T_802 = or(_T_801, take_ext_int_start) @[el2_dec_tlu_ctl.scala 866:98] + tlu_flush_lower_r <= _T_802 @[el2_dec_tlu_ctl.scala 866:21] + node _T_803 = bits(take_reset, 0, 0) @[el2_dec_tlu_ctl.scala 868:41] + node _T_804 = bits(sel_fir_addr, 0, 0) @[el2_dec_tlu_ctl.scala 869:20] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 870:14] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 870:32] + node _T_807 = and(_T_805, _T_806) @[el2_dec_tlu_ctl.scala 870:21] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:14] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:32] + node _T_810 = and(_T_808, _T_809) @[el2_dec_tlu_ctl.scala 871:21] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:62] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 871:39] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:80] + node _T_814 = and(_T_812, _T_813) @[el2_dec_tlu_ctl.scala 871:69] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 872:23] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 872:44] + node _T_817 = and(_T_815, _T_816) @[el2_dec_tlu_ctl.scala 872:30] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 873:28] + node _T_819 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 873:68] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[el2_dec_tlu_ctl.scala 873:66] + node _T_821 = or(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 873:46] + node _T_822 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 873:93] + node _T_823 = and(_T_821, _T_822) @[el2_dec_tlu_ctl.scala 873:91] + node _T_824 = not(sel_fir_addr) @[el2_dec_tlu_ctl.scala 873:114] + node _T_825 = and(_T_823, _T_824) @[el2_dec_tlu_ctl.scala 873:112] + node _T_826 = bits(_T_825, 0, 0) @[el2_dec_tlu_ctl.scala 873:129] + node _T_827 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 873:149] + node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_829 = not(take_nmi) @[el2_dec_tlu_ctl.scala 874:6] + node _T_830 = and(_T_829, mret_r) @[el2_dec_tlu_ctl.scala 874:16] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_tlu_ctl.scala 874:26] + node _T_832 = not(take_nmi) @[el2_dec_tlu_ctl.scala 875:6] + node _T_833 = and(_T_832, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 875:16] + node _T_834 = bits(_T_833, 0, 0) @[el2_dec_tlu_ctl.scala 875:38] + node _T_835 = not(take_nmi) @[el2_dec_tlu_ctl.scala 876:6] + node _T_836 = and(_T_835, sel_npc_resume) @[el2_dec_tlu_ctl.scala 876:16] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_tlu_ctl.scala 876:34] + node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72] + node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72] + node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72] + node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72] + node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72] + node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] + wire _T_853 : UInt<31> @[Mux.scala 27:72] + _T_853 <= _T_852 @[Mux.scala 27:72] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[el2_dec_tlu_ctl.scala 868:29] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 879:58] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 879:58] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 881:33] + io.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 882:33] + io.dec_tlu_flush_path_r <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 883:33] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[el2_dec_tlu_ctl.scala 886:44] + node _T_855 = or(_T_854, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 886:67] + node _T_856 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 886:109] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[el2_dec_tlu_ctl.scala 886:107] + node exc_or_int_valid_r = or(_T_855, _T_857) @[el2_dec_tlu_ctl.scala 886:87] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 888:82] + _T_858 <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 888:82] + interrupt_valid_r_d1 <= _T_858 @[el2_dec_tlu_ctl.scala 888:49] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 889:81] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 889:81] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 890:82] + _T_859 <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 890:82] + exc_or_int_valid_r_d1 <= _T_859 @[el2_dec_tlu_ctl.scala 890:49] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 891:89] + exc_cause_wb <= exc_cause_r @[el2_dec_tlu_ctl.scala 891:89] + node _T_860 = not(illegal_r) @[el2_dec_tlu_ctl.scala 892:119] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[el2_dec_tlu_ctl.scala 892:117] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 892:97] + i0_valid_wb <= _T_861 @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 893:81] + trigger_hit_r_d1 <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 893:81] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 894:90] + _T_862 <= take_nmi @[el2_dec_tlu_ctl.scala 894:90] + take_nmi_r_d1 <= _T_862 @[el2_dec_tlu_ctl.scala 894:57] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 895:90] + _T_863 <= pause_expired_r @[el2_dec_tlu_ctl.scala 895:90] + pause_expired_wb <= _T_863 @[el2_dec_tlu_ctl.scala 895:57] + inst csr of csr_tlu @[el2_dec_tlu_ctl.scala 897:17] + csr.clock <= clock + csr.reset <= reset + csr.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 898:44] + csr.io.active_clk <= io.active_clk @[el2_dec_tlu_ctl.scala 899:44] + csr.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 900:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 901:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 902:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 903:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[el2_dec_tlu_ctl.scala 904:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[el2_dec_tlu_ctl.scala 905:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec_tlu_ctl.scala 906:44] + csr.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 907:44] + csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec_tlu_ctl.scala 908:44] + csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec_tlu_ctl.scala 909:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec_tlu_ctl.scala 910:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[el2_dec_tlu_ctl.scala 911:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[el2_dec_tlu_ctl.scala 912:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[el2_dec_tlu_ctl.scala 913:44] + csr.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec_tlu_ctl.scala 914:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[el2_dec_tlu_ctl.scala 915:44] + csr.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec_tlu_ctl.scala 916:44] + csr.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec_tlu_ctl.scala 917:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[el2_dec_tlu_ctl.scala 918:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec_tlu_ctl.scala 919:44] + csr.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec_tlu_ctl.scala 920:44] + csr.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec_tlu_ctl.scala 921:44] + csr.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec_tlu_ctl.scala 922:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[el2_dec_tlu_ctl.scala 923:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[el2_dec_tlu_ctl.scala 924:44] + csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec_tlu_ctl.scala 925:44] + csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec_tlu_ctl.scala 926:44] + csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec_tlu_ctl.scala 927:44] + csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec_tlu_ctl.scala 928:44] + csr.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 929:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[el2_dec_tlu_ctl.scala 930:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 931:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[el2_dec_tlu_ctl.scala 932:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[el2_dec_tlu_ctl.scala 933:44] + csr.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 934:44] + csr.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec_tlu_ctl.scala 935:44] + csr.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec_tlu_ctl.scala 936:44] + csr.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec_tlu_ctl.scala 937:44] + csr.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 938:44] + csr.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec_tlu_ctl.scala 939:44] + csr.io.pic_pl <= io.pic_pl @[el2_dec_tlu_ctl.scala 940:44] + csr.io.pic_claimid <= io.pic_claimid @[el2_dec_tlu_ctl.scala 941:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec_tlu_ctl.scala 942:44] + csr.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec_tlu_ctl.scala 943:44] + csr.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec_tlu_ctl.scala 944:44] + csr.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec_tlu_ctl.scala 945:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 946:44] + csr.io.lsu_error_pkt_r.addr <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.mscause <= io.lsu_error_pkt_r.mscause @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.exc_type <= io.lsu_error_pkt_r.exc_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.inst_type <= io.lsu_error_pkt_r.inst_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.single_ecc_error <= io.lsu_error_pkt_r.single_ecc_error @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.exc_valid <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 947:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 948:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 949:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 950:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 951:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 952:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 953:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 954:44] + io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[el2_dec_tlu_ctl.scala 955:44] + io.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[el2_dec_tlu_ctl.scala 956:44] + io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[el2_dec_tlu_ctl.scala 957:44] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[el2_dec_tlu_ctl.scala 958:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec_tlu_ctl.scala 959:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[el2_dec_tlu_ctl.scala 960:44] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec_tlu_ctl.scala 961:44] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_ <= csr.io.trigger_pkt_any[0].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_ <= csr.io.trigger_pkt_any[1].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_ <= csr.io.trigger_pkt_any[2].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_ <= csr.io.trigger_pkt_any[3].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[el2_dec_tlu_ctl.scala 965:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[el2_dec_tlu_ctl.scala 966:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[el2_dec_tlu_ctl.scala 967:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[el2_dec_tlu_ctl.scala 968:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[el2_dec_tlu_ctl.scala 969:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 970:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[el2_dec_tlu_ctl.scala 971:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[el2_dec_tlu_ctl.scala 972:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[el2_dec_tlu_ctl.scala 973:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[el2_dec_tlu_ctl.scala 974:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[el2_dec_tlu_ctl.scala 975:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[el2_dec_tlu_ctl.scala 976:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[el2_dec_tlu_ctl.scala 977:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[el2_dec_tlu_ctl.scala 978:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 979:40] + io.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[el2_dec_tlu_ctl.scala 980:40] + io.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[el2_dec_tlu_ctl.scala 981:40] + io.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[el2_dec_tlu_ctl.scala 982:40] + io.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[el2_dec_tlu_ctl.scala 983:40] + io.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[el2_dec_tlu_ctl.scala 984:40] + io.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[el2_dec_tlu_ctl.scala 985:40] + io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[el2_dec_tlu_ctl.scala 986:40] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 987:44] + csr.io.lsu_error_pkt_r.addr <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.mscause <= io.lsu_error_pkt_r.mscause @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.exc_type <= io.lsu_error_pkt_r.exc_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.inst_type <= io.lsu_error_pkt_r.inst_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.single_ecc_error <= io.lsu_error_pkt_r.single_ecc_error @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.exc_valid <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 988:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 989:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 990:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 991:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 992:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 993:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 994:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 995:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[el2_dec_tlu_ctl.scala 998:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 999:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 1000:39] + csr.io.mret_r <= mret_r @[el2_dec_tlu_ctl.scala 1001:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[el2_dec_tlu_ctl.scala 1002:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[el2_dec_tlu_ctl.scala 1003:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[el2_dec_tlu_ctl.scala 1004:39] + csr.io.timer_int_sync <= timer_int_sync @[el2_dec_tlu_ctl.scala 1005:39] + csr.io.soft_int_sync <= soft_int_sync @[el2_dec_tlu_ctl.scala 1006:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[el2_dec_tlu_ctl.scala 1007:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 1008:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 1009:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec_tlu_ctl.scala 1010:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 1011:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[el2_dec_tlu_ctl.scala 1012:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[el2_dec_tlu_ctl.scala 1013:39] + csr.io.reset_delayed <= reset_delayed @[el2_dec_tlu_ctl.scala 1014:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 1015:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 1016:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1017:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[el2_dec_tlu_ctl.scala 1018:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[el2_dec_tlu_ctl.scala 1019:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1020:39] + csr.io.inst_acc_r <= inst_acc_r @[el2_dec_tlu_ctl.scala 1021:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 1022:39] + csr.io.take_nmi <= take_nmi @[el2_dec_tlu_ctl.scala 1023:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 1024:39] + csr.io.exc_cause_r <= exc_cause_r @[el2_dec_tlu_ctl.scala 1025:39] + csr.io.i0_valid_wb <= i0_valid_wb @[el2_dec_tlu_ctl.scala 1026:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[el2_dec_tlu_ctl.scala 1027:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 1028:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 1029:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[el2_dec_tlu_ctl.scala 1030:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[el2_dec_tlu_ctl.scala 1031:39] + csr.io.exc_cause_wb <= exc_cause_wb @[el2_dec_tlu_ctl.scala 1032:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 1033:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 1034:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 1035:39] + csr.io.ebreak_r <= ebreak_r @[el2_dec_tlu_ctl.scala 1036:39] + csr.io.ecall_r <= ecall_r @[el2_dec_tlu_ctl.scala 1037:39] + csr.io.illegal_r <= illegal_r @[el2_dec_tlu_ctl.scala 1038:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[el2_dec_tlu_ctl.scala 1039:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[el2_dec_tlu_ctl.scala 1040:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[el2_dec_tlu_ctl.scala 1041:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[el2_dec_tlu_ctl.scala 1042:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[el2_dec_tlu_ctl.scala 1043:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[el2_dec_tlu_ctl.scala 1044:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[el2_dec_tlu_ctl.scala 1045:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[el2_dec_tlu_ctl.scala 1046:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[el2_dec_tlu_ctl.scala 1047:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 1048:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 1049:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 1050:51] + csr.io.take_ext_int_start <= take_ext_int_start @[el2_dec_tlu_ctl.scala 1051:47] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[el2_dec_tlu_ctl.scala 1052:43] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[el2_dec_tlu_ctl.scala 1053:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[el2_dec_tlu_ctl.scala 1054:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[el2_dec_tlu_ctl.scala 1055:39] + csr.io.debug_halt_req <= debug_halt_req @[el2_dec_tlu_ctl.scala 1056:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[el2_dec_tlu_ctl.scala 1057:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[el2_dec_tlu_ctl.scala 1058:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[el2_dec_tlu_ctl.scala 1059:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 1060:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 1061:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 1062:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[el2_dec_tlu_ctl.scala 1063:39] + csr.io.take_timer_int <= take_timer_int @[el2_dec_tlu_ctl.scala 1064:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[el2_dec_tlu_ctl.scala 1065:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[el2_dec_tlu_ctl.scala 1066:39] + csr.io.take_ext_int <= take_ext_int @[el2_dec_tlu_ctl.scala 1067:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 1068:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 1069:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 1070:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[el2_dec_tlu_ctl.scala 1071:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[el2_dec_tlu_ctl.scala 1072:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1073:39] + npc_r <= csr.io.npc_r @[el2_dec_tlu_ctl.scala 1075:31] + npc_r_d1 <= csr.io.npc_r_d1 @[el2_dec_tlu_ctl.scala 1076:31] + mie_ns <= csr.io.mie_ns @[el2_dec_tlu_ctl.scala 1077:31] + mepc <= csr.io.mepc @[el2_dec_tlu_ctl.scala 1078:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[el2_dec_tlu_ctl.scala 1079:31] + force_halt <= csr.io.force_halt @[el2_dec_tlu_ctl.scala 1080:31] + dpc <= csr.io.dpc @[el2_dec_tlu_ctl.scala 1081:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[el2_dec_tlu_ctl.scala 1082:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 1083:31] + fw_halt_req <= csr.io.fw_halt_req @[el2_dec_tlu_ctl.scala 1084:31] + mstatus <= csr.io.mstatus @[el2_dec_tlu_ctl.scala 1085:31] + dcsr <= csr.io.dcsr @[el2_dec_tlu_ctl.scala 1086:31] + mtvec <= csr.io.mtvec @[el2_dec_tlu_ctl.scala 1087:31] + mip <= csr.io.mip @[el2_dec_tlu_ctl.scala 1088:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[el2_dec_tlu_ctl.scala 1089:33] + inst csr_read of el2_dec_decode_csr_read @[el2_dec_tlu_ctl.scala 1090:22] + csr_read.clock <= clock + csr_read.reset <= reset + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 1091:31] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1092:10] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1094:44] + node _T_865 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 1094:69] + node _T_866 = and(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 1094:67] + io.dec_tlu_presync_d <= _T_866 @[el2_dec_tlu_ctl.scala 1094:25] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1095:45] + io.dec_tlu_postsync_d <= _T_867 @[el2_dec_tlu_ctl.scala 1095:25] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[el2_dec_tlu_ctl.scala 1098:52] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[el2_dec_tlu_ctl.scala 1098:74] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[el2_dec_tlu_ctl.scala 1098:94] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[el2_dec_tlu_ctl.scala 1098:114] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[el2_dec_tlu_ctl.scala 1098:136] + node _T_873 = not(UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 1098:161] + node conditionally_illegal = and(_T_872, _T_873) @[el2_dec_tlu_ctl.scala 1098:159] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[el2_dec_tlu_ctl.scala 1099:57] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[el2_dec_tlu_ctl.scala 1099:75] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[el2_dec_tlu_ctl.scala 1099:94] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[el2_dec_tlu_ctl.scala 1099:117] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[el2_dec_tlu_ctl.scala 1099:138] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[el2_dec_tlu_ctl.scala 1099:160] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[el2_dec_tlu_ctl.scala 1099:181] + node _T_881 = not(_T_880) @[el2_dec_tlu_ctl.scala 1099:38] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 1099:203] + node _T_883 = and(csr_pkt.legal, _T_882) @[el2_dec_tlu_ctl.scala 1099:35] + node _T_884 = not(fast_int_meicpct) @[el2_dec_tlu_ctl.scala 1099:225] + node _T_885 = and(_T_883, _T_884) @[el2_dec_tlu_ctl.scala 1099:223] + node _T_886 = not(conditionally_illegal) @[el2_dec_tlu_ctl.scala 1099:245] + node valid_csr = and(_T_885, _T_886) @[el2_dec_tlu_ctl.scala 1099:243] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[el2_dec_tlu_ctl.scala 1101:48] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[el2_dec_tlu_ctl.scala 1101:109] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[el2_dec_tlu_ctl.scala 1101:131] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[el2_dec_tlu_ctl.scala 1101:152] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[el2_dec_tlu_ctl.scala 1101:174] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[el2_dec_tlu_ctl.scala 1101:195] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[el2_dec_tlu_ctl.scala 1101:84] + node _T_894 = not(_T_893) @[el2_dec_tlu_ctl.scala 1101:61] + node _T_895 = and(_T_887, _T_894) @[el2_dec_tlu_ctl.scala 1101:59] + io.dec_csr_legal_d <= _T_895 @[el2_dec_tlu_ctl.scala 1101:22] + + module el2_dec_trigger : + input clock : Clock + input reset : Reset + output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + + node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] + wire _T_2 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_2[0] <= _T_1 @[el2_lib.scala 161:48] + _T_2[1] <= _T_1 @[el2_lib.scala 161:48] + _T_2[2] <= _T_1 @[el2_lib.scala 161:48] + _T_2[3] <= _T_1 @[el2_lib.scala 161:48] + _T_2[4] <= _T_1 @[el2_lib.scala 161:48] + _T_2[5] <= _T_1 @[el2_lib.scala 161:48] + _T_2[6] <= _T_1 @[el2_lib.scala 161:48] + _T_2[7] <= _T_1 @[el2_lib.scala 161:48] + _T_2[8] <= _T_1 @[el2_lib.scala 161:48] + _T_2[9] <= _T_1 @[el2_lib.scala 161:48] + _T_2[10] <= _T_1 @[el2_lib.scala 161:48] + _T_2[11] <= _T_1 @[el2_lib.scala 161:48] + _T_2[12] <= _T_1 @[el2_lib.scala 161:48] + _T_2[13] <= _T_1 @[el2_lib.scala 161:48] + _T_2[14] <= _T_1 @[el2_lib.scala 161:48] + _T_2[15] <= _T_1 @[el2_lib.scala 161:48] + _T_2[16] <= _T_1 @[el2_lib.scala 161:48] + _T_2[17] <= _T_1 @[el2_lib.scala 161:48] + _T_2[18] <= _T_1 @[el2_lib.scala 161:48] + _T_2[19] <= _T_1 @[el2_lib.scala 161:48] + _T_2[20] <= _T_1 @[el2_lib.scala 161:48] + _T_2[21] <= _T_1 @[el2_lib.scala 161:48] + _T_2[22] <= _T_1 @[el2_lib.scala 161:48] + _T_2[23] <= _T_1 @[el2_lib.scala 161:48] + _T_2[24] <= _T_1 @[el2_lib.scala 161:48] + _T_2[25] <= _T_1 @[el2_lib.scala 161:48] + _T_2[26] <= _T_1 @[el2_lib.scala 161:48] + _T_2[27] <= _T_1 @[el2_lib.scala 161:48] + _T_2[28] <= _T_1 @[el2_lib.scala 161:48] + _T_2[29] <= _T_1 @[el2_lib.scala 161:48] + _T_2[30] <= _T_1 @[el2_lib.scala 161:48] + _T_2[31] <= _T_1 @[el2_lib.scala 161:48] + node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58] + node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58] + node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_2[4]) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_2[5]) @[Cat.scala 29:58] + node _T_8 = cat(_T_7, _T_2[6]) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, _T_2[7]) @[Cat.scala 29:58] + node _T_10 = cat(_T_9, _T_2[8]) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T_2[9]) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T_2[10]) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T_2[11]) @[Cat.scala 29:58] + node _T_14 = cat(_T_13, _T_2[12]) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T_2[13]) @[Cat.scala 29:58] + node _T_16 = cat(_T_15, _T_2[14]) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, _T_2[15]) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T_2[16]) @[Cat.scala 29:58] + node _T_19 = cat(_T_18, _T_2[17]) @[Cat.scala 29:58] + node _T_20 = cat(_T_19, _T_2[18]) @[Cat.scala 29:58] + node _T_21 = cat(_T_20, _T_2[19]) @[Cat.scala 29:58] + node _T_22 = cat(_T_21, _T_2[20]) @[Cat.scala 29:58] + node _T_23 = cat(_T_22, _T_2[21]) @[Cat.scala 29:58] + node _T_24 = cat(_T_23, _T_2[22]) @[Cat.scala 29:58] + node _T_25 = cat(_T_24, _T_2[23]) @[Cat.scala 29:58] + node _T_26 = cat(_T_25, _T_2[24]) @[Cat.scala 29:58] + node _T_27 = cat(_T_26, _T_2[25]) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, _T_2[26]) @[Cat.scala 29:58] + node _T_29 = cat(_T_28, _T_2[27]) @[Cat.scala 29:58] + node _T_30 = cat(_T_29, _T_2[28]) @[Cat.scala 29:58] + node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58] + node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58] + node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58] + node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58] + node _T_36 = and(_T_33, _T_35) @[el2_dec_trigger.scala 14:127] + node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[el2_dec_trigger.scala 14:93] + wire _T_39 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_39[0] <= _T_38 @[el2_lib.scala 161:48] + _T_39[1] <= _T_38 @[el2_lib.scala 161:48] + _T_39[2] <= _T_38 @[el2_lib.scala 161:48] + _T_39[3] <= _T_38 @[el2_lib.scala 161:48] + _T_39[4] <= _T_38 @[el2_lib.scala 161:48] + _T_39[5] <= _T_38 @[el2_lib.scala 161:48] + _T_39[6] <= _T_38 @[el2_lib.scala 161:48] + _T_39[7] <= _T_38 @[el2_lib.scala 161:48] + _T_39[8] <= _T_38 @[el2_lib.scala 161:48] + _T_39[9] <= _T_38 @[el2_lib.scala 161:48] + _T_39[10] <= _T_38 @[el2_lib.scala 161:48] + _T_39[11] <= _T_38 @[el2_lib.scala 161:48] + _T_39[12] <= _T_38 @[el2_lib.scala 161:48] + _T_39[13] <= _T_38 @[el2_lib.scala 161:48] + _T_39[14] <= _T_38 @[el2_lib.scala 161:48] + _T_39[15] <= _T_38 @[el2_lib.scala 161:48] + _T_39[16] <= _T_38 @[el2_lib.scala 161:48] + _T_39[17] <= _T_38 @[el2_lib.scala 161:48] + _T_39[18] <= _T_38 @[el2_lib.scala 161:48] + _T_39[19] <= _T_38 @[el2_lib.scala 161:48] + _T_39[20] <= _T_38 @[el2_lib.scala 161:48] + _T_39[21] <= _T_38 @[el2_lib.scala 161:48] + _T_39[22] <= _T_38 @[el2_lib.scala 161:48] + _T_39[23] <= _T_38 @[el2_lib.scala 161:48] + _T_39[24] <= _T_38 @[el2_lib.scala 161:48] + _T_39[25] <= _T_38 @[el2_lib.scala 161:48] + _T_39[26] <= _T_38 @[el2_lib.scala 161:48] + _T_39[27] <= _T_38 @[el2_lib.scala 161:48] + _T_39[28] <= _T_38 @[el2_lib.scala 161:48] + _T_39[29] <= _T_38 @[el2_lib.scala 161:48] + _T_39[30] <= _T_38 @[el2_lib.scala 161:48] + _T_39[31] <= _T_38 @[el2_lib.scala 161:48] + node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58] + node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_39[4]) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_39[5]) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_39[6]) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_39[7]) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_39[8]) @[Cat.scala 29:58] + node _T_48 = cat(_T_47, _T_39[9]) @[Cat.scala 29:58] + node _T_49 = cat(_T_48, _T_39[10]) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_39[11]) @[Cat.scala 29:58] + node _T_51 = cat(_T_50, _T_39[12]) @[Cat.scala 29:58] + node _T_52 = cat(_T_51, _T_39[13]) @[Cat.scala 29:58] + node _T_53 = cat(_T_52, _T_39[14]) @[Cat.scala 29:58] + node _T_54 = cat(_T_53, _T_39[15]) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, _T_39[16]) @[Cat.scala 29:58] + node _T_56 = cat(_T_55, _T_39[17]) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, _T_39[18]) @[Cat.scala 29:58] + node _T_58 = cat(_T_57, _T_39[19]) @[Cat.scala 29:58] + node _T_59 = cat(_T_58, _T_39[20]) @[Cat.scala 29:58] + node _T_60 = cat(_T_59, _T_39[21]) @[Cat.scala 29:58] + node _T_61 = cat(_T_60, _T_39[22]) @[Cat.scala 29:58] + node _T_62 = cat(_T_61, _T_39[23]) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, _T_39[24]) @[Cat.scala 29:58] + node _T_64 = cat(_T_63, _T_39[25]) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, _T_39[26]) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, _T_39[27]) @[Cat.scala 29:58] + node _T_67 = cat(_T_66, _T_39[28]) @[Cat.scala 29:58] + node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58] + node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58] + node _T_73 = and(_T_70, _T_72) @[el2_dec_trigger.scala 14:127] + node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[el2_dec_trigger.scala 14:93] + wire _T_76 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_76[0] <= _T_75 @[el2_lib.scala 161:48] + _T_76[1] <= _T_75 @[el2_lib.scala 161:48] + _T_76[2] <= _T_75 @[el2_lib.scala 161:48] + _T_76[3] <= _T_75 @[el2_lib.scala 161:48] + _T_76[4] <= _T_75 @[el2_lib.scala 161:48] + _T_76[5] <= _T_75 @[el2_lib.scala 161:48] + _T_76[6] <= _T_75 @[el2_lib.scala 161:48] + _T_76[7] <= _T_75 @[el2_lib.scala 161:48] + _T_76[8] <= _T_75 @[el2_lib.scala 161:48] + _T_76[9] <= _T_75 @[el2_lib.scala 161:48] + _T_76[10] <= _T_75 @[el2_lib.scala 161:48] + _T_76[11] <= _T_75 @[el2_lib.scala 161:48] + _T_76[12] <= _T_75 @[el2_lib.scala 161:48] + _T_76[13] <= _T_75 @[el2_lib.scala 161:48] + _T_76[14] <= _T_75 @[el2_lib.scala 161:48] + _T_76[15] <= _T_75 @[el2_lib.scala 161:48] + _T_76[16] <= _T_75 @[el2_lib.scala 161:48] + _T_76[17] <= _T_75 @[el2_lib.scala 161:48] + _T_76[18] <= _T_75 @[el2_lib.scala 161:48] + _T_76[19] <= _T_75 @[el2_lib.scala 161:48] + _T_76[20] <= _T_75 @[el2_lib.scala 161:48] + _T_76[21] <= _T_75 @[el2_lib.scala 161:48] + _T_76[22] <= _T_75 @[el2_lib.scala 161:48] + _T_76[23] <= _T_75 @[el2_lib.scala 161:48] + _T_76[24] <= _T_75 @[el2_lib.scala 161:48] + _T_76[25] <= _T_75 @[el2_lib.scala 161:48] + _T_76[26] <= _T_75 @[el2_lib.scala 161:48] + _T_76[27] <= _T_75 @[el2_lib.scala 161:48] + _T_76[28] <= _T_75 @[el2_lib.scala 161:48] + _T_76[29] <= _T_75 @[el2_lib.scala 161:48] + _T_76[30] <= _T_75 @[el2_lib.scala 161:48] + _T_76[31] <= _T_75 @[el2_lib.scala 161:48] + node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58] + node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58] + node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58] + node _T_80 = cat(_T_79, _T_76[4]) @[Cat.scala 29:58] + node _T_81 = cat(_T_80, _T_76[5]) @[Cat.scala 29:58] + node _T_82 = cat(_T_81, _T_76[6]) @[Cat.scala 29:58] + node _T_83 = cat(_T_82, _T_76[7]) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76[8]) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_76[9]) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76[10]) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_76[11]) @[Cat.scala 29:58] + node _T_88 = cat(_T_87, _T_76[12]) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_76[13]) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_76[14]) @[Cat.scala 29:58] + node _T_91 = cat(_T_90, _T_76[15]) @[Cat.scala 29:58] + node _T_92 = cat(_T_91, _T_76[16]) @[Cat.scala 29:58] + node _T_93 = cat(_T_92, _T_76[17]) @[Cat.scala 29:58] + node _T_94 = cat(_T_93, _T_76[18]) @[Cat.scala 29:58] + node _T_95 = cat(_T_94, _T_76[19]) @[Cat.scala 29:58] + node _T_96 = cat(_T_95, _T_76[20]) @[Cat.scala 29:58] + node _T_97 = cat(_T_96, _T_76[21]) @[Cat.scala 29:58] + node _T_98 = cat(_T_97, _T_76[22]) @[Cat.scala 29:58] + node _T_99 = cat(_T_98, _T_76[23]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_76[24]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_76[25]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_76[26]) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_76[27]) @[Cat.scala 29:58] + node _T_104 = cat(_T_103, _T_76[28]) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58] + node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58] + node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58] + node _T_110 = and(_T_107, _T_109) @[el2_dec_trigger.scala 14:127] + node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[el2_dec_trigger.scala 14:93] + wire _T_113 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_113[0] <= _T_112 @[el2_lib.scala 161:48] + _T_113[1] <= _T_112 @[el2_lib.scala 161:48] + _T_113[2] <= _T_112 @[el2_lib.scala 161:48] + _T_113[3] <= _T_112 @[el2_lib.scala 161:48] + _T_113[4] <= _T_112 @[el2_lib.scala 161:48] + _T_113[5] <= _T_112 @[el2_lib.scala 161:48] + _T_113[6] <= _T_112 @[el2_lib.scala 161:48] + _T_113[7] <= _T_112 @[el2_lib.scala 161:48] + _T_113[8] <= _T_112 @[el2_lib.scala 161:48] + _T_113[9] <= _T_112 @[el2_lib.scala 161:48] + _T_113[10] <= _T_112 @[el2_lib.scala 161:48] + _T_113[11] <= _T_112 @[el2_lib.scala 161:48] + _T_113[12] <= _T_112 @[el2_lib.scala 161:48] + _T_113[13] <= _T_112 @[el2_lib.scala 161:48] + _T_113[14] <= _T_112 @[el2_lib.scala 161:48] + _T_113[15] <= _T_112 @[el2_lib.scala 161:48] + _T_113[16] <= _T_112 @[el2_lib.scala 161:48] + _T_113[17] <= _T_112 @[el2_lib.scala 161:48] + _T_113[18] <= _T_112 @[el2_lib.scala 161:48] + _T_113[19] <= _T_112 @[el2_lib.scala 161:48] + _T_113[20] <= _T_112 @[el2_lib.scala 161:48] + _T_113[21] <= _T_112 @[el2_lib.scala 161:48] + _T_113[22] <= _T_112 @[el2_lib.scala 161:48] + _T_113[23] <= _T_112 @[el2_lib.scala 161:48] + _T_113[24] <= _T_112 @[el2_lib.scala 161:48] + _T_113[25] <= _T_112 @[el2_lib.scala 161:48] + _T_113[26] <= _T_112 @[el2_lib.scala 161:48] + _T_113[27] <= _T_112 @[el2_lib.scala 161:48] + _T_113[28] <= _T_112 @[el2_lib.scala 161:48] + _T_113[29] <= _T_112 @[el2_lib.scala 161:48] + _T_113[30] <= _T_112 @[el2_lib.scala 161:48] + _T_113[31] <= _T_112 @[el2_lib.scala 161:48] + node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_113[4]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_113[5]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_113[6]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_113[7]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_113[8]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_113[9]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_113[10]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_113[11]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_113[12]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_113[13]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_113[14]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113[15]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_113[16]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_113[17]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_113[18]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_113[19]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_113[20]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_113[21]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_113[22]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_113[23]) @[Cat.scala 29:58] + node _T_137 = cat(_T_136, _T_113[24]) @[Cat.scala 29:58] + node _T_138 = cat(_T_137, _T_113[25]) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_113[26]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_113[27]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_113[28]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58] + node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58] + node _T_147 = and(_T_144, _T_146) @[el2_dec_trigger.scala 14:127] + wire dec_i0_match_data : UInt<32>[4] @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[0] <= _T_36 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[1] <= _T_73 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] + node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] + node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_150 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 232:45] + node _T_152 = not(_T_151) @[el2_lib.scala 232:39] + node _T_153 = and(_T_149, _T_152) @[el2_lib.scala 232:37] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[el2_lib.scala 233:60] + node _T_156 = eq(_T_154, _T_155) @[el2_lib.scala 233:52] + node _T_157 = or(_T_153, _T_156) @[el2_lib.scala 233:41] + _T_150[0] <= _T_157 @[el2_lib.scala 233:18] + node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_159 = andr(_T_158) @[el2_lib.scala 235:36] + node _T_160 = and(_T_159, _T_153) @[el2_lib.scala 235:41] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[el2_lib.scala 235:86] + node _T_163 = eq(_T_161, _T_162) @[el2_lib.scala 235:78] + node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[el2_lib.scala 235:23] + _T_150[1] <= _T_164 @[el2_lib.scala 235:17] + node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_166 = andr(_T_165) @[el2_lib.scala 235:36] + node _T_167 = and(_T_166, _T_153) @[el2_lib.scala 235:41] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[el2_lib.scala 235:86] + node _T_170 = eq(_T_168, _T_169) @[el2_lib.scala 235:78] + node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[el2_lib.scala 235:23] + _T_150[2] <= _T_171 @[el2_lib.scala 235:17] + node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_173 = andr(_T_172) @[el2_lib.scala 235:36] + node _T_174 = and(_T_173, _T_153) @[el2_lib.scala 235:41] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[el2_lib.scala 235:86] + node _T_177 = eq(_T_175, _T_176) @[el2_lib.scala 235:78] + node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[el2_lib.scala 235:23] + _T_150[3] <= _T_178 @[el2_lib.scala 235:17] + node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_180 = andr(_T_179) @[el2_lib.scala 235:36] + node _T_181 = and(_T_180, _T_153) @[el2_lib.scala 235:41] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[el2_lib.scala 235:86] + node _T_184 = eq(_T_182, _T_183) @[el2_lib.scala 235:78] + node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[el2_lib.scala 235:23] + _T_150[4] <= _T_185 @[el2_lib.scala 235:17] + node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_187 = andr(_T_186) @[el2_lib.scala 235:36] + node _T_188 = and(_T_187, _T_153) @[el2_lib.scala 235:41] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[el2_lib.scala 235:86] + node _T_191 = eq(_T_189, _T_190) @[el2_lib.scala 235:78] + node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[el2_lib.scala 235:23] + _T_150[5] <= _T_192 @[el2_lib.scala 235:17] + node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_194 = andr(_T_193) @[el2_lib.scala 235:36] + node _T_195 = and(_T_194, _T_153) @[el2_lib.scala 235:41] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[el2_lib.scala 235:86] + node _T_198 = eq(_T_196, _T_197) @[el2_lib.scala 235:78] + node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[el2_lib.scala 235:23] + _T_150[6] <= _T_199 @[el2_lib.scala 235:17] + node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_201 = andr(_T_200) @[el2_lib.scala 235:36] + node _T_202 = and(_T_201, _T_153) @[el2_lib.scala 235:41] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[el2_lib.scala 235:86] + node _T_205 = eq(_T_203, _T_204) @[el2_lib.scala 235:78] + node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[el2_lib.scala 235:23] + _T_150[7] <= _T_206 @[el2_lib.scala 235:17] + node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_208 = andr(_T_207) @[el2_lib.scala 235:36] + node _T_209 = and(_T_208, _T_153) @[el2_lib.scala 235:41] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[el2_lib.scala 235:86] + node _T_212 = eq(_T_210, _T_211) @[el2_lib.scala 235:78] + node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[el2_lib.scala 235:23] + _T_150[8] <= _T_213 @[el2_lib.scala 235:17] + node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_215 = andr(_T_214) @[el2_lib.scala 235:36] + node _T_216 = and(_T_215, _T_153) @[el2_lib.scala 235:41] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[el2_lib.scala 235:86] + node _T_219 = eq(_T_217, _T_218) @[el2_lib.scala 235:78] + node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[el2_lib.scala 235:23] + _T_150[9] <= _T_220 @[el2_lib.scala 235:17] + node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_222 = andr(_T_221) @[el2_lib.scala 235:36] + node _T_223 = and(_T_222, _T_153) @[el2_lib.scala 235:41] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[el2_lib.scala 235:86] + node _T_226 = eq(_T_224, _T_225) @[el2_lib.scala 235:78] + node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[el2_lib.scala 235:23] + _T_150[10] <= _T_227 @[el2_lib.scala 235:17] + node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_229 = andr(_T_228) @[el2_lib.scala 235:36] + node _T_230 = and(_T_229, _T_153) @[el2_lib.scala 235:41] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[el2_lib.scala 235:86] + node _T_233 = eq(_T_231, _T_232) @[el2_lib.scala 235:78] + node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[el2_lib.scala 235:23] + _T_150[11] <= _T_234 @[el2_lib.scala 235:17] + node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_236 = andr(_T_235) @[el2_lib.scala 235:36] + node _T_237 = and(_T_236, _T_153) @[el2_lib.scala 235:41] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[el2_lib.scala 235:86] + node _T_240 = eq(_T_238, _T_239) @[el2_lib.scala 235:78] + node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[el2_lib.scala 235:23] + _T_150[12] <= _T_241 @[el2_lib.scala 235:17] + node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_243 = andr(_T_242) @[el2_lib.scala 235:36] + node _T_244 = and(_T_243, _T_153) @[el2_lib.scala 235:41] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[el2_lib.scala 235:86] + node _T_247 = eq(_T_245, _T_246) @[el2_lib.scala 235:78] + node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[el2_lib.scala 235:23] + _T_150[13] <= _T_248 @[el2_lib.scala 235:17] + node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_250 = andr(_T_249) @[el2_lib.scala 235:36] + node _T_251 = and(_T_250, _T_153) @[el2_lib.scala 235:41] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[el2_lib.scala 235:86] + node _T_254 = eq(_T_252, _T_253) @[el2_lib.scala 235:78] + node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[el2_lib.scala 235:23] + _T_150[14] <= _T_255 @[el2_lib.scala 235:17] + node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_257 = andr(_T_256) @[el2_lib.scala 235:36] + node _T_258 = and(_T_257, _T_153) @[el2_lib.scala 235:41] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[el2_lib.scala 235:86] + node _T_261 = eq(_T_259, _T_260) @[el2_lib.scala 235:78] + node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[el2_lib.scala 235:23] + _T_150[15] <= _T_262 @[el2_lib.scala 235:17] + node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_264 = andr(_T_263) @[el2_lib.scala 235:36] + node _T_265 = and(_T_264, _T_153) @[el2_lib.scala 235:41] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[el2_lib.scala 235:86] + node _T_268 = eq(_T_266, _T_267) @[el2_lib.scala 235:78] + node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[el2_lib.scala 235:23] + _T_150[16] <= _T_269 @[el2_lib.scala 235:17] + node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_271 = andr(_T_270) @[el2_lib.scala 235:36] + node _T_272 = and(_T_271, _T_153) @[el2_lib.scala 235:41] + node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[el2_lib.scala 235:86] + node _T_275 = eq(_T_273, _T_274) @[el2_lib.scala 235:78] + node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[el2_lib.scala 235:23] + _T_150[17] <= _T_276 @[el2_lib.scala 235:17] + node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_278 = andr(_T_277) @[el2_lib.scala 235:36] + node _T_279 = and(_T_278, _T_153) @[el2_lib.scala 235:41] + node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[el2_lib.scala 235:86] + node _T_282 = eq(_T_280, _T_281) @[el2_lib.scala 235:78] + node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[el2_lib.scala 235:23] + _T_150[18] <= _T_283 @[el2_lib.scala 235:17] + node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_285 = andr(_T_284) @[el2_lib.scala 235:36] + node _T_286 = and(_T_285, _T_153) @[el2_lib.scala 235:41] + node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[el2_lib.scala 235:86] + node _T_289 = eq(_T_287, _T_288) @[el2_lib.scala 235:78] + node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[el2_lib.scala 235:23] + _T_150[19] <= _T_290 @[el2_lib.scala 235:17] + node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_292 = andr(_T_291) @[el2_lib.scala 235:36] + node _T_293 = and(_T_292, _T_153) @[el2_lib.scala 235:41] + node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[el2_lib.scala 235:86] + node _T_296 = eq(_T_294, _T_295) @[el2_lib.scala 235:78] + node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[el2_lib.scala 235:23] + _T_150[20] <= _T_297 @[el2_lib.scala 235:17] + node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_299 = andr(_T_298) @[el2_lib.scala 235:36] + node _T_300 = and(_T_299, _T_153) @[el2_lib.scala 235:41] + node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[el2_lib.scala 235:86] + node _T_303 = eq(_T_301, _T_302) @[el2_lib.scala 235:78] + node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[el2_lib.scala 235:23] + _T_150[21] <= _T_304 @[el2_lib.scala 235:17] + node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_306 = andr(_T_305) @[el2_lib.scala 235:36] + node _T_307 = and(_T_306, _T_153) @[el2_lib.scala 235:41] + node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[el2_lib.scala 235:86] + node _T_310 = eq(_T_308, _T_309) @[el2_lib.scala 235:78] + node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[el2_lib.scala 235:23] + _T_150[22] <= _T_311 @[el2_lib.scala 235:17] + node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_313 = andr(_T_312) @[el2_lib.scala 235:36] + node _T_314 = and(_T_313, _T_153) @[el2_lib.scala 235:41] + node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[el2_lib.scala 235:86] + node _T_317 = eq(_T_315, _T_316) @[el2_lib.scala 235:78] + node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[el2_lib.scala 235:23] + _T_150[23] <= _T_318 @[el2_lib.scala 235:17] + node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_320 = andr(_T_319) @[el2_lib.scala 235:36] + node _T_321 = and(_T_320, _T_153) @[el2_lib.scala 235:41] + node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[el2_lib.scala 235:86] + node _T_324 = eq(_T_322, _T_323) @[el2_lib.scala 235:78] + node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[el2_lib.scala 235:23] + _T_150[24] <= _T_325 @[el2_lib.scala 235:17] + node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_327 = andr(_T_326) @[el2_lib.scala 235:36] + node _T_328 = and(_T_327, _T_153) @[el2_lib.scala 235:41] + node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[el2_lib.scala 235:86] + node _T_331 = eq(_T_329, _T_330) @[el2_lib.scala 235:78] + node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[el2_lib.scala 235:23] + _T_150[25] <= _T_332 @[el2_lib.scala 235:17] + node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_334 = andr(_T_333) @[el2_lib.scala 235:36] + node _T_335 = and(_T_334, _T_153) @[el2_lib.scala 235:41] + node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[el2_lib.scala 235:86] + node _T_338 = eq(_T_336, _T_337) @[el2_lib.scala 235:78] + node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[el2_lib.scala 235:23] + _T_150[26] <= _T_339 @[el2_lib.scala 235:17] + node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_341 = andr(_T_340) @[el2_lib.scala 235:36] + node _T_342 = and(_T_341, _T_153) @[el2_lib.scala 235:41] + node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[el2_lib.scala 235:86] + node _T_345 = eq(_T_343, _T_344) @[el2_lib.scala 235:78] + node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[el2_lib.scala 235:23] + _T_150[27] <= _T_346 @[el2_lib.scala 235:17] + node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_348 = andr(_T_347) @[el2_lib.scala 235:36] + node _T_349 = and(_T_348, _T_153) @[el2_lib.scala 235:41] + node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[el2_lib.scala 235:86] + node _T_352 = eq(_T_350, _T_351) @[el2_lib.scala 235:78] + node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[el2_lib.scala 235:23] + _T_150[28] <= _T_353 @[el2_lib.scala 235:17] + node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_355 = andr(_T_354) @[el2_lib.scala 235:36] + node _T_356 = and(_T_355, _T_153) @[el2_lib.scala 235:41] + node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[el2_lib.scala 235:86] + node _T_359 = eq(_T_357, _T_358) @[el2_lib.scala 235:78] + node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[el2_lib.scala 235:23] + _T_150[29] <= _T_360 @[el2_lib.scala 235:17] + node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_362 = andr(_T_361) @[el2_lib.scala 235:36] + node _T_363 = and(_T_362, _T_153) @[el2_lib.scala 235:41] + node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[el2_lib.scala 235:86] + node _T_366 = eq(_T_364, _T_365) @[el2_lib.scala 235:78] + node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[el2_lib.scala 235:23] + _T_150[30] <= _T_367 @[el2_lib.scala 235:17] + node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_369 = andr(_T_368) @[el2_lib.scala 235:36] + node _T_370 = and(_T_369, _T_153) @[el2_lib.scala 235:41] + node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[el2_lib.scala 235:86] + node _T_373 = eq(_T_371, _T_372) @[el2_lib.scala 235:78] + node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[el2_lib.scala 235:23] + _T_150[31] <= _T_374 @[el2_lib.scala 235:17] + node _T_375 = cat(_T_150[1], _T_150[0]) @[el2_lib.scala 236:14] + node _T_376 = cat(_T_150[3], _T_150[2]) @[el2_lib.scala 236:14] + node _T_377 = cat(_T_376, _T_375) @[el2_lib.scala 236:14] + node _T_378 = cat(_T_150[5], _T_150[4]) @[el2_lib.scala 236:14] + node _T_379 = cat(_T_150[7], _T_150[6]) @[el2_lib.scala 236:14] + node _T_380 = cat(_T_379, _T_378) @[el2_lib.scala 236:14] + node _T_381 = cat(_T_380, _T_377) @[el2_lib.scala 236:14] + node _T_382 = cat(_T_150[9], _T_150[8]) @[el2_lib.scala 236:14] + node _T_383 = cat(_T_150[11], _T_150[10]) @[el2_lib.scala 236:14] + node _T_384 = cat(_T_383, _T_382) @[el2_lib.scala 236:14] + node _T_385 = cat(_T_150[13], _T_150[12]) @[el2_lib.scala 236:14] + node _T_386 = cat(_T_150[15], _T_150[14]) @[el2_lib.scala 236:14] + node _T_387 = cat(_T_386, _T_385) @[el2_lib.scala 236:14] + node _T_388 = cat(_T_387, _T_384) @[el2_lib.scala 236:14] + node _T_389 = cat(_T_388, _T_381) @[el2_lib.scala 236:14] + node _T_390 = cat(_T_150[17], _T_150[16]) @[el2_lib.scala 236:14] + node _T_391 = cat(_T_150[19], _T_150[18]) @[el2_lib.scala 236:14] + node _T_392 = cat(_T_391, _T_390) @[el2_lib.scala 236:14] + node _T_393 = cat(_T_150[21], _T_150[20]) @[el2_lib.scala 236:14] + node _T_394 = cat(_T_150[23], _T_150[22]) @[el2_lib.scala 236:14] + node _T_395 = cat(_T_394, _T_393) @[el2_lib.scala 236:14] + node _T_396 = cat(_T_395, _T_392) @[el2_lib.scala 236:14] + node _T_397 = cat(_T_150[25], _T_150[24]) @[el2_lib.scala 236:14] + node _T_398 = cat(_T_150[27], _T_150[26]) @[el2_lib.scala 236:14] + node _T_399 = cat(_T_398, _T_397) @[el2_lib.scala 236:14] + node _T_400 = cat(_T_150[29], _T_150[28]) @[el2_lib.scala 236:14] + node _T_401 = cat(_T_150[31], _T_150[30]) @[el2_lib.scala 236:14] + node _T_402 = cat(_T_401, _T_400) @[el2_lib.scala 236:14] + node _T_403 = cat(_T_402, _T_399) @[el2_lib.scala 236:14] + node _T_404 = cat(_T_403, _T_396) @[el2_lib.scala 236:14] + node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 236:14] + node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] + node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] + node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_409 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 232:45] + node _T_411 = not(_T_410) @[el2_lib.scala 232:39] + node _T_412 = and(_T_408, _T_411) @[el2_lib.scala 232:37] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[el2_lib.scala 233:60] + node _T_415 = eq(_T_413, _T_414) @[el2_lib.scala 233:52] + node _T_416 = or(_T_412, _T_415) @[el2_lib.scala 233:41] + _T_409[0] <= _T_416 @[el2_lib.scala 233:18] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_418 = andr(_T_417) @[el2_lib.scala 235:36] + node _T_419 = and(_T_418, _T_412) @[el2_lib.scala 235:41] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[el2_lib.scala 235:86] + node _T_422 = eq(_T_420, _T_421) @[el2_lib.scala 235:78] + node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[el2_lib.scala 235:23] + _T_409[1] <= _T_423 @[el2_lib.scala 235:17] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_425 = andr(_T_424) @[el2_lib.scala 235:36] + node _T_426 = and(_T_425, _T_412) @[el2_lib.scala 235:41] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[el2_lib.scala 235:86] + node _T_429 = eq(_T_427, _T_428) @[el2_lib.scala 235:78] + node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[el2_lib.scala 235:23] + _T_409[2] <= _T_430 @[el2_lib.scala 235:17] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_432 = andr(_T_431) @[el2_lib.scala 235:36] + node _T_433 = and(_T_432, _T_412) @[el2_lib.scala 235:41] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[el2_lib.scala 235:86] + node _T_436 = eq(_T_434, _T_435) @[el2_lib.scala 235:78] + node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[el2_lib.scala 235:23] + _T_409[3] <= _T_437 @[el2_lib.scala 235:17] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_439 = andr(_T_438) @[el2_lib.scala 235:36] + node _T_440 = and(_T_439, _T_412) @[el2_lib.scala 235:41] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[el2_lib.scala 235:86] + node _T_443 = eq(_T_441, _T_442) @[el2_lib.scala 235:78] + node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[el2_lib.scala 235:23] + _T_409[4] <= _T_444 @[el2_lib.scala 235:17] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_446 = andr(_T_445) @[el2_lib.scala 235:36] + node _T_447 = and(_T_446, _T_412) @[el2_lib.scala 235:41] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[el2_lib.scala 235:86] + node _T_450 = eq(_T_448, _T_449) @[el2_lib.scala 235:78] + node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[el2_lib.scala 235:23] + _T_409[5] <= _T_451 @[el2_lib.scala 235:17] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_453 = andr(_T_452) @[el2_lib.scala 235:36] + node _T_454 = and(_T_453, _T_412) @[el2_lib.scala 235:41] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[el2_lib.scala 235:86] + node _T_457 = eq(_T_455, _T_456) @[el2_lib.scala 235:78] + node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[el2_lib.scala 235:23] + _T_409[6] <= _T_458 @[el2_lib.scala 235:17] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_460 = andr(_T_459) @[el2_lib.scala 235:36] + node _T_461 = and(_T_460, _T_412) @[el2_lib.scala 235:41] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[el2_lib.scala 235:86] + node _T_464 = eq(_T_462, _T_463) @[el2_lib.scala 235:78] + node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[el2_lib.scala 235:23] + _T_409[7] <= _T_465 @[el2_lib.scala 235:17] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_467 = andr(_T_466) @[el2_lib.scala 235:36] + node _T_468 = and(_T_467, _T_412) @[el2_lib.scala 235:41] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[el2_lib.scala 235:86] + node _T_471 = eq(_T_469, _T_470) @[el2_lib.scala 235:78] + node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[el2_lib.scala 235:23] + _T_409[8] <= _T_472 @[el2_lib.scala 235:17] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_474 = andr(_T_473) @[el2_lib.scala 235:36] + node _T_475 = and(_T_474, _T_412) @[el2_lib.scala 235:41] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[el2_lib.scala 235:86] + node _T_478 = eq(_T_476, _T_477) @[el2_lib.scala 235:78] + node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[el2_lib.scala 235:23] + _T_409[9] <= _T_479 @[el2_lib.scala 235:17] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_481 = andr(_T_480) @[el2_lib.scala 235:36] + node _T_482 = and(_T_481, _T_412) @[el2_lib.scala 235:41] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[el2_lib.scala 235:86] + node _T_485 = eq(_T_483, _T_484) @[el2_lib.scala 235:78] + node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[el2_lib.scala 235:23] + _T_409[10] <= _T_486 @[el2_lib.scala 235:17] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_488 = andr(_T_487) @[el2_lib.scala 235:36] + node _T_489 = and(_T_488, _T_412) @[el2_lib.scala 235:41] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[el2_lib.scala 235:86] + node _T_492 = eq(_T_490, _T_491) @[el2_lib.scala 235:78] + node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[el2_lib.scala 235:23] + _T_409[11] <= _T_493 @[el2_lib.scala 235:17] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_495 = andr(_T_494) @[el2_lib.scala 235:36] + node _T_496 = and(_T_495, _T_412) @[el2_lib.scala 235:41] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[el2_lib.scala 235:86] + node _T_499 = eq(_T_497, _T_498) @[el2_lib.scala 235:78] + node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[el2_lib.scala 235:23] + _T_409[12] <= _T_500 @[el2_lib.scala 235:17] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_502 = andr(_T_501) @[el2_lib.scala 235:36] + node _T_503 = and(_T_502, _T_412) @[el2_lib.scala 235:41] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[el2_lib.scala 235:86] + node _T_506 = eq(_T_504, _T_505) @[el2_lib.scala 235:78] + node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[el2_lib.scala 235:23] + _T_409[13] <= _T_507 @[el2_lib.scala 235:17] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_509 = andr(_T_508) @[el2_lib.scala 235:36] + node _T_510 = and(_T_509, _T_412) @[el2_lib.scala 235:41] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[el2_lib.scala 235:86] + node _T_513 = eq(_T_511, _T_512) @[el2_lib.scala 235:78] + node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[el2_lib.scala 235:23] + _T_409[14] <= _T_514 @[el2_lib.scala 235:17] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_516 = andr(_T_515) @[el2_lib.scala 235:36] + node _T_517 = and(_T_516, _T_412) @[el2_lib.scala 235:41] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[el2_lib.scala 235:86] + node _T_520 = eq(_T_518, _T_519) @[el2_lib.scala 235:78] + node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[el2_lib.scala 235:23] + _T_409[15] <= _T_521 @[el2_lib.scala 235:17] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_523 = andr(_T_522) @[el2_lib.scala 235:36] + node _T_524 = and(_T_523, _T_412) @[el2_lib.scala 235:41] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[el2_lib.scala 235:86] + node _T_527 = eq(_T_525, _T_526) @[el2_lib.scala 235:78] + node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[el2_lib.scala 235:23] + _T_409[16] <= _T_528 @[el2_lib.scala 235:17] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_530 = andr(_T_529) @[el2_lib.scala 235:36] + node _T_531 = and(_T_530, _T_412) @[el2_lib.scala 235:41] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[el2_lib.scala 235:86] + node _T_534 = eq(_T_532, _T_533) @[el2_lib.scala 235:78] + node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[el2_lib.scala 235:23] + _T_409[17] <= _T_535 @[el2_lib.scala 235:17] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_537 = andr(_T_536) @[el2_lib.scala 235:36] + node _T_538 = and(_T_537, _T_412) @[el2_lib.scala 235:41] + node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[el2_lib.scala 235:86] + node _T_541 = eq(_T_539, _T_540) @[el2_lib.scala 235:78] + node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[el2_lib.scala 235:23] + _T_409[18] <= _T_542 @[el2_lib.scala 235:17] + node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_544 = andr(_T_543) @[el2_lib.scala 235:36] + node _T_545 = and(_T_544, _T_412) @[el2_lib.scala 235:41] + node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[el2_lib.scala 235:86] + node _T_548 = eq(_T_546, _T_547) @[el2_lib.scala 235:78] + node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[el2_lib.scala 235:23] + _T_409[19] <= _T_549 @[el2_lib.scala 235:17] + node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_551 = andr(_T_550) @[el2_lib.scala 235:36] + node _T_552 = and(_T_551, _T_412) @[el2_lib.scala 235:41] + node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[el2_lib.scala 235:86] + node _T_555 = eq(_T_553, _T_554) @[el2_lib.scala 235:78] + node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[el2_lib.scala 235:23] + _T_409[20] <= _T_556 @[el2_lib.scala 235:17] + node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_558 = andr(_T_557) @[el2_lib.scala 235:36] + node _T_559 = and(_T_558, _T_412) @[el2_lib.scala 235:41] + node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[el2_lib.scala 235:86] + node _T_562 = eq(_T_560, _T_561) @[el2_lib.scala 235:78] + node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[el2_lib.scala 235:23] + _T_409[21] <= _T_563 @[el2_lib.scala 235:17] + node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_565 = andr(_T_564) @[el2_lib.scala 235:36] + node _T_566 = and(_T_565, _T_412) @[el2_lib.scala 235:41] + node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[el2_lib.scala 235:86] + node _T_569 = eq(_T_567, _T_568) @[el2_lib.scala 235:78] + node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[el2_lib.scala 235:23] + _T_409[22] <= _T_570 @[el2_lib.scala 235:17] + node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_572 = andr(_T_571) @[el2_lib.scala 235:36] + node _T_573 = and(_T_572, _T_412) @[el2_lib.scala 235:41] + node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[el2_lib.scala 235:86] + node _T_576 = eq(_T_574, _T_575) @[el2_lib.scala 235:78] + node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[el2_lib.scala 235:23] + _T_409[23] <= _T_577 @[el2_lib.scala 235:17] + node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_579 = andr(_T_578) @[el2_lib.scala 235:36] + node _T_580 = and(_T_579, _T_412) @[el2_lib.scala 235:41] + node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[el2_lib.scala 235:86] + node _T_583 = eq(_T_581, _T_582) @[el2_lib.scala 235:78] + node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[el2_lib.scala 235:23] + _T_409[24] <= _T_584 @[el2_lib.scala 235:17] + node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_586 = andr(_T_585) @[el2_lib.scala 235:36] + node _T_587 = and(_T_586, _T_412) @[el2_lib.scala 235:41] + node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[el2_lib.scala 235:86] + node _T_590 = eq(_T_588, _T_589) @[el2_lib.scala 235:78] + node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[el2_lib.scala 235:23] + _T_409[25] <= _T_591 @[el2_lib.scala 235:17] + node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_593 = andr(_T_592) @[el2_lib.scala 235:36] + node _T_594 = and(_T_593, _T_412) @[el2_lib.scala 235:41] + node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[el2_lib.scala 235:86] + node _T_597 = eq(_T_595, _T_596) @[el2_lib.scala 235:78] + node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[el2_lib.scala 235:23] + _T_409[26] <= _T_598 @[el2_lib.scala 235:17] + node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_600 = andr(_T_599) @[el2_lib.scala 235:36] + node _T_601 = and(_T_600, _T_412) @[el2_lib.scala 235:41] + node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[el2_lib.scala 235:86] + node _T_604 = eq(_T_602, _T_603) @[el2_lib.scala 235:78] + node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[el2_lib.scala 235:23] + _T_409[27] <= _T_605 @[el2_lib.scala 235:17] + node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_607 = andr(_T_606) @[el2_lib.scala 235:36] + node _T_608 = and(_T_607, _T_412) @[el2_lib.scala 235:41] + node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[el2_lib.scala 235:86] + node _T_611 = eq(_T_609, _T_610) @[el2_lib.scala 235:78] + node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[el2_lib.scala 235:23] + _T_409[28] <= _T_612 @[el2_lib.scala 235:17] + node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_614 = andr(_T_613) @[el2_lib.scala 235:36] + node _T_615 = and(_T_614, _T_412) @[el2_lib.scala 235:41] + node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[el2_lib.scala 235:86] + node _T_618 = eq(_T_616, _T_617) @[el2_lib.scala 235:78] + node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[el2_lib.scala 235:23] + _T_409[29] <= _T_619 @[el2_lib.scala 235:17] + node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_621 = andr(_T_620) @[el2_lib.scala 235:36] + node _T_622 = and(_T_621, _T_412) @[el2_lib.scala 235:41] + node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[el2_lib.scala 235:86] + node _T_625 = eq(_T_623, _T_624) @[el2_lib.scala 235:78] + node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[el2_lib.scala 235:23] + _T_409[30] <= _T_626 @[el2_lib.scala 235:17] + node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_628 = andr(_T_627) @[el2_lib.scala 235:36] + node _T_629 = and(_T_628, _T_412) @[el2_lib.scala 235:41] + node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[el2_lib.scala 235:86] + node _T_632 = eq(_T_630, _T_631) @[el2_lib.scala 235:78] + node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[el2_lib.scala 235:23] + _T_409[31] <= _T_633 @[el2_lib.scala 235:17] + node _T_634 = cat(_T_409[1], _T_409[0]) @[el2_lib.scala 236:14] + node _T_635 = cat(_T_409[3], _T_409[2]) @[el2_lib.scala 236:14] + node _T_636 = cat(_T_635, _T_634) @[el2_lib.scala 236:14] + node _T_637 = cat(_T_409[5], _T_409[4]) @[el2_lib.scala 236:14] + node _T_638 = cat(_T_409[7], _T_409[6]) @[el2_lib.scala 236:14] + node _T_639 = cat(_T_638, _T_637) @[el2_lib.scala 236:14] + node _T_640 = cat(_T_639, _T_636) @[el2_lib.scala 236:14] + node _T_641 = cat(_T_409[9], _T_409[8]) @[el2_lib.scala 236:14] + node _T_642 = cat(_T_409[11], _T_409[10]) @[el2_lib.scala 236:14] + node _T_643 = cat(_T_642, _T_641) @[el2_lib.scala 236:14] + node _T_644 = cat(_T_409[13], _T_409[12]) @[el2_lib.scala 236:14] + node _T_645 = cat(_T_409[15], _T_409[14]) @[el2_lib.scala 236:14] + node _T_646 = cat(_T_645, _T_644) @[el2_lib.scala 236:14] + node _T_647 = cat(_T_646, _T_643) @[el2_lib.scala 236:14] + node _T_648 = cat(_T_647, _T_640) @[el2_lib.scala 236:14] + node _T_649 = cat(_T_409[17], _T_409[16]) @[el2_lib.scala 236:14] + node _T_650 = cat(_T_409[19], _T_409[18]) @[el2_lib.scala 236:14] + node _T_651 = cat(_T_650, _T_649) @[el2_lib.scala 236:14] + node _T_652 = cat(_T_409[21], _T_409[20]) @[el2_lib.scala 236:14] + node _T_653 = cat(_T_409[23], _T_409[22]) @[el2_lib.scala 236:14] + node _T_654 = cat(_T_653, _T_652) @[el2_lib.scala 236:14] + node _T_655 = cat(_T_654, _T_651) @[el2_lib.scala 236:14] + node _T_656 = cat(_T_409[25], _T_409[24]) @[el2_lib.scala 236:14] + node _T_657 = cat(_T_409[27], _T_409[26]) @[el2_lib.scala 236:14] + node _T_658 = cat(_T_657, _T_656) @[el2_lib.scala 236:14] + node _T_659 = cat(_T_409[29], _T_409[28]) @[el2_lib.scala 236:14] + node _T_660 = cat(_T_409[31], _T_409[30]) @[el2_lib.scala 236:14] + node _T_661 = cat(_T_660, _T_659) @[el2_lib.scala 236:14] + node _T_662 = cat(_T_661, _T_658) @[el2_lib.scala 236:14] + node _T_663 = cat(_T_662, _T_655) @[el2_lib.scala 236:14] + node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 236:14] + node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] + node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] + node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_668 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 232:45] + node _T_670 = not(_T_669) @[el2_lib.scala 232:39] + node _T_671 = and(_T_667, _T_670) @[el2_lib.scala 232:37] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[el2_lib.scala 233:60] + node _T_674 = eq(_T_672, _T_673) @[el2_lib.scala 233:52] + node _T_675 = or(_T_671, _T_674) @[el2_lib.scala 233:41] + _T_668[0] <= _T_675 @[el2_lib.scala 233:18] + node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_677 = andr(_T_676) @[el2_lib.scala 235:36] + node _T_678 = and(_T_677, _T_671) @[el2_lib.scala 235:41] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[el2_lib.scala 235:86] + node _T_681 = eq(_T_679, _T_680) @[el2_lib.scala 235:78] + node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[el2_lib.scala 235:23] + _T_668[1] <= _T_682 @[el2_lib.scala 235:17] + node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_684 = andr(_T_683) @[el2_lib.scala 235:36] + node _T_685 = and(_T_684, _T_671) @[el2_lib.scala 235:41] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[el2_lib.scala 235:86] + node _T_688 = eq(_T_686, _T_687) @[el2_lib.scala 235:78] + node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[el2_lib.scala 235:23] + _T_668[2] <= _T_689 @[el2_lib.scala 235:17] + node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_691 = andr(_T_690) @[el2_lib.scala 235:36] + node _T_692 = and(_T_691, _T_671) @[el2_lib.scala 235:41] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[el2_lib.scala 235:86] + node _T_695 = eq(_T_693, _T_694) @[el2_lib.scala 235:78] + node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[el2_lib.scala 235:23] + _T_668[3] <= _T_696 @[el2_lib.scala 235:17] + node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_698 = andr(_T_697) @[el2_lib.scala 235:36] + node _T_699 = and(_T_698, _T_671) @[el2_lib.scala 235:41] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[el2_lib.scala 235:86] + node _T_702 = eq(_T_700, _T_701) @[el2_lib.scala 235:78] + node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[el2_lib.scala 235:23] + _T_668[4] <= _T_703 @[el2_lib.scala 235:17] + node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_705 = andr(_T_704) @[el2_lib.scala 235:36] + node _T_706 = and(_T_705, _T_671) @[el2_lib.scala 235:41] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[el2_lib.scala 235:86] + node _T_709 = eq(_T_707, _T_708) @[el2_lib.scala 235:78] + node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[el2_lib.scala 235:23] + _T_668[5] <= _T_710 @[el2_lib.scala 235:17] + node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_712 = andr(_T_711) @[el2_lib.scala 235:36] + node _T_713 = and(_T_712, _T_671) @[el2_lib.scala 235:41] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[el2_lib.scala 235:86] + node _T_716 = eq(_T_714, _T_715) @[el2_lib.scala 235:78] + node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[el2_lib.scala 235:23] + _T_668[6] <= _T_717 @[el2_lib.scala 235:17] + node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_719 = andr(_T_718) @[el2_lib.scala 235:36] + node _T_720 = and(_T_719, _T_671) @[el2_lib.scala 235:41] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[el2_lib.scala 235:86] + node _T_723 = eq(_T_721, _T_722) @[el2_lib.scala 235:78] + node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[el2_lib.scala 235:23] + _T_668[7] <= _T_724 @[el2_lib.scala 235:17] + node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_726 = andr(_T_725) @[el2_lib.scala 235:36] + node _T_727 = and(_T_726, _T_671) @[el2_lib.scala 235:41] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[el2_lib.scala 235:86] + node _T_730 = eq(_T_728, _T_729) @[el2_lib.scala 235:78] + node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[el2_lib.scala 235:23] + _T_668[8] <= _T_731 @[el2_lib.scala 235:17] + node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_733 = andr(_T_732) @[el2_lib.scala 235:36] + node _T_734 = and(_T_733, _T_671) @[el2_lib.scala 235:41] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[el2_lib.scala 235:86] + node _T_737 = eq(_T_735, _T_736) @[el2_lib.scala 235:78] + node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[el2_lib.scala 235:23] + _T_668[9] <= _T_738 @[el2_lib.scala 235:17] + node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_740 = andr(_T_739) @[el2_lib.scala 235:36] + node _T_741 = and(_T_740, _T_671) @[el2_lib.scala 235:41] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[el2_lib.scala 235:86] + node _T_744 = eq(_T_742, _T_743) @[el2_lib.scala 235:78] + node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[el2_lib.scala 235:23] + _T_668[10] <= _T_745 @[el2_lib.scala 235:17] + node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_747 = andr(_T_746) @[el2_lib.scala 235:36] + node _T_748 = and(_T_747, _T_671) @[el2_lib.scala 235:41] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[el2_lib.scala 235:86] + node _T_751 = eq(_T_749, _T_750) @[el2_lib.scala 235:78] + node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[el2_lib.scala 235:23] + _T_668[11] <= _T_752 @[el2_lib.scala 235:17] + node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_754 = andr(_T_753) @[el2_lib.scala 235:36] + node _T_755 = and(_T_754, _T_671) @[el2_lib.scala 235:41] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[el2_lib.scala 235:86] + node _T_758 = eq(_T_756, _T_757) @[el2_lib.scala 235:78] + node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[el2_lib.scala 235:23] + _T_668[12] <= _T_759 @[el2_lib.scala 235:17] + node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_761 = andr(_T_760) @[el2_lib.scala 235:36] + node _T_762 = and(_T_761, _T_671) @[el2_lib.scala 235:41] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[el2_lib.scala 235:86] + node _T_765 = eq(_T_763, _T_764) @[el2_lib.scala 235:78] + node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[el2_lib.scala 235:23] + _T_668[13] <= _T_766 @[el2_lib.scala 235:17] + node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_768 = andr(_T_767) @[el2_lib.scala 235:36] + node _T_769 = and(_T_768, _T_671) @[el2_lib.scala 235:41] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[el2_lib.scala 235:86] + node _T_772 = eq(_T_770, _T_771) @[el2_lib.scala 235:78] + node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[el2_lib.scala 235:23] + _T_668[14] <= _T_773 @[el2_lib.scala 235:17] + node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_775 = andr(_T_774) @[el2_lib.scala 235:36] + node _T_776 = and(_T_775, _T_671) @[el2_lib.scala 235:41] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[el2_lib.scala 235:86] + node _T_779 = eq(_T_777, _T_778) @[el2_lib.scala 235:78] + node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[el2_lib.scala 235:23] + _T_668[15] <= _T_780 @[el2_lib.scala 235:17] + node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_782 = andr(_T_781) @[el2_lib.scala 235:36] + node _T_783 = and(_T_782, _T_671) @[el2_lib.scala 235:41] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[el2_lib.scala 235:86] + node _T_786 = eq(_T_784, _T_785) @[el2_lib.scala 235:78] + node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[el2_lib.scala 235:23] + _T_668[16] <= _T_787 @[el2_lib.scala 235:17] + node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_789 = andr(_T_788) @[el2_lib.scala 235:36] + node _T_790 = and(_T_789, _T_671) @[el2_lib.scala 235:41] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[el2_lib.scala 235:86] + node _T_793 = eq(_T_791, _T_792) @[el2_lib.scala 235:78] + node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[el2_lib.scala 235:23] + _T_668[17] <= _T_794 @[el2_lib.scala 235:17] + node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_796 = andr(_T_795) @[el2_lib.scala 235:36] + node _T_797 = and(_T_796, _T_671) @[el2_lib.scala 235:41] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[el2_lib.scala 235:86] + node _T_800 = eq(_T_798, _T_799) @[el2_lib.scala 235:78] + node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[el2_lib.scala 235:23] + _T_668[18] <= _T_801 @[el2_lib.scala 235:17] + node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_803 = andr(_T_802) @[el2_lib.scala 235:36] + node _T_804 = and(_T_803, _T_671) @[el2_lib.scala 235:41] + node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[el2_lib.scala 235:86] + node _T_807 = eq(_T_805, _T_806) @[el2_lib.scala 235:78] + node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[el2_lib.scala 235:23] + _T_668[19] <= _T_808 @[el2_lib.scala 235:17] + node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_810 = andr(_T_809) @[el2_lib.scala 235:36] + node _T_811 = and(_T_810, _T_671) @[el2_lib.scala 235:41] + node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[el2_lib.scala 235:86] + node _T_814 = eq(_T_812, _T_813) @[el2_lib.scala 235:78] + node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[el2_lib.scala 235:23] + _T_668[20] <= _T_815 @[el2_lib.scala 235:17] + node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_817 = andr(_T_816) @[el2_lib.scala 235:36] + node _T_818 = and(_T_817, _T_671) @[el2_lib.scala 235:41] + node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[el2_lib.scala 235:86] + node _T_821 = eq(_T_819, _T_820) @[el2_lib.scala 235:78] + node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[el2_lib.scala 235:23] + _T_668[21] <= _T_822 @[el2_lib.scala 235:17] + node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_824 = andr(_T_823) @[el2_lib.scala 235:36] + node _T_825 = and(_T_824, _T_671) @[el2_lib.scala 235:41] + node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[el2_lib.scala 235:86] + node _T_828 = eq(_T_826, _T_827) @[el2_lib.scala 235:78] + node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[el2_lib.scala 235:23] + _T_668[22] <= _T_829 @[el2_lib.scala 235:17] + node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_831 = andr(_T_830) @[el2_lib.scala 235:36] + node _T_832 = and(_T_831, _T_671) @[el2_lib.scala 235:41] + node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[el2_lib.scala 235:86] + node _T_835 = eq(_T_833, _T_834) @[el2_lib.scala 235:78] + node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[el2_lib.scala 235:23] + _T_668[23] <= _T_836 @[el2_lib.scala 235:17] + node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_838 = andr(_T_837) @[el2_lib.scala 235:36] + node _T_839 = and(_T_838, _T_671) @[el2_lib.scala 235:41] + node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[el2_lib.scala 235:86] + node _T_842 = eq(_T_840, _T_841) @[el2_lib.scala 235:78] + node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[el2_lib.scala 235:23] + _T_668[24] <= _T_843 @[el2_lib.scala 235:17] + node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_845 = andr(_T_844) @[el2_lib.scala 235:36] + node _T_846 = and(_T_845, _T_671) @[el2_lib.scala 235:41] + node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[el2_lib.scala 235:86] + node _T_849 = eq(_T_847, _T_848) @[el2_lib.scala 235:78] + node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[el2_lib.scala 235:23] + _T_668[25] <= _T_850 @[el2_lib.scala 235:17] + node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_852 = andr(_T_851) @[el2_lib.scala 235:36] + node _T_853 = and(_T_852, _T_671) @[el2_lib.scala 235:41] + node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[el2_lib.scala 235:86] + node _T_856 = eq(_T_854, _T_855) @[el2_lib.scala 235:78] + node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[el2_lib.scala 235:23] + _T_668[26] <= _T_857 @[el2_lib.scala 235:17] + node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_859 = andr(_T_858) @[el2_lib.scala 235:36] + node _T_860 = and(_T_859, _T_671) @[el2_lib.scala 235:41] + node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[el2_lib.scala 235:86] + node _T_863 = eq(_T_861, _T_862) @[el2_lib.scala 235:78] + node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[el2_lib.scala 235:23] + _T_668[27] <= _T_864 @[el2_lib.scala 235:17] + node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_866 = andr(_T_865) @[el2_lib.scala 235:36] + node _T_867 = and(_T_866, _T_671) @[el2_lib.scala 235:41] + node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[el2_lib.scala 235:86] + node _T_870 = eq(_T_868, _T_869) @[el2_lib.scala 235:78] + node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[el2_lib.scala 235:23] + _T_668[28] <= _T_871 @[el2_lib.scala 235:17] + node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_873 = andr(_T_872) @[el2_lib.scala 235:36] + node _T_874 = and(_T_873, _T_671) @[el2_lib.scala 235:41] + node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[el2_lib.scala 235:86] + node _T_877 = eq(_T_875, _T_876) @[el2_lib.scala 235:78] + node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[el2_lib.scala 235:23] + _T_668[29] <= _T_878 @[el2_lib.scala 235:17] + node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_880 = andr(_T_879) @[el2_lib.scala 235:36] + node _T_881 = and(_T_880, _T_671) @[el2_lib.scala 235:41] + node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[el2_lib.scala 235:86] + node _T_884 = eq(_T_882, _T_883) @[el2_lib.scala 235:78] + node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[el2_lib.scala 235:23] + _T_668[30] <= _T_885 @[el2_lib.scala 235:17] + node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_887 = andr(_T_886) @[el2_lib.scala 235:36] + node _T_888 = and(_T_887, _T_671) @[el2_lib.scala 235:41] + node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[el2_lib.scala 235:86] + node _T_891 = eq(_T_889, _T_890) @[el2_lib.scala 235:78] + node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[el2_lib.scala 235:23] + _T_668[31] <= _T_892 @[el2_lib.scala 235:17] + node _T_893 = cat(_T_668[1], _T_668[0]) @[el2_lib.scala 236:14] + node _T_894 = cat(_T_668[3], _T_668[2]) @[el2_lib.scala 236:14] + node _T_895 = cat(_T_894, _T_893) @[el2_lib.scala 236:14] + node _T_896 = cat(_T_668[5], _T_668[4]) @[el2_lib.scala 236:14] + node _T_897 = cat(_T_668[7], _T_668[6]) @[el2_lib.scala 236:14] + node _T_898 = cat(_T_897, _T_896) @[el2_lib.scala 236:14] + node _T_899 = cat(_T_898, _T_895) @[el2_lib.scala 236:14] + node _T_900 = cat(_T_668[9], _T_668[8]) @[el2_lib.scala 236:14] + node _T_901 = cat(_T_668[11], _T_668[10]) @[el2_lib.scala 236:14] + node _T_902 = cat(_T_901, _T_900) @[el2_lib.scala 236:14] + node _T_903 = cat(_T_668[13], _T_668[12]) @[el2_lib.scala 236:14] + node _T_904 = cat(_T_668[15], _T_668[14]) @[el2_lib.scala 236:14] + node _T_905 = cat(_T_904, _T_903) @[el2_lib.scala 236:14] + node _T_906 = cat(_T_905, _T_902) @[el2_lib.scala 236:14] + node _T_907 = cat(_T_906, _T_899) @[el2_lib.scala 236:14] + node _T_908 = cat(_T_668[17], _T_668[16]) @[el2_lib.scala 236:14] + node _T_909 = cat(_T_668[19], _T_668[18]) @[el2_lib.scala 236:14] + node _T_910 = cat(_T_909, _T_908) @[el2_lib.scala 236:14] + node _T_911 = cat(_T_668[21], _T_668[20]) @[el2_lib.scala 236:14] + node _T_912 = cat(_T_668[23], _T_668[22]) @[el2_lib.scala 236:14] + node _T_913 = cat(_T_912, _T_911) @[el2_lib.scala 236:14] + node _T_914 = cat(_T_913, _T_910) @[el2_lib.scala 236:14] + node _T_915 = cat(_T_668[25], _T_668[24]) @[el2_lib.scala 236:14] + node _T_916 = cat(_T_668[27], _T_668[26]) @[el2_lib.scala 236:14] + node _T_917 = cat(_T_916, _T_915) @[el2_lib.scala 236:14] + node _T_918 = cat(_T_668[29], _T_668[28]) @[el2_lib.scala 236:14] + node _T_919 = cat(_T_668[31], _T_668[30]) @[el2_lib.scala 236:14] + node _T_920 = cat(_T_919, _T_918) @[el2_lib.scala 236:14] + node _T_921 = cat(_T_920, _T_917) @[el2_lib.scala 236:14] + node _T_922 = cat(_T_921, _T_914) @[el2_lib.scala 236:14] + node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 236:14] + node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] + node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] + node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_927 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 232:45] + node _T_929 = not(_T_928) @[el2_lib.scala 232:39] + node _T_930 = and(_T_926, _T_929) @[el2_lib.scala 232:37] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[el2_lib.scala 233:60] + node _T_933 = eq(_T_931, _T_932) @[el2_lib.scala 233:52] + node _T_934 = or(_T_930, _T_933) @[el2_lib.scala 233:41] + _T_927[0] <= _T_934 @[el2_lib.scala 233:18] + node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_936 = andr(_T_935) @[el2_lib.scala 235:36] + node _T_937 = and(_T_936, _T_930) @[el2_lib.scala 235:41] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[el2_lib.scala 235:86] + node _T_940 = eq(_T_938, _T_939) @[el2_lib.scala 235:78] + node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[el2_lib.scala 235:23] + _T_927[1] <= _T_941 @[el2_lib.scala 235:17] + node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_943 = andr(_T_942) @[el2_lib.scala 235:36] + node _T_944 = and(_T_943, _T_930) @[el2_lib.scala 235:41] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[el2_lib.scala 235:86] + node _T_947 = eq(_T_945, _T_946) @[el2_lib.scala 235:78] + node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[el2_lib.scala 235:23] + _T_927[2] <= _T_948 @[el2_lib.scala 235:17] + node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_950 = andr(_T_949) @[el2_lib.scala 235:36] + node _T_951 = and(_T_950, _T_930) @[el2_lib.scala 235:41] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[el2_lib.scala 235:86] + node _T_954 = eq(_T_952, _T_953) @[el2_lib.scala 235:78] + node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[el2_lib.scala 235:23] + _T_927[3] <= _T_955 @[el2_lib.scala 235:17] + node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_957 = andr(_T_956) @[el2_lib.scala 235:36] + node _T_958 = and(_T_957, _T_930) @[el2_lib.scala 235:41] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[el2_lib.scala 235:86] + node _T_961 = eq(_T_959, _T_960) @[el2_lib.scala 235:78] + node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[el2_lib.scala 235:23] + _T_927[4] <= _T_962 @[el2_lib.scala 235:17] + node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_964 = andr(_T_963) @[el2_lib.scala 235:36] + node _T_965 = and(_T_964, _T_930) @[el2_lib.scala 235:41] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[el2_lib.scala 235:86] + node _T_968 = eq(_T_966, _T_967) @[el2_lib.scala 235:78] + node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[el2_lib.scala 235:23] + _T_927[5] <= _T_969 @[el2_lib.scala 235:17] + node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_971 = andr(_T_970) @[el2_lib.scala 235:36] + node _T_972 = and(_T_971, _T_930) @[el2_lib.scala 235:41] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[el2_lib.scala 235:86] + node _T_975 = eq(_T_973, _T_974) @[el2_lib.scala 235:78] + node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[el2_lib.scala 235:23] + _T_927[6] <= _T_976 @[el2_lib.scala 235:17] + node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_978 = andr(_T_977) @[el2_lib.scala 235:36] + node _T_979 = and(_T_978, _T_930) @[el2_lib.scala 235:41] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[el2_lib.scala 235:86] + node _T_982 = eq(_T_980, _T_981) @[el2_lib.scala 235:78] + node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[el2_lib.scala 235:23] + _T_927[7] <= _T_983 @[el2_lib.scala 235:17] + node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_985 = andr(_T_984) @[el2_lib.scala 235:36] + node _T_986 = and(_T_985, _T_930) @[el2_lib.scala 235:41] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[el2_lib.scala 235:86] + node _T_989 = eq(_T_987, _T_988) @[el2_lib.scala 235:78] + node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[el2_lib.scala 235:23] + _T_927[8] <= _T_990 @[el2_lib.scala 235:17] + node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_992 = andr(_T_991) @[el2_lib.scala 235:36] + node _T_993 = and(_T_992, _T_930) @[el2_lib.scala 235:41] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[el2_lib.scala 235:86] + node _T_996 = eq(_T_994, _T_995) @[el2_lib.scala 235:78] + node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[el2_lib.scala 235:23] + _T_927[9] <= _T_997 @[el2_lib.scala 235:17] + node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_999 = andr(_T_998) @[el2_lib.scala 235:36] + node _T_1000 = and(_T_999, _T_930) @[el2_lib.scala 235:41] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[el2_lib.scala 235:86] + node _T_1003 = eq(_T_1001, _T_1002) @[el2_lib.scala 235:78] + node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[el2_lib.scala 235:23] + _T_927[10] <= _T_1004 @[el2_lib.scala 235:17] + node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_1006 = andr(_T_1005) @[el2_lib.scala 235:36] + node _T_1007 = and(_T_1006, _T_930) @[el2_lib.scala 235:41] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[el2_lib.scala 235:86] + node _T_1010 = eq(_T_1008, _T_1009) @[el2_lib.scala 235:78] + node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[el2_lib.scala 235:23] + _T_927[11] <= _T_1011 @[el2_lib.scala 235:17] + node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_1013 = andr(_T_1012) @[el2_lib.scala 235:36] + node _T_1014 = and(_T_1013, _T_930) @[el2_lib.scala 235:41] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[el2_lib.scala 235:86] + node _T_1017 = eq(_T_1015, _T_1016) @[el2_lib.scala 235:78] + node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[el2_lib.scala 235:23] + _T_927[12] <= _T_1018 @[el2_lib.scala 235:17] + node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_1020 = andr(_T_1019) @[el2_lib.scala 235:36] + node _T_1021 = and(_T_1020, _T_930) @[el2_lib.scala 235:41] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[el2_lib.scala 235:86] + node _T_1024 = eq(_T_1022, _T_1023) @[el2_lib.scala 235:78] + node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[el2_lib.scala 235:23] + _T_927[13] <= _T_1025 @[el2_lib.scala 235:17] + node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_1027 = andr(_T_1026) @[el2_lib.scala 235:36] + node _T_1028 = and(_T_1027, _T_930) @[el2_lib.scala 235:41] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[el2_lib.scala 235:86] + node _T_1031 = eq(_T_1029, _T_1030) @[el2_lib.scala 235:78] + node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[el2_lib.scala 235:23] + _T_927[14] <= _T_1032 @[el2_lib.scala 235:17] + node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_1034 = andr(_T_1033) @[el2_lib.scala 235:36] + node _T_1035 = and(_T_1034, _T_930) @[el2_lib.scala 235:41] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[el2_lib.scala 235:86] + node _T_1038 = eq(_T_1036, _T_1037) @[el2_lib.scala 235:78] + node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[el2_lib.scala 235:23] + _T_927[15] <= _T_1039 @[el2_lib.scala 235:17] + node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_1041 = andr(_T_1040) @[el2_lib.scala 235:36] + node _T_1042 = and(_T_1041, _T_930) @[el2_lib.scala 235:41] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[el2_lib.scala 235:86] + node _T_1045 = eq(_T_1043, _T_1044) @[el2_lib.scala 235:78] + node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[el2_lib.scala 235:23] + _T_927[16] <= _T_1046 @[el2_lib.scala 235:17] + node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_1048 = andr(_T_1047) @[el2_lib.scala 235:36] + node _T_1049 = and(_T_1048, _T_930) @[el2_lib.scala 235:41] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[el2_lib.scala 235:86] + node _T_1052 = eq(_T_1050, _T_1051) @[el2_lib.scala 235:78] + node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[el2_lib.scala 235:23] + _T_927[17] <= _T_1053 @[el2_lib.scala 235:17] + node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_1055 = andr(_T_1054) @[el2_lib.scala 235:36] + node _T_1056 = and(_T_1055, _T_930) @[el2_lib.scala 235:41] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[el2_lib.scala 235:86] + node _T_1059 = eq(_T_1057, _T_1058) @[el2_lib.scala 235:78] + node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[el2_lib.scala 235:23] + _T_927[18] <= _T_1060 @[el2_lib.scala 235:17] + node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_1062 = andr(_T_1061) @[el2_lib.scala 235:36] + node _T_1063 = and(_T_1062, _T_930) @[el2_lib.scala 235:41] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[el2_lib.scala 235:86] + node _T_1066 = eq(_T_1064, _T_1065) @[el2_lib.scala 235:78] + node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[el2_lib.scala 235:23] + _T_927[19] <= _T_1067 @[el2_lib.scala 235:17] + node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_1069 = andr(_T_1068) @[el2_lib.scala 235:36] + node _T_1070 = and(_T_1069, _T_930) @[el2_lib.scala 235:41] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[el2_lib.scala 235:86] + node _T_1073 = eq(_T_1071, _T_1072) @[el2_lib.scala 235:78] + node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[el2_lib.scala 235:23] + _T_927[20] <= _T_1074 @[el2_lib.scala 235:17] + node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_1076 = andr(_T_1075) @[el2_lib.scala 235:36] + node _T_1077 = and(_T_1076, _T_930) @[el2_lib.scala 235:41] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[el2_lib.scala 235:86] + node _T_1080 = eq(_T_1078, _T_1079) @[el2_lib.scala 235:78] + node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[el2_lib.scala 235:23] + _T_927[21] <= _T_1081 @[el2_lib.scala 235:17] + node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_1083 = andr(_T_1082) @[el2_lib.scala 235:36] + node _T_1084 = and(_T_1083, _T_930) @[el2_lib.scala 235:41] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[el2_lib.scala 235:86] + node _T_1087 = eq(_T_1085, _T_1086) @[el2_lib.scala 235:78] + node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[el2_lib.scala 235:23] + _T_927[22] <= _T_1088 @[el2_lib.scala 235:17] + node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_1090 = andr(_T_1089) @[el2_lib.scala 235:36] + node _T_1091 = and(_T_1090, _T_930) @[el2_lib.scala 235:41] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[el2_lib.scala 235:86] + node _T_1094 = eq(_T_1092, _T_1093) @[el2_lib.scala 235:78] + node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[el2_lib.scala 235:23] + _T_927[23] <= _T_1095 @[el2_lib.scala 235:17] + node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_1097 = andr(_T_1096) @[el2_lib.scala 235:36] + node _T_1098 = and(_T_1097, _T_930) @[el2_lib.scala 235:41] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[el2_lib.scala 235:86] + node _T_1101 = eq(_T_1099, _T_1100) @[el2_lib.scala 235:78] + node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[el2_lib.scala 235:23] + _T_927[24] <= _T_1102 @[el2_lib.scala 235:17] + node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_1104 = andr(_T_1103) @[el2_lib.scala 235:36] + node _T_1105 = and(_T_1104, _T_930) @[el2_lib.scala 235:41] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[el2_lib.scala 235:86] + node _T_1108 = eq(_T_1106, _T_1107) @[el2_lib.scala 235:78] + node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[el2_lib.scala 235:23] + _T_927[25] <= _T_1109 @[el2_lib.scala 235:17] + node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_1111 = andr(_T_1110) @[el2_lib.scala 235:36] + node _T_1112 = and(_T_1111, _T_930) @[el2_lib.scala 235:41] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[el2_lib.scala 235:86] + node _T_1115 = eq(_T_1113, _T_1114) @[el2_lib.scala 235:78] + node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[el2_lib.scala 235:23] + _T_927[26] <= _T_1116 @[el2_lib.scala 235:17] + node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_1118 = andr(_T_1117) @[el2_lib.scala 235:36] + node _T_1119 = and(_T_1118, _T_930) @[el2_lib.scala 235:41] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[el2_lib.scala 235:86] + node _T_1122 = eq(_T_1120, _T_1121) @[el2_lib.scala 235:78] + node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[el2_lib.scala 235:23] + _T_927[27] <= _T_1123 @[el2_lib.scala 235:17] + node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_1125 = andr(_T_1124) @[el2_lib.scala 235:36] + node _T_1126 = and(_T_1125, _T_930) @[el2_lib.scala 235:41] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[el2_lib.scala 235:86] + node _T_1129 = eq(_T_1127, _T_1128) @[el2_lib.scala 235:78] + node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[el2_lib.scala 235:23] + _T_927[28] <= _T_1130 @[el2_lib.scala 235:17] + node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_1132 = andr(_T_1131) @[el2_lib.scala 235:36] + node _T_1133 = and(_T_1132, _T_930) @[el2_lib.scala 235:41] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[el2_lib.scala 235:86] + node _T_1136 = eq(_T_1134, _T_1135) @[el2_lib.scala 235:78] + node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[el2_lib.scala 235:23] + _T_927[29] <= _T_1137 @[el2_lib.scala 235:17] + node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_1139 = andr(_T_1138) @[el2_lib.scala 235:36] + node _T_1140 = and(_T_1139, _T_930) @[el2_lib.scala 235:41] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[el2_lib.scala 235:86] + node _T_1143 = eq(_T_1141, _T_1142) @[el2_lib.scala 235:78] + node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[el2_lib.scala 235:23] + _T_927[30] <= _T_1144 @[el2_lib.scala 235:17] + node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_1146 = andr(_T_1145) @[el2_lib.scala 235:36] + node _T_1147 = and(_T_1146, _T_930) @[el2_lib.scala 235:41] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[el2_lib.scala 235:86] + node _T_1150 = eq(_T_1148, _T_1149) @[el2_lib.scala 235:78] + node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[el2_lib.scala 235:23] + _T_927[31] <= _T_1151 @[el2_lib.scala 235:17] + node _T_1152 = cat(_T_927[1], _T_927[0]) @[el2_lib.scala 236:14] + node _T_1153 = cat(_T_927[3], _T_927[2]) @[el2_lib.scala 236:14] + node _T_1154 = cat(_T_1153, _T_1152) @[el2_lib.scala 236:14] + node _T_1155 = cat(_T_927[5], _T_927[4]) @[el2_lib.scala 236:14] + node _T_1156 = cat(_T_927[7], _T_927[6]) @[el2_lib.scala 236:14] + node _T_1157 = cat(_T_1156, _T_1155) @[el2_lib.scala 236:14] + node _T_1158 = cat(_T_1157, _T_1154) @[el2_lib.scala 236:14] + node _T_1159 = cat(_T_927[9], _T_927[8]) @[el2_lib.scala 236:14] + node _T_1160 = cat(_T_927[11], _T_927[10]) @[el2_lib.scala 236:14] + node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 236:14] + node _T_1162 = cat(_T_927[13], _T_927[12]) @[el2_lib.scala 236:14] + node _T_1163 = cat(_T_927[15], _T_927[14]) @[el2_lib.scala 236:14] + node _T_1164 = cat(_T_1163, _T_1162) @[el2_lib.scala 236:14] + node _T_1165 = cat(_T_1164, _T_1161) @[el2_lib.scala 236:14] + node _T_1166 = cat(_T_1165, _T_1158) @[el2_lib.scala 236:14] + node _T_1167 = cat(_T_927[17], _T_927[16]) @[el2_lib.scala 236:14] + node _T_1168 = cat(_T_927[19], _T_927[18]) @[el2_lib.scala 236:14] + node _T_1169 = cat(_T_1168, _T_1167) @[el2_lib.scala 236:14] + node _T_1170 = cat(_T_927[21], _T_927[20]) @[el2_lib.scala 236:14] + node _T_1171 = cat(_T_927[23], _T_927[22]) @[el2_lib.scala 236:14] + node _T_1172 = cat(_T_1171, _T_1170) @[el2_lib.scala 236:14] + node _T_1173 = cat(_T_1172, _T_1169) @[el2_lib.scala 236:14] + node _T_1174 = cat(_T_927[25], _T_927[24]) @[el2_lib.scala 236:14] + node _T_1175 = cat(_T_927[27], _T_927[26]) @[el2_lib.scala 236:14] + node _T_1176 = cat(_T_1175, _T_1174) @[el2_lib.scala 236:14] + node _T_1177 = cat(_T_927[29], _T_927[28]) @[el2_lib.scala 236:14] + node _T_1178 = cat(_T_927[31], _T_927[30]) @[el2_lib.scala 236:14] + node _T_1179 = cat(_T_1178, _T_1177) @[el2_lib.scala 236:14] + node _T_1180 = cat(_T_1179, _T_1176) @[el2_lib.scala 236:14] + node _T_1181 = cat(_T_1180, _T_1173) @[el2_lib.scala 236:14] + node _T_1182 = cat(_T_1181, _T_1166) @[el2_lib.scala 236:14] + node _T_1183 = and(_T_925, _T_1182) @[el2_dec_trigger.scala 15:109] + node _T_1184 = cat(_T_1183, _T_924) @[Cat.scala 29:58] + node _T_1185 = cat(_T_1184, _T_665) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_406) @[Cat.scala 29:58] + io.dec_i0_trigger_match_d <= _T_1186 @[el2_dec_trigger.scala 15:29] + + module el2_dec : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<32>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<32>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<32>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<9>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<32>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<32>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<32>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<70>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<32>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<13>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<32>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<32>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<32>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<9>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + + io.dec_i0_pc_d <= UInt<1>("h00") @[el2_dec.scala 272:18] + wire dec_i0_inst_wb1 : UInt<32> + dec_i0_inst_wb1 <= UInt<1>("h00") + wire dec_i0_pc_wb1 : UInt<32> + dec_i0_pc_wb1 <= UInt<1>("h00") + wire dec_tlu_i0_valid_wb1 : UInt<1> + dec_tlu_i0_valid_wb1 <= UInt<1>("h00") + wire dec_tlu_int_valid_wb1 : UInt<1> + dec_tlu_int_valid_wb1 <= UInt<1>("h00") + wire dec_tlu_exc_cause_wb1 : UInt<5> + dec_tlu_exc_cause_wb1 <= UInt<1>("h00") + wire dec_tlu_mtval_wb1 : UInt<32> + dec_tlu_mtval_wb1 <= UInt<1>("h00") + wire dec_tlu_i0_exc_valid_wb1 : UInt<1> + dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00") + inst instbuff of el2_dec_ib_ctl @[el2_dec.scala 352:24] + instbuff.clock <= clock + instbuff.reset <= reset + inst decode of el2_dec_decode_ctl @[el2_dec.scala 353:22] + decode.clock <= clock + decode.reset <= reset + inst gpr of el2_dec_gpr_ctl @[el2_dec.scala 354:19] + gpr.clock <= clock + gpr.reset <= reset + inst tlu of el2_dec_tlu_ctl @[el2_dec.scala 355:19] + tlu.clock <= clock + tlu.reset <= reset + inst dec_trigger of el2_dec_trigger @[el2_dec.scala 356:27] + dec_trigger.clock <= clock + dec_trigger.reset <= reset + instbuff.io.dbg_cmd_valid <= io.dbg_cmd_valid @[el2_dec.scala 363:45] + instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 364:45] + instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 365:45] + instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 366:45] + instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 367:55] + instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 367:55] + instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 367:55] + instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 367:55] + instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 367:55] + instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 367:55] + instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 367:55] + instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 367:55] + instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 367:55] + instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 368:35] + instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 369:35] + instbuff.io.ifu_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec.scala 370:35] + instbuff.io.ifu_i0_pc4 <= io.ifu_i0_pc4 @[el2_dec.scala 371:35] + instbuff.io.ifu_i0_valid <= io.ifu_i0_valid @[el2_dec.scala 372:35] + instbuff.io.ifu_i0_icaf <= io.ifu_i0_icaf @[el2_dec.scala 373:35] + instbuff.io.ifu_i0_icaf_type <= io.ifu_i0_icaf_type @[el2_dec.scala 374:35] + instbuff.io.ifu_i0_icaf_f1 <= io.ifu_i0_icaf_f1 @[el2_dec.scala 375:35] + instbuff.io.ifu_i0_dbecc <= io.ifu_i0_dbecc @[el2_dec.scala 376:35] + instbuff.io.ifu_i0_instr <= io.ifu_i0_instr @[el2_dec.scala 377:35] + instbuff.io.ifu_i0_pc <= io.ifu_i0_pc @[el2_dec.scala 378:35] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 380:38] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 381:38] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 382:38] + decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 383:38] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[el2_dec.scala 384:38] + decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 385:38] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 385:38] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 386:38] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 387:38] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 388:38] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 389:38] + decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 390:38] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 391:38] + io.dec_debug_wdata_rs1_d <= instbuff.io.dec_debug_wdata_rs1_d @[el2_dec.scala 392:38] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 393:38] + dec_trigger.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 399:30] + dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 400:34] + dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 400:34] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 409:48] + decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 410:48] + decode.io.ifu_i0_cinst <= io.ifu_i0_cinst @[el2_dec.scala 411:48] + decode.io.lsu_nonblock_load_valid_m <= io.lsu_nonblock_load_valid_m @[el2_dec.scala 412:48] + decode.io.lsu_nonblock_load_tag_m <= io.lsu_nonblock_load_tag_m @[el2_dec.scala 413:48] + decode.io.lsu_nonblock_load_inv_r <= io.lsu_nonblock_load_inv_r @[el2_dec.scala 414:48] + decode.io.lsu_nonblock_load_inv_tag_r <= io.lsu_nonblock_load_inv_tag_r @[el2_dec.scala 415:48] + decode.io.lsu_nonblock_load_data_valid <= io.lsu_nonblock_load_data_valid @[el2_dec.scala 416:48] + decode.io.lsu_nonblock_load_data_error <= io.lsu_nonblock_load_data_error @[el2_dec.scala 417:48] + decode.io.lsu_nonblock_load_data_tag <= io.lsu_nonblock_load_data_tag @[el2_dec.scala 418:48] + decode.io.lsu_nonblock_load_data <= io.lsu_nonblock_load_data @[el2_dec.scala 419:48] + decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[el2_dec.scala 420:48] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 421:48] + decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[el2_dec.scala 422:48] + decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[el2_dec.scala 423:48] + decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 424:48] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 425:48] + decode.io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 426:48] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 427:48] + decode.io.dbg_cmd_wrdata <= io.dbg_cmd_wrdata @[el2_dec.scala 428:48] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 429:48] + decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 430:48] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 431:48] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 432:48] + decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 433:48] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 433:48] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 434:48] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 435:48] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 436:48] + decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 437:48] + decode.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 438:48] + decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[el2_dec.scala 439:48] + decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 440:48] + decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 441:48] + decode.io.exu_div_wren <= io.exu_div_wren @[el2_dec.scala 442:48] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 443:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 444:48] + decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 445:48] + decode.io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 446:48] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 447:48] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 448:48] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 449:48] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 450:48] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 451:48] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 452:48] + decode.io.exu_csr_rs1_x <= io.exu_csr_rs1_x @[el2_dec.scala 453:48] + decode.io.lsu_result_m <= io.lsu_result_m @[el2_dec.scala 454:48] + decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[el2_dec.scala 455:48] + decode.io.exu_flush_final <= io.exu_flush_final @[el2_dec.scala 456:48] + decode.io.exu_i0_pc_x <= io.exu_i0_pc_x @[el2_dec.scala 457:48] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 458:48] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 459:48] + decode.io.exu_i0_result_x <= io.exu_i0_result_x @[el2_dec.scala 460:48] + decode.io.free_clk <= io.free_clk @[el2_dec.scala 462:48] + decode.io.active_clk <= io.active_clk @[el2_dec.scala 463:48] + decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[el2_dec.scala 464:48] + decode.io.scan_mode <= io.scan_mode @[el2_dec.scala 466:48] + io.dec_extint_stall <= decode.io.dec_extint_stall @[el2_dec.scala 468:40] + dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 469:40] + dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[el2_dec.scala 470:40] + io.dec_i0_rs1_en_d <= decode.io.dec_i0_rs1_en_d @[el2_dec.scala 471:40] + io.dec_i0_rs2_en_d <= decode.io.dec_i0_rs2_en_d @[el2_dec.scala 472:40] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 473:40] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 474:40] + io.dec_i0_immed_d <= decode.io.dec_i0_immed_d @[el2_dec.scala 475:40] + io.dec_i0_br_immed_d <= decode.io.dec_i0_br_immed_d @[el2_dec.scala 476:40] + io.i0_ap.csr_imm <= decode.io.i0_ap.csr_imm @[el2_dec.scala 477:40] + io.i0_ap.csr_write <= decode.io.i0_ap.csr_write @[el2_dec.scala 477:40] + io.i0_ap.predict_nt <= decode.io.i0_ap.predict_nt @[el2_dec.scala 477:40] + io.i0_ap.predict_t <= decode.io.i0_ap.predict_t @[el2_dec.scala 477:40] + io.i0_ap.jal <= decode.io.i0_ap.jal @[el2_dec.scala 477:40] + io.i0_ap.unsign <= decode.io.i0_ap.unsign @[el2_dec.scala 477:40] + io.i0_ap.slt <= decode.io.i0_ap.slt @[el2_dec.scala 477:40] + io.i0_ap.sub <= decode.io.i0_ap.sub @[el2_dec.scala 477:40] + io.i0_ap.add <= decode.io.i0_ap.add @[el2_dec.scala 477:40] + io.i0_ap.bge <= decode.io.i0_ap.bge @[el2_dec.scala 477:40] + io.i0_ap.blt <= decode.io.i0_ap.blt @[el2_dec.scala 477:40] + io.i0_ap.bne <= decode.io.i0_ap.bne @[el2_dec.scala 477:40] + io.i0_ap.beq <= decode.io.i0_ap.beq @[el2_dec.scala 477:40] + io.i0_ap.sra <= decode.io.i0_ap.sra @[el2_dec.scala 477:40] + io.i0_ap.srl <= decode.io.i0_ap.srl @[el2_dec.scala 477:40] + io.i0_ap.sll <= decode.io.i0_ap.sll @[el2_dec.scala 477:40] + io.i0_ap.lxor <= decode.io.i0_ap.lxor @[el2_dec.scala 477:40] + io.i0_ap.lor <= decode.io.i0_ap.lor @[el2_dec.scala 477:40] + io.i0_ap.land <= decode.io.i0_ap.land @[el2_dec.scala 477:40] + io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 478:40] + io.dec_i0_alu_decode_d <= decode.io.dec_i0_alu_decode_d @[el2_dec.scala 479:40] + io.dec_i0_rs1_bypass_data_d <= decode.io.dec_i0_rs1_bypass_data_d @[el2_dec.scala 480:40] + io.dec_i0_rs2_bypass_data_d <= decode.io.dec_i0_rs2_bypass_data_d @[el2_dec.scala 481:40] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 482:40] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 483:40] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 484:40] + io.dec_i0_select_pc_d <= decode.io.dec_i0_select_pc_d @[el2_dec.scala 485:40] + io.dec_i0_rs1_bypass_en_d <= decode.io.dec_i0_rs1_bypass_en_d @[el2_dec.scala 486:40] + io.dec_i0_rs2_bypass_en_d <= decode.io.dec_i0_rs2_bypass_en_d @[el2_dec.scala 487:40] + io.lsu_p.valid <= decode.io.lsu_p.valid @[el2_dec.scala 488:40] + io.lsu_p.store_data_bypass_m <= decode.io.lsu_p.store_data_bypass_m @[el2_dec.scala 488:40] + io.lsu_p.load_ldst_bypass_d <= decode.io.lsu_p.load_ldst_bypass_d @[el2_dec.scala 488:40] + io.lsu_p.store_data_bypass_d <= decode.io.lsu_p.store_data_bypass_d @[el2_dec.scala 488:40] + io.lsu_p.dma <= decode.io.lsu_p.dma @[el2_dec.scala 488:40] + io.lsu_p.unsign <= decode.io.lsu_p.unsign @[el2_dec.scala 488:40] + io.lsu_p.store <= decode.io.lsu_p.store @[el2_dec.scala 488:40] + io.lsu_p.load <= decode.io.lsu_p.load @[el2_dec.scala 488:40] + io.lsu_p.dword <= decode.io.lsu_p.dword @[el2_dec.scala 488:40] + io.lsu_p.word <= decode.io.lsu_p.word @[el2_dec.scala 488:40] + io.lsu_p.half <= decode.io.lsu_p.half @[el2_dec.scala 488:40] + io.lsu_p.by <= decode.io.lsu_p.by @[el2_dec.scala 488:40] + io.lsu_p.fast_int <= decode.io.lsu_p.fast_int @[el2_dec.scala 488:40] + io.mul_p.bfp <= decode.io.mul_p.bfp @[el2_dec.scala 489:40] + io.mul_p.crc32c_w <= decode.io.mul_p.crc32c_w @[el2_dec.scala 489:40] + io.mul_p.crc32c_h <= decode.io.mul_p.crc32c_h @[el2_dec.scala 489:40] + io.mul_p.crc32c_b <= decode.io.mul_p.crc32c_b @[el2_dec.scala 489:40] + io.mul_p.crc32_w <= decode.io.mul_p.crc32_w @[el2_dec.scala 489:40] + io.mul_p.crc32_h <= decode.io.mul_p.crc32_h @[el2_dec.scala 489:40] + io.mul_p.crc32_b <= decode.io.mul_p.crc32_b @[el2_dec.scala 489:40] + io.mul_p.unshfl <= decode.io.mul_p.unshfl @[el2_dec.scala 489:40] + io.mul_p.shfl <= decode.io.mul_p.shfl @[el2_dec.scala 489:40] + io.mul_p.grev <= decode.io.mul_p.grev @[el2_dec.scala 489:40] + io.mul_p.clmulr <= decode.io.mul_p.clmulr @[el2_dec.scala 489:40] + io.mul_p.clmulh <= decode.io.mul_p.clmulh @[el2_dec.scala 489:40] + io.mul_p.clmul <= decode.io.mul_p.clmul @[el2_dec.scala 489:40] + io.mul_p.bdep <= decode.io.mul_p.bdep @[el2_dec.scala 489:40] + io.mul_p.bext <= decode.io.mul_p.bext @[el2_dec.scala 489:40] + io.mul_p.low <= decode.io.mul_p.low @[el2_dec.scala 489:40] + io.mul_p.rs2_sign <= decode.io.mul_p.rs2_sign @[el2_dec.scala 489:40] + io.mul_p.rs1_sign <= decode.io.mul_p.rs1_sign @[el2_dec.scala 489:40] + io.mul_p.valid <= decode.io.mul_p.valid @[el2_dec.scala 489:40] + io.div_p.rem <= decode.io.div_p.rem @[el2_dec.scala 490:40] + io.div_p.unsign <= decode.io.div_p.unsign @[el2_dec.scala 490:40] + io.div_p.valid <= decode.io.div_p.valid @[el2_dec.scala 490:40] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 491:40] + io.dec_div_cancel <= decode.io.dec_div_cancel @[el2_dec.scala 492:40] + io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[el2_dec.scala 493:40] + io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[el2_dec.scala 494:40] + io.dec_csr_ren_d <= decode.io.dec_csr_ren_d @[el2_dec.scala 495:40] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 496:40] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 497:40] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 498:40] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 499:40] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 500:40] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 501:40] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 502:40] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 503:40] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 504:40] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 504:40] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 505:40] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 506:40] + io.pred_correct_npc_x <= decode.io.pred_correct_npc_x @[el2_dec.scala 507:40] + io.dec_i0_predict_p_d.way <= decode.io.dec_i0_predict_p_d.way @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.pja <= decode.io.dec_i0_predict_p_d.pja @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.pret <= decode.io.dec_i0_predict_p_d.pret @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.pcall <= decode.io.dec_i0_predict_p_d.pcall @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.prett <= decode.io.dec_i0_predict_p_d.prett @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.br_start_error <= decode.io.dec_i0_predict_p_d.br_start_error @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.br_error <= decode.io.dec_i0_predict_p_d.br_error @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.valid <= decode.io.dec_i0_predict_p_d.valid @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.toffset <= decode.io.dec_i0_predict_p_d.toffset @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.hist <= decode.io.dec_i0_predict_p_d.hist @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.pc4 <= decode.io.dec_i0_predict_p_d.pc4 @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.boffset <= decode.io.dec_i0_predict_p_d.boffset @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.ataken <= decode.io.dec_i0_predict_p_d.ataken @[el2_dec.scala 508:40] + io.dec_i0_predict_p_d.misp <= decode.io.dec_i0_predict_p_d.misp @[el2_dec.scala 508:40] + io.i0_predict_fghr_d <= decode.io.i0_predict_fghr_d @[el2_dec.scala 509:40] + io.i0_predict_index_d <= decode.io.i0_predict_index_d @[el2_dec.scala 510:40] + io.i0_predict_btag_d <= decode.io.i0_predict_btag_d @[el2_dec.scala 511:40] + io.dec_data_en <= decode.io.dec_data_en @[el2_dec.scala 512:40] + io.dec_ctl_en <= decode.io.dec_ctl_en @[el2_dec.scala 513:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 514:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 515:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 516:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 517:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 518:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 519:40] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pause_state @[el2_dec.scala 520:40] + io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[el2_dec.scala 521:40] + tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 522:40] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 529:23] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 530:23] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 531:23] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 532:23] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 533:23] + gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 534:23] + gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 535:23] + gpr.io.wd1 <= io.lsu_nonblock_load_data @[el2_dec.scala 536:23] + gpr.io.wen2 <= io.exu_div_wren @[el2_dec.scala 537:23] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 538:23] + gpr.io.wd2 <= io.exu_div_result @[el2_dec.scala 539:23] + gpr.io.scan_mode <= io.scan_mode @[el2_dec.scala 542:23] + io.gpr_i0_rs1_d <= gpr.io.rd0 @[el2_dec.scala 544:19] + io.gpr_i0_rs2_d <= gpr.io.rd1 @[el2_dec.scala 545:19] + tlu.io.active_clk <= io.active_clk @[el2_dec.scala 554:45] + tlu.io.free_clk <= io.free_clk @[el2_dec.scala 555:45] + tlu.io.scan_mode <= io.scan_mode @[el2_dec.scala 557:45] + tlu.io.rst_vec <= io.rst_vec @[el2_dec.scala 558:45] + tlu.io.nmi_int <= io.nmi_int @[el2_dec.scala 559:45] + tlu.io.nmi_vec <= io.nmi_vec @[el2_dec.scala 560:45] + tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_dec.scala 561:45] + tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_dec.scala 562:45] + tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[el2_dec.scala 563:45] + tlu.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec.scala 564:45] + tlu.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec.scala 565:45] + tlu.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec.scala 566:45] + tlu.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec.scala 567:45] + tlu.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec.scala 568:45] + tlu.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec.scala 569:45] + tlu.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec.scala 570:45] + tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 571:45] + tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 572:45] + tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 573:45] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 574:45] + tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 575:45] + tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 576:45] + tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec.scala 577:45] + tlu.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec.scala 578:45] + tlu.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec.scala 579:45] + tlu.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec.scala 580:45] + tlu.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec.scala 581:45] + tlu.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 582:45] + tlu.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec.scala 583:45] + tlu.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec.scala 584:45] + tlu.io.lsu_pmu_load_external_m <= io.lsu_pmu_load_external_m @[el2_dec.scala 585:45] + tlu.io.lsu_pmu_store_external_m <= io.lsu_pmu_store_external_m @[el2_dec.scala 586:45] + tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec.scala 587:45] + tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec.scala 588:45] + tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec.scala 589:45] + tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec.scala 590:45] + tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[el2_dec.scala 591:45] + tlu.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec.scala 592:45] + tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec.scala 593:45] + tlu.io.lsu_error_pkt_r.addr <= io.lsu_error_pkt_r.addr @[el2_dec.scala 594:45] + tlu.io.lsu_error_pkt_r.mscause <= io.lsu_error_pkt_r.mscause @[el2_dec.scala 594:45] + tlu.io.lsu_error_pkt_r.exc_type <= io.lsu_error_pkt_r.exc_type @[el2_dec.scala 594:45] + tlu.io.lsu_error_pkt_r.inst_type <= io.lsu_error_pkt_r.inst_type @[el2_dec.scala 594:45] + tlu.io.lsu_error_pkt_r.single_ecc_error <= io.lsu_error_pkt_r.single_ecc_error @[el2_dec.scala 594:45] + tlu.io.lsu_error_pkt_r.exc_valid <= io.lsu_error_pkt_r.exc_valid @[el2_dec.scala 594:45] + tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[el2_dec.scala 595:45] + tlu.io.dec_pause_state <= decode.io.dec_pause_state @[el2_dec.scala 596:45] + tlu.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec.scala 597:45] + tlu.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec.scala 598:45] + tlu.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec.scala 599:45] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 600:45] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 601:45] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 602:45] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 603:45] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 604:45] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 605:45] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 606:45] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 607:45] + tlu.io.exu_npc_r <= io.exu_npc_r @[el2_dec.scala 608:45] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 609:45] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 610:45] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 610:45] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 611:45] + tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 612:45] + tlu.io.exu_i0_br_hist_r <= io.exu_i0_br_hist_r @[el2_dec.scala 613:45] + tlu.io.exu_i0_br_error_r <= io.exu_i0_br_error_r @[el2_dec.scala 614:45] + tlu.io.exu_i0_br_start_error_r <= io.exu_i0_br_start_error_r @[el2_dec.scala 615:45] + tlu.io.exu_i0_br_valid_r <= io.exu_i0_br_valid_r @[el2_dec.scala 616:45] + tlu.io.exu_i0_br_mp_r <= io.exu_i0_br_mp_r @[el2_dec.scala 617:45] + tlu.io.exu_i0_br_middle_r <= io.exu_i0_br_middle_r @[el2_dec.scala 618:45] + tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[el2_dec.scala 619:45] + tlu.io.dbg_halt_req <= io.dbg_halt_req @[el2_dec.scala 620:45] + tlu.io.dbg_resume_req <= io.dbg_resume_req @[el2_dec.scala 621:45] + tlu.io.ifu_miss_state_idle <= io.ifu_miss_state_idle @[el2_dec.scala 622:45] + tlu.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 623:45] + tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 624:45] + tlu.io.ifu_ic_error_start <= io.ifu_ic_error_start @[el2_dec.scala 625:45] + tlu.io.ifu_iccm_rd_ecc_single_err <= io.ifu_iccm_rd_ecc_single_err @[el2_dec.scala 626:45] + tlu.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec.scala 627:45] + tlu.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec.scala 628:45] + tlu.io.pic_claimid <= io.pic_claimid @[el2_dec.scala 629:45] + tlu.io.pic_pl <= io.pic_pl @[el2_dec.scala 630:45] + tlu.io.mhwakeup <= io.mhwakeup @[el2_dec.scala 631:45] + tlu.io.mexintpend <= io.mexintpend @[el2_dec.scala 632:45] + tlu.io.timer_int <= io.timer_int @[el2_dec.scala 633:45] + tlu.io.soft_int <= io.soft_int @[el2_dec.scala 634:45] + tlu.io.core_id <= io.core_id @[el2_dec.scala 635:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_dec.scala 636:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_dec.scala 637:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec.scala 638:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[el2_dec.scala 640:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[el2_dec.scala 641:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[el2_dec.scala 642:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[el2_dec.scala 643:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[el2_dec.scala 644:28] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 645:36] + io.dec_tlu_flush_noredir_r <= tlu.io.dec_tlu_flush_noredir_r @[el2_dec.scala 646:34] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[el2_dec.scala 647:34] + io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 648:34] + io.dec_tlu_flush_err_r <= tlu.io.dec_tlu_flush_err_r @[el2_dec.scala 649:34] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 650:37] + io.dec_tlu_meihap <= tlu.io.dec_tlu_meihap @[el2_dec.scala 651:29] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 652:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 652:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 652:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 652:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 652:29] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 653:29] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 653:29] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec.scala 653:29] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec.scala 653:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[el2_dec.scala 654:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[el2_dec.scala 655:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[el2_dec.scala 656:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[el2_dec.scala 657:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[el2_dec.scala 658:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[el2_dec.scala 659:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 660:29] + io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 661:29] + io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 662:29] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 663:33] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 664:33] + io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 665:42] + io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 665:42] + io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 665:42] + io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 665:42] + io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 665:42] + io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 665:42] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 666:42] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 667:42] + io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 668:34] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 669:34] + io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 670:34] + io.dec_tlu_flush_path_r <= tlu.io.dec_tlu_flush_path_r @[el2_dec.scala 671:34] + io.dec_tlu_fence_i_r <= tlu.io.dec_tlu_fence_i_r @[el2_dec.scala 672:34] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 673:35] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 674:35] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 675:35] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 676:35] + io.dec_tlu_mrac_ff <= tlu.io.dec_tlu_mrac_ff @[el2_dec.scala 677:29] + io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 678:29] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[el2_dec.scala 679:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[el2_dec.scala 680:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[el2_dec.scala 681:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[el2_dec.scala 682:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec.scala 683:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[el2_dec.scala 684:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[el2_dec.scala 685:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[el2_dec.scala 686:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 687:32] + io.dec_tlu_external_ldfwd_disable <= tlu.io.dec_tlu_external_ldfwd_disable @[el2_dec.scala 688:43] + io.dec_tlu_sideeffect_posted_disable <= tlu.io.dec_tlu_sideeffect_posted_disable @[el2_dec.scala 689:43] + io.dec_tlu_core_ecc_disable <= tlu.io.dec_tlu_core_ecc_disable @[el2_dec.scala 690:43] + io.dec_tlu_bpred_disable <= tlu.io.dec_tlu_bpred_disable @[el2_dec.scala 691:43] + io.dec_tlu_wb_coalescing_disable <= tlu.io.dec_tlu_wb_coalescing_disable @[el2_dec.scala 692:43] + io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[el2_dec.scala 694:35] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[el2_dec.scala 695:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[el2_dec.scala 697:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[el2_dec.scala 698:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[el2_dec.scala 699:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[el2_dec.scala 700:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[el2_dec.scala 701:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[el2_dec.scala 702:36] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[el2_dec.scala 709:21] + diff --git a/el2_dec.v b/el2_dec.v new file mode 100644 index 00000000..1b9aecc4 --- /dev/null +++ b/el2_dec.v @@ -0,0 +1,14144 @@ +module el2_dec_ib_ctl( + input io_dbg_cmd_valid, + input io_dbg_cmd_write, + input [1:0] io_dbg_cmd_type, + input [31:0] io_dbg_cmd_addr, + input io_i0_brp_valid, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, + input [7:0] io_ifu_i0_bp_index, + input [7:0] io_ifu_i0_bp_fghr, + input [4:0] io_ifu_i0_bp_btag, + input io_ifu_i0_valid, + input io_ifu_i0_icaf, + input [1:0] io_ifu_i0_icaf_type, + input io_ifu_i0_icaf_f1, + input io_ifu_i0_dbecc, + input [31:0] io_ifu_i0_instr, + input [30:0] io_ifu_i0_pc, + output io_dec_ib0_valid_d, + output [1:0] io_dec_i0_icaf_type_d, + output [31:0] io_dec_i0_instr_d, + output [30:0] io_dec_i0_pc_d, + output io_dec_i0_brp_valid, + output [11:0] io_dec_i0_brp_toffset, + output [1:0] io_dec_i0_brp_hist, + output io_dec_i0_brp_br_error, + output io_dec_i0_brp_br_start_error, + output [30:0] io_dec_i0_brp_prett, + output io_dec_i0_brp_way, + output io_dec_i0_brp_ret, + output [7:0] io_dec_i0_bp_index, + output [7:0] io_dec_i0_bp_fghr, + output [4:0] io_dec_i0_bp_btag, + output io_dec_i0_icaf_d, + output io_dec_i0_icaf_f1_d, + output io_dec_i0_dbecc_d, + output io_dec_debug_wdata_rs1_d, + output io_dec_debug_fence_d +); + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40] + wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] + wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] + wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] + wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24] +endmodule +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 465:26] + wire clkhdr_CK; // @[el2_lib.scala 465:26] + wire clkhdr_EN; // @[el2_lib.scala 465:26] + wire clkhdr_SE; // @[el2_lib.scala 465:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18] +endmodule +module el2_dec_dec_ctl( + input [31:0] io_ins, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] + wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] + wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] + wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] + wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] + wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] + wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] + wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] + wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] + wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] + wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] + wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] + wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] + wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] + wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] + wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] + wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] + wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] + wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] + wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] + wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] + wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] + wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] + wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] + wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] + wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] + wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] + wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] + wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] + wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] + wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] + wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] + wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] + wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] + wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] + wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] + wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] + wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] + wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] + wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] + wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] + wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] + wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] + wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] + wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] + wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] + wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] + wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] + wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] + wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] + wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] + wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] + wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] + wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] + wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] + wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] + wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] + wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] + wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] + wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] + wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] + wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] + wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] + wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] + wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] + wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] + wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] + wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] + wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] + wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] + wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] + wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] + wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] + wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] + wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] + wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] + wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] + wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] + wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] + wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] + wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] + wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] + wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] + wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] + wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] + wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] + wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] + wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] + wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] + wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] + wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] + wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] + assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] + assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] + assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] + assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] + assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] + assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] + assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] + assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] + assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] + assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] + assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] + assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] + assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] + assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] + assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] + assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] + assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] + assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] + assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] + assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] + assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] + assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] + assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] + assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] + assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] + assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] + assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] + assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] + assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] + assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] + assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] + assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] + assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] + assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] + assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] + assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] + assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] + assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] + assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] + assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] + assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] + assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] + assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] + assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] + assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] + assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] + assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] +endmodule +module el2_dec_decode_ctl( + input clock, + input reset, + input io_dec_tlu_flush_extint, + input io_dec_tlu_force_halt, + output io_dec_extint_stall, + input [15:0] io_ifu_i0_cinst, + input io_lsu_nonblock_load_valid_m, + input [1:0] io_lsu_nonblock_load_tag_m, + input io_lsu_nonblock_load_inv_r, + input [1:0] io_lsu_nonblock_load_inv_tag_r, + input io_lsu_nonblock_load_data_valid, + input io_lsu_nonblock_load_data_error, + input [1:0] io_lsu_nonblock_load_data_tag, + input [31:0] io_lsu_nonblock_load_data, + input [3:0] io_dec_i0_trigger_match_d, + input io_dec_tlu_wr_pause_r, + input io_dec_tlu_pipelining_disable, + input [3:0] io_lsu_trigger_match_m, + input io_lsu_pmu_misaligned_m, + input io_dec_tlu_debug_stall, + input io_dec_tlu_flush_leak_one_r, + input io_dec_debug_fence_d, + input [1:0] io_dbg_cmd_wrdata, + input io_dec_i0_icaf_d, + input io_dec_i0_icaf_f1_d, + input [1:0] io_dec_i0_icaf_type_d, + input io_dec_i0_dbecc_d, + input io_dec_i0_brp_valid, + input [11:0] io_dec_i0_brp_toffset, + input [1:0] io_dec_i0_brp_hist, + input io_dec_i0_brp_br_error, + input io_dec_i0_brp_br_start_error, + input [30:0] io_dec_i0_brp_prett, + input io_dec_i0_brp_way, + input io_dec_i0_brp_ret, + input [7:0] io_dec_i0_bp_index, + input [7:0] io_dec_i0_bp_fghr, + input [4:0] io_dec_i0_bp_btag, + input io_lsu_idle_any, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_exu_div_wren, + input io_dec_tlu_i0_kill_writeb_wb, + input io_dec_tlu_flush_lower_wb, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_flush_pause_r, + input io_dec_tlu_presync_d, + input io_dec_tlu_postsync_d, + input io_dec_i0_pc4_d, + input [31:0] io_dec_csr_rddata_d, + input io_dec_csr_legal_d, + input [31:0] io_exu_csr_rs1_x, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_exu_flush_final, + input [30:0] io_exu_i0_pc_x, + input [31:0] io_dec_i0_instr_d, + input io_dec_ib0_valid_d, + input [31:0] io_exu_i0_result_x, + input io_free_clk, + input io_active_clk, + input io_clk_override, + output io_dec_i0_rs1_en_d, + output io_dec_i0_rs2_en_d, + output [4:0] io_dec_i0_rs1_d, + output [4:0] io_dec_i0_rs2_d, + output [31:0] io_dec_i0_immed_d, + output [11:0] io_dec_i0_br_immed_d, + output io_i0_ap_land, + output io_i0_ap_lor, + output io_i0_ap_lxor, + output io_i0_ap_sll, + output io_i0_ap_srl, + output io_i0_ap_sra, + output io_i0_ap_beq, + output io_i0_ap_bne, + output io_i0_ap_blt, + output io_i0_ap_bge, + output io_i0_ap_add, + output io_i0_ap_sub, + output io_i0_ap_slt, + output io_i0_ap_unsign, + output io_i0_ap_jal, + output io_i0_ap_predict_t, + output io_i0_ap_predict_nt, + output io_i0_ap_csr_write, + output io_i0_ap_csr_imm, + output io_dec_i0_decode_d, + output io_dec_i0_alu_decode_d, + output [31:0] io_dec_i0_rs1_bypass_data_d, + output [31:0] io_dec_i0_rs2_bypass_data_d, + output [4:0] io_dec_i0_waddr_r, + output io_dec_i0_wen_r, + output [31:0] io_dec_i0_wdata_r, + output io_dec_i0_select_pc_d, + output [1:0] io_dec_i0_rs1_bypass_en_d, + output [1:0] io_dec_i0_rs2_bypass_en_d, + output io_lsu_p_fast_int, + output io_lsu_p_by, + output io_lsu_p_half, + output io_lsu_p_word, + output io_lsu_p_load, + output io_lsu_p_store, + output io_lsu_p_unsign, + output io_lsu_p_store_data_bypass_d, + output io_lsu_p_load_ldst_bypass_d, + output io_lsu_p_valid, + output io_mul_p_valid, + output io_mul_p_rs1_sign, + output io_mul_p_rs2_sign, + output io_mul_p_low, + output io_div_p_valid, + output io_div_p_unsign, + output io_div_p_rem, + output [4:0] io_div_waddr_wb, + output io_dec_div_cancel, + output io_dec_lsu_valid_raw_d, + output [11:0] io_dec_lsu_offset_d, + output io_dec_csr_ren_d, + output io_dec_csr_wen_unq_d, + output io_dec_csr_any_unq_d, + output [11:0] io_dec_csr_rdaddr_d, + output io_dec_csr_wen_r, + output [11:0] io_dec_csr_wraddr_r, + output [31:0] io_dec_csr_wrdata_r, + output io_dec_csr_stall_int_ff, + output io_dec_tlu_i0_valid_r, + output io_dec_tlu_packet_r_legal, + output io_dec_tlu_packet_r_icaf, + output io_dec_tlu_packet_r_icaf_f1, + output [1:0] io_dec_tlu_packet_r_icaf_type, + output io_dec_tlu_packet_r_fence_i, + output [3:0] io_dec_tlu_packet_r_i0trigger, + output [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + output io_dec_tlu_packet_r_pmu_i0_br_unpred, + output io_dec_tlu_packet_r_pmu_divide, + output io_dec_tlu_packet_r_pmu_lsu_misaligned, + output [30:0] io_dec_tlu_i0_pc_r, + output [31:0] io_dec_illegal_inst, + output [30:0] io_pred_correct_npc_x, + output io_dec_i0_predict_p_d_pc4, + output [1:0] io_dec_i0_predict_p_d_hist, + output [11:0] io_dec_i0_predict_p_d_toffset, + output io_dec_i0_predict_p_d_valid, + output io_dec_i0_predict_p_d_br_error, + output io_dec_i0_predict_p_d_br_start_error, + output [30:0] io_dec_i0_predict_p_d_prett, + output io_dec_i0_predict_p_d_pcall, + output io_dec_i0_predict_p_d_pret, + output io_dec_i0_predict_p_d_pja, + output io_dec_i0_predict_p_d_way, + output [7:0] io_i0_predict_fghr_d, + output [7:0] io_i0_predict_index_d, + output [4:0] io_i0_predict_btag_d, + output [1:0] io_dec_data_en, + output [1:0] io_dec_ctl_en, + output io_dec_pmu_instr_decoded, + output io_dec_pmu_decode_stall, + output io_dec_pmu_presync_stall, + output io_dec_pmu_postsync_stall, + output io_dec_nonblock_load_wen, + output [4:0] io_dec_nonblock_load_waddr, + output io_dec_pause_state, + output io_dec_pause_state_cg, + output io_dec_div_active, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; +`endif // RANDOMIZE_REG_INIT + wire data_gated_cgc_io_l1clk; // @[el2_dec_decode_ctl.scala 221:29] + wire data_gated_cgc_io_clk; // @[el2_dec_decode_ctl.scala 221:29] + wire data_gated_cgc_io_en; // @[el2_dec_decode_ctl.scala 221:29] + wire data_gated_cgc_io_scan_mode; // @[el2_dec_decode_ctl.scala 221:29] + wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 395:22] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 502:29] + wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51] + reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 503:29] + wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32] + wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73] + wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32] + wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56] + reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 403:56] + wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 402:73] + wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 402:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 402:53] + wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32] + wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56] + wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 405:45] + reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 406:56] + wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 405:81] + wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 405:63] + wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32] + wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56] + reg pause_stall; // @[el2_dec_decode_ctl.scala 500:50] + wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 499:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 498:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 498:47] + reg [31:0] write_csr_data; // @[el2_lib.scala 491:16] + wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 498:109] + wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 498:91] + wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 498:76] + wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 499:61] + wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 499:59] + wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32] + wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56] + wire _T_17 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 229:62] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_17; // @[el2_dec_decode_ctl.scala 229:60] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire [20:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 411:79] + wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 411:112] + wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 411:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 412:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 625:16] + wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 412:76] + wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 412:98] + wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 412:89] + wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 412:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 414:38] + wire _T_19 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 240:75] + wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 413:67] + wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 413:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 416:38] + wire _T_20 = _T_19 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 240:90] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 420:37] + wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 420:65] + wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 420:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 623:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 420:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 420:111] + wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 420:101] + wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 420:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 421:32] + wire _T_21 = _T_20 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:103] + wire _T_22 = ~_T_21; // @[el2_dec_decode_ctl.scala 240:56] + wire i0_notbr_error = i0_brp_valid & _T_22; // @[el2_dec_decode_ctl.scala 240:54] + wire _T_30 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 245:57] + wire _T_24 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 243:47] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 418:41] + wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 418:26] + wire _T_25 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 243:96] + wire _T_26 = _T_24 & _T_25; // @[el2_dec_decode_ctl.scala 243:71] + wire _T_27 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 243:116] + wire i0_br_toffset_error = _T_26 & _T_27; // @[el2_dec_decode_ctl.scala 243:114] + wire _T_31 = _T_30 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 245:74] + wire _T_28 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 244:47] + wire i0_ret_error = _T_28 & _T_27; // @[el2_dec_decode_ctl.scala 244:67] + wire i0_br_error = _T_31 | i0_ret_error; // @[el2_dec_decode_ctl.scala 245:96] + wire _T_38 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 250:47] + wire i0_br_error_all = _T_38 & _T_17; // @[el2_dec_decode_ctl.scala 250:79] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 259:36] + wire _T_40 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 263:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_postsync = _T_40 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 263:50] + wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 529:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 521:48] + wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 529:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_csr_write = _T_40 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 263:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 460:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 460:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_csr_read = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 263:50] + wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 465:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 465:39] + wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 529:112] + wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 529:99] + wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 529:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_legal = _T_40 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 263:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 531:34] + wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 533:40] + wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 533:51] + wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 533:37] + wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 573:56] + wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 573:54] + wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 573:39] + reg postsync_stall; // @[el2_dec_decode_ctl.scala 571:53] + reg x_d_i0valid; // @[el2_lib.scala 501:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 573:88] + wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 573:69] + wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] + wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] + reg flush_final_r; // @[el2_dec_decode_ctl.scala 619:52] + wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32] + wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56] + wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 537:47] + reg illegal_lockout; // @[el2_dec_decode_ctl.scala 541:54] + wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 540:40] + wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 540:61] + wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 540:59] + wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 647:46] + wire _T_32 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 246:67] + wire _T_35 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 247:84] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_pm_alu = _T_40 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_fence_i = _T_40 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_fence = _T_40 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_div = _T_40 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_mul = _T_40 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_mret = _T_40 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_ecall = _T_40 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_ebreak = _T_40 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_presync = _T_40 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_csr_set = _T_40 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_csr_clr = _T_40 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_word = _T_40 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_half = _T_40 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_by = _T_40 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_jal = _T_40 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_condbr = _T_40 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_lsu = _T_40 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_store = _T_40 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_load = _T_40 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_imm20 = _T_40 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_shimm5 = _T_40 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_rd = _T_40 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_imm12 = _T_40 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_rs2 = _T_40 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_alu = _T_40 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] + wire _T_43 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 277:38] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] + wire _T_44 = _T_43 | i0_pja; // @[el2_dec_decode_ctl.scala 277:49] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] + wire i0_predict_br = _T_44 | i0_pret; // @[el2_dec_decode_ctl.scala 277:58] + wire _T_46 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 279:50] + wire _T_47 = ~_T_46; // @[el2_dec_decode_ctl.scala 279:26] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 281:20] + wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 314:63] + reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 350:47] + wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_93 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_94 = cam_data_reset & _T_93; // @[el2_dec_decode_ctl.scala 325:45] + reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 350:47] + wire cam_data_reset_val_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 325:83] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 329:39] + wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 306:78] + reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_119 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_120 = cam_data_reset & _T_119; // @[el2_dec_decode_ctl.scala 325:45] + reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 350:47] + wire cam_data_reset_val_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 325:83] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 329:39] + wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 306:126] + wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 306:158] + reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_145 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_146 = cam_data_reset & _T_145; // @[el2_dec_decode_ctl.scala 325:45] + reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 350:47] + wire cam_data_reset_val_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 325:83] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 329:39] + wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 306:126] + wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 306:126] + wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 306:158] + reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_171 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_172 = cam_data_reset & _T_171; // @[el2_dec_decode_ctl.scala 325:45] + reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 350:47] + wire cam_data_reset_val_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 325:83] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 329:39] + wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 306:126] + wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 306:126] + wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 306:158] + wire _T_80 = _T_50 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_81 = _T_56 ? _T_58 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_82 = _T_65 ? _T_67 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_83 = _T_77 ? _T_79 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_127 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] + wire [1:0] _T_84 = _GEN_127 | _T_81; // @[Mux.scala 27:72] + wire [2:0] _GEN_128 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] + wire [2:0] _T_85 = _GEN_128 | _T_82; // @[Mux.scala 27:72] + wire [3:0] _GEN_129 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_129 | _T_83; // @[Mux.scala 27:72] + reg x_d_i0load; // @[el2_lib.scala 501:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 501:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 317:31] + reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 655:72] + wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] + wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 658:49] + wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] + reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] + reg r_d_i0load; // @[el2_lib.scala 501:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 322:56] + wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_90 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_91 = io_lsu_nonblock_load_inv_r & _T_90; // @[el2_dec_decode_ctl.scala 324:45] + wire cam_inv_reset_val_0 = _T_91 & cam_0_valid; // @[el2_dec_decode_ctl.scala 324:82] + reg r_d_i0v; // @[el2_lib.scala 501:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 690:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 690:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 698:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 698:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 501:16] + reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_102 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 337:80] + wire _T_103 = i0_wen_r & _T_102; // @[el2_dec_decode_ctl.scala 337:64] + reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_105 = _T_103 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 337:95] + wire _T_106 = cam_inv_reset_val_0 | _T_105; // @[el2_dec_decode_ctl.scala 337:44] + wire _GEN_52 = _T_106 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_55 = _T_106 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 332:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 332:28] + wire _T_109 = nonblock_load_valid_m_delay & _T_90; // @[el2_dec_decode_ctl.scala 342:44] + wire _T_111 = _T_109 & cam_0_valid; // @[el2_dec_decode_ctl.scala 342:95] + wire nonblock_load_write_0 = _T_93 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 351:66] + wire _T_116 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_117 = io_lsu_nonblock_load_inv_r & _T_116; // @[el2_dec_decode_ctl.scala 324:45] + wire cam_inv_reset_val_1 = _T_117 & cam_1_valid; // @[el2_dec_decode_ctl.scala 324:82] + reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_128 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 337:80] + wire _T_129 = i0_wen_r & _T_128; // @[el2_dec_decode_ctl.scala 337:64] + reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_131 = _T_129 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 337:95] + wire _T_132 = cam_inv_reset_val_1 | _T_131; // @[el2_dec_decode_ctl.scala 337:44] + wire _GEN_63 = _T_132 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_66 = _T_132 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 332:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 332:28] + wire _T_135 = nonblock_load_valid_m_delay & _T_116; // @[el2_dec_decode_ctl.scala 342:44] + wire _T_137 = _T_135 & cam_1_valid; // @[el2_dec_decode_ctl.scala 342:95] + wire nonblock_load_write_1 = _T_119 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 351:66] + wire _T_142 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_143 = io_lsu_nonblock_load_inv_r & _T_142; // @[el2_dec_decode_ctl.scala 324:45] + wire cam_inv_reset_val_2 = _T_143 & cam_2_valid; // @[el2_dec_decode_ctl.scala 324:82] + reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_154 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 337:80] + wire _T_155 = i0_wen_r & _T_154; // @[el2_dec_decode_ctl.scala 337:64] + reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_157 = _T_155 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 337:95] + wire _T_158 = cam_inv_reset_val_2 | _T_157; // @[el2_dec_decode_ctl.scala 337:44] + wire _GEN_74 = _T_158 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_77 = _T_158 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 332:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 332:28] + wire _T_161 = nonblock_load_valid_m_delay & _T_142; // @[el2_dec_decode_ctl.scala 342:44] + wire _T_163 = _T_161 & cam_2_valid; // @[el2_dec_decode_ctl.scala 342:95] + wire nonblock_load_write_2 = _T_145 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 351:66] + wire _T_168 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_169 = io_lsu_nonblock_load_inv_r & _T_168; // @[el2_dec_decode_ctl.scala 324:45] + wire cam_inv_reset_val_3 = _T_169 & cam_3_valid; // @[el2_dec_decode_ctl.scala 324:82] + reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_180 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 337:80] + wire _T_181 = i0_wen_r & _T_180; // @[el2_dec_decode_ctl.scala 337:64] + reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 350:47] + wire _T_183 = _T_181 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 337:95] + wire _T_184 = cam_inv_reset_val_3 | _T_183; // @[el2_dec_decode_ctl.scala 337:44] + wire _GEN_85 = _T_184 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_88 = _T_184 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 337:116] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 332:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 332:28] + wire _T_187 = nonblock_load_valid_m_delay & _T_168; // @[el2_dec_decode_ctl.scala 342:44] + wire _T_189 = _T_187 & cam_3_valid; // @[el2_dec_decode_ctl.scala 342:95] + wire nonblock_load_write_3 = _T_171 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 351:66] + wire _T_194 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 356:44] + wire nonblock_load_cancel = _T_194 & i0_wen_r; // @[el2_dec_decode_ctl.scala 356:76] + wire _T_195 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 357:95] + wire _T_196 = _T_195 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 357:95] + wire _T_197 = _T_196 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 357:95] + wire _T_199 = io_lsu_nonblock_load_data_valid & _T_197; // @[el2_dec_decode_ctl.scala 357:64] + wire _T_200 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 357:109] + wire _T_202 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 358:54] + wire _T_203 = _T_202 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 358:66] + wire _T_204 = _T_203 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 358:97] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 624:16] + wire _T_205 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 358:137] + wire _T_206 = _T_205 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 358:149] + wire _T_207 = _T_206 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 358:180] + wire i0_nonblock_boundary_stall = _T_204 | _T_207; // @[el2_dec_decode_ctl.scala 358:118] + wire [4:0] _T_209 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_210 = _T_209 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 362:88] + wire _T_211 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 362:121] + wire _T_212 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 362:149] + wire _T_213 = _T_211 & _T_212; // @[el2_dec_decode_ctl.scala 362:136] + wire _T_214 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 362:182] + wire _T_215 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 362:210] + wire _T_216 = _T_214 & _T_215; // @[el2_dec_decode_ctl.scala 362:197] + wire [4:0] _T_218 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_219 = _T_218 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 362:88] + wire _T_220 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 362:121] + wire _T_221 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 362:149] + wire _T_222 = _T_220 & _T_221; // @[el2_dec_decode_ctl.scala 362:136] + wire _T_223 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 362:182] + wire _T_224 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 362:210] + wire _T_225 = _T_223 & _T_224; // @[el2_dec_decode_ctl.scala 362:197] + wire [4:0] _T_227 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_228 = _T_227 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 362:88] + wire _T_229 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 362:121] + wire _T_230 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 362:149] + wire _T_231 = _T_229 & _T_230; // @[el2_dec_decode_ctl.scala 362:136] + wire _T_232 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 362:182] + wire _T_233 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 362:210] + wire _T_234 = _T_232 & _T_233; // @[el2_dec_decode_ctl.scala 362:197] + wire [4:0] _T_236 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_237 = _T_236 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 362:88] + wire _T_238 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 362:121] + wire _T_239 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 362:149] + wire _T_240 = _T_238 & _T_239; // @[el2_dec_decode_ctl.scala 362:136] + wire _T_241 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 362:182] + wire _T_242 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 362:210] + wire _T_243 = _T_241 & _T_242; // @[el2_dec_decode_ctl.scala 362:197] + wire [4:0] _T_244 = _T_210 | _T_219; // @[el2_dec_decode_ctl.scala 363:69] + wire [4:0] _T_245 = _T_244 | _T_228; // @[el2_dec_decode_ctl.scala 363:69] + wire _T_246 = _T_213 | _T_222; // @[el2_dec_decode_ctl.scala 363:102] + wire _T_247 = _T_246 | _T_231; // @[el2_dec_decode_ctl.scala 363:102] + wire ld_stall_1 = _T_247 | _T_240; // @[el2_dec_decode_ctl.scala 363:102] + wire _T_248 = _T_216 | _T_225; // @[el2_dec_decode_ctl.scala 363:134] + wire _T_249 = _T_248 | _T_234; // @[el2_dec_decode_ctl.scala 363:134] + wire ld_stall_2 = _T_249 | _T_243; // @[el2_dec_decode_ctl.scala 363:134] + wire _T_250 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 365:38] + wire i0_nonblock_load_stall = _T_250 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 365:51] + wire _T_252 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 374:34] + wire [3:0] _T_254 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 458:36] + wire _T_255 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 386:16] + wire _T_257 = ~csr_read; // @[el2_dec_decode_ctl.scala 387:6] + wire _T_258 = _T_257 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 387:16] + wire _T_260 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 388:18] + wire _T_261 = csr_read & _T_260; // @[el2_dec_decode_ctl.scala 388:16] + wire [3:0] _T_263 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_264 = i0_dp_load ? 4'h2 : _T_263; // @[Mux.scala 98:16] + wire [3:0] _T_265 = i0_dp_store ? 4'h3 : _T_264; // @[Mux.scala 98:16] + wire [3:0] _T_266 = i0_dp_pm_alu ? 4'h4 : _T_265; // @[Mux.scala 98:16] + wire [3:0] _T_267 = _T_261 ? 4'h5 : _T_266; // @[Mux.scala 98:16] + wire [3:0] _T_268 = _T_258 ? 4'h6 : _T_267; // @[Mux.scala 98:16] + wire [3:0] _T_269 = _T_255 ? 4'h7 : _T_268; // @[Mux.scala 98:16] + wire [3:0] _T_270 = i0_dp_ebreak ? 4'h8 : _T_269; // @[Mux.scala 98:16] + wire [3:0] _T_271 = i0_dp_ecall ? 4'h9 : _T_270; // @[Mux.scala 98:16] + wire [3:0] _T_272 = i0_dp_fence ? 4'ha : _T_271; // @[Mux.scala 98:16] + wire [3:0] _T_273 = i0_dp_fence_i ? 4'hb : _T_272; // @[Mux.scala 98:16] + wire [3:0] _T_274 = i0_dp_mret ? 4'hc : _T_273; // @[Mux.scala 98:16] + wire [3:0] _T_275 = i0_dp_condbr ? 4'hd : _T_274; // @[Mux.scala 98:16] + wire [3:0] _T_276 = i0_dp_jal ? 4'he : _T_275; // @[Mux.scala 98:16] + reg lsu_idle; // @[el2_dec_decode_ctl.scala 399:45] + wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 423:35] + wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 423:32] + wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 423:52] + wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 423:50] + wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 423:67] + reg _T_339; // @[el2_dec_decode_ctl.scala 435:58] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 577:40] + wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 791:43] + reg x_d_i0v; // @[el2_lib.scala 501:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 772:58] + wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 778:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 778:24] + wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 791:58] + reg i0_x_c_load; // @[Reg.scala 15:16] + reg i0_r_c_load; // @[Reg.scala 15:16] + wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 777:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 777:24] + wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 791:78] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 774:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 774:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 774:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 775:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 775:58] + wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 780:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 780:24] + wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:43] + wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 779:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 779:24] + wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 792:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 466:42] + reg r_d_csrwen; // @[el2_lib.scala 501:16] + reg r_d_i0valid; // @[el2_lib.scala 501:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 501:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 477:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 477:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 477:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 477:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 477:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 477:119] + reg csr_read_x; // @[el2_dec_decode_ctl.scala 479:52] + reg csr_clr_x; // @[el2_dec_decode_ctl.scala 480:51] + reg csr_set_x; // @[el2_dec_decode_ctl.scala 481:51] + reg csr_write_x; // @[el2_dec_decode_ctl.scala 482:53] + reg csr_imm_x; // @[el2_dec_decode_ctl.scala 483:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 660:50] + reg [4:0] csrimm_x; // @[el2_lib.scala 491:16] + reg [31:0] csr_rddata_x; // @[el2_lib.scala 491:16] + wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] + wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 491:5] + wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] + wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 494:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 494:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 495:35] + wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] + wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] + wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 505:44] + wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 505:64] + wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 505:61] + wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 508:59] + wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 510:34] + wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 510:46] + wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 510:61] + wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 510:75] + reg r_d_csrwonly; // @[el2_lib.scala 501:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 713:37] + reg [31:0] i0_result_r_raw; // @[el2_lib.scala 491:16] + wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 713:27] + reg x_d_csrwonly; // @[el2_lib.scala 501:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 519:38] + reg wbd_csrwonly; // @[el2_lib.scala 501:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 519:53] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 522:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 523:40] + wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 526:34] + wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 526:57] + wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 526:73] + wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 526:91] + wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58] + wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 538:44] + reg [31:0] _T_465; // @[el2_lib.scala 491:16] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 542:42] + wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 544:40] + wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 544:59] + wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 544:81] + wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 544:95] + wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 545:20] + wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 545:45] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 567:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 568:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 570:37] + wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 545:62] + wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 546:19] + wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 546:36] + wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 546:34] + wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 545:79] + wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 546:47] + wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 741:49] + wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 741:88] + wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 741:69] + wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:25] + wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 742:64] + wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 742:45] + wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 741:102] + wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 547:21] + wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 547:45] + wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 549:65] + wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 549:39] + wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:63] + wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 550:38] + wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 551:38] + wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 551:57] + wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 555:46] + wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 555:44] + wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 555:61] + wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 556:46] + wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 556:44] + wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] + wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 556:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 557:46] + wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:51] + wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 589:44] + wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] + wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 657:49] + wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 657:53] + reg x_t_legal; // @[el2_lib.scala 501:16] + reg x_t_icaf; // @[el2_lib.scala 501:16] + reg x_t_icaf_f1; // @[el2_lib.scala 501:16] + reg [1:0] x_t_icaf_type; // @[el2_lib.scala 501:16] + reg x_t_fence_i; // @[el2_lib.scala 501:16] + reg [3:0] x_t_i0trigger; // @[el2_lib.scala 501:16] + reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 501:16] + reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 501:16] + wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] + wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 602:39] + reg r_t_legal; // @[el2_lib.scala 501:16] + reg r_t_icaf; // @[el2_lib.scala 501:16] + reg r_t_icaf_f1; // @[el2_lib.scala 501:16] + reg [1:0] r_t_icaf_type; // @[el2_lib.scala 501:16] + reg r_t_fence_i; // @[el2_lib.scala 501:16] + reg [3:0] r_t_i0trigger; // @[el2_lib.scala 501:16] + reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 501:16] + reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 501:16] + reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 605:36] + reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 606:37] + reg r_d_i0store; // @[el2_lib.scala 501:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 610:56] + wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 610:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 610:95] + reg r_d_i0div; // @[el2_lib.scala 501:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 616:53] + wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 627:49] + wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] + wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 629:48] + wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 629:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 633:38] + wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 634:27] + wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] + wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = {_T_586,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] + wire [31:0] _T_684 = i0_dp_imm12 ? _T_589 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_618 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] + wire [31:0] _T_685 = i0_dp_shimm5 ? _T_618 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_689 = _T_684 | _T_685; // @[Mux.scala 27:72] + wire [31:0] _T_638 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_686 = i0_jalimm20 ? _T_638 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_690 = _T_689 | _T_686; // @[Mux.scala 27:72] + wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72] + wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 645:26] + wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] + wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72] + wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 649:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] + reg i0_x_c_mul; // @[Reg.scala 15:16] + reg i0_x_c_alu; // @[Reg.scala 15:16] + reg i0_r_c_mul; // @[Reg.scala 15:16] + reg i0_r_c_alu; // @[Reg.scala 15:16] + wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 659:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] + reg x_d_i0store; // @[el2_lib.scala 501:16] + reg x_d_i0div; // @[el2_lib.scala 501:16] + reg x_d_csrwen; // @[el2_lib.scala 501:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 501:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 683:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 684:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 699:49] + wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 699:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 699:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 708:42] + wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 714:52] + wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + reg [11:0] last_br_immed_x; // @[el2_lib.scala 491:16] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 722:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 722:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 724:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 724:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 725:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 724:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 726:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 725:59] + wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 730:51] + wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 731:26] + wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 731:24] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 731:51] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 731:39] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 731:72] + wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 730:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 734:55] + wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 736:62] + wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 736:60] + wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 736:81] + wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 736:79] + reg _T_821; // @[el2_dec_decode_ctl.scala 738:54] + reg [4:0] _T_830; // @[Reg.scala 27:20] + reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 491:16] + wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 206:31] + wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 207:27] + wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 208:27] + wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 210:28] + wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 210:26] + wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 211:20] + wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 211:26] + wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 212:26] + wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72] + wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 777:61] + wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 777:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 777:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 777:24] + wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 779:61] + wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 779:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 779:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 779:24] + wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 797:62] + wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 797:119] + wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 797:89] + wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 799:62] + wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 799:119] + wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 799:89] + wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 802:66] + wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 802:45] + wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 802:108] + wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 802:196] + wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 802:153] + wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58] + wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 804:67] + wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 804:45] + wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 804:109] + wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 804:196] + wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 804:153] + wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58] + wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 806:75] + wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 806:96] + wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 806:113] + wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 806:93] + wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 807:75] + wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 807:96] + wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:113] + wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 807:93] + wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 812:6] + wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 812:25] + wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 812:23] + wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 812:42] + wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72] + wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 817:6] + wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 817:25] + wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 817:23] + wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 817:42] + wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72] + wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 819:68] + wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 819:50] + wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 819:89] + wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 819:87] + wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 819:112] + wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 821:6] + wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 821:27] + wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 821:39] + wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 822:39] + wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72] + rvclkhdr data_gated_cgc ( // @[el2_dec_decode_ctl.scala 221:29] + .io_l1clk(data_gated_cgc_io_l1clk), + .io_clk(data_gated_cgc_io_clk), + .io_en(data_gated_cgc_io_en), + .io_scan_mode(data_gated_cgc_io_scan_mode) + ); + el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 395:22] + .io_ins(i0_dec_io_ins), + .io_out_alu(i0_dec_io_out_alu), + .io_out_rs1(i0_dec_io_out_rs1), + .io_out_rs2(i0_dec_io_out_rs2), + .io_out_imm12(i0_dec_io_out_imm12), + .io_out_rd(i0_dec_io_out_rd), + .io_out_shimm5(i0_dec_io_out_shimm5), + .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), + .io_out_load(i0_dec_io_out_load), + .io_out_store(i0_dec_io_out_store), + .io_out_lsu(i0_dec_io_out_lsu), + .io_out_add(i0_dec_io_out_add), + .io_out_sub(i0_dec_io_out_sub), + .io_out_land(i0_dec_io_out_land), + .io_out_lor(i0_dec_io_out_lor), + .io_out_lxor(i0_dec_io_out_lxor), + .io_out_sll(i0_dec_io_out_sll), + .io_out_sra(i0_dec_io_out_sra), + .io_out_srl(i0_dec_io_out_srl), + .io_out_slt(i0_dec_io_out_slt), + .io_out_unsign(i0_dec_io_out_unsign), + .io_out_condbr(i0_dec_io_out_condbr), + .io_out_beq(i0_dec_io_out_beq), + .io_out_bne(i0_dec_io_out_bne), + .io_out_bge(i0_dec_io_out_bge), + .io_out_blt(i0_dec_io_out_blt), + .io_out_jal(i0_dec_io_out_jal), + .io_out_by(i0_dec_io_out_by), + .io_out_half(i0_dec_io_out_half), + .io_out_word(i0_dec_io_out_word), + .io_out_csr_read(i0_dec_io_out_csr_read), + .io_out_csr_clr(i0_dec_io_out_csr_clr), + .io_out_csr_set(i0_dec_io_out_csr_set), + .io_out_csr_write(i0_dec_io_out_csr_write), + .io_out_csr_imm(i0_dec_io_out_csr_imm), + .io_out_presync(i0_dec_io_out_presync), + .io_out_postsync(i0_dec_io_out_postsync), + .io_out_ebreak(i0_dec_io_out_ebreak), + .io_out_ecall(i0_dec_io_out_ecall), + .io_out_mret(i0_dec_io_out_mret), + .io_out_mul(i0_dec_io_out_mul), + .io_out_rs1_sign(i0_dec_io_out_rs1_sign), + .io_out_rs2_sign(i0_dec_io_out_rs2_sign), + .io_out_low(i0_dec_io_out_low), + .io_out_div(i0_dec_io_out_div), + .io_out_rem(i0_dec_io_out_rem), + .io_out_fence(i0_dec_io_out_fence), + .io_out_fence_i(i0_dec_io_out_fence_i), + .io_out_pm_alu(i0_dec_io_out_pm_alu), + .io_out_legal(i0_dec_io_out_legal) + ); + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 495:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 495:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 495:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 495:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 495:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 435:23] + assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 627:24] + assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 628:24] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 630:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 631:19] + assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 636:21] + assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 714:24] + assign io_i0_ap_land = _T_40 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 288:20] + assign io_i0_ap_lor = _T_40 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 289:20] + assign io_i0_ap_lxor = _T_40 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 290:20] + assign io_i0_ap_sll = _T_40 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 291:20] + assign io_i0_ap_srl = _T_40 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 292:20] + assign io_i0_ap_sra = _T_40 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 293:20] + assign io_i0_ap_beq = _T_40 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 296:20] + assign io_i0_ap_bne = _T_40 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 297:20] + assign io_i0_ap_blt = _T_40 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 298:20] + assign io_i0_ap_bge = _T_40 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 299:20] + assign io_i0_ap_add = _T_40 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 286:20] + assign io_i0_ap_sub = _T_40 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 287:20] + assign io_i0_ap_slt = _T_40 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 294:20] + assign io_i0_ap_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 295:20] + assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 302:22] + assign io_i0_ap_predict_t = _T_46 & i0_predict_br; // @[el2_dec_decode_ctl.scala 284:26] + assign io_i0_ap_predict_nt = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 283:26] + assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 300:22] + assign io_i0_ap_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 301:22] + assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 555:22 el2_dec_decode_ctl.scala 621:22] + assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 575:26] + assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 809:31] + assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 814:31] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 697:27] + assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 699:32] + assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 700:26] + assign io_dec_i0_select_pc_d = _T_40 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 274:25] + assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 806:34] + assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 807:34] + assign io_lsu_p_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 441:24] + assign io_lsu_p_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 447:35] + assign io_lsu_p_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 448:35] + assign io_lsu_p_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 440:24 el2_dec_decode_ctl.scala 449:35] + assign io_lsu_p_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 439:24 el2_dec_decode_ctl.scala 445:35] + assign io_lsu_p_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 446:35] + assign io_lsu_p_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 453:35] + assign io_lsu_p_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 451:35] + assign io_lsu_p_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 450:35] + assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 442:24 el2_dec_decode_ctl.scala 444:35] + assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 430:21] + assign io_mul_p_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] + assign io_mul_p_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:21] + assign io_mul_p_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:21] + assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 426:21] + assign io_div_p_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 427:21] + assign io_div_p_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 428:21] + assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 744:19] + assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 733:29] + assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 819:26] + assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 820:23] + assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 457:21] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 466:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 469:24] + assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 474:20] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 470:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 517:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 477:27] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 581:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 615:39 el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 762:27] + assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 539:23] + assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 767:25] + assign io_dec_i0_predict_p_d_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 237:38] + assign io_dec_i0_predict_p_d_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 238:38] + assign io_dec_i0_predict_p_d_toffset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 251:44] + assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 239:38] + assign io_dec_i0_predict_p_d_br_error = _T_32 & _T_17; // @[el2_dec_decode_ctl.scala 246:51] + assign io_dec_i0_predict_p_d_br_start_error = _T_35 & _T_17; // @[el2_dec_decode_ctl.scala 247:51] + assign io_dec_i0_predict_p_d_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 236:38] + assign io_dec_i0_predict_p_d_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 233:38] + assign io_dec_i0_predict_p_d_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 235:38] + assign io_dec_i0_predict_p_d_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 234:38] + assign io_dec_i0_predict_p_d_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 253:51] + assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 252:32] + assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 248:32] + assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 249:32] + assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 665:27] + assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 666:27] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 560:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 561:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 563:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 562:29] + assign io_dec_nonblock_load_wen = _T_199 & _T_200; // @[el2_dec_decode_ctl.scala 357:28] + assign io_dec_nonblock_load_waddr = _T_245 | _T_237; // @[el2_dec_decode_ctl.scala 354:29 el2_dec_decode_ctl.scala 364:29] + assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 501:22] + assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 505:25] + assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 738:21] + assign data_gated_cgc_io_clk = clock; // @[el2_dec_decode_ctl.scala 224:31] + assign data_gated_cgc_io_en = _T_15 | _T_16; // @[el2_dec_decode_ctl.scala 222:31] + assign data_gated_cgc_io_scan_mode = io_scan_mode; // @[el2_dec_decode_ctl.scala 223:31] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 396:16] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + tlu_wr_pause_r1 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + tlu_wr_pause_r2 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + leak1_i1_stall = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + leak1_i0_stall = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + pause_stall = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + write_csr_data = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + postsync_stall = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + x_d_i0valid = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + flush_final_r = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + illegal_lockout = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + cam_raw_0_tag = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + cam_raw_0_valid = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + cam_raw_1_tag = _RAND_12[2:0]; + _RAND_13 = {1{`RANDOM}}; + cam_raw_1_valid = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + cam_raw_2_tag = _RAND_14[2:0]; + _RAND_15 = {1{`RANDOM}}; + cam_raw_2_valid = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + cam_raw_3_tag = _RAND_16[2:0]; + _RAND_17 = {1{`RANDOM}}; + cam_raw_3_valid = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + x_d_i0load = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + x_d_i0rd = _RAND_19[4:0]; + _RAND_20 = {1{`RANDOM}}; + _T_701 = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + nonblock_load_valid_m_delay = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + r_d_i0load = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + r_d_i0v = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + r_d_i0rd = _RAND_24[4:0]; + _RAND_25 = {1{`RANDOM}}; + cam_raw_0_rd = _RAND_25[4:0]; + _RAND_26 = {1{`RANDOM}}; + cam_raw_0_wb = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + cam_raw_1_rd = _RAND_27[4:0]; + _RAND_28 = {1{`RANDOM}}; + cam_raw_1_wb = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + cam_raw_2_rd = _RAND_29[4:0]; + _RAND_30 = {1{`RANDOM}}; + cam_raw_2_wb = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + cam_raw_3_rd = _RAND_31[4:0]; + _RAND_32 = {1{`RANDOM}}; + cam_raw_3_wb = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + lsu_idle = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_339 = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + x_d_i0v = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + i0_x_c_load = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + i0_r_c_load = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + r_d_csrwen = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + r_d_i0valid = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + r_d_csrwaddr = _RAND_40[11:0]; + _RAND_41 = {1{`RANDOM}}; + csr_read_x = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + csr_clr_x = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + csr_set_x = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + csr_write_x = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + csr_imm_x = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + csrimm_x = _RAND_46[4:0]; + _RAND_47 = {1{`RANDOM}}; + csr_rddata_x = _RAND_47[31:0]; + _RAND_48 = {1{`RANDOM}}; + r_d_csrwonly = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + i0_result_r_raw = _RAND_49[31:0]; + _RAND_50 = {1{`RANDOM}}; + x_d_csrwonly = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + wbd_csrwonly = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_465 = _RAND_52[31:0]; + _RAND_53 = {1{`RANDOM}}; + x_t_legal = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + x_t_icaf = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + x_t_icaf_f1 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + x_t_icaf_type = _RAND_56[1:0]; + _RAND_57 = {1{`RANDOM}}; + x_t_fence_i = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + x_t_i0trigger = _RAND_58[3:0]; + _RAND_59 = {1{`RANDOM}}; + x_t_pmu_i0_itype = _RAND_59[3:0]; + _RAND_60 = {1{`RANDOM}}; + x_t_pmu_i0_br_unpred = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + r_t_legal = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + r_t_icaf = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + r_t_icaf_f1 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + r_t_icaf_type = _RAND_64[1:0]; + _RAND_65 = {1{`RANDOM}}; + r_t_fence_i = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + r_t_i0trigger = _RAND_66[3:0]; + _RAND_67 = {1{`RANDOM}}; + r_t_pmu_i0_itype = _RAND_67[3:0]; + _RAND_68 = {1{`RANDOM}}; + r_t_pmu_i0_br_unpred = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + lsu_trigger_match_r = _RAND_69[3:0]; + _RAND_70 = {1{`RANDOM}}; + lsu_pmu_misaligned_r = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + r_d_i0store = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + r_d_i0div = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + i0_x_c_mul = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + i0_x_c_alu = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + i0_r_c_mul = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + i0_r_c_alu = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + x_d_i0store = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + x_d_i0div = _RAND_78[0:0]; + _RAND_79 = {1{`RANDOM}}; + x_d_csrwen = _RAND_79[0:0]; + _RAND_80 = {1{`RANDOM}}; + x_d_csrwaddr = _RAND_80[11:0]; + _RAND_81 = {1{`RANDOM}}; + last_br_immed_x = _RAND_81[11:0]; + _RAND_82 = {1{`RANDOM}}; + _T_821 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + _T_830 = _RAND_83[4:0]; + _RAND_84 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_84[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + tlu_wr_pause_r1 = 1'h0; + end + if (reset) begin + tlu_wr_pause_r2 = 1'h0; + end + if (reset) begin + leak1_i1_stall = 1'h0; + end + if (reset) begin + leak1_i0_stall = 1'h0; + end + if (reset) begin + pause_stall = 1'h0; + end + if (reset) begin + write_csr_data = 32'h0; + end + if (reset) begin + postsync_stall = 1'h0; + end + if (reset) begin + x_d_i0valid = 1'h0; + end + if (reset) begin + flush_final_r = 1'h0; + end + if (reset) begin + illegal_lockout = 1'h0; + end + if (reset) begin + cam_raw_0_tag = 3'h0; + end + if (reset) begin + cam_raw_0_valid = 1'h0; + end + if (reset) begin + cam_raw_1_tag = 3'h0; + end + if (reset) begin + cam_raw_1_valid = 1'h0; + end + if (reset) begin + cam_raw_2_tag = 3'h0; + end + if (reset) begin + cam_raw_2_valid = 1'h0; + end + if (reset) begin + cam_raw_3_tag = 3'h0; + end + if (reset) begin + cam_raw_3_valid = 1'h0; + end + if (reset) begin + x_d_i0load = 1'h0; + end + if (reset) begin + x_d_i0rd = 5'h0; + end + if (reset) begin + _T_701 = 3'h0; + end + if (reset) begin + nonblock_load_valid_m_delay = 1'h0; + end + if (reset) begin + r_d_i0load = 1'h0; + end + if (reset) begin + r_d_i0v = 1'h0; + end + if (reset) begin + r_d_i0rd = 5'h0; + end + if (reset) begin + cam_raw_0_rd = 5'h0; + end + if (reset) begin + cam_raw_0_wb = 1'h0; + end + if (reset) begin + cam_raw_1_rd = 5'h0; + end + if (reset) begin + cam_raw_1_wb = 1'h0; + end + if (reset) begin + cam_raw_2_rd = 5'h0; + end + if (reset) begin + cam_raw_2_wb = 1'h0; + end + if (reset) begin + cam_raw_3_rd = 5'h0; + end + if (reset) begin + cam_raw_3_wb = 1'h0; + end + if (reset) begin + lsu_idle = 1'h0; + end + if (reset) begin + _T_339 = 1'h0; + end + if (reset) begin + x_d_i0v = 1'h0; + end + if (reset) begin + r_d_csrwen = 1'h0; + end + if (reset) begin + r_d_i0valid = 1'h0; + end + if (reset) begin + r_d_csrwaddr = 12'h0; + end + if (reset) begin + csr_read_x = 1'h0; + end + if (reset) begin + csr_clr_x = 1'h0; + end + if (reset) begin + csr_set_x = 1'h0; + end + if (reset) begin + csr_write_x = 1'h0; + end + if (reset) begin + csr_imm_x = 1'h0; + end + if (reset) begin + csrimm_x = 5'h0; + end + if (reset) begin + csr_rddata_x = 32'h0; + end + if (reset) begin + r_d_csrwonly = 1'h0; + end + if (reset) begin + i0_result_r_raw = 32'h0; + end + if (reset) begin + x_d_csrwonly = 1'h0; + end + if (reset) begin + wbd_csrwonly = 1'h0; + end + if (reset) begin + _T_465 = 32'h0; + end + if (reset) begin + x_t_legal = 1'h0; + end + if (reset) begin + x_t_icaf = 1'h0; + end + if (reset) begin + x_t_icaf_f1 = 1'h0; + end + if (reset) begin + x_t_icaf_type = 2'h0; + end + if (reset) begin + x_t_fence_i = 1'h0; + end + if (reset) begin + x_t_i0trigger = 4'h0; + end + if (reset) begin + x_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + x_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_t_legal = 1'h0; + end + if (reset) begin + r_t_icaf = 1'h0; + end + if (reset) begin + r_t_icaf_f1 = 1'h0; + end + if (reset) begin + r_t_icaf_type = 2'h0; + end + if (reset) begin + r_t_fence_i = 1'h0; + end + if (reset) begin + r_t_i0trigger = 4'h0; + end + if (reset) begin + r_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + r_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + lsu_trigger_match_r = 4'h0; + end + if (reset) begin + lsu_pmu_misaligned_r = 1'h0; + end + if (reset) begin + r_d_i0store = 1'h0; + end + if (reset) begin + r_d_i0div = 1'h0; + end + if (reset) begin + x_d_i0store = 1'h0; + end + if (reset) begin + x_d_i0div = 1'h0; + end + if (reset) begin + x_d_csrwen = 1'h0; + end + if (reset) begin + x_d_csrwaddr = 12'h0; + end + if (reset) begin + last_br_immed_x = 12'h0; + end + if (reset) begin + _T_821 = 1'h0; + end + if (reset) begin + _T_830 = 5'h0; + end + if (reset) begin + dec_i0_pc_r = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_active_clk) begin + if (i0_x_ctl_en) begin + i0_x_c_load <= i0_d_c_load; + end + if (i0_r_ctl_en) begin + i0_r_c_load <= i0_x_c_load; + end + if (i0_x_ctl_en) begin + i0_x_c_mul <= i0_d_c_mul; + end + if (i0_x_ctl_en) begin + i0_x_c_alu <= i0_d_c_alu; + end + if (i0_r_ctl_en) begin + i0_r_c_mul <= i0_x_c_mul; + end + if (i0_r_ctl_en) begin + i0_r_c_alu <= i0_x_c_alu; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + tlu_wr_pause_r1 <= 1'h0; + end else begin + tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + tlu_wr_pause_r2 <= 1'h0; + end else begin + tlu_wr_pause_r2 <= tlu_wr_pause_r1; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + leak1_i1_stall <= 1'h0; + end else begin + leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_280; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + leak1_i0_stall <= 1'h0; + end else begin + leak1_i0_stall <= _T_283 | _T_285; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + pause_stall <= 1'h0; + end else begin + pause_stall <= _T_412 & _T_413; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + write_csr_data <= 32'h0; + end else if (pause_stall) begin + write_csr_data <= _T_423; + end else if (io_dec_tlu_wr_pause_r) begin + write_csr_data <= io_dec_csr_wrdata_r; + end else begin + write_csr_data <= write_csr_data_x; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + postsync_stall <= 1'h0; + end else begin + postsync_stall <= _T_506 | _T_507; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0valid <= 1'h0; + end else begin + x_d_i0valid <= io_dec_i0_decode_d; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + flush_final_r <= 1'h0; + end else begin + flush_final_r <= io_exu_flush_final; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + illegal_lockout <= 1'h0; + end else begin + illegal_lockout <= _T_466 & _T_467; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_tag <= 3'h0; + end else if (cam_wen[0]) begin + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_106) begin + cam_raw_0_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_0_valid <= 1'h0; + end else begin + cam_raw_0_valid <= _GEN_56; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_tag <= 3'h0; + end else if (cam_wen[1]) begin + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_132) begin + cam_raw_1_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_1_valid <= 1'h0; + end else begin + cam_raw_1_valid <= _GEN_67; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_tag <= 3'h0; + end else if (cam_wen[2]) begin + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_158) begin + cam_raw_2_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_2_valid <= 1'h0; + end else begin + cam_raw_2_valid <= _GEN_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_tag <= 3'h0; + end else if (cam_wen[3]) begin + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_184) begin + cam_raw_3_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_3_valid <= 1'h0; + end else begin + cam_raw_3_valid <= _GEN_89; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0load <= 1'h0; + end else begin + x_d_i0load <= i0_dp_load & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0rd <= 5'h0; + end else begin + x_d_i0rd <= io_dec_i0_instr_d[11:7]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_701 <= 3'h0; + end else begin + _T_701 <= i0_pipe_en[3:1]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + nonblock_load_valid_m_delay <= 1'h0; + end else if (i0_r_ctl_en) begin + nonblock_load_valid_m_delay <= io_lsu_nonblock_load_valid_m; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0load <= 1'h0; + end else begin + r_d_i0load <= x_d_i0load; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0v <= 1'h0; + end else begin + r_d_i0v <= _T_733 & _T_279; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0rd <= 5'h0; + end else begin + r_d_i0rd <= x_d_i0rd; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_rd <= 5'h0; + end else if (cam_wen[0]) begin + if (x_d_i0load) begin + cam_raw_0_rd <= x_d_i0rd; + end else begin + cam_raw_0_rd <= 5'h0; + end + end else if (_T_106) begin + cam_raw_0_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_wb <= 1'h0; + end else begin + cam_raw_0_wb <= _T_111 | _GEN_57; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_rd <= 5'h0; + end else if (cam_wen[1]) begin + if (x_d_i0load) begin + cam_raw_1_rd <= x_d_i0rd; + end else begin + cam_raw_1_rd <= 5'h0; + end + end else if (_T_132) begin + cam_raw_1_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_wb <= 1'h0; + end else begin + cam_raw_1_wb <= _T_137 | _GEN_68; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_rd <= 5'h0; + end else if (cam_wen[2]) begin + if (x_d_i0load) begin + cam_raw_2_rd <= x_d_i0rd; + end else begin + cam_raw_2_rd <= 5'h0; + end + end else if (_T_158) begin + cam_raw_2_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_wb <= 1'h0; + end else begin + cam_raw_2_wb <= _T_163 | _GEN_79; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_rd <= 5'h0; + end else if (cam_wen[3]) begin + if (x_d_i0load) begin + cam_raw_3_rd <= x_d_i0rd; + end else begin + cam_raw_3_rd <= 5'h0; + end + end else if (_T_184) begin + cam_raw_3_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_wb <= 1'h0; + end else begin + cam_raw_3_wb <= _T_189 | _GEN_90; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_idle <= 1'h0; + end else begin + lsu_idle <= io_lsu_idle_any; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + _T_339 <= 1'h0; + end else begin + _T_339 <= io_dec_tlu_flush_extint; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0v <= 1'h0; + end else begin + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwen <= 1'h0; + end else begin + r_d_csrwen <= x_d_csrwen; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0valid <= 1'h0; + end else begin + r_d_i0valid <= _T_737 & _T_279; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwaddr <= 12'h0; + end else begin + r_d_csrwaddr <= x_d_csrwaddr; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_read_x <= 1'h0; + end else begin + csr_read_x <= i0_dp_csr_read & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_clr_x <= 1'h0; + end else begin + csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_set_x <= 1'h0; + end else begin + csr_set_x <= i0_dp_csr_set & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_write_x <= 1'h0; + end else begin + csr_write_x <= i0_csr_write & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_imm_x <= 1'h0; + end else if (_T_40) begin + csr_imm_x <= 1'h0; + end else begin + csr_imm_x <= i0_dp_raw_csr_imm; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + csrimm_x <= 5'h0; + end else begin + csrimm_x <= io_dec_i0_instr_d[19:15]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + csr_rddata_x <= 32'h0; + end else begin + csr_rddata_x <= io_dec_csr_rddata_d; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwonly <= 1'h0; + end else begin + r_d_csrwonly <= x_d_csrwonly; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + i0_result_r_raw <= 32'h0; + end else if (_T_761) begin + i0_result_r_raw <= io_lsu_result_m; + end else begin + i0_result_r_raw <= io_exu_i0_result_x; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwonly <= 1'h0; + end else begin + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + wbd_csrwonly <= 1'h0; + end else begin + wbd_csrwonly <= r_d_csrwonly; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + _T_465 <= 32'h0; + end else if (io_dec_i0_pc4_d) begin + _T_465 <= io_dec_i0_instr_d; + end else begin + _T_465 <= _T_462; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_legal <= 1'h0; + end else begin + x_t_legal <= io_dec_i0_decode_d & i0_legal; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf <= 1'h0; + end else begin + x_t_icaf <= i0_icaf_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf_f1 <= 1'h0; + end else begin + x_t_icaf_f1 <= io_dec_i0_icaf_f1_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf_type <= 2'h0; + end else begin + x_t_icaf_type <= io_dec_i0_icaf_type_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_fence_i <= 1'h0; + end else begin + x_t_fence_i <= _T_517 & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_i0trigger <= 4'h0; + end else begin + x_t_i0trigger <= io_dec_i0_trigger_match_d & _T_522; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_itype <= 4'h0; + end else begin + x_t_pmu_i0_itype <= _T_254 & _T_276; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else begin + x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_252; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_legal <= 1'h0; + end else begin + r_t_legal <= x_t_legal; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf <= 1'h0; + end else begin + r_t_icaf <= x_t_icaf; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf_f1 <= 1'h0; + end else begin + r_t_icaf_f1 <= x_t_icaf_f1; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf_type <= 2'h0; + end else begin + r_t_icaf_type <= x_t_icaf_type; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_fence_i <= 1'h0; + end else begin + r_t_fence_i <= x_t_fence_i; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_i0trigger <= 4'h0; + end else begin + r_t_i0trigger <= x_t_i0trigger & _T_531; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_pmu_i0_itype <= 4'h0; + end else begin + r_t_pmu_i0_itype <= x_t_pmu_i0_itype; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_pmu_i0_br_unpred <= 1'h0; + end else begin + r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + lsu_trigger_match_r <= 4'h0; + end else begin + lsu_trigger_match_r <= io_lsu_trigger_match_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + lsu_pmu_misaligned_r <= 1'h0; + end else begin + lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0store <= 1'h0; + end else begin + r_d_i0store <= x_d_i0store; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0div <= 1'h0; + end else begin + r_d_i0div <= x_d_i0div; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0store <= 1'h0; + end else begin + x_d_i0store <= i0_dp_store & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0div <= 1'h0; + end else begin + x_d_i0div <= i0_dp_div & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwen <= 1'h0; + end else begin + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwaddr <= 12'h0; + end else begin + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + last_br_immed_x <= 12'h0; + end else if (io_i0_ap_predict_nt) begin + last_br_immed_x <= _T_781; + end else if (_T_314) begin + last_br_immed_x <= i0_pcall_imm[12:1]; + end else begin + last_br_immed_x <= _T_323; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_821 <= 1'h0; + end else begin + _T_821 <= i0_div_decode_d | _T_820; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_830 <= 5'h0; + end else if (i0_div_decode_d) begin + _T_830 <= i0r_rd; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else begin + dec_i0_pc_r <= io_exu_i0_pc_x; + end + end +endmodule +module el2_dec_gpr_ctl( + input clock, + input reset, + input [4:0] io_raddr0, + input [4:0] io_raddr1, + input io_wen0, + input [4:0] io_waddr0, + input [31:0] io_wd0, + input io_wen1, + input [4:0] io_waddr1, + input [31:0] io_wd1, + input io_wen2, + input [4:0] io_waddr2, + input [31:0] io_wd2, + output [31:0] io_rd0, + output [31:0] io_rd1, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 485:23] + wire _T_95 = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_1 = io_wen0 & _T_95; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_112 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_2 = io_wen0 & _T_112; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_129 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_3 = io_wen0 & _T_129; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_146 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_4 = io_wen0 & _T_146; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_163 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_5 = io_wen0 & _T_163; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_180 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_6 = io_wen0 & _T_180; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_197 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_7 = io_wen0 & _T_197; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_214 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_8 = io_wen0 & _T_214; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_231 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_9 = io_wen0 & _T_231; // @[el2_dec_gpr_ctl.scala 26:28] + wire [9:0] _T_8 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_248 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_10 = io_wen0 & _T_248; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_265 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_11 = io_wen0 & _T_265; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_282 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_12 = io_wen0 & _T_282; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_299 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_13 = io_wen0 & _T_299; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_316 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_14 = io_wen0 & _T_316; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_333 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_15 = io_wen0 & _T_333; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_350 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_16 = io_wen0 & _T_350; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_367 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_17 = io_wen0 & _T_367; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_384 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_18 = io_wen0 & _T_384; // @[el2_dec_gpr_ctl.scala 26:28] + wire [18:0] _T_17 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_8}; // @[Cat.scala 29:58] + wire _T_401 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_19 = io_wen0 & _T_401; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_418 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_20 = io_wen0 & _T_418; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_435 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_21 = io_wen0 & _T_435; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_452 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_22 = io_wen0 & _T_452; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_469 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_23 = io_wen0 & _T_469; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_486 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_24 = io_wen0 & _T_486; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_503 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_25 = io_wen0 & _T_503; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_520 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_26 = io_wen0 & _T_520; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_537 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_27 = io_wen0 & _T_537; // @[el2_dec_gpr_ctl.scala 26:28] + wire [27:0] _T_26 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_17}; // @[Cat.scala 29:58] + wire _T_554 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_28 = io_wen0 & _T_554; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_571 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_29 = io_wen0 & _T_571; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_588 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_30 = io_wen0 & _T_588; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_605 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_31 = io_wen0 & _T_605; // @[el2_dec_gpr_ctl.scala 26:28] + wire [31:0] _T_30 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_26}; // @[Cat.scala 29:58] + wire _T_97 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_1 = io_wen1 & _T_97; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_114 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_2 = io_wen1 & _T_114; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_131 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_3 = io_wen1 & _T_131; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_148 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_4 = io_wen1 & _T_148; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_165 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_5 = io_wen1 & _T_165; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_182 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_6 = io_wen1 & _T_182; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_199 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_7 = io_wen1 & _T_199; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_216 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_8 = io_wen1 & _T_216; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_233 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_9 = io_wen1 & _T_233; // @[el2_dec_gpr_ctl.scala 27:28] + wire [9:0] _T_39 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_250 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_10 = io_wen1 & _T_250; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_267 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_11 = io_wen1 & _T_267; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_284 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_12 = io_wen1 & _T_284; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_301 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_13 = io_wen1 & _T_301; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_318 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_14 = io_wen1 & _T_318; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_335 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_15 = io_wen1 & _T_335; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_352 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_16 = io_wen1 & _T_352; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_369 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_17 = io_wen1 & _T_369; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_386 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_18 = io_wen1 & _T_386; // @[el2_dec_gpr_ctl.scala 27:28] + wire [18:0] _T_48 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_39}; // @[Cat.scala 29:58] + wire _T_403 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_19 = io_wen1 & _T_403; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_420 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_20 = io_wen1 & _T_420; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_437 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_21 = io_wen1 & _T_437; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_454 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_22 = io_wen1 & _T_454; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_471 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_23 = io_wen1 & _T_471; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_488 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_24 = io_wen1 & _T_488; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_505 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_25 = io_wen1 & _T_505; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_522 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_26 = io_wen1 & _T_522; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_539 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_27 = io_wen1 & _T_539; // @[el2_dec_gpr_ctl.scala 27:28] + wire [27:0] _T_57 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_48}; // @[Cat.scala 29:58] + wire _T_556 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_28 = io_wen1 & _T_556; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_573 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_29 = io_wen1 & _T_573; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_590 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_30 = io_wen1 & _T_590; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_607 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_31 = io_wen1 & _T_607; // @[el2_dec_gpr_ctl.scala 27:28] + wire [31:0] _T_61 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_57}; // @[Cat.scala 29:58] + wire [31:0] _T_62 = _T_30 | _T_61; // @[el2_dec_gpr_ctl.scala 23:51] + wire _T_99 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_1 = io_wen2 & _T_99; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_116 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_2 = io_wen2 & _T_116; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_133 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_3 = io_wen2 & _T_133; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_150 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_4 = io_wen2 & _T_150; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_167 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_5 = io_wen2 & _T_167; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_184 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_6 = io_wen2 & _T_184; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_201 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_7 = io_wen2 & _T_201; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_218 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_8 = io_wen2 & _T_218; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_235 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_9 = io_wen2 & _T_235; // @[el2_dec_gpr_ctl.scala 28:28] + wire [9:0] _T_71 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_252 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_10 = io_wen2 & _T_252; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_269 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_11 = io_wen2 & _T_269; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_286 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_12 = io_wen2 & _T_286; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_303 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_13 = io_wen2 & _T_303; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_320 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_14 = io_wen2 & _T_320; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_337 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_15 = io_wen2 & _T_337; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_354 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_16 = io_wen2 & _T_354; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_371 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_17 = io_wen2 & _T_371; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_388 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_18 = io_wen2 & _T_388; // @[el2_dec_gpr_ctl.scala 28:28] + wire [18:0] _T_80 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_71}; // @[Cat.scala 29:58] + wire _T_405 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_19 = io_wen2 & _T_405; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_422 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_20 = io_wen2 & _T_422; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_439 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_21 = io_wen2 & _T_439; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_456 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_22 = io_wen2 & _T_456; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_473 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_23 = io_wen2 & _T_473; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_490 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_24 = io_wen2 & _T_490; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_507 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_25 = io_wen2 & _T_507; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_524 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_26 = io_wen2 & _T_524; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_541 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_27 = io_wen2 & _T_541; // @[el2_dec_gpr_ctl.scala 28:28] + wire [27:0] _T_89 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_80}; // @[Cat.scala 29:58] + wire _T_558 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_28 = io_wen2 & _T_558; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_575 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_29 = io_wen2 & _T_575; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_592 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_30 = io_wen2 & _T_592; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_609 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_31 = io_wen2 & _T_609; // @[el2_dec_gpr_ctl.scala 28:28] + wire [31:0] _T_93 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_89}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_62 | _T_93; // @[el2_dec_gpr_ctl.scala 23:89] + wire [31:0] _T_102 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_103 = _T_102 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_105 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_106 = _T_105 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_107 = _T_103 | _T_106; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_109 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_119 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_120 = _T_119 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_122 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_123 = _T_122 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_124 = _T_120 | _T_123; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_126 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_136 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_137 = _T_136 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_139 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_140 = _T_139 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_141 = _T_137 | _T_140; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_143 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_153 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_154 = _T_153 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_156 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_157 = _T_156 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_158 = _T_154 | _T_157; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_160 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_170 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_171 = _T_170 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_173 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_174 = _T_173 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_175 = _T_171 | _T_174; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_177 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_187 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_188 = _T_187 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_190 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_191 = _T_190 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_192 = _T_188 | _T_191; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_194 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_204 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_205 = _T_204 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_207 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_208 = _T_207 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_209 = _T_205 | _T_208; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_211 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_221 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_222 = _T_221 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_224 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_225 = _T_224 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_226 = _T_222 | _T_225; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_228 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_238 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_239 = _T_238 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_241 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_242 = _T_241 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_243 = _T_239 | _T_242; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_245 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_255 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_256 = _T_255 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_258 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_259 = _T_258 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_260 = _T_256 | _T_259; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_262 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_272 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_273 = _T_272 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_275 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_276 = _T_275 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_277 = _T_273 | _T_276; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_279 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_289 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_290 = _T_289 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_292 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_293 = _T_292 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_294 = _T_290 | _T_293; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_296 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_306 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_307 = _T_306 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_309 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_310 = _T_309 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_311 = _T_307 | _T_310; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_313 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_323 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_324 = _T_323 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_326 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_327 = _T_326 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_328 = _T_324 | _T_327; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_330 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_340 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_341 = _T_340 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_343 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_344 = _T_343 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_345 = _T_341 | _T_344; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_347 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_357 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_358 = _T_357 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_360 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_361 = _T_360 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_362 = _T_358 | _T_361; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_364 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_374 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_375 = _T_374 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_377 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_378 = _T_377 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_379 = _T_375 | _T_378; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_381 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_391 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_392 = _T_391 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_394 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_395 = _T_394 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_396 = _T_392 | _T_395; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_398 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_408 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_409 = _T_408 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_411 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_412 = _T_411 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_413 = _T_409 | _T_412; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_415 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_425 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_426 = _T_425 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_428 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_429 = _T_428 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_430 = _T_426 | _T_429; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_432 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_442 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_443 = _T_442 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_445 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_446 = _T_445 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_447 = _T_443 | _T_446; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_449 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_459 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_460 = _T_459 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_462 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_463 = _T_462 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_464 = _T_460 | _T_463; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_466 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_476 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_477 = _T_476 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_479 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_480 = _T_479 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_481 = _T_477 | _T_480; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_483 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_493 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_494 = _T_493 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_496 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_497 = _T_496 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_498 = _T_494 | _T_497; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_500 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_510 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_511 = _T_510 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_513 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_514 = _T_513 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_515 = _T_511 | _T_514; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_517 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_527 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_528 = _T_527 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_530 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_531 = _T_530 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_532 = _T_528 | _T_531; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_534 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_535 = _T_534 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_544 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_545 = _T_544 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_547 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_548 = _T_547 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_549 = _T_545 | _T_548; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_551 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_552 = _T_551 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_561 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_562 = _T_561 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_564 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_565 = _T_564 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_566 = _T_562 | _T_565; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_568 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_569 = _T_568 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_578 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_579 = _T_578 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_581 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_582 = _T_581 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_583 = _T_579 | _T_582; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_585 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_586 = _T_585 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_595 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_596 = _T_595 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_598 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_599 = _T_598 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_600 = _T_596 | _T_599; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_602 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_603 = _T_602 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_612 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_613 = _T_612 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_615 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_616 = _T_615 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_617 = _T_613 | _T_616; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_619 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_620 = _T_619 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + reg [31:0] gpr_out_1; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_2; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_3; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_4; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_5; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_6; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_7; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_8; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_9; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_10; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_11; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_12; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_13; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_14; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_15; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_16; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_17; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_18; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_19; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_20; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_21; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_22; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_23; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_24; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_25; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_26; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_27; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_28; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_29; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_30; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_31; // @[el2_lib.scala 491:16] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:49] + wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72] + wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72] + wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72] + wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72] + wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72] + wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72] + wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72] + wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72] + wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72] + wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72] + wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72] + wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72] + wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72] + wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72] + wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72] + wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72] + wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72] + wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72] + wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72] + wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72] + wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72] + wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72] + wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] + wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] + wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:49] + wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72] + wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72] + wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72] + wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72] + wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72] + wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72] + wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72] + wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72] + wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72] + wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72] + wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72] + wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72] + wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72] + wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72] + wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72] + wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72] + wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72] + wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72] + wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72] + wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72] + wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72] + wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72] + wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72] + wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 21:9 el2_dec_gpr_ctl.scala 36:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 22:9 el2_dec_gpr_ctl.scala 37:9] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[el2_lib.scala 488:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[el2_lib.scala 488:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[el2_lib.scala 488:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[el2_lib.scala 488:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[el2_lib.scala 488:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[el2_lib.scala 488:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[el2_lib.scala 488:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[el2_lib.scala 488:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[el2_lib.scala 488:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[el2_lib.scala 488:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[el2_lib.scala 488:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[el2_lib.scala 488:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[el2_lib.scala 488:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[el2_lib.scala 488:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[el2_lib.scala 488:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[el2_lib.scala 488:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[el2_lib.scala 488:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + gpr_out_1 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + gpr_out_2 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + gpr_out_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + gpr_out_4 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + gpr_out_5 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + gpr_out_6 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + gpr_out_7 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + gpr_out_8 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + gpr_out_9 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + gpr_out_10 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + gpr_out_11 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + gpr_out_12 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + gpr_out_13 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + gpr_out_14 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + gpr_out_15 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + gpr_out_16 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + gpr_out_17 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + gpr_out_18 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + gpr_out_19 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + gpr_out_20 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + gpr_out_21 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + gpr_out_22 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + gpr_out_23 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + gpr_out_24 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + gpr_out_25 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + gpr_out_26 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + gpr_out_27 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + gpr_out_28 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + gpr_out_29 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + gpr_out_30 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + gpr_out_31 = _RAND_30[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + gpr_out_1 = 32'h0; + end + if (reset) begin + gpr_out_2 = 32'h0; + end + if (reset) begin + gpr_out_3 = 32'h0; + end + if (reset) begin + gpr_out_4 = 32'h0; + end + if (reset) begin + gpr_out_5 = 32'h0; + end + if (reset) begin + gpr_out_6 = 32'h0; + end + if (reset) begin + gpr_out_7 = 32'h0; + end + if (reset) begin + gpr_out_8 = 32'h0; + end + if (reset) begin + gpr_out_9 = 32'h0; + end + if (reset) begin + gpr_out_10 = 32'h0; + end + if (reset) begin + gpr_out_11 = 32'h0; + end + if (reset) begin + gpr_out_12 = 32'h0; + end + if (reset) begin + gpr_out_13 = 32'h0; + end + if (reset) begin + gpr_out_14 = 32'h0; + end + if (reset) begin + gpr_out_15 = 32'h0; + end + if (reset) begin + gpr_out_16 = 32'h0; + end + if (reset) begin + gpr_out_17 = 32'h0; + end + if (reset) begin + gpr_out_18 = 32'h0; + end + if (reset) begin + gpr_out_19 = 32'h0; + end + if (reset) begin + gpr_out_20 = 32'h0; + end + if (reset) begin + gpr_out_21 = 32'h0; + end + if (reset) begin + gpr_out_22 = 32'h0; + end + if (reset) begin + gpr_out_23 = 32'h0; + end + if (reset) begin + gpr_out_24 = 32'h0; + end + if (reset) begin + gpr_out_25 = 32'h0; + end + if (reset) begin + gpr_out_26 = 32'h0; + end + if (reset) begin + gpr_out_27 = 32'h0; + end + if (reset) begin + gpr_out_28 = 32'h0; + end + if (reset) begin + gpr_out_29 = 32'h0; + end + if (reset) begin + gpr_out_30 = 32'h0; + end + if (reset) begin + gpr_out_31 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_1 <= 32'h0; + end else begin + gpr_out_1 <= _T_107 | _T_110; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_2 <= 32'h0; + end else begin + gpr_out_2 <= _T_124 | _T_127; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_3 <= 32'h0; + end else begin + gpr_out_3 <= _T_141 | _T_144; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_4 <= 32'h0; + end else begin + gpr_out_4 <= _T_158 | _T_161; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_5 <= 32'h0; + end else begin + gpr_out_5 <= _T_175 | _T_178; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_6 <= 32'h0; + end else begin + gpr_out_6 <= _T_192 | _T_195; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_7 <= 32'h0; + end else begin + gpr_out_7 <= _T_209 | _T_212; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_8 <= 32'h0; + end else begin + gpr_out_8 <= _T_226 | _T_229; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_9 <= 32'h0; + end else begin + gpr_out_9 <= _T_243 | _T_246; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_10 <= 32'h0; + end else begin + gpr_out_10 <= _T_260 | _T_263; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_11 <= 32'h0; + end else begin + gpr_out_11 <= _T_277 | _T_280; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_12 <= 32'h0; + end else begin + gpr_out_12 <= _T_294 | _T_297; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_13 <= 32'h0; + end else begin + gpr_out_13 <= _T_311 | _T_314; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_14 <= 32'h0; + end else begin + gpr_out_14 <= _T_328 | _T_331; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_15 <= 32'h0; + end else begin + gpr_out_15 <= _T_345 | _T_348; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_16 <= 32'h0; + end else begin + gpr_out_16 <= _T_362 | _T_365; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_17 <= 32'h0; + end else begin + gpr_out_17 <= _T_379 | _T_382; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_18 <= 32'h0; + end else begin + gpr_out_18 <= _T_396 | _T_399; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_19 <= 32'h0; + end else begin + gpr_out_19 <= _T_413 | _T_416; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_20 <= 32'h0; + end else begin + gpr_out_20 <= _T_430 | _T_433; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_21 <= 32'h0; + end else begin + gpr_out_21 <= _T_447 | _T_450; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_22 <= 32'h0; + end else begin + gpr_out_22 <= _T_464 | _T_467; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_23 <= 32'h0; + end else begin + gpr_out_23 <= _T_481 | _T_484; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_24 <= 32'h0; + end else begin + gpr_out_24 <= _T_498 | _T_501; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_25 <= 32'h0; + end else begin + gpr_out_25 <= _T_515 | _T_518; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_26 <= 32'h0; + end else begin + gpr_out_26 <= _T_532 | _T_535; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_27 <= 32'h0; + end else begin + gpr_out_27 <= _T_549 | _T_552; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_28 <= 32'h0; + end else begin + gpr_out_28 <= _T_566 | _T_569; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_29 <= 32'h0; + end else begin + gpr_out_29 <= _T_583 | _T_586; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_30 <= 32'h0; + end else begin + gpr_out_30 <= _T_600 | _T_603; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_31 <= 32'h0; + end else begin + gpr_out_31 <= _T_617 | _T_620; + end + end +endmodule +module el2_dec_timer_ctl( + input clock, + input reset, + input io_free_clk, + input io_scan_mode, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_csr_mitctl0, + input io_csr_mitctl1, + input io_csr_mitb0, + input io_csr_mitb1, + input io_csr_mitcnt0, + input io_csr_mitcnt1, + input io_dec_pause_state, + input io_dec_tlu_pmu_fw_halted, + input io_internal_dbg_halt_timers, + output [31:0] io_dec_timer_rddata_d, + output io_dec_timer_read_d, + output io_dec_timer_t0_pulse, + output io_dec_timer_t1_pulse +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + reg [31:0] mitcnt0; // @[el2_lib.scala 491:16] + reg [31:0] mitb0_b; // @[el2_lib.scala 491:16] + wire [31:0] mitb0 = ~mitb0_b; // @[el2_dec_tlu_ctl.scala 2791:14] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2752:30] + reg [31:0] mitcnt1; // @[el2_lib.scala 491:16] + reg [31:0] mitb1_b; // @[el2_lib.scala 491:16] + wire [31:0] mitb1 = ~mitb1_b; // @[el2_dec_tlu_ctl.scala 2800:12] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2753:30] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[el2_dec_tlu_ctl.scala 2763:66] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[el2_dec_tlu_ctl.scala 2763:43] + reg [1:0] _T_57; // @[el2_dec_tlu_ctl.scala 2816:67] + reg mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2815:54] + wire _T_58 = ~mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2816:90] + wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] + wire _T_2 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 2765:50] + wire _T_4 = _T_2 | mitctl0[2]; // @[el2_dec_tlu_ctl.scala 2765:70] + wire _T_5 = mitctl0[0] & _T_4; // @[el2_dec_tlu_ctl.scala 2765:47] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2765:106] + wire _T_8 = _T_6 | mitctl0[1]; // @[el2_dec_tlu_ctl.scala 2765:132] + wire _T_9 = _T_5 & _T_8; // @[el2_dec_tlu_ctl.scala 2765:103] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:60] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] + reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] + reg mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2829:49] + wire _T_67 = ~mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2830:69] + wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] + wire _T_23 = _T_2 | mitctl1[2]; // @[el2_dec_tlu_ctl.scala 2777:70] + wire _T_24 = mitctl1[0] & _T_23; // @[el2_dec_tlu_ctl.scala 2777:47] + wire _T_27 = _T_6 | mitctl1[1]; // @[el2_dec_tlu_ctl.scala 2777:132] + wire _T_28 = _T_24 & _T_27; // @[el2_dec_tlu_ctl.scala 2777:103] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[el2_dec_tlu_ctl.scala 2777:165] + wire _T_32 = ~mitctl1[3]; // @[el2_dec_tlu_ctl.scala 2780:54] + wire _T_33 = _T_32 | mit0_match_ns; // @[el2_dec_tlu_ctl.scala 2780:66] + wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[el2_dec_tlu_ctl.scala 2780:29] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[el2_dec_tlu_ctl.scala 2782:52] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[el2_dec_tlu_ctl.scala 2789:64] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[el2_dec_tlu_ctl.scala 2798:63] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[el2_dec_tlu_ctl.scala 2811:66] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[el2_dec_tlu_ctl.scala 2811:43] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[el2_dec_tlu_ctl.scala 2812:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[el2_dec_tlu_ctl.scala 2826:65] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[el2_dec_tlu_ctl.scala 2826:43] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[el2_dec_tlu_ctl.scala 2827:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 2832:43] + wire _T_70 = _T_69 | io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 2832:60] + wire _T_71 = _T_70 | io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 2832:75] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 2832:90] + wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] + wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] + wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_86 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_87 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_88 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_89 = io_csr_mitctl0 ? _T_81 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_90 = io_csr_mitctl1 ? _T_84 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_91 = _T_85 | _T_86; // @[Mux.scala 27:72] + wire [31:0] _T_92 = _T_91 | _T_87; // @[Mux.scala 27:72] + wire [31:0] _T_93 = _T_92 | _T_88; // @[Mux.scala 27:72] + wire [31:0] _T_94 = _T_93 | _T_89; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[el2_dec_tlu_ctl.scala 2833:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 2832:25] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2755:25] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2756:25] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mitcnt0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + mitb0_b = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + mitcnt1 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + mitb1_b = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + _T_57 = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + mitctl0_0_b = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[2:0]; + _RAND_7 = {1{`RANDOM}}; + mitctl1_0_b = _RAND_7[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mitcnt0 = 32'h0; + end + if (reset) begin + mitb0_b = 32'h0; + end + if (reset) begin + mitcnt1 = 32'h0; + end + if (reset) begin + mitb1_b = 32'h0; + end + if (reset) begin + _T_57 = 2'h0; + end + if (reset) begin + mitctl0_0_b = 1'h0; + end + if (reset) begin + _T_66 = 3'h0; + end + if (reset) begin + mitctl1_0_b = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt0 <= 32'h0; + end else if (mit0_match_ns) begin + mitcnt0 <= 32'h0; + end else if (wr_mitcnt0_r) begin + mitcnt0 <= io_dec_csr_wrdata_r; + end else begin + mitcnt0 <= mitcnt0_inc; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mitb0_b <= 32'h0; + end else begin + mitb0_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt1 <= 32'h0; + end else if (mit1_match_ns) begin + mitcnt1 <= 32'h0; + end else if (wr_mitcnt1_r) begin + mitcnt1 <= io_dec_csr_wrdata_r; + end else begin + mitcnt1 <= mitcnt1_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + mitb1_b <= 32'h0; + end else begin + mitb1_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_57 <= 2'h0; + end else begin + _T_57 <= mitctl0_ns[2:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl0_0_b <= 1'h0; + end else begin + mitctl0_0_b <= ~mitctl0_ns[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 3'h0; + end else begin + _T_66 <= mitctl1_ns[3:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl1_0_b <= 1'h0; + end else begin + mitctl1_0_b <= ~mitctl1_ns[0]; + end + end +endmodule +module csr_tlu( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_scan_mode, + input [31:0] io_dec_csr_wrdata_r, + input [11:0] io_dec_csr_wraddr_r, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_unq_d, + input io_dec_i0_decode_d, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_ifu_ic_debug_rd_data_valid, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_pmu_bus_trxn, + input io_dma_iccm_stall_any, + input io_dma_dccm_stall_any, + input io_lsu_store_stall_any, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_decode_stall, + input io_ifu_pmu_fetch_stall, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_instr_decoded, + input io_ifu_pmu_instr_aligned, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + output io_dec_tlu_int_valid_wb1, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + input io_dec_csr_wen_r, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + input io_dec_tlu_dbg_halted, + input io_dma_pmu_dccm_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_any_write, + input io_dma_pmu_any_read, + input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_i0_valid_r, + input io_dec_csr_any_unq_d, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output [31:0] io_dec_csr_rddata_d, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_wr_pause_r, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_trxn, + input [70:0] io_ifu_ic_debug_rd_data, + output [3:0] io_dec_tlu_meipt, + input [3:0] io_pic_pl, + output [3:0] io_dec_tlu_meicurpl, + output [29:0] io_dec_tlu_meihap, + input [7:0] io_pic_claimid, + input io_iccm_dma_sb_error, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_external_ldfwd_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + input [31:0] io_dec_illegal_inst, + input io_lsu_error_pkt_r_mscause, + input io_mexintpend, + input [30:0] io_exu_npc_r, + input io_mpc_reset_run_req, + input [30:0] io_rst_vec, + input [27:0] io_core_id, + input [31:0] io_dec_timer_rddata_d, + input io_dec_timer_read_d, + output io_dec_csr_wen_r_mod, + input io_rfpc_i0_r, + input io_i0_trigger_hit_r, + output io_fw_halt_req, + output [1:0] io_mstatus, + input io_exc_or_int_valid_r, + input io_mret_r, + output io_mstatus_mie_ns, + input io_dcsr_single_step_running_f, + output [15:0] io_dcsr, + output [30:0] io_mtvec, + output [5:0] io_mip, + input io_dec_timer_t0_pulse, + input io_dec_timer_t1_pulse, + input io_timer_int_sync, + input io_soft_int_sync, + output [5:0] io_mie_ns, + input io_csr_wr_clk, + input io_ebreak_to_debug_mode_r, + input io_dec_tlu_pmu_fw_halted, + input [1:0] io_lsu_fir_error, + output [30:0] io_npc_r, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_flush_noredir_r_d1, + input [30:0] io_tlu_flush_path_r_d1, + output [30:0] io_npc_r_d1, + input io_reset_delayed, + output [30:0] io_mepc, + input io_interrupt_valid_r, + input io_i0_exception_valid_r, + input io_lsu_exc_valid_r, + input io_mepc_trigger_hit_sel_pc_r, + input io_e4e5_int_clk, + input io_lsu_i0_exc_r, + input io_inst_acc_r, + input io_inst_acc_second_r, + input io_take_nmi, + input [31:0] io_lsu_error_pkt_addr_r, + input [4:0] io_exc_cause_r, + input io_i0_valid_wb, + input io_exc_or_int_valid_r_d1, + input io_interrupt_valid_r_d1, + input io_clk_override, + input io_i0_exception_valid_r_d1, + input io_lsu_i0_exc_r_d1, + input io_nmi_lsu_store_type, + input io_nmi_lsu_load_type, + input io_tlu_i0_commit_cmt, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + output io_mdseac_locked_ns, + input io_mdseac_locked_f, + input io_nmi_int_detected_f, + input io_internal_dbg_halt_mode_f2, + input io_ext_int_freeze_d1, + input io_ic_perr_r_d1, + input io_iccm_sbecc_r_d1, + input io_lsu_single_ecc_error_r_d1, + input io_ifu_miss_state_idle_f, + input io_lsu_idle_any_f, + input io_dbg_tlu_halted_f, + input io_dbg_tlu_halted, + input io_debug_halt_req_f, + output io_force_halt, + input io_take_ext_int_start, + input io_trigger_hit_dmode_r_d1, + input io_trigger_hit_r_d1, + input io_dcsr_single_step_done_f, + input io_ebreak_to_debug_mode_r_d1, + input io_debug_halt_req, + input io_allow_dbg_halt_csr_write, + input io_internal_dbg_halt_mode_f, + input io_enter_debug_halt_req, + input io_internal_dbg_halt_mode, + input io_request_debug_mode_done, + input io_request_debug_mode_r, + output [30:0] io_dpc, + input [3:0] io_update_hit_bit_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_dec_tlu_br0_start_error_r, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + input io_csr_pkt_csr_misa, + input io_csr_pkt_csr_mvendorid, + input io_csr_pkt_csr_marchid, + input io_csr_pkt_csr_mimpid, + input io_csr_pkt_csr_mhartid, + input io_csr_pkt_csr_mstatus, + input io_csr_pkt_csr_mtvec, + input io_csr_pkt_csr_mip, + input io_csr_pkt_csr_mie, + input io_csr_pkt_csr_mcyclel, + input io_csr_pkt_csr_mcycleh, + input io_csr_pkt_csr_minstretl, + input io_csr_pkt_csr_minstreth, + input io_csr_pkt_csr_mscratch, + input io_csr_pkt_csr_mepc, + input io_csr_pkt_csr_mcause, + input io_csr_pkt_csr_mscause, + input io_csr_pkt_csr_mtval, + input io_csr_pkt_csr_mrac, + input io_csr_pkt_csr_mdseac, + input io_csr_pkt_csr_meihap, + input io_csr_pkt_csr_meivt, + input io_csr_pkt_csr_meipt, + input io_csr_pkt_csr_meicurpl, + input io_csr_pkt_csr_meicidpl, + input io_csr_pkt_csr_dcsr, + input io_csr_pkt_csr_mcgc, + input io_csr_pkt_csr_mfdc, + input io_csr_pkt_csr_dpc, + input io_csr_pkt_csr_mtsel, + input io_csr_pkt_csr_mtdata1, + input io_csr_pkt_csr_mtdata2, + input io_csr_pkt_csr_mhpmc3, + input io_csr_pkt_csr_mhpmc4, + input io_csr_pkt_csr_mhpmc5, + input io_csr_pkt_csr_mhpmc6, + input io_csr_pkt_csr_mhpmc3h, + input io_csr_pkt_csr_mhpmc4h, + input io_csr_pkt_csr_mhpmc5h, + input io_csr_pkt_csr_mhpmc6h, + input io_csr_pkt_csr_mhpme3, + input io_csr_pkt_csr_mhpme4, + input io_csr_pkt_csr_mhpme5, + input io_csr_pkt_csr_mhpme6, + input io_csr_pkt_csr_mcountinhibit, + input io_csr_pkt_csr_mpmc, + input io_csr_pkt_csr_micect, + input io_csr_pkt_csr_miccmect, + input io_csr_pkt_csr_mdccmect, + input io_csr_pkt_csr_mfdht, + input io_csr_pkt_csr_mfdhs, + input io_csr_pkt_csr_dicawics, + input io_csr_pkt_csr_dicad0h, + input io_csr_pkt_csr_dicad0, + input io_csr_pkt_csr_dicad1, + output [9:0] io_mtdata1_t_0, + output [9:0] io_mtdata1_t_1, + output [9:0] io_mtdata1_t_2, + output [9:0] io_mtdata1_t_3 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [63:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [63:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [95:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 474:22] + wire _T = ~io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 1530:46] + wire _T_1 = io_dec_csr_wen_r & _T; // @[el2_dec_tlu_ctl.scala 1530:44] + wire _T_2 = ~io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 1530:69] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[el2_dec_tlu_ctl.scala 1531:72] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[el2_dec_tlu_ctl.scala 1531:43] + wire _T_496 = io_dec_csr_wraddr_r == 12'h7c6; // @[el2_dec_tlu_ctl.scala 1917:69] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_496; // @[el2_dec_tlu_ctl.scala 1917:40] + wire _T_507 = ~io_dec_csr_wrdata_r[1]; // @[el2_dec_tlu_ctl.scala 1924:38] + reg mpmc_b; // @[el2_dec_tlu_ctl.scala 1926:45] + wire mpmc = ~mpmc_b; // @[el2_dec_tlu_ctl.scala 1929:11] + wire _T_508 = ~mpmc; // @[el2_dec_tlu_ctl.scala 1924:63] + wire mpmc_b_ns = wr_mpmc_r ? _T_507 : _T_508; // @[el2_dec_tlu_ctl.scala 1924:19] + wire _T_6 = ~mpmc_b_ns; // @[el2_dec_tlu_ctl.scala 1534:29] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1534:40] + wire _T_7 = ~wr_mstatus_r; // @[el2_dec_tlu_ctl.scala 1537:6] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1537:20] + wire _T_12 = wr_mstatus_r & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1538:19] + wire _T_15 = ~io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1539:18] + wire _T_16 = io_mret_r & _T_15; // @[el2_dec_tlu_ctl.scala 1539:16] + wire [1:0] _T_19 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_22 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] + wire _T_24 = wr_mstatus_r & _T_15; // @[el2_dec_tlu_ctl.scala 1541:19] + wire [1:0] _T_28 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + wire _T_31 = _T_7 & _T_15; // @[el2_dec_tlu_ctl.scala 1542:20] + wire _T_32 = ~io_mret_r; // @[el2_dec_tlu_ctl.scala 1542:47] + wire _T_33 = _T_31 & _T_32; // @[el2_dec_tlu_ctl.scala 1542:45] + wire _T_34 = ~set_mie_pmu_fw_halt; // @[el2_dec_tlu_ctl.scala 1542:60] + wire _T_35 = _T_33 & _T_34; // @[el2_dec_tlu_ctl.scala 1542:58] + wire _T_37 = _T_8 & io_mstatus[0]; // @[Mux.scala 27:72] + wire _T_38 = _T_12 & io_dec_csr_wrdata_r[3]; // @[Mux.scala 27:72] + wire [1:0] _T_39 = _T_16 ? _T_19 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_40 = set_mie_pmu_fw_halt ? _T_22 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_41 = _T_24 ? _T_28 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_42 = _T_35 ? io_mstatus : 2'h0; // @[Mux.scala 27:72] + wire _T_43 = _T_37 | _T_38; // @[Mux.scala 27:72] + wire [1:0] _GEN_9 = {{1'd0}, _T_43}; // @[Mux.scala 27:72] + wire [1:0] _T_44 = _GEN_9 | _T_39; // @[Mux.scala 27:72] + wire [1:0] _T_45 = _T_44 | _T_40; // @[Mux.scala 27:72] + wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] + wire _T_50 = ~io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1545:51] + wire _T_52 = _T_50 | io_dcsr[11]; // @[el2_dec_tlu_ctl.scala 1545:82] + reg [1:0] _T_54; // @[el2_dec_tlu_ctl.scala 1547:12] + wire _T_56 = io_dec_csr_wraddr_r == 12'h305; // @[el2_dec_tlu_ctl.scala 1556:70] + reg [30:0] _T_60; // @[el2_lib.scala 491:16] + reg [31:0] mdccmect; // @[el2_lib.scala 491:16] + wire [62:0] _T_572 = 63'hffffffff << mdccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1975:42] + wire [31:0] _T_574 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_574}; // @[el2_dec_tlu_ctl.scala 1975:62] + wire [62:0] _T_575 = _T_572 & _GEN_10; // @[el2_dec_tlu_ctl.scala 1975:62] + wire mdccme_ce_req = |_T_575; // @[el2_dec_tlu_ctl.scala 1975:95] + reg [31:0] miccmect; // @[el2_lib.scala 491:16] + wire [62:0] _T_552 = 63'hffffffff << miccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1960:42] + wire [31:0] _T_554 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_554}; // @[el2_dec_tlu_ctl.scala 1960:62] + wire [62:0] _T_555 = _T_552 & _GEN_11; // @[el2_dec_tlu_ctl.scala 1960:62] + wire miccme_ce_req = |_T_555; // @[el2_dec_tlu_ctl.scala 1960:95] + wire _T_61 = mdccme_ce_req | miccme_ce_req; // @[el2_dec_tlu_ctl.scala 1570:31] + reg [31:0] micect; // @[el2_lib.scala 491:16] + wire [62:0] _T_530 = 63'hffffffff << micect[31:27]; // @[el2_dec_tlu_ctl.scala 1946:39] + wire _T_531 = |_T_530; // @[el2_dec_tlu_ctl.scala 1946:57] + wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] + wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1455:41 el2_dec_tlu_ctl.scala 1946:15] + wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] + wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] + wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] + reg [5:0] _T_66; // @[el2_dec_tlu_ctl.scala 1574:12] + wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[el2_dec_tlu_ctl.scala 1586:68] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[el2_dec_tlu_ctl.scala 1586:39] + wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + reg [5:0] mie; // @[el2_dec_tlu_ctl.scala 1589:12] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1596:55] + wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[el2_dec_tlu_ctl.scala 1598:72] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[el2_dec_tlu_ctl.scala 1598:43] + wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1600:72] + wire _T_84 = kill_ebreak_count_r | _T_83; // @[el2_dec_tlu_ctl.scala 1600:47] + wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 1600:95] + reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] + reg temp_ncount0; // @[Reg.scala 27:20] + wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire _T_87 = _T_85 | mcountinhibit[0]; // @[el2_dec_tlu_ctl.scala 1600:122] + wire mcyclel_cout_in = ~_T_87; // @[el2_dec_tlu_ctl.scala 1600:25] + wire [31:0] _T_88 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] + reg [32:0] _T_95; // @[el2_lib.scala 491:16] + wire [31:0] mcyclel = _T_95[31:0]; // @[el2_dec_tlu_ctl.scala 1607:11] + wire [31:0] _T_90 = mcyclel + _T_88; // @[el2_dec_tlu_ctl.scala 1604:26] + wire [32:0] mcyclel_inc = {{1'd0}, _T_90}; // @[el2_dec_tlu_ctl.scala 1604:15] + wire mcyclel_cout = mcyclel_inc[32]; // @[el2_dec_tlu_ctl.scala 1606:33] + wire _T_99 = io_dec_csr_wraddr_r == 12'hb80; // @[el2_dec_tlu_ctl.scala 1614:69] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_99; // @[el2_dec_tlu_ctl.scala 1614:40] + wire _T_96 = ~wr_mcycleh_r; // @[el2_dec_tlu_ctl.scala 1608:72] + reg mcyclel_cout_f; // @[el2_dec_tlu_ctl.scala 1608:55] + wire [31:0] _T_101 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] + reg [31:0] mcycleh; // @[el2_lib.scala 491:16] + wire [31:0] mcycleh_inc = mcycleh + _T_101; // @[el2_dec_tlu_ctl.scala 1616:29] + wire _T_107 = io_ebreak_r | io_ecall_r; // @[el2_dec_tlu_ctl.scala 1633:73] + wire _T_108 = _T_107 | io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 1633:86] + wire _T_109 = _T_108 | io_illegal_r; // @[el2_dec_tlu_ctl.scala 1633:114] + wire _T_111 = _T_109 | mcountinhibit[2]; // @[el2_dec_tlu_ctl.scala 1633:129] + wire _T_113 = ~_T_111; // @[el2_dec_tlu_ctl.scala 1633:59] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_113; // @[el2_dec_tlu_ctl.scala 1633:57] + wire _T_115 = io_dec_csr_wraddr_r == 12'hb02; // @[el2_dec_tlu_ctl.scala 1635:74] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_115; // @[el2_dec_tlu_ctl.scala 1635:45] + wire [31:0] _T_116 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] + reg [32:0] _T_122; // @[el2_lib.scala 491:16] + wire [31:0] minstretl = _T_122[31:0]; // @[el2_dec_tlu_ctl.scala 1642:13] + wire [31:0] _T_118 = minstretl + _T_116; // @[el2_dec_tlu_ctl.scala 1637:30] + wire [32:0] minstretl_inc = {{1'd0}, _T_118}; // @[el2_dec_tlu_ctl.scala 1637:17] + wire minstretl_cout = minstretl_inc[32]; // @[el2_dec_tlu_ctl.scala 1638:37] + reg minstret_enable_f; // @[el2_dec_tlu_ctl.scala 1643:57] + wire _T_126 = io_dec_csr_wraddr_r == 12'hb82; // @[el2_dec_tlu_ctl.scala 1652:72] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_126; // @[el2_dec_tlu_ctl.scala 1652:43] + wire _T_123 = ~wr_minstreth_r; // @[el2_dec_tlu_ctl.scala 1644:76] + reg minstretl_cout_f; // @[el2_dec_tlu_ctl.scala 1644:57] + wire [31:0] _T_129 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] + reg [31:0] minstreth; // @[el2_lib.scala 491:16] + wire [31:0] minstreth_inc = minstreth + _T_129; // @[el2_dec_tlu_ctl.scala 1655:30] + wire _T_137 = io_dec_csr_wraddr_r == 12'h340; // @[el2_dec_tlu_ctl.scala 1666:73] + reg [31:0] mscratch; // @[el2_lib.scala 491:16] + wire _T_140 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 1677:23] + wire _T_141 = ~io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1677:48] + wire _T_142 = _T_140 & _T_141; // @[el2_dec_tlu_ctl.scala 1677:46] + wire sel_exu_npc_r = _T_142 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1677:73] + wire _T_144 = _T_140 & io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1678:48] + wire _T_145 = ~io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1678:76] + wire sel_flush_npc_r = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 1678:74] + wire _T_146 = ~sel_exu_npc_r; // @[el2_dec_tlu_ctl.scala 1679:24] + wire _T_147 = ~sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1679:41] + wire sel_hold_npc_r = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 1679:39] + wire _T_149 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 1683:6] + wire _T_150 = _T_149 & io_reset_delayed; // @[el2_dec_tlu_ctl.scala 1683:28] + wire [30:0] _T_154 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_155 = _T_150 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_156 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_157 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_158 = _T_154 | _T_155; // @[Mux.scala 27:72] + wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72] + wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49] + reg [30:0] _T_165; // @[el2_lib.scala 491:16] + wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45] + wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5] + wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[el2_lib.scala 491:16] + wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72] + wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40] + wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30] + wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51] + wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16] + wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6] + wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17] + wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72] + wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72] + reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48] + wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42] + wire _T_197 = io_exc_or_int_valid_r & io_take_nmi; // @[el2_dec_tlu_ctl.scala 1714:52] + wire mcause_sel_nmi_store = _T_197 & io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 1714:66] + wire mcause_sel_nmi_load = _T_197 & io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 1715:65] + wire _T_200 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1716:83] + wire mcause_sel_nmi_ext = _T_197 & _T_200; // @[el2_dec_tlu_ctl.scala 1716:64] + wire _T_201 = &io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1722:52] + wire _T_204 = ~io_lsu_fir_error[0]; // @[el2_dec_tlu_ctl.scala 1722:81] + wire _T_205 = io_lsu_fir_error[1] & _T_204; // @[el2_dec_tlu_ctl.scala 1722:79] + wire [31:0] _T_210 = {30'h3c000400,_T_201,_T_205}; // @[Cat.scala 29:58] + wire _T_211 = ~io_take_nmi; // @[el2_dec_tlu_ctl.scala 1728:30] + wire _T_212 = io_exc_or_int_valid_r & _T_211; // @[el2_dec_tlu_ctl.scala 1728:28] + wire [31:0] _T_215 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] + wire _T_217 = wr_mcause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1729:18] + wire _T_219 = ~wr_mcause_r; // @[el2_dec_tlu_ctl.scala 1730:6] + wire _T_221 = _T_219 & _T_15; // @[el2_dec_tlu_ctl.scala 1730:19] + wire [31:0] _T_223 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_224 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_225 = mcause_sel_nmi_ext ? _T_210 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_226 = _T_212 ? _T_215 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_227 = _T_217 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mcause; // @[el2_dec_tlu_ctl.scala 1732:47] + wire [31:0] _T_228 = _T_221 ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_229 = _T_223 | _T_224; // @[Mux.scala 27:72] + wire [31:0] _T_230 = _T_229 | _T_225; // @[Mux.scala 27:72] + wire [31:0] _T_231 = _T_230 | _T_226; // @[Mux.scala 27:72] + wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] + wire _T_236 = io_dec_csr_wraddr_r == 12'h7ff; // @[el2_dec_tlu_ctl.scala 1739:72] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_236; // @[el2_dec_tlu_ctl.scala 1739:43] + wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] + wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] + wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] + wire _T_243 = io_lsu_i0_exc_r & io_lsu_error_pkt_r_mscause; // @[Mux.scala 27:72] + wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] + wire _T_247 = _T_243 | io_i0_trigger_hit_r; // @[Mux.scala 27:72] + wire [1:0] _GEN_13 = {{1'd0}, _T_247}; // @[Mux.scala 27:72] + wire [1:0] _T_248 = _GEN_13 | _T_245; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_248}; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _GEN_14 | _T_246; // @[Mux.scala 27:72] + wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] + wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] + wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] + wire [3:0] _T_259 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_260 = _T_252 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] + reg [3:0] mscause; // @[el2_dec_tlu_ctl.scala 1755:48] + wire [3:0] _T_261 = _T_257 ? mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72] + wire _T_266 = io_dec_csr_wraddr_r == 12'h343; // @[el2_dec_tlu_ctl.scala 1762:70] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_266; // @[el2_dec_tlu_ctl.scala 1762:41] + wire _T_267 = ~io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1763:84] + wire _T_268 = io_inst_acc_r & _T_267; // @[el2_dec_tlu_ctl.scala 1763:82] + wire _T_269 = io_ebreak_r | _T_268; // @[el2_dec_tlu_ctl.scala 1763:65] + wire _T_270 = _T_269 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1763:107] + wire _T_271 = io_exc_or_int_valid_r & _T_270; // @[el2_dec_tlu_ctl.scala 1763:50] + wire mtval_capture_pc_r = _T_271 & _T_211; // @[el2_dec_tlu_ctl.scala 1763:139] + wire _T_273 = io_inst_acc_r & io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1764:73] + wire _T_274 = io_exc_or_int_valid_r & _T_273; // @[el2_dec_tlu_ctl.scala 1764:56] + wire mtval_capture_pc_plus2_r = _T_274 & _T_211; // @[el2_dec_tlu_ctl.scala 1764:97] + wire _T_276 = io_exc_or_int_valid_r & io_illegal_r; // @[el2_dec_tlu_ctl.scala 1765:52] + wire mtval_capture_inst_r = _T_276 & _T_211; // @[el2_dec_tlu_ctl.scala 1765:67] + wire _T_278 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1766:51] + wire mtval_capture_lsu_r = _T_278 & _T_211; // @[el2_dec_tlu_ctl.scala 1766:72] + wire _T_280 = ~mtval_capture_pc_r; // @[el2_dec_tlu_ctl.scala 1767:47] + wire _T_281 = io_exc_or_int_valid_r & _T_280; // @[el2_dec_tlu_ctl.scala 1767:45] + wire _T_282 = ~mtval_capture_inst_r; // @[el2_dec_tlu_ctl.scala 1767:69] + wire _T_283 = _T_281 & _T_282; // @[el2_dec_tlu_ctl.scala 1767:67] + wire _T_284 = ~mtval_capture_lsu_r; // @[el2_dec_tlu_ctl.scala 1767:93] + wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91] + wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116] + wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114] + wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84] + wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58] + wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19] + wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17] + wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21] + wire _T_300 = _T_211 & _T_299; // @[el2_dec_tlu_ctl.scala 1776:19] + wire _T_302 = _T_300 & _T_280; // @[el2_dec_tlu_ctl.scala 1776:33] + wire _T_304 = _T_302 & _T_282; // @[el2_dec_tlu_ctl.scala 1776:55] + wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81] + wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79] + wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96] + wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47] + wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72] + wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72] + wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72] + wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] + wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69] + reg [8:0] mcgc; // @[el2_lib.scala 491:16] + wire _T_335 = io_dec_csr_wraddr_r == 12'h7f9; // @[el2_dec_tlu_ctl.scala 1823:69] + reg [14:0] mfdc_int; // @[el2_lib.scala 491:16] + wire [2:0] _T_339 = ~io_dec_csr_wrdata_r[18:16]; // @[el2_dec_tlu_ctl.scala 1832:20] + wire _T_342 = ~io_dec_csr_wrdata_r[6]; // @[el2_dec_tlu_ctl.scala 1832:75] + wire [6:0] _T_344 = {_T_342,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_345 = {_T_339,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_348 = ~mfdc_int[14:12]; // @[el2_dec_tlu_ctl.scala 1833:20] + wire _T_351 = ~mfdc_int[6]; // @[el2_dec_tlu_ctl.scala 1833:63] + wire [18:0] mfdc = {_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_365 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 1856:78] + wire _T_366 = io_dec_csr_wen_r_mod & _T_365; // @[el2_dec_tlu_ctl.scala 1856:49] + wire _T_368 = _T_366 & _T_295; // @[el2_dec_tlu_ctl.scala 1856:88] + wire _T_369 = ~io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1856:114] + wire _T_372 = io_dec_csr_wraddr_r == 12'h7c0; // @[el2_dec_tlu_ctl.scala 1863:69] + wire _T_376 = ~io_dec_csr_wrdata_r[31]; // @[el2_dec_tlu_ctl.scala 1866:72] + wire _T_377 = io_dec_csr_wrdata_r[30] & _T_376; // @[el2_dec_tlu_ctl.scala 1866:70] + wire _T_381 = ~io_dec_csr_wrdata_r[29]; // @[el2_dec_tlu_ctl.scala 1867:56] + wire _T_382 = io_dec_csr_wrdata_r[28] & _T_381; // @[el2_dec_tlu_ctl.scala 1867:54] + wire _T_386 = ~io_dec_csr_wrdata_r[27]; // @[el2_dec_tlu_ctl.scala 1868:56] + wire _T_387 = io_dec_csr_wrdata_r[26] & _T_386; // @[el2_dec_tlu_ctl.scala 1868:54] + wire _T_391 = ~io_dec_csr_wrdata_r[25]; // @[el2_dec_tlu_ctl.scala 1869:56] + wire _T_392 = io_dec_csr_wrdata_r[24] & _T_391; // @[el2_dec_tlu_ctl.scala 1869:54] + wire _T_396 = ~io_dec_csr_wrdata_r[23]; // @[el2_dec_tlu_ctl.scala 1870:56] + wire _T_397 = io_dec_csr_wrdata_r[22] & _T_396; // @[el2_dec_tlu_ctl.scala 1870:54] + wire _T_401 = ~io_dec_csr_wrdata_r[21]; // @[el2_dec_tlu_ctl.scala 1871:56] + wire _T_402 = io_dec_csr_wrdata_r[20] & _T_401; // @[el2_dec_tlu_ctl.scala 1871:54] + wire _T_406 = ~io_dec_csr_wrdata_r[19]; // @[el2_dec_tlu_ctl.scala 1872:56] + wire _T_407 = io_dec_csr_wrdata_r[18] & _T_406; // @[el2_dec_tlu_ctl.scala 1872:54] + wire _T_411 = ~io_dec_csr_wrdata_r[17]; // @[el2_dec_tlu_ctl.scala 1873:56] + wire _T_412 = io_dec_csr_wrdata_r[16] & _T_411; // @[el2_dec_tlu_ctl.scala 1873:54] + wire _T_416 = ~io_dec_csr_wrdata_r[15]; // @[el2_dec_tlu_ctl.scala 1874:56] + wire _T_417 = io_dec_csr_wrdata_r[14] & _T_416; // @[el2_dec_tlu_ctl.scala 1874:54] + wire _T_421 = ~io_dec_csr_wrdata_r[13]; // @[el2_dec_tlu_ctl.scala 1875:56] + wire _T_422 = io_dec_csr_wrdata_r[12] & _T_421; // @[el2_dec_tlu_ctl.scala 1875:54] + wire _T_426 = ~io_dec_csr_wrdata_r[11]; // @[el2_dec_tlu_ctl.scala 1876:56] + wire _T_427 = io_dec_csr_wrdata_r[10] & _T_426; // @[el2_dec_tlu_ctl.scala 1876:54] + wire _T_431 = ~io_dec_csr_wrdata_r[9]; // @[el2_dec_tlu_ctl.scala 1877:56] + wire _T_432 = io_dec_csr_wrdata_r[8] & _T_431; // @[el2_dec_tlu_ctl.scala 1877:53] + wire _T_436 = ~io_dec_csr_wrdata_r[7]; // @[el2_dec_tlu_ctl.scala 1878:56] + wire _T_437 = io_dec_csr_wrdata_r[6] & _T_436; // @[el2_dec_tlu_ctl.scala 1878:53] + wire _T_441 = ~io_dec_csr_wrdata_r[5]; // @[el2_dec_tlu_ctl.scala 1879:56] + wire _T_442 = io_dec_csr_wrdata_r[4] & _T_441; // @[el2_dec_tlu_ctl.scala 1879:53] + wire _T_446 = ~io_dec_csr_wrdata_r[3]; // @[el2_dec_tlu_ctl.scala 1880:56] + wire _T_447 = io_dec_csr_wrdata_r[2] & _T_446; // @[el2_dec_tlu_ctl.scala 1880:53] + wire _T_452 = io_dec_csr_wrdata_r[0] & _T_507; // @[el2_dec_tlu_ctl.scala 1881:53] + wire [7:0] _T_459 = {io_dec_csr_wrdata_r[7],_T_437,io_dec_csr_wrdata_r[5],_T_442,io_dec_csr_wrdata_r[3],_T_447,io_dec_csr_wrdata_r[1],_T_452}; // @[Cat.scala 29:58] + wire [15:0] _T_467 = {io_dec_csr_wrdata_r[15],_T_417,io_dec_csr_wrdata_r[13],_T_422,io_dec_csr_wrdata_r[11],_T_427,io_dec_csr_wrdata_r[9],_T_432,_T_459}; // @[Cat.scala 29:58] + wire [7:0] _T_474 = {io_dec_csr_wrdata_r[23],_T_397,io_dec_csr_wrdata_r[21],_T_402,io_dec_csr_wrdata_r[19],_T_407,io_dec_csr_wrdata_r[17],_T_412}; // @[Cat.scala 29:58] + wire [15:0] _T_482 = {io_dec_csr_wrdata_r[31],_T_377,io_dec_csr_wrdata_r[29],_T_382,io_dec_csr_wrdata_r[27],_T_387,io_dec_csr_wrdata_r[25],_T_392,_T_474}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[el2_lib.scala 491:16] + wire _T_485 = io_dec_csr_wraddr_r == 12'hbc0; // @[el2_dec_tlu_ctl.scala 1894:70] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_485; // @[el2_dec_tlu_ctl.scala 1894:41] + wire _T_486 = ~wr_mdeau_r; // @[el2_dec_tlu_ctl.scala 1904:60] + wire _T_487 = io_mdseac_locked_f & _T_486; // @[el2_dec_tlu_ctl.scala 1904:58] + wire _T_489 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 1906:50] + wire _T_490 = ~io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1906:87] + wire _T_491 = _T_489 & _T_490; // @[el2_dec_tlu_ctl.scala 1906:85] + wire _T_492 = ~io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1906:112] + wire mdseac_en = _T_491 & _T_492; // @[el2_dec_tlu_ctl.scala 1906:110] + reg [31:0] mdseac; // @[el2_lib.scala 491:16] + wire _T_498 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[el2_dec_tlu_ctl.scala 1921:31] + wire _T_499 = ~io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1921:58] + wire _T_500 = _T_498 & _T_499; // @[el2_dec_tlu_ctl.scala 1921:56] + wire _T_501 = ~io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1921:90] + wire _T_514 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[el2_dec_tlu_ctl.scala 1938:49] + wire [4:0] csr_sat = _T_514 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[el2_dec_tlu_ctl.scala 1938:20] + wire _T_517 = io_dec_csr_wraddr_r == 12'h7f0; // @[el2_dec_tlu_ctl.scala 1940:71] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_517; // @[el2_dec_tlu_ctl.scala 1940:42] + wire [26:0] _T_518 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_15 = {{5'd0}, _T_518}; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_520 = micect + _GEN_15; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_523 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_520[26:0]; // @[el2_dec_tlu_ctl.scala 1941:14] + wire [31:0] _T_525 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_536 = io_dec_csr_wraddr_r == 12'h7f1; // @[el2_dec_tlu_ctl.scala 1955:77] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_536; // @[el2_dec_tlu_ctl.scala 1955:48] + wire _T_538 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 1956:71] + wire [26:0] _T_539 = {26'h0,_T_538}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_539; // @[el2_dec_tlu_ctl.scala 1956:34] + wire [31:0] _T_546 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_547 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1959:49] + wire _T_558 = io_dec_csr_wraddr_r == 12'h7f2; // @[el2_dec_tlu_ctl.scala 1969:77] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_558; // @[el2_dec_tlu_ctl.scala 1969:48] + wire [26:0] _T_560 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_560; // @[el2_dec_tlu_ctl.scala 1970:34] + wire [31:0] _T_567 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_578 = io_dec_csr_wraddr_r == 12'h7ce; // @[el2_dec_tlu_ctl.scala 1985:70] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_578; // @[el2_dec_tlu_ctl.scala 1985:41] + reg [5:0] mfdht; // @[el2_dec_tlu_ctl.scala 1989:44] + wire _T_583 = io_dec_csr_wraddr_r == 12'h7cf; // @[el2_dec_tlu_ctl.scala 1998:70] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_583; // @[el2_dec_tlu_ctl.scala 1998:41] + wire _T_586 = ~io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2001:30] + wire _T_587 = io_dbg_tlu_halted & _T_586; // @[el2_dec_tlu_ctl.scala 2001:28] + wire _T_589 = ~io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 2001:65] + wire _T_590 = ~io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 2001:85] + wire [1:0] _T_591 = {_T_589,_T_590}; // @[Cat.scala 29:58] + reg [1:0] mfdhs; // @[Reg.scala 27:20] + wire _T_593 = wr_mfdhs_r | io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2003:72] + reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] + wire [31:0] _T_598 = force_halt_ctr_f + 32'h1; // @[el2_dec_tlu_ctl.scala 2005:75] + wire [62:0] _T_605 = 63'hffffffff << mfdht[5:1]; // @[el2_dec_tlu_ctl.scala 2010:72] + wire [62:0] _GEN_16 = {{31'd0}, force_halt_ctr_f}; // @[el2_dec_tlu_ctl.scala 2010:49] + wire [62:0] _T_606 = _GEN_16 & _T_605; // @[el2_dec_tlu_ctl.scala 2010:49] + wire _T_607 = |_T_606; // @[el2_dec_tlu_ctl.scala 2010:88] + wire _T_610 = io_dec_csr_wraddr_r == 12'hbc8; // @[el2_dec_tlu_ctl.scala 2018:70] + reg [21:0] meivt; // @[el2_lib.scala 491:16] + wire _T_630 = io_dec_csr_wraddr_r == 12'hbca; // @[el2_dec_tlu_ctl.scala 2069:70] + wire _T_631 = io_dec_csr_wen_r_mod & _T_630; // @[el2_dec_tlu_ctl.scala 2069:41] + wire wr_meicpct_r = _T_631 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2069:84] + reg [7:0] meihap; // @[el2_lib.scala 491:16] + wire [31:0] _T_615 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire _T_617 = io_dec_csr_wraddr_r == 12'hbcc; // @[el2_dec_tlu_ctl.scala 2042:73] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_617; // @[el2_dec_tlu_ctl.scala 2042:44] + reg [3:0] meicurpl; // @[el2_dec_tlu_ctl.scala 2045:47] + wire _T_622 = io_dec_csr_wraddr_r == 12'hbcb; // @[el2_dec_tlu_ctl.scala 2057:74] + wire _T_623 = io_dec_csr_wen_r_mod & _T_622; // @[el2_dec_tlu_ctl.scala 2057:45] + wire wr_meicidpl_r = _T_623 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2057:89] + reg [3:0] meicidpl; // @[el2_dec_tlu_ctl.scala 2062:45] + wire _T_634 = io_dec_csr_wraddr_r == 12'hbc9; // @[el2_dec_tlu_ctl.scala 2078:70] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_634; // @[el2_dec_tlu_ctl.scala 2078:41] + reg [3:0] meipt; // @[el2_dec_tlu_ctl.scala 2081:44] + wire _T_638 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 2109:90] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_638; // @[el2_dec_tlu_ctl.scala 2109:67] + wire _T_639 = ~io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 2112:35] + wire _T_640 = io_dcsr_single_step_done_f & _T_639; // @[el2_dec_tlu_ctl.scala 2112:33] + wire _T_641 = ~trigger_hit_for_dscr_cause_r_d1; // @[el2_dec_tlu_ctl.scala 2112:67] + wire _T_642 = _T_640 & _T_641; // @[el2_dec_tlu_ctl.scala 2112:65] + wire _T_643 = ~io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 2112:102] + wire _T_644 = _T_642 & _T_643; // @[el2_dec_tlu_ctl.scala 2112:100] + wire _T_647 = io_debug_halt_req & _T_639; // @[el2_dec_tlu_ctl.scala 2113:24] + wire _T_649 = _T_647 & _T_641; // @[el2_dec_tlu_ctl.scala 2113:56] + wire _T_652 = io_ebreak_to_debug_mode_r_d1 & _T_641; // @[el2_dec_tlu_ctl.scala 2114:35] + wire [2:0] _T_655 = _T_644 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_656 = _T_649 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_652 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = _T_655 | _T_656; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_659 | _T_657; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_660 | _T_658; // @[Mux.scala 27:72] + wire _T_662 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 2117:47] + wire _T_664 = io_dec_csr_wraddr_r == 12'h7b0; // @[el2_dec_tlu_ctl.scala 2117:99] + wire wr_dcsr_r = _T_662 & _T_664; // @[el2_dec_tlu_ctl.scala 2117:70] + wire _T_666 = io_dcsr[8:6] == 3'h3; // @[el2_dec_tlu_ctl.scala 2123:76] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_666; // @[el2_dec_tlu_ctl.scala 2123:60] + wire _T_667 = ~io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2124:60] + wire _T_668 = _T_667 | dcsr_cause_upgradeable; // @[el2_dec_tlu_ctl.scala 2124:79] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_668; // @[el2_dec_tlu_ctl.scala 2124:57] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 2126:49] + wire [15:0] _T_674 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_680 = nmi_in_debug_mode | io_dcsr[3]; // @[el2_dec_tlu_ctl.scala 2128:146] + wire [15:0] _T_689 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_680,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_694 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_696 = enter_debug_halt_req_le | wr_dcsr_r; // @[el2_dec_tlu_ctl.scala 2130:55] + wire _T_697 = _T_696 | io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 2130:67] + reg [15:0] _T_700; // @[el2_lib.scala 491:16] + wire _T_703 = io_dec_csr_wraddr_r == 12'h7b1; // @[el2_dec_tlu_ctl.scala 2138:98] + wire wr_dpc_r = _T_662 & _T_703; // @[el2_dec_tlu_ctl.scala 2138:69] + wire _T_706 = ~io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 2139:68] + wire dpc_capture_npc = _T_587 & _T_706; // @[el2_dec_tlu_ctl.scala 2139:66] + wire _T_707 = ~io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2143:6] + wire _T_708 = ~dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2143:24] + wire _T_709 = _T_707 & _T_708; // @[el2_dec_tlu_ctl.scala 2143:22] + wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41] + wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22] + wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72] + wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37] + reg [30:0] _T_725; // @[el2_lib.scala 491:16] + wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_732 = io_dec_csr_wraddr_r == 12'h7c8; // @[el2_dec_tlu_ctl.scala 2162:103] + reg [16:0] dicawics; // @[el2_lib.scala 491:16] + wire _T_736 = io_dec_csr_wraddr_r == 12'h7c9; // @[el2_dec_tlu_ctl.scala 2180:101] + wire wr_dicad0_r = _T_662 & _T_736; // @[el2_dec_tlu_ctl.scala 2180:72] + reg [70:0] dicad0; // @[el2_lib.scala 491:16] + wire _T_742 = io_dec_csr_wraddr_r == 12'h7cc; // @[el2_dec_tlu_ctl.scala 2193:102] + wire wr_dicad0h_r = _T_662 & _T_742; // @[el2_dec_tlu_ctl.scala 2193:73] + reg [31:0] dicad0h; // @[el2_lib.scala 491:16] + wire _T_750 = io_dec_csr_wraddr_r == 12'h7ca; // @[el2_dec_tlu_ctl.scala 2205:103] + wire _T_751 = _T_662 & _T_750; // @[el2_dec_tlu_ctl.scala 2205:74] + wire _T_755 = _T_751 | io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 2209:81] + reg [31:0] _T_757; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_757[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_762 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_764 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 2237:53] + wire _T_765 = _T_764 & io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 2237:76] + wire _T_766 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 2237:99] + wire _T_767 = _T_765 & _T_766; // @[el2_dec_tlu_ctl.scala 2237:97] + wire _T_769 = io_dec_csr_rdaddr_d == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2237:150] + wire _T_772 = io_dec_csr_wraddr_r == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2238:105] + reg icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2241:59] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7a0; // @[el2_dec_tlu_ctl.scala 2252:70] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_774; // @[el2_dec_tlu_ctl.scala 2252:41] + reg [1:0] mtsel; // @[el2_dec_tlu_ctl.scala 2255:44] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_406; // @[el2_dec_tlu_ctl.scala 2290:43] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_406; // @[el2_dec_tlu_ctl.scala 2292:45] + wire _T_785 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2294:47] + wire tdata_action = _T_785 & io_dec_csr_wrdata_r[12]; // @[el2_dec_tlu_ctl.scala 2294:70] + wire [9:0] tdata_wrdata_r = {_T_785,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_800 = io_dec_csr_wraddr_r == 12'h7a1; // @[el2_dec_tlu_ctl.scala 2300:100] + wire _T_801 = io_dec_csr_wen_r_mod & _T_800; // @[el2_dec_tlu_ctl.scala 2300:71] + wire _T_802 = mtsel == 2'h0; // @[el2_dec_tlu_ctl.scala 2300:122] + wire _T_803 = _T_801 & _T_802; // @[el2_dec_tlu_ctl.scala 2300:113] + wire _T_805 = ~io_mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_0 = _T_803 & _T_806; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_814 = ~io_mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_1 = _T_803 & _T_815; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_823 = ~io_mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_2 = _T_803 & _T_824; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_832 = ~io_mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_833 = _T_832 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_3 = _T_803 & _T_833; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_839 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_842 = {io_mtdata1_t_0[9],_T_839,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_848 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_851 = {io_mtdata1_t_1[9],_T_848,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_857 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_860 = {io_mtdata1_t_2[9],_T_857,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_866 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_869 = {io_mtdata1_t_3[9],_T_866,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_871; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_872; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_873; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_874; // @[el2_dec_tlu_ctl.scala 2303:76] + wire [31:0] _T_889 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire _T_890 = mtsel == 2'h1; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_904 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire _T_905 = mtsel == 2'h2; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_919 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire _T_920 = mtsel == 2'h3; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_934 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = _T_802 ? _T_889 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_936 = _T_890 ? _T_904 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_905 ? _T_919 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_920 ? _T_934 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_935 | _T_936; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_939 | _T_937; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_940 | _T_938; // @[Mux.scala 27:72] + wire _T_967 = io_dec_csr_wraddr_r == 12'h7a2; // @[el2_dec_tlu_ctl.scala 2320:99] + wire _T_968 = io_dec_csr_wen_r_mod & _T_967; // @[el2_dec_tlu_ctl.scala 2320:70] + wire _T_970 = _T_968 & _T_802; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_979 = _T_968 & _T_890; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_988 = _T_968 & _T_905; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_997 = _T_968 & _T_920; // @[el2_dec_tlu_ctl.scala 2320:112] + reg [31:0] mtdata2_t_0; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_1; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_2; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_3; // @[el2_lib.scala 491:16] + wire [31:0] _T_1014 = _T_802 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1015 = _T_890 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_905 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_920 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_1014 | _T_1015; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1018 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [3:0] _T_1022 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1022; // @[el2_dec_tlu_ctl.scala 2345:60] + wire _T_1024 = ~mcountinhibit[3]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme3; // @[Reg.scala 27:20] + wire _T_1025 = mhpme3 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1027 = mhpme3 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1029 = mhpme3 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1031 = mhpme3 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1033 = ~io_illegal_r; // @[el2_dec_tlu_ctl.scala 2355:83] + wire _T_1034 = io_tlu_i0_commit_cmt & _T_1033; // @[el2_dec_tlu_ctl.scala 2355:81] + wire _T_1035 = mhpme3 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1037 = ~io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2356:83] + wire _T_1038 = io_tlu_i0_commit_cmt & _T_1037; // @[el2_dec_tlu_ctl.scala 2356:81] + wire _T_1040 = _T_1038 & _T_1033; // @[el2_dec_tlu_ctl.scala 2356:102] + wire _T_1041 = mhpme3 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1043 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2357:81] + wire _T_1045 = _T_1043 & _T_1033; // @[el2_dec_tlu_ctl.scala 2357:102] + wire _T_1046 = mhpme3 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1048 = mhpme3 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1050 = mhpme3 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1052 = mhpme3 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1054 = pmu_i0_itype_qual == 4'h1; // @[el2_dec_tlu_ctl.scala 2361:78] + wire _T_1055 = mhpme3 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1057 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2362:92] + wire _T_1058 = mhpme3 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1060 = pmu_i0_itype_qual == 4'h2; // @[el2_dec_tlu_ctl.scala 2363:78] + wire _T_1061 = mhpme3 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1063 = pmu_i0_itype_qual == 4'h3; // @[el2_dec_tlu_ctl.scala 2364:78] + wire _T_1064 = mhpme3 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1067 = mhpme3 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1068 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1067; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1070 = _T_1060 & _T_1068; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1072 = _T_1070 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1074 = _T_1072 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1075 = mhpme3 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[el2_dec_tlu_ctl.scala 2368:76] + wire _T_1078 = mhpme3 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[el2_dec_tlu_ctl.scala 2369:76] + wire _T_1081 = mhpme3 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[el2_dec_tlu_ctl.scala 2370:76] + wire _T_1084 = mhpme3 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[el2_dec_tlu_ctl.scala 2371:76] + wire _T_1087 = mhpme3 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[el2_dec_tlu_ctl.scala 2372:76] + wire _T_1090 = mhpme3 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[el2_dec_tlu_ctl.scala 2373:76] + wire _T_1093 = mhpme3 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[el2_dec_tlu_ctl.scala 2374:76] + wire _T_1096 = mhpme3 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[el2_dec_tlu_ctl.scala 2375:76] + wire _T_1099 = mhpme3 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[el2_dec_tlu_ctl.scala 2376:76] + wire _T_1102 = mhpme3 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[el2_dec_tlu_ctl.scala 2377:76] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[el2_dec_tlu_ctl.scala 2377:109] + wire _T_1106 = _T_1104 | _T_1105; // @[el2_dec_tlu_ctl.scala 2377:88] + wire _T_1107 = mhpme3 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2378:82] + wire _T_1110 = mhpme3 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2379:84] + wire _T_1113 = mhpme3 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2380:97] + wire _T_1116 = mhpme3 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1120 = mhpme3 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1122 = mhpme3 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1124 = mhpme3 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1126 = mhpme3 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1128 = mhpme3 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1130 = mhpme3 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 2388:85] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 2388:107] + wire _T_1134 = mhpme3 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 2389:79] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 2389:104] + wire _T_1138 = mhpme3 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1140 = mhpme3 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1142 = mhpme3 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 2392:84] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 2392:116] + wire _T_1146 = mhpme3 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1148 = mhpme3 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1150 = mhpme3 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1152 = mhpme3 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1154 = mhpme3 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1156 = mhpme3 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1158 = mhpme3 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1160 = mhpme3 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1164 = ~io_mstatus[0]; // @[el2_dec_tlu_ctl.scala 2400:60] + wire _T_1165 = mhpme3 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire [5:0] _T_1172 = io_mip & mie; // @[el2_dec_tlu_ctl.scala 2401:100] + wire [5:0] _GEN_17 = {{5'd0}, _T_1164}; // @[el2_dec_tlu_ctl.scala 2401:85] + wire [5:0] _T_1173 = _GEN_17 & _T_1172; // @[el2_dec_tlu_ctl.scala 2401:85] + wire _T_1174 = mhpme3 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[el2_dec_tlu_ctl.scala 2402:78] + wire _T_1177 = mhpme3 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 2403:81] + wire _T_1180 = mhpme3 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 2404:81] + wire _T_1183 = mhpme3 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1185 = mhpme3 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1187 = mhpme3 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1189 = mhpme3 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1191 = mhpme3 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1194 = _T_1027 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & _T_1034; // @[Mux.scala 27:72] + wire _T_1197 = _T_1035 & _T_1040; // @[Mux.scala 27:72] + wire _T_1198 = _T_1041 & _T_1045; // @[Mux.scala 27:72] + wire _T_1199 = _T_1046 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & _T_1054; // @[Mux.scala 27:72] + wire _T_1203 = _T_1055 & _T_1057; // @[Mux.scala 27:72] + wire _T_1204 = _T_1058 & _T_1060; // @[Mux.scala 27:72] + wire _T_1205 = _T_1061 & _T_1063; // @[Mux.scala 27:72] + wire _T_1206 = _T_1064 & _T_1074; // @[Mux.scala 27:72] + wire _T_1207 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1208 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1209 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1210 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1211 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1212 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1213 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1214 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1215 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1216 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1217 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1218 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1219 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1220 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1222 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1225 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1228 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1229 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1230 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1231 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1232 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1233 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1235 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1236 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1238 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1240 = _T_1165 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1241 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1242 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1243 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1244 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1245 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1246 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1247 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1025 | _T_1194; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1195; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1196; // @[Mux.scala 27:72] + wire _T_1252 = _T_1251 | _T_1197; // @[Mux.scala 27:72] + wire _T_1253 = _T_1252 | _T_1198; // @[Mux.scala 27:72] + wire _T_1254 = _T_1253 | _T_1199; // @[Mux.scala 27:72] + wire _T_1255 = _T_1254 | _T_1200; // @[Mux.scala 27:72] + wire _T_1256 = _T_1255 | _T_1201; // @[Mux.scala 27:72] + wire _T_1257 = _T_1256 | _T_1202; // @[Mux.scala 27:72] + wire _T_1258 = _T_1257 | _T_1203; // @[Mux.scala 27:72] + wire _T_1259 = _T_1258 | _T_1204; // @[Mux.scala 27:72] + wire _T_1260 = _T_1259 | _T_1205; // @[Mux.scala 27:72] + wire _T_1261 = _T_1260 | _T_1206; // @[Mux.scala 27:72] + wire _T_1262 = _T_1261 | _T_1207; // @[Mux.scala 27:72] + wire _T_1263 = _T_1262 | _T_1208; // @[Mux.scala 27:72] + wire _T_1264 = _T_1263 | _T_1209; // @[Mux.scala 27:72] + wire _T_1265 = _T_1264 | _T_1210; // @[Mux.scala 27:72] + wire _T_1266 = _T_1265 | _T_1211; // @[Mux.scala 27:72] + wire _T_1267 = _T_1266 | _T_1212; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1213; // @[Mux.scala 27:72] + wire _T_1269 = _T_1268 | _T_1214; // @[Mux.scala 27:72] + wire _T_1270 = _T_1269 | _T_1215; // @[Mux.scala 27:72] + wire _T_1271 = _T_1270 | _T_1216; // @[Mux.scala 27:72] + wire _T_1272 = _T_1271 | _T_1217; // @[Mux.scala 27:72] + wire _T_1273 = _T_1272 | _T_1218; // @[Mux.scala 27:72] + wire _T_1274 = _T_1273 | _T_1219; // @[Mux.scala 27:72] + wire _T_1275 = _T_1274 | _T_1220; // @[Mux.scala 27:72] + wire _T_1276 = _T_1275 | _T_1201; // @[Mux.scala 27:72] + wire _T_1277 = _T_1276 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1223; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1224; // @[Mux.scala 27:72] + wire _T_1280 = _T_1279 | _T_1225; // @[Mux.scala 27:72] + wire _T_1281 = _T_1280 | _T_1226; // @[Mux.scala 27:72] + wire _T_1282 = _T_1281 | _T_1227; // @[Mux.scala 27:72] + wire _T_1283 = _T_1282 | _T_1228; // @[Mux.scala 27:72] + wire _T_1284 = _T_1283 | _T_1229; // @[Mux.scala 27:72] + wire _T_1285 = _T_1284 | _T_1230; // @[Mux.scala 27:72] + wire _T_1286 = _T_1285 | _T_1231; // @[Mux.scala 27:72] + wire _T_1287 = _T_1286 | _T_1232; // @[Mux.scala 27:72] + wire _T_1288 = _T_1287 | _T_1233; // @[Mux.scala 27:72] + wire _T_1289 = _T_1288 | _T_1234; // @[Mux.scala 27:72] + wire _T_1290 = _T_1289 | _T_1235; // @[Mux.scala 27:72] + wire _T_1291 = _T_1290 | _T_1236; // @[Mux.scala 27:72] + wire _T_1292 = _T_1291 | _T_1237; // @[Mux.scala 27:72] + wire _T_1293 = _T_1292 | _T_1238; // @[Mux.scala 27:72] + wire _T_1294 = _T_1293 | _T_1239; // @[Mux.scala 27:72] + wire [5:0] _GEN_18 = {{5'd0}, _T_1294}; // @[Mux.scala 27:72] + wire [5:0] _T_1295 = _GEN_18 | _T_1240; // @[Mux.scala 27:72] + wire [5:0] _GEN_19 = {{5'd0}, _T_1241}; // @[Mux.scala 27:72] + wire [5:0] _T_1296 = _T_1295 | _GEN_19; // @[Mux.scala 27:72] + wire [5:0] _GEN_20 = {{5'd0}, _T_1242}; // @[Mux.scala 27:72] + wire [5:0] _T_1297 = _T_1296 | _GEN_20; // @[Mux.scala 27:72] + wire [5:0] _GEN_21 = {{5'd0}, _T_1243}; // @[Mux.scala 27:72] + wire [5:0] _T_1298 = _T_1297 | _GEN_21; // @[Mux.scala 27:72] + wire [5:0] _GEN_22 = {{5'd0}, _T_1244}; // @[Mux.scala 27:72] + wire [5:0] _T_1299 = _T_1298 | _GEN_22; // @[Mux.scala 27:72] + wire [5:0] _GEN_23 = {{5'd0}, _T_1245}; // @[Mux.scala 27:72] + wire [5:0] _T_1300 = _T_1299 | _GEN_23; // @[Mux.scala 27:72] + wire [5:0] _GEN_24 = {{5'd0}, _T_1246}; // @[Mux.scala 27:72] + wire [5:0] _T_1301 = _T_1300 | _GEN_24; // @[Mux.scala 27:72] + wire [5:0] _GEN_25 = {{5'd0}, _T_1247}; // @[Mux.scala 27:72] + wire [5:0] _T_1302 = _T_1301 | _GEN_25; // @[Mux.scala 27:72] + wire [5:0] _GEN_26 = {{5'd0}, _T_1248}; // @[Mux.scala 27:72] + wire [5:0] _T_1303 = _T_1302 | _GEN_26; // @[Mux.scala 27:72] + wire [5:0] _GEN_27 = {{5'd0}, _T_1024}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1305 = _GEN_27 & _T_1303; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1307 = ~mcountinhibit[4]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme4; // @[Reg.scala 27:20] + wire _T_1308 = mhpme4 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1310 = mhpme4 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1312 = mhpme4 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1314 = mhpme4 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1318 = mhpme4 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1324 = mhpme4 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1329 = mhpme4 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1331 = mhpme4 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1333 = mhpme4 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1335 = mhpme4 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1338 = mhpme4 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1341 = mhpme4 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1344 = mhpme4 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1347 = mhpme4 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1350 = mhpme4 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1351 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1350; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1353 = _T_1060 & _T_1351; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1355 = _T_1353 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1357 = _T_1355 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1358 = mhpme4 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1361 = mhpme4 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1364 = mhpme4 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1367 = mhpme4 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1370 = mhpme4 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1373 = mhpme4 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1376 = mhpme4 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1379 = mhpme4 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1382 = mhpme4 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1385 = mhpme4 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1390 = mhpme4 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1393 = mhpme4 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1396 = mhpme4 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1399 = mhpme4 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1403 = mhpme4 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1405 = mhpme4 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1407 = mhpme4 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1409 = mhpme4 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1411 = mhpme4 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1413 = mhpme4 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1417 = mhpme4 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1421 = mhpme4 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1423 = mhpme4 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1425 = mhpme4 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1429 = mhpme4 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1431 = mhpme4 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1433 = mhpme4 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1435 = mhpme4 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1437 = mhpme4 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1439 = mhpme4 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1441 = mhpme4 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1443 = mhpme4 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1448 = mhpme4 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1457 = mhpme4 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1460 = mhpme4 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1463 = mhpme4 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1466 = mhpme4 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1468 = mhpme4 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1470 = mhpme4 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1472 = mhpme4 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1474 = mhpme4 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1477 = _T_1310 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & _T_1034; // @[Mux.scala 27:72] + wire _T_1480 = _T_1318 & _T_1040; // @[Mux.scala 27:72] + wire _T_1481 = _T_1324 & _T_1045; // @[Mux.scala 27:72] + wire _T_1482 = _T_1329 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & _T_1054; // @[Mux.scala 27:72] + wire _T_1486 = _T_1338 & _T_1057; // @[Mux.scala 27:72] + wire _T_1487 = _T_1341 & _T_1060; // @[Mux.scala 27:72] + wire _T_1488 = _T_1344 & _T_1063; // @[Mux.scala 27:72] + wire _T_1489 = _T_1347 & _T_1357; // @[Mux.scala 27:72] + wire _T_1490 = _T_1358 & _T_1077; // @[Mux.scala 27:72] + wire _T_1491 = _T_1361 & _T_1080; // @[Mux.scala 27:72] + wire _T_1492 = _T_1364 & _T_1083; // @[Mux.scala 27:72] + wire _T_1493 = _T_1367 & _T_1086; // @[Mux.scala 27:72] + wire _T_1494 = _T_1370 & _T_1089; // @[Mux.scala 27:72] + wire _T_1495 = _T_1373 & _T_1092; // @[Mux.scala 27:72] + wire _T_1496 = _T_1376 & _T_1095; // @[Mux.scala 27:72] + wire _T_1497 = _T_1379 & _T_1098; // @[Mux.scala 27:72] + wire _T_1498 = _T_1382 & _T_1101; // @[Mux.scala 27:72] + wire _T_1499 = _T_1385 & _T_1106; // @[Mux.scala 27:72] + wire _T_1500 = _T_1390 & _T_1109; // @[Mux.scala 27:72] + wire _T_1501 = _T_1393 & _T_1112; // @[Mux.scala 27:72] + wire _T_1502 = _T_1396 & _T_1115; // @[Mux.scala 27:72] + wire _T_1503 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1505 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1506 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1508 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1509 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1413 & _T_1133; // @[Mux.scala 27:72] + wire _T_1511 = _T_1417 & _T_1137; // @[Mux.scala 27:72] + wire _T_1512 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1513 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1514 = _T_1425 & _T_1145; // @[Mux.scala 27:72] + wire _T_1515 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1516 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1517 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1518 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1519 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1520 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1521 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1522 = _T_1443 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1523 = _T_1448 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1524 = _T_1457 & _T_1176; // @[Mux.scala 27:72] + wire _T_1525 = _T_1460 & _T_1179; // @[Mux.scala 27:72] + wire _T_1526 = _T_1463 & _T_1182; // @[Mux.scala 27:72] + wire _T_1527 = _T_1466 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1528 = _T_1468 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1529 = _T_1470 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1530 = _T_1472 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1474 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1308 | _T_1477; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1478; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1479; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1480; // @[Mux.scala 27:72] + wire _T_1536 = _T_1535 | _T_1481; // @[Mux.scala 27:72] + wire _T_1537 = _T_1536 | _T_1482; // @[Mux.scala 27:72] + wire _T_1538 = _T_1537 | _T_1483; // @[Mux.scala 27:72] + wire _T_1539 = _T_1538 | _T_1484; // @[Mux.scala 27:72] + wire _T_1540 = _T_1539 | _T_1485; // @[Mux.scala 27:72] + wire _T_1541 = _T_1540 | _T_1486; // @[Mux.scala 27:72] + wire _T_1542 = _T_1541 | _T_1487; // @[Mux.scala 27:72] + wire _T_1543 = _T_1542 | _T_1488; // @[Mux.scala 27:72] + wire _T_1544 = _T_1543 | _T_1489; // @[Mux.scala 27:72] + wire _T_1545 = _T_1544 | _T_1490; // @[Mux.scala 27:72] + wire _T_1546 = _T_1545 | _T_1491; // @[Mux.scala 27:72] + wire _T_1547 = _T_1546 | _T_1492; // @[Mux.scala 27:72] + wire _T_1548 = _T_1547 | _T_1493; // @[Mux.scala 27:72] + wire _T_1549 = _T_1548 | _T_1494; // @[Mux.scala 27:72] + wire _T_1550 = _T_1549 | _T_1495; // @[Mux.scala 27:72] + wire _T_1551 = _T_1550 | _T_1496; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1497; // @[Mux.scala 27:72] + wire _T_1553 = _T_1552 | _T_1498; // @[Mux.scala 27:72] + wire _T_1554 = _T_1553 | _T_1499; // @[Mux.scala 27:72] + wire _T_1555 = _T_1554 | _T_1500; // @[Mux.scala 27:72] + wire _T_1556 = _T_1555 | _T_1501; // @[Mux.scala 27:72] + wire _T_1557 = _T_1556 | _T_1502; // @[Mux.scala 27:72] + wire _T_1558 = _T_1557 | _T_1503; // @[Mux.scala 27:72] + wire _T_1559 = _T_1558 | _T_1484; // @[Mux.scala 27:72] + wire _T_1560 = _T_1559 | _T_1505; // @[Mux.scala 27:72] + wire _T_1561 = _T_1560 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1507; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1508; // @[Mux.scala 27:72] + wire _T_1564 = _T_1563 | _T_1509; // @[Mux.scala 27:72] + wire _T_1565 = _T_1564 | _T_1510; // @[Mux.scala 27:72] + wire _T_1566 = _T_1565 | _T_1511; // @[Mux.scala 27:72] + wire _T_1567 = _T_1566 | _T_1512; // @[Mux.scala 27:72] + wire _T_1568 = _T_1567 | _T_1513; // @[Mux.scala 27:72] + wire _T_1569 = _T_1568 | _T_1514; // @[Mux.scala 27:72] + wire _T_1570 = _T_1569 | _T_1515; // @[Mux.scala 27:72] + wire _T_1571 = _T_1570 | _T_1516; // @[Mux.scala 27:72] + wire _T_1572 = _T_1571 | _T_1517; // @[Mux.scala 27:72] + wire _T_1573 = _T_1572 | _T_1518; // @[Mux.scala 27:72] + wire _T_1574 = _T_1573 | _T_1519; // @[Mux.scala 27:72] + wire _T_1575 = _T_1574 | _T_1520; // @[Mux.scala 27:72] + wire _T_1576 = _T_1575 | _T_1521; // @[Mux.scala 27:72] + wire _T_1577 = _T_1576 | _T_1522; // @[Mux.scala 27:72] + wire [5:0] _GEN_29 = {{5'd0}, _T_1577}; // @[Mux.scala 27:72] + wire [5:0] _T_1578 = _GEN_29 | _T_1523; // @[Mux.scala 27:72] + wire [5:0] _GEN_30 = {{5'd0}, _T_1524}; // @[Mux.scala 27:72] + wire [5:0] _T_1579 = _T_1578 | _GEN_30; // @[Mux.scala 27:72] + wire [5:0] _GEN_31 = {{5'd0}, _T_1525}; // @[Mux.scala 27:72] + wire [5:0] _T_1580 = _T_1579 | _GEN_31; // @[Mux.scala 27:72] + wire [5:0] _GEN_32 = {{5'd0}, _T_1526}; // @[Mux.scala 27:72] + wire [5:0] _T_1581 = _T_1580 | _GEN_32; // @[Mux.scala 27:72] + wire [5:0] _GEN_33 = {{5'd0}, _T_1527}; // @[Mux.scala 27:72] + wire [5:0] _T_1582 = _T_1581 | _GEN_33; // @[Mux.scala 27:72] + wire [5:0] _GEN_34 = {{5'd0}, _T_1528}; // @[Mux.scala 27:72] + wire [5:0] _T_1583 = _T_1582 | _GEN_34; // @[Mux.scala 27:72] + wire [5:0] _GEN_35 = {{5'd0}, _T_1529}; // @[Mux.scala 27:72] + wire [5:0] _T_1584 = _T_1583 | _GEN_35; // @[Mux.scala 27:72] + wire [5:0] _GEN_36 = {{5'd0}, _T_1530}; // @[Mux.scala 27:72] + wire [5:0] _T_1585 = _T_1584 | _GEN_36; // @[Mux.scala 27:72] + wire [5:0] _GEN_37 = {{5'd0}, _T_1531}; // @[Mux.scala 27:72] + wire [5:0] _T_1586 = _T_1585 | _GEN_37; // @[Mux.scala 27:72] + wire [5:0] _GEN_38 = {{5'd0}, _T_1307}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1588 = _GEN_38 & _T_1586; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1590 = ~mcountinhibit[5]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme5; // @[Reg.scala 27:20] + wire _T_1591 = mhpme5 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1593 = mhpme5 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1595 = mhpme5 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1597 = mhpme5 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1601 = mhpme5 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1607 = mhpme5 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1612 = mhpme5 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1614 = mhpme5 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1616 = mhpme5 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1618 = mhpme5 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1621 = mhpme5 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1624 = mhpme5 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1627 = mhpme5 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1630 = mhpme5 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1633 = mhpme5 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1634 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1633; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1636 = _T_1060 & _T_1634; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1638 = _T_1636 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1640 = _T_1638 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1641 = mhpme5 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1644 = mhpme5 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1647 = mhpme5 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1650 = mhpme5 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1653 = mhpme5 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1656 = mhpme5 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1659 = mhpme5 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1662 = mhpme5 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1665 = mhpme5 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1668 = mhpme5 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1673 = mhpme5 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1676 = mhpme5 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1679 = mhpme5 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1682 = mhpme5 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1686 = mhpme5 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1688 = mhpme5 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1690 = mhpme5 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1692 = mhpme5 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1694 = mhpme5 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1696 = mhpme5 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1700 = mhpme5 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1704 = mhpme5 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1706 = mhpme5 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1708 = mhpme5 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1712 = mhpme5 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1714 = mhpme5 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1716 = mhpme5 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1718 = mhpme5 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1720 = mhpme5 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1722 = mhpme5 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1724 = mhpme5 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1726 = mhpme5 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1731 = mhpme5 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1740 = mhpme5 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1743 = mhpme5 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1746 = mhpme5 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1749 = mhpme5 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1751 = mhpme5 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1753 = mhpme5 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1755 = mhpme5 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1757 = mhpme5 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1760 = _T_1593 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1761 = _T_1595 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1762 = _T_1597 & _T_1034; // @[Mux.scala 27:72] + wire _T_1763 = _T_1601 & _T_1040; // @[Mux.scala 27:72] + wire _T_1764 = _T_1607 & _T_1045; // @[Mux.scala 27:72] + wire _T_1765 = _T_1612 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1766 = _T_1614 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1767 = _T_1616 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1768 = _T_1618 & _T_1054; // @[Mux.scala 27:72] + wire _T_1769 = _T_1621 & _T_1057; // @[Mux.scala 27:72] + wire _T_1770 = _T_1624 & _T_1060; // @[Mux.scala 27:72] + wire _T_1771 = _T_1627 & _T_1063; // @[Mux.scala 27:72] + wire _T_1772 = _T_1630 & _T_1640; // @[Mux.scala 27:72] + wire _T_1773 = _T_1641 & _T_1077; // @[Mux.scala 27:72] + wire _T_1774 = _T_1644 & _T_1080; // @[Mux.scala 27:72] + wire _T_1775 = _T_1647 & _T_1083; // @[Mux.scala 27:72] + wire _T_1776 = _T_1650 & _T_1086; // @[Mux.scala 27:72] + wire _T_1777 = _T_1653 & _T_1089; // @[Mux.scala 27:72] + wire _T_1778 = _T_1656 & _T_1092; // @[Mux.scala 27:72] + wire _T_1779 = _T_1659 & _T_1095; // @[Mux.scala 27:72] + wire _T_1780 = _T_1662 & _T_1098; // @[Mux.scala 27:72] + wire _T_1781 = _T_1665 & _T_1101; // @[Mux.scala 27:72] + wire _T_1782 = _T_1668 & _T_1106; // @[Mux.scala 27:72] + wire _T_1783 = _T_1673 & _T_1109; // @[Mux.scala 27:72] + wire _T_1784 = _T_1676 & _T_1112; // @[Mux.scala 27:72] + wire _T_1785 = _T_1679 & _T_1115; // @[Mux.scala 27:72] + wire _T_1786 = _T_1682 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1788 = _T_1686 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1789 = _T_1688 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1790 = _T_1690 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1791 = _T_1692 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1792 = _T_1694 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1793 = _T_1696 & _T_1133; // @[Mux.scala 27:72] + wire _T_1794 = _T_1700 & _T_1137; // @[Mux.scala 27:72] + wire _T_1795 = _T_1704 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1796 = _T_1706 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1797 = _T_1708 & _T_1145; // @[Mux.scala 27:72] + wire _T_1798 = _T_1712 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1799 = _T_1714 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1800 = _T_1716 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1801 = _T_1718 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1802 = _T_1720 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1803 = _T_1722 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1804 = _T_1724 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1805 = _T_1726 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1806 = _T_1731 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1807 = _T_1740 & _T_1176; // @[Mux.scala 27:72] + wire _T_1808 = _T_1743 & _T_1179; // @[Mux.scala 27:72] + wire _T_1809 = _T_1746 & _T_1182; // @[Mux.scala 27:72] + wire _T_1810 = _T_1749 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1811 = _T_1751 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1812 = _T_1753 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1813 = _T_1755 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1814 = _T_1757 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1815 = _T_1591 | _T_1760; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1761; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1762; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1763; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1764; // @[Mux.scala 27:72] + wire _T_1820 = _T_1819 | _T_1765; // @[Mux.scala 27:72] + wire _T_1821 = _T_1820 | _T_1766; // @[Mux.scala 27:72] + wire _T_1822 = _T_1821 | _T_1767; // @[Mux.scala 27:72] + wire _T_1823 = _T_1822 | _T_1768; // @[Mux.scala 27:72] + wire _T_1824 = _T_1823 | _T_1769; // @[Mux.scala 27:72] + wire _T_1825 = _T_1824 | _T_1770; // @[Mux.scala 27:72] + wire _T_1826 = _T_1825 | _T_1771; // @[Mux.scala 27:72] + wire _T_1827 = _T_1826 | _T_1772; // @[Mux.scala 27:72] + wire _T_1828 = _T_1827 | _T_1773; // @[Mux.scala 27:72] + wire _T_1829 = _T_1828 | _T_1774; // @[Mux.scala 27:72] + wire _T_1830 = _T_1829 | _T_1775; // @[Mux.scala 27:72] + wire _T_1831 = _T_1830 | _T_1776; // @[Mux.scala 27:72] + wire _T_1832 = _T_1831 | _T_1777; // @[Mux.scala 27:72] + wire _T_1833 = _T_1832 | _T_1778; // @[Mux.scala 27:72] + wire _T_1834 = _T_1833 | _T_1779; // @[Mux.scala 27:72] + wire _T_1835 = _T_1834 | _T_1780; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1781; // @[Mux.scala 27:72] + wire _T_1837 = _T_1836 | _T_1782; // @[Mux.scala 27:72] + wire _T_1838 = _T_1837 | _T_1783; // @[Mux.scala 27:72] + wire _T_1839 = _T_1838 | _T_1784; // @[Mux.scala 27:72] + wire _T_1840 = _T_1839 | _T_1785; // @[Mux.scala 27:72] + wire _T_1841 = _T_1840 | _T_1786; // @[Mux.scala 27:72] + wire _T_1842 = _T_1841 | _T_1767; // @[Mux.scala 27:72] + wire _T_1843 = _T_1842 | _T_1788; // @[Mux.scala 27:72] + wire _T_1844 = _T_1843 | _T_1789; // @[Mux.scala 27:72] + wire _T_1845 = _T_1844 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1791; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1792; // @[Mux.scala 27:72] + wire _T_1848 = _T_1847 | _T_1793; // @[Mux.scala 27:72] + wire _T_1849 = _T_1848 | _T_1794; // @[Mux.scala 27:72] + wire _T_1850 = _T_1849 | _T_1795; // @[Mux.scala 27:72] + wire _T_1851 = _T_1850 | _T_1796; // @[Mux.scala 27:72] + wire _T_1852 = _T_1851 | _T_1797; // @[Mux.scala 27:72] + wire _T_1853 = _T_1852 | _T_1798; // @[Mux.scala 27:72] + wire _T_1854 = _T_1853 | _T_1799; // @[Mux.scala 27:72] + wire _T_1855 = _T_1854 | _T_1800; // @[Mux.scala 27:72] + wire _T_1856 = _T_1855 | _T_1801; // @[Mux.scala 27:72] + wire _T_1857 = _T_1856 | _T_1802; // @[Mux.scala 27:72] + wire _T_1858 = _T_1857 | _T_1803; // @[Mux.scala 27:72] + wire _T_1859 = _T_1858 | _T_1804; // @[Mux.scala 27:72] + wire _T_1860 = _T_1859 | _T_1805; // @[Mux.scala 27:72] + wire [5:0] _GEN_40 = {{5'd0}, _T_1860}; // @[Mux.scala 27:72] + wire [5:0] _T_1861 = _GEN_40 | _T_1806; // @[Mux.scala 27:72] + wire [5:0] _GEN_41 = {{5'd0}, _T_1807}; // @[Mux.scala 27:72] + wire [5:0] _T_1862 = _T_1861 | _GEN_41; // @[Mux.scala 27:72] + wire [5:0] _GEN_42 = {{5'd0}, _T_1808}; // @[Mux.scala 27:72] + wire [5:0] _T_1863 = _T_1862 | _GEN_42; // @[Mux.scala 27:72] + wire [5:0] _GEN_43 = {{5'd0}, _T_1809}; // @[Mux.scala 27:72] + wire [5:0] _T_1864 = _T_1863 | _GEN_43; // @[Mux.scala 27:72] + wire [5:0] _GEN_44 = {{5'd0}, _T_1810}; // @[Mux.scala 27:72] + wire [5:0] _T_1865 = _T_1864 | _GEN_44; // @[Mux.scala 27:72] + wire [5:0] _GEN_45 = {{5'd0}, _T_1811}; // @[Mux.scala 27:72] + wire [5:0] _T_1866 = _T_1865 | _GEN_45; // @[Mux.scala 27:72] + wire [5:0] _GEN_46 = {{5'd0}, _T_1812}; // @[Mux.scala 27:72] + wire [5:0] _T_1867 = _T_1866 | _GEN_46; // @[Mux.scala 27:72] + wire [5:0] _GEN_47 = {{5'd0}, _T_1813}; // @[Mux.scala 27:72] + wire [5:0] _T_1868 = _T_1867 | _GEN_47; // @[Mux.scala 27:72] + wire [5:0] _GEN_48 = {{5'd0}, _T_1814}; // @[Mux.scala 27:72] + wire [5:0] _T_1869 = _T_1868 | _GEN_48; // @[Mux.scala 27:72] + wire [5:0] _GEN_49 = {{5'd0}, _T_1590}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1871 = _GEN_49 & _T_1869; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1873 = ~mcountinhibit[6]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme6; // @[Reg.scala 27:20] + wire _T_1874 = mhpme6 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1876 = mhpme6 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1878 = mhpme6 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1880 = mhpme6 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1884 = mhpme6 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1890 = mhpme6 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1895 = mhpme6 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1897 = mhpme6 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1899 = mhpme6 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1901 = mhpme6 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1904 = mhpme6 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1907 = mhpme6 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1910 = mhpme6 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1913 = mhpme6 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1916 = mhpme6 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1917 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1916; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1919 = _T_1060 & _T_1917; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1921 = _T_1919 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1923 = _T_1921 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1924 = mhpme6 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1927 = mhpme6 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1930 = mhpme6 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1933 = mhpme6 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1936 = mhpme6 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1939 = mhpme6 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1942 = mhpme6 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1945 = mhpme6 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1948 = mhpme6 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1951 = mhpme6 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1956 = mhpme6 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1959 = mhpme6 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1962 = mhpme6 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1965 = mhpme6 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1969 = mhpme6 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1971 = mhpme6 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1973 = mhpme6 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1975 = mhpme6 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1977 = mhpme6 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1979 = mhpme6 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1983 = mhpme6 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1987 = mhpme6 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1989 = mhpme6 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1991 = mhpme6 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1995 = mhpme6 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1997 = mhpme6 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1999 = mhpme6 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_2001 = mhpme6 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_2003 = mhpme6 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_2005 = mhpme6 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_2007 = mhpme6 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_2009 = mhpme6 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_2014 = mhpme6 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_2023 = mhpme6 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_2026 = mhpme6 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_2029 = mhpme6 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_2032 = mhpme6 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_2034 = mhpme6 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_2036 = mhpme6 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_2038 = mhpme6 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_2040 = mhpme6 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_2043 = _T_1876 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2044 = _T_1878 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2045 = _T_1880 & _T_1034; // @[Mux.scala 27:72] + wire _T_2046 = _T_1884 & _T_1040; // @[Mux.scala 27:72] + wire _T_2047 = _T_1890 & _T_1045; // @[Mux.scala 27:72] + wire _T_2048 = _T_1895 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2049 = _T_1897 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2050 = _T_1899 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2051 = _T_1901 & _T_1054; // @[Mux.scala 27:72] + wire _T_2052 = _T_1904 & _T_1057; // @[Mux.scala 27:72] + wire _T_2053 = _T_1907 & _T_1060; // @[Mux.scala 27:72] + wire _T_2054 = _T_1910 & _T_1063; // @[Mux.scala 27:72] + wire _T_2055 = _T_1913 & _T_1923; // @[Mux.scala 27:72] + wire _T_2056 = _T_1924 & _T_1077; // @[Mux.scala 27:72] + wire _T_2057 = _T_1927 & _T_1080; // @[Mux.scala 27:72] + wire _T_2058 = _T_1930 & _T_1083; // @[Mux.scala 27:72] + wire _T_2059 = _T_1933 & _T_1086; // @[Mux.scala 27:72] + wire _T_2060 = _T_1936 & _T_1089; // @[Mux.scala 27:72] + wire _T_2061 = _T_1939 & _T_1092; // @[Mux.scala 27:72] + wire _T_2062 = _T_1942 & _T_1095; // @[Mux.scala 27:72] + wire _T_2063 = _T_1945 & _T_1098; // @[Mux.scala 27:72] + wire _T_2064 = _T_1948 & _T_1101; // @[Mux.scala 27:72] + wire _T_2065 = _T_1951 & _T_1106; // @[Mux.scala 27:72] + wire _T_2066 = _T_1956 & _T_1109; // @[Mux.scala 27:72] + wire _T_2067 = _T_1959 & _T_1112; // @[Mux.scala 27:72] + wire _T_2068 = _T_1962 & _T_1115; // @[Mux.scala 27:72] + wire _T_2069 = _T_1965 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2071 = _T_1969 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2072 = _T_1971 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2073 = _T_1973 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2074 = _T_1975 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2075 = _T_1977 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2076 = _T_1979 & _T_1133; // @[Mux.scala 27:72] + wire _T_2077 = _T_1983 & _T_1137; // @[Mux.scala 27:72] + wire _T_2078 = _T_1987 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2079 = _T_1989 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2080 = _T_1991 & _T_1145; // @[Mux.scala 27:72] + wire _T_2081 = _T_1995 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2082 = _T_1997 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2083 = _T_1999 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2084 = _T_2001 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2085 = _T_2003 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2086 = _T_2005 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2087 = _T_2007 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2088 = _T_2009 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_2089 = _T_2014 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_2090 = _T_2023 & _T_1176; // @[Mux.scala 27:72] + wire _T_2091 = _T_2026 & _T_1179; // @[Mux.scala 27:72] + wire _T_2092 = _T_2029 & _T_1182; // @[Mux.scala 27:72] + wire _T_2093 = _T_2032 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2094 = _T_2034 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2095 = _T_2036 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2096 = _T_2038 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2097 = _T_2040 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2098 = _T_1874 | _T_2043; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2044; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2045; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2046; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2047; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2048; // @[Mux.scala 27:72] + wire _T_2104 = _T_2103 | _T_2049; // @[Mux.scala 27:72] + wire _T_2105 = _T_2104 | _T_2050; // @[Mux.scala 27:72] + wire _T_2106 = _T_2105 | _T_2051; // @[Mux.scala 27:72] + wire _T_2107 = _T_2106 | _T_2052; // @[Mux.scala 27:72] + wire _T_2108 = _T_2107 | _T_2053; // @[Mux.scala 27:72] + wire _T_2109 = _T_2108 | _T_2054; // @[Mux.scala 27:72] + wire _T_2110 = _T_2109 | _T_2055; // @[Mux.scala 27:72] + wire _T_2111 = _T_2110 | _T_2056; // @[Mux.scala 27:72] + wire _T_2112 = _T_2111 | _T_2057; // @[Mux.scala 27:72] + wire _T_2113 = _T_2112 | _T_2058; // @[Mux.scala 27:72] + wire _T_2114 = _T_2113 | _T_2059; // @[Mux.scala 27:72] + wire _T_2115 = _T_2114 | _T_2060; // @[Mux.scala 27:72] + wire _T_2116 = _T_2115 | _T_2061; // @[Mux.scala 27:72] + wire _T_2117 = _T_2116 | _T_2062; // @[Mux.scala 27:72] + wire _T_2118 = _T_2117 | _T_2063; // @[Mux.scala 27:72] + wire _T_2119 = _T_2118 | _T_2064; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2065; // @[Mux.scala 27:72] + wire _T_2121 = _T_2120 | _T_2066; // @[Mux.scala 27:72] + wire _T_2122 = _T_2121 | _T_2067; // @[Mux.scala 27:72] + wire _T_2123 = _T_2122 | _T_2068; // @[Mux.scala 27:72] + wire _T_2124 = _T_2123 | _T_2069; // @[Mux.scala 27:72] + wire _T_2125 = _T_2124 | _T_2050; // @[Mux.scala 27:72] + wire _T_2126 = _T_2125 | _T_2071; // @[Mux.scala 27:72] + wire _T_2127 = _T_2126 | _T_2072; // @[Mux.scala 27:72] + wire _T_2128 = _T_2127 | _T_2073; // @[Mux.scala 27:72] + wire _T_2129 = _T_2128 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2075; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2076; // @[Mux.scala 27:72] + wire _T_2132 = _T_2131 | _T_2077; // @[Mux.scala 27:72] + wire _T_2133 = _T_2132 | _T_2078; // @[Mux.scala 27:72] + wire _T_2134 = _T_2133 | _T_2079; // @[Mux.scala 27:72] + wire _T_2135 = _T_2134 | _T_2080; // @[Mux.scala 27:72] + wire _T_2136 = _T_2135 | _T_2081; // @[Mux.scala 27:72] + wire _T_2137 = _T_2136 | _T_2082; // @[Mux.scala 27:72] + wire _T_2138 = _T_2137 | _T_2083; // @[Mux.scala 27:72] + wire _T_2139 = _T_2138 | _T_2084; // @[Mux.scala 27:72] + wire _T_2140 = _T_2139 | _T_2085; // @[Mux.scala 27:72] + wire _T_2141 = _T_2140 | _T_2086; // @[Mux.scala 27:72] + wire _T_2142 = _T_2141 | _T_2087; // @[Mux.scala 27:72] + wire _T_2143 = _T_2142 | _T_2088; // @[Mux.scala 27:72] + wire [5:0] _GEN_51 = {{5'd0}, _T_2143}; // @[Mux.scala 27:72] + wire [5:0] _T_2144 = _GEN_51 | _T_2089; // @[Mux.scala 27:72] + wire [5:0] _GEN_52 = {{5'd0}, _T_2090}; // @[Mux.scala 27:72] + wire [5:0] _T_2145 = _T_2144 | _GEN_52; // @[Mux.scala 27:72] + wire [5:0] _GEN_53 = {{5'd0}, _T_2091}; // @[Mux.scala 27:72] + wire [5:0] _T_2146 = _T_2145 | _GEN_53; // @[Mux.scala 27:72] + wire [5:0] _GEN_54 = {{5'd0}, _T_2092}; // @[Mux.scala 27:72] + wire [5:0] _T_2147 = _T_2146 | _GEN_54; // @[Mux.scala 27:72] + wire [5:0] _GEN_55 = {{5'd0}, _T_2093}; // @[Mux.scala 27:72] + wire [5:0] _T_2148 = _T_2147 | _GEN_55; // @[Mux.scala 27:72] + wire [5:0] _GEN_56 = {{5'd0}, _T_2094}; // @[Mux.scala 27:72] + wire [5:0] _T_2149 = _T_2148 | _GEN_56; // @[Mux.scala 27:72] + wire [5:0] _GEN_57 = {{5'd0}, _T_2095}; // @[Mux.scala 27:72] + wire [5:0] _T_2150 = _T_2149 | _GEN_57; // @[Mux.scala 27:72] + wire [5:0] _GEN_58 = {{5'd0}, _T_2096}; // @[Mux.scala 27:72] + wire [5:0] _T_2151 = _T_2150 | _GEN_58; // @[Mux.scala 27:72] + wire [5:0] _GEN_59 = {{5'd0}, _T_2097}; // @[Mux.scala 27:72] + wire [5:0] _T_2152 = _T_2151 | _GEN_59; // @[Mux.scala 27:72] + wire [5:0] _GEN_60 = {{5'd0}, _T_1873}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_2154 = _GEN_60 & _T_2152; // @[el2_dec_tlu_ctl.scala 2351:45] + reg mhpmc_inc_r_d1_0; // @[el2_dec_tlu_ctl.scala 2413:54] + reg mhpmc_inc_r_d1_1; // @[el2_dec_tlu_ctl.scala 2414:54] + reg mhpmc_inc_r_d1_2; // @[el2_dec_tlu_ctl.scala 2415:54] + reg mhpmc_inc_r_d1_3; // @[el2_dec_tlu_ctl.scala 2416:54] + reg perfcnt_halted_d1; // @[el2_dec_tlu_ctl.scala 2417:57] + wire perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2420:68] + wire _T_2164 = ~_T_83; // @[el2_dec_tlu_ctl.scala 2421:38] + wire [3:0] _T_2166 = _T_2164 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2173 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2166 & _T_2173; // @[el2_dec_tlu_ctl.scala 2421:87] + wire _T_2175 = ~perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2423:68] + wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[el2_dec_tlu_ctl.scala 2423:66] + wire _T_2177 = ~_T_2176; // @[el2_dec_tlu_ctl.scala 2423:46] + wire _T_2180 = ~perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2424:68] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[el2_dec_tlu_ctl.scala 2424:66] + wire _T_2182 = ~_T_2181; // @[el2_dec_tlu_ctl.scala 2424:46] + wire _T_2185 = ~perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2425:68] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[el2_dec_tlu_ctl.scala 2425:66] + wire _T_2187 = ~_T_2186; // @[el2_dec_tlu_ctl.scala 2425:46] + wire _T_2190 = ~perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2426:68] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[el2_dec_tlu_ctl.scala 2426:66] + wire _T_2192 = ~_T_2191; // @[el2_dec_tlu_ctl.scala 2426:46] + wire _T_2195 = io_dec_csr_wraddr_r == 12'hb03; // @[el2_dec_tlu_ctl.scala 2432:73] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2195; // @[el2_dec_tlu_ctl.scala 2432:44] + wire _T_2196 = ~perfcnt_halted; // @[el2_dec_tlu_ctl.scala 2433:24] + wire _T_2198 = _T_2196 | perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2433:40] + wire mhpmc_inc_r_0 = _T_1305[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2199 = |mhpmc_inc_r_0; // @[el2_dec_tlu_ctl.scala 2433:87] + wire mhpmc3_wr_en1 = _T_2198 & _T_2199; // @[el2_dec_tlu_ctl.scala 2433:67] + reg [31:0] mhpmc3h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc3; // @[el2_lib.scala 491:16] + wire [63:0] _T_2202 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2203 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2202 + _T_2203; // @[el2_dec_tlu_ctl.scala 2437:50] + wire _T_2211 = io_dec_csr_wraddr_r == 12'hb83; // @[el2_dec_tlu_ctl.scala 2442:74] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2211; // @[el2_dec_tlu_ctl.scala 2442:45] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb04; // @[el2_dec_tlu_ctl.scala 2451:73] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[el2_dec_tlu_ctl.scala 2451:44] + wire _T_2220 = _T_2196 | perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2452:40] + wire mhpmc_inc_r_1 = _T_1588[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2221 = |mhpmc_inc_r_1; // @[el2_dec_tlu_ctl.scala 2452:87] + wire mhpmc4_wr_en1 = _T_2220 & _T_2221; // @[el2_dec_tlu_ctl.scala 2452:67] + reg [31:0] mhpmc4h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc4; // @[el2_lib.scala 491:16] + wire [63:0] _T_2224 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2225 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2224 + _T_2225; // @[el2_dec_tlu_ctl.scala 2457:50] + wire _T_2234 = io_dec_csr_wraddr_r == 12'hb84; // @[el2_dec_tlu_ctl.scala 2461:74] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2234; // @[el2_dec_tlu_ctl.scala 2461:45] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb05; // @[el2_dec_tlu_ctl.scala 2470:73] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[el2_dec_tlu_ctl.scala 2470:44] + wire _T_2243 = _T_2196 | perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2471:40] + wire mhpmc_inc_r_2 = _T_1871[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2244 = |mhpmc_inc_r_2; // @[el2_dec_tlu_ctl.scala 2471:87] + wire mhpmc5_wr_en1 = _T_2243 & _T_2244; // @[el2_dec_tlu_ctl.scala 2471:67] + reg [31:0] mhpmc5h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc5; // @[el2_lib.scala 491:16] + wire [63:0] _T_2247 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2248 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2247 + _T_2248; // @[el2_dec_tlu_ctl.scala 2474:50] + wire _T_2256 = io_dec_csr_wraddr_r == 12'hb85; // @[el2_dec_tlu_ctl.scala 2479:74] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2256; // @[el2_dec_tlu_ctl.scala 2479:45] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb06; // @[el2_dec_tlu_ctl.scala 2488:73] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[el2_dec_tlu_ctl.scala 2488:44] + wire _T_2265 = _T_2196 | perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2489:40] + wire mhpmc_inc_r_3 = _T_2154[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2266 = |mhpmc_inc_r_3; // @[el2_dec_tlu_ctl.scala 2489:87] + wire mhpmc6_wr_en1 = _T_2265 & _T_2266; // @[el2_dec_tlu_ctl.scala 2489:67] + reg [31:0] mhpmc6h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc6; // @[el2_lib.scala 491:16] + wire [63:0] _T_2269 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2270 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2269 + _T_2270; // @[el2_dec_tlu_ctl.scala 2492:50] + wire _T_2278 = io_dec_csr_wraddr_r == 12'hb86; // @[el2_dec_tlu_ctl.scala 2497:74] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2278; // @[el2_dec_tlu_ctl.scala 2497:45] + wire _T_2284 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[el2_dec_tlu_ctl.scala 2508:57] + wire _T_2286 = |io_dec_csr_wrdata_r[31:10]; // @[el2_dec_tlu_ctl.scala 2508:103] + wire _T_2287 = _T_2284 | _T_2286; // @[el2_dec_tlu_ctl.scala 2508:72] + wire _T_2290 = io_dec_csr_wraddr_r == 12'h323; // @[el2_dec_tlu_ctl.scala 2510:71] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2290; // @[el2_dec_tlu_ctl.scala 2510:42] + wire _T_2294 = io_dec_csr_wraddr_r == 12'h324; // @[el2_dec_tlu_ctl.scala 2517:71] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2294; // @[el2_dec_tlu_ctl.scala 2517:42] + wire _T_2298 = io_dec_csr_wraddr_r == 12'h325; // @[el2_dec_tlu_ctl.scala 2524:71] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2298; // @[el2_dec_tlu_ctl.scala 2524:42] + wire _T_2302 = io_dec_csr_wraddr_r == 12'h326; // @[el2_dec_tlu_ctl.scala 2531:71] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2302; // @[el2_dec_tlu_ctl.scala 2531:42] + wire _T_2306 = io_dec_csr_wraddr_r == 12'h320; // @[el2_dec_tlu_ctl.scala 2548:78] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2306; // @[el2_dec_tlu_ctl.scala 2548:49] + wire _T_2318 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:52] + wire _T_2319 = _T_2318 | io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:79] + wire _T_2320 = _T_2319 | io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:105] + wire _T_2321 = _T_2320 | io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:131] + wire _T_2322 = _T_2321 | io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 2564:33] + reg _T_2325; // @[el2_dec_tlu_ctl.scala 2566:63] + wire _T_2326 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 2567:92] + wire _T_2327 = ~io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 2567:138] + wire _T_2328 = io_trigger_hit_r_d1 & _T_2327; // @[el2_dec_tlu_ctl.scala 2567:136] + reg _T_2330; // @[el2_dec_tlu_ctl.scala 2567:63] + reg _T_2332; // @[el2_dec_tlu_ctl.scala 2569:63] + wire [31:0] _T_2338 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2347 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2365 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2378 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2390 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2403 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {13'h0,_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2425 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2443 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2446 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2475 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2478 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mhartid ? _T_2338 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mstatus ? _T_2347 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mtvec ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mip ? _T_2365 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mie ? _T_2378 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mepc ? _T_2390 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mscause ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_meivt ? _T_2403 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_meihap ? _T_615 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_meicurpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_meicidpl ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_meipt ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mcgc ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_mfdc ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dcsr ? _T_2425 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_dpc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dicawics ? _T_2443 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_mtsel ? _T_2446 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mfdht ? _T_2475 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mfdhs ? _T_2478 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme3 ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpme4 ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpme5 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpme6 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mcountinhibit ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mpmc ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2499 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] + wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] + wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] + wire [31:0] _T_2565 = _T_2564 | _T_2510; // @[Mux.scala 27:72] + wire [31:0] _T_2566 = _T_2565 | _T_2511; // @[Mux.scala 27:72] + wire [31:0] _T_2567 = _T_2566 | _T_2512; // @[Mux.scala 27:72] + wire [31:0] _T_2568 = _T_2567 | _T_2513; // @[Mux.scala 27:72] + wire [31:0] _T_2569 = _T_2568 | _T_2514; // @[Mux.scala 27:72] + wire [31:0] _T_2570 = _T_2569 | _T_2515; // @[Mux.scala 27:72] + wire [31:0] _T_2571 = _T_2570 | _T_2516; // @[Mux.scala 27:72] + wire [31:0] _T_2572 = _T_2571 | _T_2517; // @[Mux.scala 27:72] + wire [31:0] _T_2573 = _T_2572 | _T_2518; // @[Mux.scala 27:72] + wire [31:0] _T_2574 = _T_2573 | _T_2519; // @[Mux.scala 27:72] + wire [31:0] _T_2575 = _T_2574 | _T_2520; // @[Mux.scala 27:72] + wire [31:0] _T_2576 = _T_2575 | _T_2521; // @[Mux.scala 27:72] + wire [31:0] _T_2577 = _T_2576 | _T_2522; // @[Mux.scala 27:72] + wire [31:0] _T_2578 = _T_2577 | _T_2523; // @[Mux.scala 27:72] + wire [31:0] _T_2579 = _T_2578 | _T_2524; // @[Mux.scala 27:72] + wire [31:0] _T_2580 = _T_2579 | _T_2525; // @[Mux.scala 27:72] + wire [31:0] _T_2581 = _T_2580 | _T_2526; // @[Mux.scala 27:72] + wire [31:0] _T_2582 = _T_2581 | _T_2527; // @[Mux.scala 27:72] + wire [31:0] _T_2583 = _T_2582 | _T_2528; // @[Mux.scala 27:72] + wire [31:0] _T_2584 = _T_2583 | _T_2529; // @[Mux.scala 27:72] + wire [31:0] _T_2585 = _T_2584 | _T_2530; // @[Mux.scala 27:72] + wire [31:0] _T_2586 = _T_2585 | _T_2531; // @[Mux.scala 27:72] + wire [31:0] _T_2587 = _T_2586 | _T_2532; // @[Mux.scala 27:72] + wire [31:0] _T_2588 = _T_2587 | _T_2533; // @[Mux.scala 27:72] + wire [31:0] _T_2589 = _T_2588 | _T_2534; // @[Mux.scala 27:72] + wire [31:0] _T_2590 = _T_2589 | _T_2535; // @[Mux.scala 27:72] + wire [31:0] _T_2591 = _T_2590 | _T_2536; // @[Mux.scala 27:72] + wire [31:0] _T_2592 = _T_2591 | _T_2537; // @[Mux.scala 27:72] + wire [31:0] _T_2593 = _T_2592 | _T_2538; // @[Mux.scala 27:72] + wire [31:0] _T_2594 = _T_2593 | _T_2539; // @[Mux.scala 27:72] + wire [31:0] _T_2595 = _T_2594 | _T_2540; // @[Mux.scala 27:72] + wire [31:0] _T_2596 = _T_2595 | _T_2541; // @[Mux.scala 27:72] + wire [31:0] _T_2597 = _T_2596 | _T_2542; // @[Mux.scala 27:72] + wire [31:0] _T_2598 = _T_2597 | _T_2543; // @[Mux.scala 27:72] + wire [31:0] _T_2599 = _T_2598 | _T_2544; // @[Mux.scala 27:72] + wire [31:0] _T_2600 = _T_2599 | _T_2545; // @[Mux.scala 27:72] + wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] + wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] + wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] + wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_31_io_l1clk), + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en), + .io_scan_mode(rvclkhdr_31_io_scan_mode) + ); + rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_32_io_l1clk), + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en), + .io_scan_mode(rvclkhdr_32_io_scan_mode) + ); + rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_33_io_l1clk), + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en), + .io_scan_mode(rvclkhdr_33_io_scan_mode) + ); + rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_34_io_l1clk), + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en), + .io_scan_mode(rvclkhdr_34_io_scan_mode) + ); + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_762,dicad0[31:0]}; // @[el2_dec_tlu_ctl.scala 2232:65] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[el2_dec_tlu_ctl.scala 2235:42] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_0_match_ = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_1_match_ = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_2_match_ = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_3_match_ = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_dec_tlu_int_valid_wb1 = _T_2332; // @[el2_dec_tlu_ctl.scala 2569:31] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2330; // @[el2_dec_tlu_ctl.scala 2567:31] + assign io_dec_tlu_i0_valid_wb1 = _T_2325; // @[el2_dec_tlu_ctl.scala 2566:31] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2177; // @[el2_dec_tlu_ctl.scala 2423:23] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2182; // @[el2_dec_tlu_ctl.scala 2424:23] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2187; // @[el2_dec_tlu_ctl.scala 2425:23] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2192; // @[el2_dec_tlu_ctl.scala 2426:23] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[el2_dec_tlu_ctl.scala 1797:32] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[el2_dec_tlu_ctl.scala 1798:32] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[el2_dec_tlu_ctl.scala 1799:32] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[el2_dec_tlu_ctl.scala 1800:32] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[el2_dec_tlu_ctl.scala 1801:32] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[el2_dec_tlu_ctl.scala 1802:32] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[el2_dec_tlu_ctl.scala 1803:32] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[el2_dec_tlu_ctl.scala 1804:32] + assign io_dec_csr_rddata_d = _T_2608 | _T_2554; // @[el2_dec_tlu_ctl.scala 2576:22] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[el2_dec_tlu_ctl.scala 1847:40] + assign io_dec_tlu_wr_pause_r = _T_368 & _T_369; // @[el2_dec_tlu_ctl.scala 1856:25] + assign io_dec_tlu_meipt = meipt; // @[el2_dec_tlu_ctl.scala 2083:20] + assign io_dec_tlu_meicurpl = meicurpl; // @[el2_dec_tlu_ctl.scala 2047:23] + assign io_dec_tlu_meihap = _T_615[29:0]; // @[el2_dec_tlu_ctl.scala 2033:21] + assign io_dec_tlu_mrac_ff = mrac; // @[el2_dec_tlu_ctl.scala 1886:22] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[el2_dec_tlu_ctl.scala 1846:40] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[el2_dec_tlu_ctl.scala 1845:40] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[el2_dec_tlu_ctl.scala 1844:40] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[el2_dec_tlu_ctl.scala 1843:40] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[el2_dec_tlu_ctl.scala 1842:40] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[el2_dec_tlu_ctl.scala 1841:40] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[el2_dec_tlu_ctl.scala 1530:24] + assign io_fw_halt_req = _T_500 & _T_501; // @[el2_dec_tlu_ctl.scala 1921:18] + assign io_mstatus = _T_54; // @[el2_dec_tlu_ctl.scala 1546:14] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_52; // @[el2_dec_tlu_ctl.scala 1545:21] + assign io_dcsr = _T_700; // @[el2_dec_tlu_ctl.scala 2130:11] + assign io_mtvec = _T_60; // @[el2_dec_tlu_ctl.scala 1558:12] + assign io_mip = _T_66; // @[el2_dec_tlu_ctl.scala 1573:10] + assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[el2_dec_tlu_ctl.scala 1587:13] + assign io_npc_r = _T_159 | _T_157; // @[el2_dec_tlu_ctl.scala 1681:12] + assign io_npc_r_d1 = _T_165; // @[el2_dec_tlu_ctl.scala 1687:15] + assign io_mepc = _T_194; // @[el2_dec_tlu_ctl.scala 1706:11] + assign io_mdseac_locked_ns = mdseac_en | _T_487; // @[el2_dec_tlu_ctl.scala 1904:23] + assign io_force_halt = mfdht[0] & _T_607; // @[el2_dec_tlu_ctl.scala 2010:17] + assign io_dpc = _T_725; // @[el2_dec_tlu_ctl.scala 2147:10] + assign io_mtdata1_t_0 = _T_871; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_1 = _T_872; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_2 = _T_873; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_3 = _T_874; // @[el2_dec_tlu_ctl.scala 2303:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_56; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_137; // @[el2_lib.scala 488:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_6_io_en = _T_162 | io_reset_delayed; // @[el2_lib.scala 488:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_7_io_en = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_323; // @[el2_lib.scala 488:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_335; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_372; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = _T_491 & _T_492; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = _T_547 | io_iccm_dma_sb_error; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_610; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = _T_631 | io_take_ext_int_start; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = _T_697 | io_take_nmi; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = _T_722 | dpc_capture_npc; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_19_io_en = _T_662 & _T_732; // @[el2_lib.scala 488:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 488:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 488:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_22_io_en = _T_970 & _T_806; // @[el2_lib.scala 488:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_23_io_en = _T_979 & _T_815; // @[el2_lib.scala 488:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_24_io_en = _T_988 & _T_824; // @[el2_lib.scala 488:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_25_io_en = _T_997 & _T_833; // @[el2_lib.scala 488:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_34_io_en = _T_2322 | io_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mpmc_b = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_54 = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + _T_60 = _RAND_2[30:0]; + _RAND_3 = {1{`RANDOM}}; + mdccmect = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + miccmect = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + micect = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[5:0]; + _RAND_7 = {1{`RANDOM}}; + mie = _RAND_7[5:0]; + _RAND_8 = {1{`RANDOM}}; + temp_ncount6_2 = _RAND_8[4:0]; + _RAND_9 = {1{`RANDOM}}; + temp_ncount0 = _RAND_9[0:0]; + _RAND_10 = {2{`RANDOM}}; + _T_95 = _RAND_10[32:0]; + _RAND_11 = {1{`RANDOM}}; + mcyclel_cout_f = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + mcycleh = _RAND_12[31:0]; + _RAND_13 = {2{`RANDOM}}; + _T_122 = _RAND_13[32:0]; + _RAND_14 = {1{`RANDOM}}; + minstret_enable_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + minstretl_cout_f = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + minstreth = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + mscratch = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + _T_165 = _RAND_18[30:0]; + _RAND_19 = {1{`RANDOM}}; + pc_r_d1 = _RAND_19[30:0]; + _RAND_20 = {1{`RANDOM}}; + _T_194 = _RAND_20[30:0]; + _RAND_21 = {1{`RANDOM}}; + mcause = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + mscause = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + mtval = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + mcgc = _RAND_24[8:0]; + _RAND_25 = {1{`RANDOM}}; + mfdc_int = _RAND_25[14:0]; + _RAND_26 = {1{`RANDOM}}; + mrac = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + mdseac = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + mfdht = _RAND_28[5:0]; + _RAND_29 = {1{`RANDOM}}; + mfdhs = _RAND_29[1:0]; + _RAND_30 = {1{`RANDOM}}; + force_halt_ctr_f = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + meivt = _RAND_31[21:0]; + _RAND_32 = {1{`RANDOM}}; + meihap = _RAND_32[7:0]; + _RAND_33 = {1{`RANDOM}}; + meicurpl = _RAND_33[3:0]; + _RAND_34 = {1{`RANDOM}}; + meicidpl = _RAND_34[3:0]; + _RAND_35 = {1{`RANDOM}}; + meipt = _RAND_35[3:0]; + _RAND_36 = {1{`RANDOM}}; + _T_700 = _RAND_36[15:0]; + _RAND_37 = {1{`RANDOM}}; + _T_725 = _RAND_37[30:0]; + _RAND_38 = {1{`RANDOM}}; + dicawics = _RAND_38[16:0]; + _RAND_39 = {3{`RANDOM}}; + dicad0 = _RAND_39[70:0]; + _RAND_40 = {1{`RANDOM}}; + dicad0h = _RAND_40[31:0]; + _RAND_41 = {1{`RANDOM}}; + _T_757 = _RAND_41[31:0]; + _RAND_42 = {1{`RANDOM}}; + icache_rd_valid_f = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + icache_wr_valid_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + mtsel = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + _T_871 = _RAND_45[9:0]; + _RAND_46 = {1{`RANDOM}}; + _T_872 = _RAND_46[9:0]; + _RAND_47 = {1{`RANDOM}}; + _T_873 = _RAND_47[9:0]; + _RAND_48 = {1{`RANDOM}}; + _T_874 = _RAND_48[9:0]; + _RAND_49 = {1{`RANDOM}}; + mtdata2_t_0 = _RAND_49[31:0]; + _RAND_50 = {1{`RANDOM}}; + mtdata2_t_1 = _RAND_50[31:0]; + _RAND_51 = {1{`RANDOM}}; + mtdata2_t_2 = _RAND_51[31:0]; + _RAND_52 = {1{`RANDOM}}; + mtdata2_t_3 = _RAND_52[31:0]; + _RAND_53 = {1{`RANDOM}}; + mhpme3 = _RAND_53[9:0]; + _RAND_54 = {1{`RANDOM}}; + mhpme4 = _RAND_54[9:0]; + _RAND_55 = {1{`RANDOM}}; + mhpme5 = _RAND_55[9:0]; + _RAND_56 = {1{`RANDOM}}; + mhpme6 = _RAND_56[9:0]; + _RAND_57 = {1{`RANDOM}}; + mhpmc_inc_r_d1_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mhpmc_inc_r_d1_1 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mhpmc_inc_r_d1_2 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + mhpmc_inc_r_d1_3 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + perfcnt_halted_d1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + mhpmc3h = _RAND_62[31:0]; + _RAND_63 = {1{`RANDOM}}; + mhpmc3 = _RAND_63[31:0]; + _RAND_64 = {1{`RANDOM}}; + mhpmc4h = _RAND_64[31:0]; + _RAND_65 = {1{`RANDOM}}; + mhpmc4 = _RAND_65[31:0]; + _RAND_66 = {1{`RANDOM}}; + mhpmc5h = _RAND_66[31:0]; + _RAND_67 = {1{`RANDOM}}; + mhpmc5 = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + mhpmc6h = _RAND_68[31:0]; + _RAND_69 = {1{`RANDOM}}; + mhpmc6 = _RAND_69[31:0]; + _RAND_70 = {1{`RANDOM}}; + _T_2325 = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + _T_2330 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + _T_2332 = _RAND_72[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mpmc_b = 1'h0; + end + if (reset) begin + _T_54 = 2'h0; + end + if (reset) begin + _T_60 = 31'h0; + end + if (reset) begin + mdccmect = 32'h0; + end + if (reset) begin + miccmect = 32'h0; + end + if (reset) begin + micect = 32'h0; + end + if (reset) begin + _T_66 = 6'h0; + end + if (reset) begin + mie = 6'h0; + end + if (reset) begin + temp_ncount6_2 = 5'h0; + end + if (reset) begin + temp_ncount0 = 1'h0; + end + if (reset) begin + _T_95 = 33'h0; + end + if (reset) begin + mcyclel_cout_f = 1'h0; + end + if (reset) begin + mcycleh = 32'h0; + end + if (reset) begin + _T_122 = 33'h0; + end + if (reset) begin + minstret_enable_f = 1'h0; + end + if (reset) begin + minstretl_cout_f = 1'h0; + end + if (reset) begin + minstreth = 32'h0; + end + if (reset) begin + mscratch = 32'h0; + end + if (reset) begin + _T_165 = 31'h0; + end + if (reset) begin + pc_r_d1 = 31'h0; + end + if (reset) begin + _T_194 = 31'h0; + end + if (reset) begin + mcause = 32'h0; + end + if (reset) begin + mscause = 4'h0; + end + if (reset) begin + mtval = 32'h0; + end + if (reset) begin + mcgc = 9'h0; + end + if (reset) begin + mfdc_int = 15'h0; + end + if (reset) begin + mrac = 32'h0; + end + if (reset) begin + mdseac = 32'h0; + end + if (reset) begin + mfdht = 6'h0; + end + if (reset) begin + mfdhs = 2'h0; + end + if (reset) begin + force_halt_ctr_f = 32'h0; + end + if (reset) begin + meivt = 22'h0; + end + if (reset) begin + meihap = 8'h0; + end + if (reset) begin + meicurpl = 4'h0; + end + if (reset) begin + meicidpl = 4'h0; + end + if (reset) begin + meipt = 4'h0; + end + if (reset) begin + _T_700 = 16'h0; + end + if (reset) begin + _T_725 = 31'h0; + end + if (reset) begin + dicawics = 17'h0; + end + if (reset) begin + dicad0 = 71'h0; + end + if (reset) begin + dicad0h = 32'h0; + end + if (reset) begin + _T_757 = 32'h0; + end + if (reset) begin + icache_rd_valid_f = 1'h0; + end + if (reset) begin + icache_wr_valid_f = 1'h0; + end + if (reset) begin + mtsel = 2'h0; + end + if (reset) begin + _T_871 = 10'h0; + end + if (reset) begin + _T_872 = 10'h0; + end + if (reset) begin + _T_873 = 10'h0; + end + if (reset) begin + _T_874 = 10'h0; + end + if (reset) begin + mtdata2_t_0 = 32'h0; + end + if (reset) begin + mtdata2_t_1 = 32'h0; + end + if (reset) begin + mtdata2_t_2 = 32'h0; + end + if (reset) begin + mtdata2_t_3 = 32'h0; + end + if (reset) begin + mhpme3 = 10'h0; + end + if (reset) begin + mhpme4 = 10'h0; + end + if (reset) begin + mhpme5 = 10'h0; + end + if (reset) begin + mhpme6 = 10'h0; + end + if (reset) begin + mhpmc_inc_r_d1_0 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_1 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_2 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_3 = 1'h0; + end + if (reset) begin + perfcnt_halted_d1 = 1'h0; + end + if (reset) begin + mhpmc3h = 32'h0; + end + if (reset) begin + mhpmc3 = 32'h0; + end + if (reset) begin + mhpmc4h = 32'h0; + end + if (reset) begin + mhpmc4 = 32'h0; + end + if (reset) begin + mhpmc5h = 32'h0; + end + if (reset) begin + mhpmc5 = 32'h0; + end + if (reset) begin + mhpmc6h = 32'h0; + end + if (reset) begin + mhpmc6 = 32'h0; + end + if (reset) begin + _T_2325 = 1'h0; + end + if (reset) begin + _T_2330 = 1'h0; + end + if (reset) begin + _T_2332 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mpmc_b <= 1'h0; + end else if (wr_mpmc_r) begin + mpmc_b <= _T_507; + end else begin + mpmc_b <= _T_508; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_54 <= 2'h0; + end else begin + _T_54 <= _T_46 | _T_42; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_60 <= 31'h0; + end else begin + _T_60 <= {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + mdccmect <= 32'h0; + end else if (wr_mdccmect_r) begin + mdccmect <= _T_523; + end else begin + mdccmect <= _T_567; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + miccmect <= 32'h0; + end else if (wr_miccmect_r) begin + miccmect <= _T_523; + end else begin + miccmect <= _T_546; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + micect <= 32'h0; + end else if (wr_micect_r) begin + micect <= _T_523; + end else begin + micect <= _T_525; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 6'h0; + end else begin + _T_66 <= {_T_65,_T_63}; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mie <= 6'h0; + end else begin + mie <= io_mie_ns; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount6_2 <= 5'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount0 <= 1'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount0 <= io_dec_csr_wrdata_r[0]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_95 <= 33'h0; + end else if (wr_mcyclel_r) begin + _T_95 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_95 <= mcyclel_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mcyclel_cout_f <= 1'h0; + end else begin + mcyclel_cout_f <= mcyclel_cout & _T_96; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mcycleh <= 32'h0; + end else if (wr_mcycleh_r) begin + mcycleh <= io_dec_csr_wrdata_r; + end else begin + mcycleh <= mcycleh_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + _T_122 <= 33'h0; + end else if (wr_minstretl_r) begin + _T_122 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_122 <= minstretl_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstret_enable_f <= 1'h0; + end else begin + minstret_enable_f <= i0_valid_no_ebreak_ecall_r | wr_minstretl_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstretl_cout_f <= 1'h0; + end else begin + minstretl_cout_f <= minstretl_cout & _T_123; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + minstreth <= 32'h0; + end else if (wr_minstreth_r) begin + minstreth <= io_dec_csr_wrdata_r; + end else begin + minstreth <= minstreth_inc; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + mscratch <= 32'h0; + end else begin + mscratch <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + _T_165 <= 31'h0; + end else begin + _T_165 <= io_npc_r; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else begin + pc_r_d1 <= _T_169 | _T_170; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + _T_194 <= 31'h0; + end else begin + _T_194 <= _T_192 | _T_190; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mcause <= 32'h0; + end else begin + mcause <= _T_232 | _T_228; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mscause <= 4'h0; + end else begin + mscause <= _T_262 | _T_261; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mtval <= 32'h0; + end else begin + mtval <= _T_319 | _T_315; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + mcgc <= 9'h0; + end else begin + mcgc <= io_dec_csr_wrdata_r[8:0]; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + mfdc_int <= 15'h0; + end else begin + mfdc_int <= {_T_345,_T_344}; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + mrac <= 32'h0; + end else begin + mrac <= {_T_482,_T_467}; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + mdseac <= 32'h0; + end else begin + mdseac <= io_lsu_imprecise_error_addr_any; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdht <= 6'h0; + end else if (wr_mfdht_r) begin + mfdht <= io_dec_csr_wrdata_r[5:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdhs <= 2'h0; + end else if (_T_593) begin + if (wr_mfdhs_r) begin + mfdhs <= io_dec_csr_wrdata_r[1:0]; + end else if (_T_587) begin + mfdhs <= _T_591; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + force_halt_ctr_f <= 32'h0; + end else if (mfdht[0]) begin + if (io_debug_halt_req_f) begin + force_halt_ctr_f <= _T_598; + end else if (io_dbg_tlu_halted_f) begin + force_halt_ctr_f <= 32'h0; + end + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + meivt <= 22'h0; + end else begin + meivt <= io_dec_csr_wrdata_r[31:10]; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + meihap <= 8'h0; + end else begin + meihap <= io_pic_claimid; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meicurpl <= 4'h0; + end else if (wr_meicurpl_r) begin + meicurpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + meicidpl <= 4'h0; + end else if (wr_meicpct_r) begin + meicidpl <= io_pic_pl; + end else if (wr_meicidpl_r) begin + meicidpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + meipt <= 4'h0; + end else if (wr_meipt_r) begin + meipt <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + _T_700 <= 16'h0; + end else if (enter_debug_halt_req_le) begin + _T_700 <= _T_674; + end else if (wr_dcsr_r) begin + _T_700 <= _T_689; + end else begin + _T_700 <= _T_694; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + _T_725 <= 31'h0; + end else begin + _T_725 <= _T_720 | _T_719; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + dicawics <= 17'h0; + end else begin + dicawics <= {_T_729,io_dec_csr_wrdata_r[16:3]}; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + dicad0 <= 71'h0; + end else if (wr_dicad0_r) begin + dicad0 <= {{39'd0}, io_dec_csr_wrdata_r}; + end else begin + dicad0 <= io_ifu_ic_debug_rd_data; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + dicad0h <= 32'h0; + end else if (wr_dicad0h_r) begin + dicad0h <= io_dec_csr_wrdata_r; + end else begin + dicad0h <= io_ifu_ic_debug_rd_data[63:32]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_757 <= 32'h0; + end else if (_T_755) begin + if (_T_751) begin + _T_757 <= io_dec_csr_wrdata_r; + end else begin + _T_757 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_rd_valid_f <= 1'h0; + end else begin + icache_rd_valid_f <= _T_767 & _T_769; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_wr_valid_f <= 1'h0; + end else begin + icache_wr_valid_f <= _T_662 & _T_772; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mtsel <= 2'h0; + end else if (wr_mtsel_r) begin + mtsel <= io_dec_csr_wrdata_r[1:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_871 <= 10'h0; + end else if (wr_mtdata1_t_r_0) begin + _T_871 <= tdata_wrdata_r; + end else begin + _T_871 <= _T_842; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_872 <= 10'h0; + end else if (wr_mtdata1_t_r_1) begin + _T_872 <= tdata_wrdata_r; + end else begin + _T_872 <= _T_851; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_873 <= 10'h0; + end else if (wr_mtdata1_t_r_2) begin + _T_873 <= tdata_wrdata_r; + end else begin + _T_873 <= _T_860; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_874 <= 10'h0; + end else if (wr_mtdata1_t_r_3) begin + _T_874 <= tdata_wrdata_r; + end else begin + _T_874 <= _T_869; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_0 <= 32'h0; + end else begin + mtdata2_t_0 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_1 <= 32'h0; + end else begin + mtdata2_t_1 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_2 <= 32'h0; + end else begin + mtdata2_t_2 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_3 <= 32'h0; + end else begin + mtdata2_t_3 <= io_dec_csr_wrdata_r; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme3 <= 10'h0; + end else if (wr_mhpme3_r) begin + if (_T_2287) begin + mhpme3 <= 10'h204; + end else begin + mhpme3 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme4 <= 10'h0; + end else if (wr_mhpme4_r) begin + if (_T_2287) begin + mhpme4 <= 10'h204; + end else begin + mhpme4 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme5 <= 10'h0; + end else if (wr_mhpme5_r) begin + if (_T_2287) begin + mhpme5 <= 10'h204; + end else begin + mhpme5 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme6 <= 10'h0; + end else if (wr_mhpme6_r) begin + if (_T_2287) begin + mhpme6 <= 10'h204; + end else begin + mhpme6 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_0 <= 1'h0; + end else begin + mhpmc_inc_r_d1_0 <= _T_1305[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_1 <= 1'h0; + end else begin + mhpmc_inc_r_d1_1 <= _T_1588[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_2 <= 1'h0; + end else begin + mhpmc_inc_r_d1_2 <= _T_1871[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_3 <= 1'h0; + end else begin + mhpmc_inc_r_d1_3 <= _T_2154[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + perfcnt_halted_d1 <= 1'h0; + end else begin + perfcnt_halted_d1 <= _T_83 | io_dec_tlu_pmu_fw_halted; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3h <= 32'h0; + end else if (mhpmc3h_wr_en0) begin + mhpmc3h <= io_dec_csr_wrdata_r; + end else begin + mhpmc3h <= mhpmc3_incr[63:32]; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3 <= 32'h0; + end else if (mhpmc3_wr_en0) begin + mhpmc3 <= io_dec_csr_wrdata_r; + end else begin + mhpmc3 <= mhpmc3_incr[31:0]; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4h <= 32'h0; + end else if (mhpmc4h_wr_en0) begin + mhpmc4h <= io_dec_csr_wrdata_r; + end else begin + mhpmc4h <= mhpmc4_incr[63:32]; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4 <= 32'h0; + end else if (mhpmc4_wr_en0) begin + mhpmc4 <= io_dec_csr_wrdata_r; + end else begin + mhpmc4 <= mhpmc4_incr[31:0]; + end + end + always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5h <= 32'h0; + end else if (mhpmc5h_wr_en0) begin + mhpmc5h <= io_dec_csr_wrdata_r; + end else begin + mhpmc5h <= mhpmc5_incr[63:32]; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5 <= 32'h0; + end else if (mhpmc5_wr_en0) begin + mhpmc5 <= io_dec_csr_wrdata_r; + end else begin + mhpmc5 <= mhpmc5_incr[31:0]; + end + end + always @(posedge rvclkhdr_33_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6h <= 32'h0; + end else if (mhpmc6h_wr_en0) begin + mhpmc6h <= io_dec_csr_wrdata_r; + end else begin + mhpmc6h <= mhpmc6_incr[63:32]; + end + end + always @(posedge rvclkhdr_32_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6 <= 32'h0; + end else if (mhpmc6_wr_en0) begin + mhpmc6 <= io_dec_csr_wrdata_r; + end else begin + mhpmc6 <= mhpmc6_incr[31:0]; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2325 <= 1'h0; + end else begin + _T_2325 <= io_i0_valid_wb; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2330 <= 1'h0; + end else begin + _T_2330 <= _T_2326 | _T_2328; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2332 <= 1'h0; + end else begin + _T_2332 <= io_interrupt_valid_r_d1; + end + end +endmodule +module el2_dec_decode_csr_read( + input [11:0] io_dec_csr_rdaddr_d, + output io_csr_pkt_csr_misa, + output io_csr_pkt_csr_mvendorid, + output io_csr_pkt_csr_marchid, + output io_csr_pkt_csr_mimpid, + output io_csr_pkt_csr_mhartid, + output io_csr_pkt_csr_mstatus, + output io_csr_pkt_csr_mtvec, + output io_csr_pkt_csr_mip, + output io_csr_pkt_csr_mie, + output io_csr_pkt_csr_mcyclel, + output io_csr_pkt_csr_mcycleh, + output io_csr_pkt_csr_minstretl, + output io_csr_pkt_csr_minstreth, + output io_csr_pkt_csr_mscratch, + output io_csr_pkt_csr_mepc, + output io_csr_pkt_csr_mcause, + output io_csr_pkt_csr_mscause, + output io_csr_pkt_csr_mtval, + output io_csr_pkt_csr_mrac, + output io_csr_pkt_csr_dmst, + output io_csr_pkt_csr_mdseac, + output io_csr_pkt_csr_meihap, + output io_csr_pkt_csr_meivt, + output io_csr_pkt_csr_meipt, + output io_csr_pkt_csr_meicurpl, + output io_csr_pkt_csr_meicidpl, + output io_csr_pkt_csr_dcsr, + output io_csr_pkt_csr_mcgc, + output io_csr_pkt_csr_mfdc, + output io_csr_pkt_csr_dpc, + output io_csr_pkt_csr_mtsel, + output io_csr_pkt_csr_mtdata1, + output io_csr_pkt_csr_mtdata2, + output io_csr_pkt_csr_mhpmc3, + output io_csr_pkt_csr_mhpmc4, + output io_csr_pkt_csr_mhpmc5, + output io_csr_pkt_csr_mhpmc6, + output io_csr_pkt_csr_mhpmc3h, + output io_csr_pkt_csr_mhpmc4h, + output io_csr_pkt_csr_mhpmc5h, + output io_csr_pkt_csr_mhpmc6h, + output io_csr_pkt_csr_mhpme3, + output io_csr_pkt_csr_mhpme4, + output io_csr_pkt_csr_mhpme5, + output io_csr_pkt_csr_mhpme6, + output io_csr_pkt_csr_mcountinhibit, + output io_csr_pkt_csr_mitctl0, + output io_csr_pkt_csr_mitctl1, + output io_csr_pkt_csr_mitb0, + output io_csr_pkt_csr_mitb1, + output io_csr_pkt_csr_mitcnt0, + output io_csr_pkt_csr_mitcnt1, + output io_csr_pkt_csr_mpmc, + output io_csr_pkt_csr_meicpct, + output io_csr_pkt_csr_micect, + output io_csr_pkt_csr_miccmect, + output io_csr_pkt_csr_mdccmect, + output io_csr_pkt_csr_mfdht, + output io_csr_pkt_csr_mfdhs, + output io_csr_pkt_csr_dicawics, + output io_csr_pkt_csr_dicad0h, + output io_csr_pkt_csr_dicad0, + output io_csr_pkt_csr_dicad1, + output io_csr_pkt_csr_dicago, + output io_csr_pkt_presync, + output io_csr_pkt_postsync, + output io_csr_pkt_legal +); + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_9 = _T_1 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_10 = _T_9 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_11 = _T_10 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_20 = _T_19 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:159] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_102 = _T_101 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_103 = _T_102 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_104 = _T_103 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_120 = _T_119 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_121 = _T_120 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_122 = _T_121 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_123 = _T_122 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_138 = _T_15 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_139 = _T_138 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_140 = _T_139 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_141 = _T_140 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_157 = _T_156 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_158 = _T_157 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_159 = _T_158 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_172 = _T_75 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_173 = _T_172 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_182 = _T_75 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_218 = _T_217 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_219 = _T_218 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_220 = _T_219 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_231 = _T_230 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_241 = _T_240 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_260 = _T_259 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_261 = _T_260 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_269 = _T_268 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_310 = _T_300 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_331 = _T_330 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_332 = _T_331 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_382 = _T_381 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_397 = _T_103 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_411 = _T_15 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_412 = _T_411 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_413 = _T_412 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_427 = _T_426 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_428 = _T_427 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_444 = _T_119 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_445 = _T_444 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_447 = _T_446 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_461 = _T_460 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_491 = _T_490 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_492 = _T_491 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_493 = _T_492 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_506 = _T_505 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_508 = _T_507 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_553 = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_564 = _T_563 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_585 = _T_563 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_615 = _T_614 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_625 = _T_624 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_668 = _T_196 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_669 = _T_668 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_716 = _T_1 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_718 = _T_717 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_719 = _T_718 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_738 = _T_737 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_748 = _T_726 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_787 = _T_311 | _T_553; // @[el2_dec_tlu_ctl.scala 2716:73] + wire _T_799 = _T_3 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_800 = _T_799 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_801 = _T_800 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_802 = _T_801 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_804 = _T_787 | _T_803; // @[el2_dec_tlu_ctl.scala 2716:113] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_814 = _T_813 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_816 = _T_815 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_817 = _T_804 | _T_816; // @[el2_dec_tlu_ctl.scala 2716:147] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_829 = _T_828 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_830 = _T_817 | _T_829; // @[el2_dec_tlu_ctl.scala 2717:41] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_842 = _T_841 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_843 = _T_842 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_844 = _T_843 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_869 = _T_311 | _T_70; // @[el2_dec_tlu_ctl.scala 2718:73] + wire _T_879 = _T_869 | _T_183; // @[el2_dec_tlu_ctl.scala 2718:113] + wire _T_889 = _T_879 | _T_342; // @[el2_dec_tlu_ctl.scala 2718:154] + wire _T_904 = _T_1 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_905 = _T_904 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_906 = _T_905 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_907 = _T_906 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_908 = _T_907 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_909 = _T_908 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_910 = _T_889 | _T_909; // @[el2_dec_tlu_ctl.scala 2719:41] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_923 = _T_922 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_924 = _T_923 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_925 = _T_924 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_926 = _T_910 | _T_925; // @[el2_dec_tlu_ctl.scala 2719:81] + wire _T_937 = _T_231 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_961 = _T_960 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_962 = _T_961 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_964 = _T_963 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_983 = _T_1 & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_986 = _T_985 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_987 = _T_986 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_988 = _T_987 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_989 = _T_988 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_990 = _T_989 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_991 = _T_990 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_992 = _T_964 | _T_991; // @[el2_dec_tlu_ctl.scala 2721:73] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1014 = _T_1013 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1015 = _T_1014 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1016 = _T_992 | _T_1015; // @[el2_dec_tlu_ctl.scala 2721:121] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1036 = _T_1035 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1037 = _T_1036 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1038 = _T_1037 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1039 = _T_1038 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1040 = _T_1039 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1041 = _T_1016 | _T_1040; // @[el2_dec_tlu_ctl.scala 2722:57] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1056 = _T_1055 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1057 = _T_1056 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1058 = _T_1057 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1059 = _T_1041 | _T_1058; // @[el2_dec_tlu_ctl.scala 2722:105] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1084 = _T_1059 | _T_1083; // @[el2_dec_tlu_ctl.scala 2723:65] + wire _T_1105 = _T_1079 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1106 = _T_1105 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1107 = _T_1084 | _T_1106; // @[el2_dec_tlu_ctl.scala 2723:113] + wire _T_1125 = _T_1033 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1126 = _T_1125 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1127 = _T_1126 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1129 = _T_1128 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1130 = _T_1129 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1132 = _T_1107 | _T_1131; // @[el2_dec_tlu_ctl.scala 2724:57] + wire _T_1152 = _T_958 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1154 = _T_1153 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1155 = _T_1154 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1156 = _T_1155 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1157 = _T_1132 | _T_1156; // @[el2_dec_tlu_ctl.scala 2724:113] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1177 = _T_1157 | _T_1176; // @[el2_dec_tlu_ctl.scala 2725:57] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1203 = _T_1202 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1204 = _T_1203 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1205 = _T_1177 | _T_1204; // @[el2_dec_tlu_ctl.scala 2725:113] + wire _T_1224 = _T_959 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1225 = _T_1224 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1228 = _T_1205 | _T_1227; // @[el2_dec_tlu_ctl.scala 2726:57] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1249 = _T_1248 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1251 = _T_1228 | _T_1250; // @[el2_dec_tlu_ctl.scala 2726:113] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1276 = _T_1251 | _T_1275; // @[el2_dec_tlu_ctl.scala 2727:57] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1298 = _T_1276 | _T_1297; // @[el2_dec_tlu_ctl.scala 2727:113] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1316 = _T_1315 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1317 = _T_1316 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1319 = _T_1318 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1320 = _T_1298 | _T_1319; // @[el2_dec_tlu_ctl.scala 2728:65] + wire _T_1343 = _T_1318 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1344 = _T_1343 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1345 = _T_1320 | _T_1344; // @[el2_dec_tlu_ctl.scala 2728:121] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1362 = _T_1345 | _T_1361; // @[el2_dec_tlu_ctl.scala 2729:57] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1385 = _T_1362 | _T_1384; // @[el2_dec_tlu_ctl.scala 2729:113] + wire _T_1406 = _T_1225 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1407 = _T_1385 | _T_1406; // @[el2_dec_tlu_ctl.scala 2730:57] + wire _T_1430 = _T_1226 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1431 = _T_1407 | _T_1430; // @[el2_dec_tlu_ctl.scala 2730:113] + wire _T_1455 = _T_1153 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1456 = _T_1455 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1457 = _T_1456 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1458 = _T_1457 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1459 = _T_1431 | _T_1458; // @[el2_dec_tlu_ctl.scala 2731:57] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1476 = _T_1459 | _T_1475; // @[el2_dec_tlu_ctl.scala 2731:105] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1499 = _T_1498 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1500 = _T_1499 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1501 = _T_1500 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1502 = _T_1501 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1503 = _T_1476 | _T_1502; // @[el2_dec_tlu_ctl.scala 2732:65] + wire _T_1526 = _T_986 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1527 = _T_1526 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1528 = _T_1527 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1529 = _T_1528 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1530 = _T_1529 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1531 = _T_1503 | _T_1530; // @[el2_dec_tlu_ctl.scala 2732:113] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1551 = _T_1531 | _T_1550; // @[el2_dec_tlu_ctl.scala 2733:57] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1568 = _T_1551 | _T_1567; // @[el2_dec_tlu_ctl.scala 2733:113] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1588 = _T_1568 | _T_1587; // @[el2_dec_tlu_ctl.scala 2734:65] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2650:49] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2651:49] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[el2_dec_tlu_ctl.scala 2652:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2653:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2654:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[el2_dec_tlu_ctl.scala 2655:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2656:49] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2657:57] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[el2_dec_tlu_ctl.scala 2658:57] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[el2_dec_tlu_ctl.scala 2659:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[el2_dec_tlu_ctl.scala 2660:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[el2_dec_tlu_ctl.scala 2661:49] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[el2_dec_tlu_ctl.scala 2662:49] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[el2_dec_tlu_ctl.scala 2663:49] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2664:49] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[el2_dec_tlu_ctl.scala 2665:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2666:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2667:49] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[el2_dec_tlu_ctl.scala 2668:49] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[el2_dec_tlu_ctl.scala 2669:49] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[el2_dec_tlu_ctl.scala 2670:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2671:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[el2_dec_tlu_ctl.scala 2672:49] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2673:49] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2674:49] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2675:49] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[el2_dec_tlu_ctl.scala 2676:49] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[el2_dec_tlu_ctl.scala 2677:49] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2678:49] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2679:57] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[el2_dec_tlu_ctl.scala 2680:49] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2681:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2682:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2683:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[el2_dec_tlu_ctl.scala 2684:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2685:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[el2_dec_tlu_ctl.scala 2686:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2687:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[el2_dec_tlu_ctl.scala 2688:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2689:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[el2_dec_tlu_ctl.scala 2690:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2691:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[el2_dec_tlu_ctl.scala 2692:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2693:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[el2_dec_tlu_ctl.scala 2694:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2695:41] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[el2_dec_tlu_ctl.scala 2696:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2697:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2698:49] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[el2_dec_tlu_ctl.scala 2699:49] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[el2_dec_tlu_ctl.scala 2700:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2701:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2702:49] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[el2_dec_tlu_ctl.scala 2704:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[el2_dec_tlu_ctl.scala 2706:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2707:49] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[el2_dec_tlu_ctl.scala 2708:49] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[el2_dec_tlu_ctl.scala 2709:49] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2710:49] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[el2_dec_tlu_ctl.scala 2711:49] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[el2_dec_tlu_ctl.scala 2712:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2713:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[el2_dec_tlu_ctl.scala 2714:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2715:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[el2_dec_tlu_ctl.scala 2716:26] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[el2_dec_tlu_ctl.scala 2718:24] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[el2_dec_tlu_ctl.scala 2721:20] +endmodule +module el2_dec_tlu_ctl( + input clock, + input reset, + input io_active_clk, + input io_free_clk, + input io_scan_mode, + input [30:0] io_rst_vec, + input io_nmi_int, + input [30:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + input io_lsu_fastint_stall_any, + input io_ifu_pmu_instr_aligned, + input io_ifu_pmu_fetch_stall, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_ifu_pmu_bus_trxn, + input io_dec_pmu_instr_decoded, + input io_dec_pmu_decode_stall, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_exu_pmu_i0_br_misp, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_pc4, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_error, + input io_lsu_pmu_bus_busy, + input io_lsu_pmu_load_external_m, + input io_lsu_pmu_store_external_m, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_iccm_dma_sb_error, + input io_lsu_error_pkt_r_exc_valid, + input io_lsu_error_pkt_r_single_ecc_error, + input io_lsu_error_pkt_r_inst_type, + input io_lsu_error_pkt_r_exc_type, + input io_lsu_error_pkt_r_mscause, + input io_lsu_error_pkt_r_addr, + input io_lsu_single_ecc_error_incr, + input io_dec_pause_state, + input io_lsu_imprecise_error_store_any, + input io_lsu_imprecise_error_load_any, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_dec_csr_wen_unq_d, + input io_dec_csr_any_unq_d, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_r, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_dec_csr_stall_int_ff, + input io_dec_tlu_i0_valid_r, + input [30:0] io_exu_npc_r, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_packet_r_legal, + input io_dec_tlu_packet_r_icaf, + input io_dec_tlu_packet_r_icaf_f1, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input io_dec_tlu_packet_r_fence_i, + input [3:0] io_dec_tlu_packet_r_i0trigger, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input [31:0] io_dec_illegal_inst, + input io_dec_i0_decode_d, + input [1:0] io_exu_i0_br_hist_r, + input io_exu_i0_br_error_r, + input io_exu_i0_br_start_error_r, + input io_exu_i0_br_valid_r, + input io_exu_i0_br_mp_r, + input io_exu_i0_br_middle_r, + input io_exu_i0_br_way_r, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_debug_stall, + output io_dec_tlu_flush_noredir_r, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_leak_one_r, + output io_dec_tlu_flush_err_r, + output io_dec_tlu_flush_extint, + output [29:0] io_dec_tlu_meihap, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_ifu_miss_state_idle, + input io_lsu_idle_any, + input io_dec_div_active, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_ic_error_start, + input io_ifu_iccm_rd_ecc_single_err, + input [70:0] io_ifu_ic_debug_rd_data, + input io_ifu_ic_debug_rd_data_valid, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input [7:0] io_pic_claimid, + input [3:0] io_pic_pl, + input io_mhwakeup, + input io_mexintpend, + input io_timer_int, + input io_soft_int, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + output [3:0] io_dec_tlu_meicurpl, + output [3:0] io_dec_tlu_meipt, + output [31:0] io_dec_csr_rddata_d, + output io_dec_csr_legal_d, + output io_dec_tlu_br0_r_pkt_valid, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, + output io_dec_tlu_i0_kill_writeb_wb, + output io_dec_tlu_flush_lower_wb, + output io_dec_tlu_i0_commit_cmt, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_flush_lower_r, + output [30:0] io_dec_tlu_flush_path_r, + output io_dec_tlu_fence_i_r, + output io_dec_tlu_wr_pause_r, + output io_dec_tlu_flush_pause_r, + output io_dec_tlu_presync_d, + output io_dec_tlu_postsync_d, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_force_halt, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_external_ldfwd_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_pipelining_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; +`endif // RANDOMIZE_REG_INIT + wire int_timers_clock; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_reset; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_free_clk; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_scan_mode; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 355:24] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 474:22] + wire csr_clock; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_reset; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_free_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_active_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_scan_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 897:17] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_pic_pl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [29:0] csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire [7:0] csr_io_pic_claimid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_error_pkt_r_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_rst_vec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [27:0] csr_io_core_id; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mret_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire [15:0] csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_timer_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_soft_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_wr_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_reset_delayed; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_e4e5_int_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_nmi; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_exc_cause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_valid_wb; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ecall_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_illegal_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_allow_dbg_halt_csr_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_update_hit_bit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_timer_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 1090:22] + reg dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 447:81] + wire _T = ~dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 354:33] + reg mpc_halt_state_f; // @[el2_dec_tlu_ctl.scala 442:81] + wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] + wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] + reg [6:0] _T_8; // @[el2_lib.scala 174:81] + reg [6:0] syncro_ff; // @[el2_lib.scala 174:58] + wire nmi_int_sync = syncro_ff[6]; // @[el2_dec_tlu_ctl.scala 382:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[el2_dec_tlu_ctl.scala 385:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 345:41 el2_dec_tlu_ctl.scala 1083:31] + reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] + wire _T_11 = io_lsu_error_pkt_r_exc_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:65] + reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[el2_dec_tlu_ctl.scala 395:29] + reg debug_mode_status; // @[el2_dec_tlu_ctl.scala 405:73] + reg i_cpu_run_req_d1_raw; // @[el2_dec_tlu_ctl.scala 653:72] + reg nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 420:64] + wire _T_37 = ~nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 429:39] + wire _T_38 = nmi_int_sync & _T_37; // @[el2_dec_tlu_ctl.scala 429:37] + reg mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 686:89] + wire _T_35 = ~mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 427:26] + wire _T_36 = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 427:78] + wire nmi_lsu_detected = _T_35 & _T_36; // @[el2_dec_tlu_ctl.scala 427:43] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[el2_dec_tlu_ctl.scala 429:57] + reg nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 421:72] + reg take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 894:90] + wire _T_40 = ~take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 429:100] + wire _T_41 = nmi_int_detected_f & _T_40; // @[el2_dec_tlu_ctl.scala 429:98] + wire _T_42 = _T_39 | _T_41; // @[el2_dec_tlu_ctl.scala 429:76] + reg take_ext_int_start_d3; // @[el2_dec_tlu_ctl.scala 826:58] + wire _T_43 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 429:159] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] + wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 344:41 el2_dec_tlu_ctl.scala 1082:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 350:41 el2_dec_tlu_ctl.scala 1088:31] + wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 339:41 el2_dec_tlu_ctl.scala 1077:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] + wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[el2_dec_tlu_ctl.scala 802:82] + wire _T_392 = _T_391 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 680:83] + reg int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 660:65] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:100] + reg int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 661:65] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:124] + wire _T_608 = _T_632 & mip[2]; // @[el2_dec_tlu_ctl.scala 799:65] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[el2_dec_tlu_ctl.scala 799:83] + wire _T_395 = io_mhwakeup & mhwakeup_ready; // @[el2_dec_tlu_ctl.scala 680:163] + wire _T_396 = _T_394 | _T_395; // @[el2_dec_tlu_ctl.scala 680:148] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[el2_dec_tlu_ctl.scala 680:182] + reg i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 652:80] + wire _T_398 = ~i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 680:207] + wire _T_399 = _T_397 & _T_398; // @[el2_dec_tlu_ctl.scala 680:205] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[el2_dec_tlu_ctl.scala 680:44] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 396:49] + wire _T_685 = ~_T_43; // @[el2_dec_tlu_ctl.scala 831:45] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 831:43] + wire _T_698 = ~soft_int_ready; // @[el2_dec_tlu_ctl.scala 848:39] + wire _T_699 = timer_int_ready & _T_698; // @[el2_dec_tlu_ctl.scala 848:37] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[el2_dec_tlu_ctl.scala 800:103] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[el2_dec_tlu_ctl.scala 800:101] + wire _T_700 = ~ext_int_ready; // @[el2_dec_tlu_ctl.scala 848:57] + wire _T_701 = _T_699 & _T_700; // @[el2_dec_tlu_ctl.scala 848:55] + wire _T_622 = _T_632 & mip[5]; // @[el2_dec_tlu_ctl.scala 801:64] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[el2_dec_tlu_ctl.scala 801:82] + wire _T_702 = ~ce_int_ready; // @[el2_dec_tlu_ctl.scala 848:74] + wire _T_703 = _T_701 & _T_702; // @[el2_dec_tlu_ctl.scala 848:72] + wire _T_152 = ~debug_mode_status; // @[el2_dec_tlu_ctl.scala 503:31] + reg dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 546:81] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 480:42] + reg ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 827:58] + wire _T_107 = ~ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 480:65] + wire dbg_halt_req_final = _T_106 & _T_107; // @[el2_dec_tlu_ctl.scala 480:63] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[el2_dec_tlu_ctl.scala 439:61] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 483:44] + reg reset_detect; // @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected; // @[el2_dec_tlu_ctl.scala 417:80] + wire reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 418:64] + wire _T_110 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 483:89] + wire _T_111 = reset_delayed & _T_110; // @[el2_dec_tlu_ctl.scala 483:87] + wire _T_112 = _T_109 | _T_111; // @[el2_dec_tlu_ctl.scala 483:70] + wire _T_114 = _T_112 & _T_152; // @[el2_dec_tlu_ctl.scala 483:113] + wire debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 483:141] + wire _T_153 = _T_152 & debug_halt_req; // @[el2_dec_tlu_ctl.scala 503:57] + reg dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 538:81] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 503:75] + reg trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 537:81] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 503:101] + reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] + reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 342:57 el2_dec_tlu_ctl.scala 1080:31] + reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] + wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] + reg ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 532:73] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 497:89] + wire _T_145 = ~debug_halt_req; // @[el2_dec_tlu_ctl.scala 497:115] + wire _T_146 = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 497:113] + reg debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 539:81] + wire _T_147 = ~debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 497:133] + wire _T_148 = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 497:131] + wire _T_149 = ~io_dec_div_active; // @[el2_dec_tlu_ctl.scala 497:154] + wire _T_150 = _T_148 & _T_149; // @[el2_dec_tlu_ctl.scala 497:152] + wire core_empty = force_halt | _T_150; // @[el2_dec_tlu_ctl.scala 497:28] + wire _T_163 = debug_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 513:42] + reg dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 529:73] + reg dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 545:73] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 493:50] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[el2_dec_tlu_ctl.scala 493:48] + reg take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 824:58] + wire _T_134 = ~take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 493:78] + wire _T_135 = _T_133 & _T_134; // @[el2_dec_tlu_ctl.scala 493:76] + reg halt_taken_f; // @[el2_dec_tlu_ctl.scala 530:81] + reg dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 533:81] + wire _T_136 = ~dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:120] + wire _T_137 = halt_taken_f & _T_136; // @[el2_dec_tlu_ctl.scala 493:118] + reg pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 659:73] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:140] + wire _T_139 = _T_137 & _T_138; // @[el2_dec_tlu_ctl.scala 493:138] + reg interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 888:82] + wire _T_140 = ~interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 493:163] + wire _T_141 = _T_139 & _T_140; // @[el2_dec_tlu_ctl.scala 493:161] + wire halt_taken = _T_135 | _T_141; // @[el2_dec_tlu_ctl.scala 493:102] + wire _T_164 = _T_163 & halt_taken; // @[el2_dec_tlu_ctl.scala 513:55] + reg debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 536:81] + wire _T_165 = ~debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 513:91] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[el2_dec_tlu_ctl.scala 513:89] + wire dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 513:69] + wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] + wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 348:41 el2_dec_tlu_ctl.scala 1086:31] + wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] + wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] + wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] + wire _T_160 = debug_mode_status & _T_159; // @[el2_dec_tlu_ctl.scala 506:75] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 506:47] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[el2_dec_tlu_ctl.scala 519:54] + reg dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 544:73] + wire _T_178 = ~dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 519:105] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[el2_dec_tlu_ctl.scala 519:103] + wire dcsr_single_step_running = _T_177 | _T_179; // @[el2_dec_tlu_ctl.scala 519:73] + wire _T_665 = ~dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 820:54] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 820:80] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[el2_dec_tlu_ctl.scala 820:51] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[el2_dec_tlu_ctl.scala 649:56] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 346:41 el2_dec_tlu_ctl.scala 1084:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] + reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] + wire _T_372 = _T_371 & halt_taken; // @[el2_dec_tlu_ctl.scala 671:57] + wire _T_373 = ~enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 671:72] + wire _T_374 = _T_372 & _T_373; // @[el2_dec_tlu_ctl.scala 671:70] + wire _T_375 = ~i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 671:120] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[el2_dec_tlu_ctl.scala 671:118] + wire _T_377 = _T_374 | _T_376; // @[el2_dec_tlu_ctl.scala 671:95] + wire _T_378 = ~debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 671:142] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[el2_dec_tlu_ctl.scala 671:140] + wire _T_361 = ~pmu_fw_tlu_halted; // @[el2_dec_tlu_ctl.scala 667:71] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[el2_dec_tlu_ctl.scala 667:69] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[el2_dec_tlu_ctl.scala 667:48] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[el2_dec_tlu_ctl.scala 667:92] + reg internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 657:66] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[el2_dec_tlu_ctl.scala 668:82] + wire _T_369 = _T_367 & _T_378; // @[el2_dec_tlu_ctl.scala 668:102] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[el2_dec_tlu_ctl.scala 668:51] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 820:106] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 820:134] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 852:34] + wire _T_739 = nmi_int_detected & _T_738; // @[el2_dec_tlu_ctl.scala 852:32] + wire _T_740 = ~internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 852:64] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[el2_dec_tlu_ctl.scala 852:118] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 852:140] + wire _T_744 = _T_742 & _T_743; // @[el2_dec_tlu_ctl.scala 852:138] + wire _T_746 = _T_744 & _T_178; // @[el2_dec_tlu_ctl.scala 852:163] + wire _T_747 = _T_740 | _T_746; // @[el2_dec_tlu_ctl.scala 852:88] + wire _T_748 = _T_739 & _T_747; // @[el2_dec_tlu_ctl.scala 852:61] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[el2_dec_tlu_ctl.scala 738:51] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 738:64] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 600:57] + wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_300 = ~_T_299; // @[el2_dec_tlu_ctl.scala 600:22] + wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[el2_dec_tlu_ctl.scala 598:52] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] + wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[el2_dec_tlu_ctl.scala 590:56] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 746:48] + wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_282 = _T_279 & _T_281; // @[el2_dec_tlu_ctl.scala 590:71] + wire _T_283 = io_exu_i0_br_error_r | io_exu_i0_br_start_error_r; // @[el2_dec_tlu_ctl.scala 590:128] + wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_286 = _T_282 | _T_285; // @[el2_dec_tlu_ctl.scala 590:97] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[el2_dec_tlu_ctl.scala 590:37] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:89] + wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[el2_dec_tlu_ctl.scala 593:50] + wire [3:0] _T_289 = io_lsu_error_pkt_r_exc_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 347:41 el2_dec_tlu_ctl.scala 1085:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 587:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 587:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 587:352] + wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[el2_dec_tlu_ctl.scala 598:145] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[el2_dec_tlu_ctl.scala 600:83] + wire _T_303 = ~mtdata1_t_2[5]; // @[el2_dec_tlu_ctl.scala 603:59] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[el2_dec_tlu_ctl.scala 603:88] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[el2_dec_tlu_ctl.scala 603:56] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[el2_dec_tlu_ctl.scala 603:156] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[el2_dec_tlu_ctl.scala 603:124] + wire _T_315 = ~mtdata1_t_0[5]; // @[el2_dec_tlu_ctl.scala 603:195] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[el2_dec_tlu_ctl.scala 603:224] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[el2_dec_tlu_ctl.scala 603:192] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[el2_dec_tlu_ctl.scala 603:292] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[el2_dec_tlu_ctl.scala 603:260] + wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 606:56] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 738:90] + wire _T_466 = _T_464 & _T_465; // @[el2_dec_tlu_ctl.scala 738:88] + wire _T_468 = ~dcsr[15]; // @[el2_dec_tlu_ctl.scala 738:110] + wire _T_469 = _T_466 & _T_468; // @[el2_dec_tlu_ctl.scala 738:108] + reg tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 408:72] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 713:43] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[el2_dec_tlu_ctl.scala 713:41] + wire _T_432 = _T_430 & _T_283; // @[el2_dec_tlu_ctl.scala 713:65] + reg ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 402:81] + reg iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 403:89] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 713:137] + wire _T_435 = _T_433 & _T_107; // @[el2_dec_tlu_ctl.scala 713:156] + wire _T_436 = _T_432 | _T_435; // @[el2_dec_tlu_ctl.scala 713:120] + wire _T_438 = _T_436 & _T_465; // @[el2_dec_tlu_ctl.scala 713:179] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[el2_dec_tlu_ctl.scala 701:46] + wire _T_411 = ~io_lsu_error_pkt_r_inst_type; // @[el2_dec_tlu_ctl.scala 701:69] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_single_ecc_error; // @[el2_dec_tlu_ctl.scala 701:99] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[el2_dec_tlu_ctl.scala 701:66] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 713:203] + wire rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 713:200] + wire _T_470 = ~rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 738:132] + wire ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 738:130] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[el2_dec_tlu_ctl.scala 739:51] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 739:64] + wire _T_475 = _T_473 & _T_465; // @[el2_dec_tlu_ctl.scala 739:88] + wire ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 739:108] + wire _T_523 = ebreak_r | ecall_r; // @[el2_dec_tlu_ctl.scala 766:40] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[el2_dec_tlu_ctl.scala 740:17] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 740:46] + wire _T_481 = _T_479 & _T_465; // @[el2_dec_tlu_ctl.scala 740:70] + wire illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 740:90] + wire _T_524 = _T_523 | illegal_r; // @[el2_dec_tlu_ctl.scala 766:50] + wire _T_511 = inst_acc_r_raw & _T_470; // @[el2_dec_tlu_ctl.scala 747:32] + wire inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 747:45] + wire _T_525 = _T_524 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 766:62] + wire _T_527 = _T_525 & _T_470; // @[el2_dec_tlu_ctl.scala 766:76] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 766:91] + wire i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 766:89] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 865:48] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_tlu_ctl.scala 689:60] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_exc_valid & _T_402; // @[el2_dec_tlu_ctl.scala 689:58] + wire _T_403 = io_lsu_error_pkt_r_exc_valid & lsu_exc_valid_r_raw; // @[el2_dec_tlu_ctl.scala 691:39] + wire _T_405 = _T_403 & _T_465; // @[el2_dec_tlu_ctl.scala 691:61] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 691:81] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 865:60] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 743:49] + wire _T_492 = _T_490 & _T_465; // @[el2_dec_tlu_ctl.scala 743:73] + wire fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 743:94] + wire _T_791 = _T_790 | fence_i_r; // @[el2_dec_tlu_ctl.scala 865:78] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 865:90] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[el2_dec_tlu_ctl.scala 704:49] + wire _T_415 = ~lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 704:64] + wire _T_416 = _T_414 & _T_415; // @[el2_dec_tlu_ctl.scala 704:62] + wire _T_417 = ~inst_acc_r; // @[el2_dec_tlu_ctl.scala 704:81] + wire _T_418 = _T_416 & _T_417; // @[el2_dec_tlu_ctl.scala 704:78] + wire _T_420 = _T_418 & _T_528; // @[el2_dec_tlu_ctl.scala 704:93] + reg request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 542:81] + wire _T_421 = ~request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 704:120] + wire _T_422 = _T_420 & _T_421; // @[el2_dec_tlu_ctl.scala 704:118] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 704:145] + reg iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 401:72] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 722:51] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[el2_dec_tlu_ctl.scala 741:51] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 741:64] + wire _T_487 = _T_485 & _T_465; // @[el2_dec_tlu_ctl.scala 741:88] + wire mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 741:108] + wire _T_446 = _T_523 | mret_r; // @[el2_dec_tlu_ctl.scala 722:97] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 851:31] + wire _T_447 = _T_446 | take_reset; // @[el2_dec_tlu_ctl.scala 722:106] + wire _T_448 = _T_447 | illegal_r; // @[el2_dec_tlu_ctl.scala 722:119] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 722:175] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[el2_dec_tlu_ctl.scala 722:152] + wire _T_451 = _T_448 | _T_450; // @[el2_dec_tlu_ctl.scala 722:131] + wire _T_452 = ~_T_451; // @[el2_dec_tlu_ctl.scala 722:76] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[el2_dec_tlu_ctl.scala 722:74] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 865:107] + wire _T_794 = _T_793 | debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 865:134] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 863:42] + wire _T_211 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 562:22] + reg dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 541:73] + wire _T_212 = _T_211 & dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 562:42] + wire _T_213 = ext_int_ready | ce_int_ready; // @[el2_dec_tlu_ctl.scala 562:80] + wire _T_214 = _T_213 | timer_int_ready; // @[el2_dec_tlu_ctl.scala 562:95] + wire _T_215 = _T_214 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 562:113] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:130] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:154] + wire _T_218 = _T_217 | nmi_int_detected; // @[el2_dec_tlu_ctl.scala 562:178] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 562:197] + wire _T_220 = ~_T_219; // @[el2_dec_tlu_ctl.scala 562:64] + wire _T_221 = _T_212 & _T_220; // @[el2_dec_tlu_ctl.scala 562:62] + wire _T_223 = _T_221 & _T_140; // @[el2_dec_tlu_ctl.scala 562:218] + wire _T_225 = _T_223 & _T_378; // @[el2_dec_tlu_ctl.scala 562:242] + wire _T_226 = ~pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 562:264] + wire _T_227 = _T_225 & _T_226; // @[el2_dec_tlu_ctl.scala 562:262] + wire _T_228 = ~halt_taken_f; // @[el2_dec_tlu_ctl.scala 562:285] + wire pause_expired_r = _T_227 & _T_228; // @[el2_dec_tlu_ctl.scala 562:283] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 863:65] + wire _T_795 = _T_794 | sel_npc_resume; // @[el2_dec_tlu_ctl.scala 865:156] + reg dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 540:73] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 865:174] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 865:200] + wire _T_749 = ~synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 852:194] + wire _T_750 = _T_748 & _T_749; // @[el2_dec_tlu_ctl.scala 852:192] + wire _T_751 = ~mret_r; // @[el2_dec_tlu_ctl.scala 852:217] + wire _T_752 = _T_750 & _T_751; // @[el2_dec_tlu_ctl.scala 852:215] + wire _T_753 = ~take_reset; // @[el2_dec_tlu_ctl.scala 852:227] + wire _T_754 = _T_752 & _T_753; // @[el2_dec_tlu_ctl.scala 852:225] + wire _T_519 = _T_466 & dcsr[15]; // @[el2_dec_tlu_ctl.scala 750:120] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 750:141] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 852:241] + wire _T_756 = _T_754 & _T_755; // @[el2_dec_tlu_ctl.scala 852:239] + wire _T_760 = _T_107 | _T_44; // @[el2_dec_tlu_ctl.scala 852:287] + wire take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 852:265] + wire _T_670 = _T_669 | take_nmi; // @[el2_dec_tlu_ctl.scala 820:154] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 820:165] + wire _T_672 = _T_671 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 820:190] + reg exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 890:82] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 820:213] + wire _T_674 = _T_673 | mret_r; // @[el2_dec_tlu_ctl.scala 820:237] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 820:246] + wire _T_704 = ~block_interrupts; // @[el2_dec_tlu_ctl.scala 848:90] + wire take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 848:88] + wire _T_762 = take_ext_int | take_timer_int; // @[el2_dec_tlu_ctl.scala 855:37] + wire _T_693 = soft_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 847:35] + wire _T_695 = _T_693 & _T_702; // @[el2_dec_tlu_ctl.scala 847:52] + wire take_soft_int = _T_695 & _T_704; // @[el2_dec_tlu_ctl.scala 847:68] + wire _T_763 = _T_762 | take_soft_int; // @[el2_dec_tlu_ctl.scala 855:54] + wire _T_764 = _T_763 | take_nmi; // @[el2_dec_tlu_ctl.scala 855:70] + wire _T_689 = ce_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 846:32] + wire take_ce_int = _T_689 & _T_704; // @[el2_dec_tlu_ctl.scala 846:49] + wire _T_765 = _T_764 | take_ce_int; // @[el2_dec_tlu_ctl.scala 855:81] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[el2_dec_tlu_ctl.scala 806:48] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 807:46] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 849:48] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 849:73] + wire _T_709 = _T_707 & _T_631; // @[el2_dec_tlu_ctl.scala 849:99] + wire _T_710 = ~timer_int_ready; // @[el2_dec_tlu_ctl.scala 849:128] + wire _T_711 = _T_709 & _T_710; // @[el2_dec_tlu_ctl.scala 849:126] + wire _T_713 = _T_711 & _T_698; // @[el2_dec_tlu_ctl.scala 849:145] + wire _T_715 = _T_713 & _T_700; // @[el2_dec_tlu_ctl.scala 849:163] + wire _T_717 = _T_715 & _T_702; // @[el2_dec_tlu_ctl.scala 849:180] + wire take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 849:196] + wire _T_766 = _T_765 | take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 855:95] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[el2_dec_tlu_ctl.scala 808:48] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 809:46] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 850:48] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 850:73] + wire _T_723 = _T_721 & _T_631; // @[el2_dec_tlu_ctl.scala 850:99] + wire _T_725 = ~_T_706; // @[el2_dec_tlu_ctl.scala 850:128] + wire _T_726 = _T_723 & _T_725; // @[el2_dec_tlu_ctl.scala 850:126] + wire _T_728 = _T_726 & _T_710; // @[el2_dec_tlu_ctl.scala 850:176] + wire _T_730 = _T_728 & _T_698; // @[el2_dec_tlu_ctl.scala 850:195] + wire _T_732 = _T_730 & _T_700; // @[el2_dec_tlu_ctl.scala 850:213] + wire _T_734 = _T_732 & _T_702; // @[el2_dec_tlu_ctl.scala 850:230] + wire take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 850:246] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 855:117] + wire _T_15 = _T_14 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 396:68] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 396:88] + wire _T_17 = _T_16 | reset_delayed; // @[el2_dec_tlu_ctl.scala 396:111] + wire _T_18 = _T_17 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 396:127] + reg pause_expired_wb; // @[el2_dec_tlu_ctl.scala 895:90] + wire _T_19 = _T_18 | pause_expired_wb; // @[el2_dec_tlu_ctl.scala 396:145] + wire _T_496 = io_ifu_ic_error_start & _T_107; // @[el2_dec_tlu_ctl.scala 744:42] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 744:92] + wire _T_499 = _T_496 & _T_498; // @[el2_dec_tlu_ctl.scala 744:63] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 744:122] + wire ic_perr_r = _T_499 & _T_500; // @[el2_dec_tlu_ctl.scala 744:120] + wire _T_20 = _T_19 | ic_perr_r; // @[el2_dec_tlu_ctl.scala 396:164] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 396:176] + wire _T_503 = io_ifu_iccm_rd_ecc_single_err & _T_107; // @[el2_dec_tlu_ctl.scala 745:50] + wire _T_506 = _T_503 & _T_498; // @[el2_dec_tlu_ctl.scala 745:71] + wire iccm_sbecc_r = _T_506 & _T_500; // @[el2_dec_tlu_ctl.scala 745:128] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[el2_dec_tlu_ctl.scala 396:191] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 396:206] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 396:224] + reg lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 407:64] + reg _T_32; // @[el2_dec_tlu_ctl.scala 409:65] + reg internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33; // @[el2_dec_tlu_ctl.scala 411:73] + reg nmi_lsu_load_type_f; // @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f; // @[el2_dec_tlu_ctl.scala 423:64] + wire _T_46 = nmi_lsu_detected & io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 431:42] + wire _T_49 = ~_T_41; // @[el2_dec_tlu_ctl.scala 431:78] + wire _T_50 = _T_46 & _T_49; // @[el2_dec_tlu_ctl.scala 431:76] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 431:141] + wire _T_54 = nmi_lsu_detected & io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 432:43] + wire _T_58 = _T_54 & _T_49; // @[el2_dec_tlu_ctl.scala 432:78] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 432:144] + reg mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 441:64] + reg mpc_run_state_f; // @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 446:80] + reg dbg_run_state_f; // @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65; // @[el2_dec_tlu_ctl.scala 449:73] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 453:65] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[el2_dec_tlu_ctl.scala 453:63] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 454:64] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[el2_dec_tlu_ctl.scala 454:62] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[el2_dec_tlu_ctl.scala 456:42] + wire _T_71 = _T_68 | _T_111; // @[el2_dec_tlu_ctl.scala 456:74] + wire _T_72 = ~mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 456:119] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[el2_dec_tlu_ctl.scala 456:117] + wire _T_74 = ~mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 457:74] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[el2_dec_tlu_ctl.scala 457:72] + wire _T_76 = mpc_run_state_f | _T_75; // @[el2_dec_tlu_ctl.scala 457:40] + wire _T_77 = ~dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 457:127] + wire _T_78 = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 457:125] + wire mpc_run_state_ns = _T_76 & _T_78; // @[el2_dec_tlu_ctl.scala 457:97] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 459:64] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 459:90] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 459:115] + wire _T_83 = dbg_halt_state_f | _T_82; // @[el2_dec_tlu_ctl.scala 459:42] + wire _T_84 = ~io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 459:147] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[el2_dec_tlu_ctl.scala 459:145] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 460:40] + wire dbg_run_state_ns = _T_86 & _T_78; // @[el2_dec_tlu_ctl.scala 460:61] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 466:53] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 467:47] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[el2_dec_tlu_ctl.scala 467:97] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[el2_dec_tlu_ctl.scala 470:45] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 470:72] + wire _T_99 = ~dbg_halt_state_ns; // @[el2_dec_tlu_ctl.scala 471:53] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[el2_dec_tlu_ctl.scala 471:51] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 471:74] + wire _T_102 = _T_100 & _T_101; // @[el2_dec_tlu_ctl.scala 471:72] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 471:123] + wire _T_118 = mpc_run_state_ns & _T_99; // @[el2_dec_tlu_ctl.scala 485:67] + wire _T_119 = ~mpc_halt_state_ns; // @[el2_dec_tlu_ctl.scala 485:111] + wire _T_120 = dbg_run_state_ns & _T_119; // @[el2_dec_tlu_ctl.scala 485:109] + wire _T_121 = _T_118 | _T_120; // @[el2_dec_tlu_ctl.scala 485:89] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 490:37] + wire _T_124 = _T_122 & _T_749; // @[el2_dec_tlu_ctl.scala 490:58] + wire _T_126 = _T_124 & _T_751; // @[el2_dec_tlu_ctl.scala 490:81] + wire _T_128 = _T_126 & _T_228; // @[el2_dec_tlu_ctl.scala 490:91] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 490:109] + wire _T_130 = _T_128 & _T_129; // @[el2_dec_tlu_ctl.scala 490:107] + wire take_halt = _T_130 & _T_753; // @[el2_dec_tlu_ctl.scala 490:137] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 515:43] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[el2_dec_tlu_ctl.scala 517:53] + wire _T_174 = _T_172 & dcsr[2]; // @[el2_dec_tlu_ctl.scala 517:78] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 612:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 612:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 612:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 612:241] + wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[el2_dec_tlu_ctl.scala 618:56] + wire i0_trigger_action_r = |_T_343; // @[el2_dec_tlu_ctl.scala 618:74] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[el2_dec_tlu_ctl.scala 620:44] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 524:51] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[el2_dec_tlu_ctl.scala 524:104] + reg request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 543:73] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 526:58] + reg _T_190; // @[el2_dec_tlu_ctl.scala 534:73] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 555:56] + wire _T_202 = take_halt | _T_201; // @[el2_dec_tlu_ctl.scala 555:43] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[el2_dec_tlu_ctl.scala 555:82] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 555:129] + wire _T_205 = _T_203 | _T_204; // @[el2_dec_tlu_ctl.scala 555:109] + wire take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 828:41] + wire _T_207 = ~interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 560:55] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 560:53] + wire _T_209 = ~take_ext_int_start; // @[el2_dec_tlu_ctl.scala 560:76] + wire _T_231 = io_dec_tlu_flush_lower_r & dcsr[2]; // @[el2_dec_tlu_ctl.scala 564:60] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 564:103] + wire _T_233 = _T_231 & _T_232; // @[el2_dec_tlu_ctl.scala 564:78] + wire _T_234 = ~io_dec_tlu_flush_noredir_r; // @[el2_dec_tlu_ctl.scala 564:133] + wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire _T_345 = ~trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 622:54] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 622:52] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 650:52] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 650:77] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[el2_dec_tlu_ctl.scala 650:99] + reg _T_353; // @[el2_dec_tlu_ctl.scala 654:73] + reg _T_354; // @[el2_dec_tlu_ctl.scala 655:81] + reg _T_355; // @[el2_dec_tlu_ctl.scala 656:81] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[el2_dec_tlu_ctl.scala 674:88] + wire _T_386 = _T_384 & _T_152; // @[el2_dec_tlu_ctl.scala 674:108] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:40] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:87] + reg lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 687:64] + reg lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 694:73] + wire _T_408 = ~io_lsu_error_pkt_r_exc_type; // @[el2_dec_tlu_ctl.scala 695:39] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[el2_dec_tlu_ctl.scala 695:37] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_exc_type; // @[el2_dec_tlu_ctl.scala 696:37] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_inst_type; // @[el2_dec_tlu_ctl.scala 697:37] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 707:37] + wire _T_425 = _T_424 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 707:52] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 707:78] + wire _T_427 = _T_425 | _T_426; // @[el2_dec_tlu_ctl.scala 707:65] + wire _T_441 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 716:69] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[el2_dec_tlu_ctl.scala 716:67] + wire _T_453 = io_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 725:50] + wire _T_455 = io_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 726:62] + wire _T_457 = io_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 727:46] + wire _T_459 = _T_457 & _T_429; // @[el2_dec_tlu_ctl.scala 727:70] + wire _T_460 = ~io_exu_i0_br_mp_r; // @[el2_dec_tlu_ctl.scala 727:97] + wire _T_461 = ~io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 727:118] + wire _T_462 = _T_460 | _T_461; // @[el2_dec_tlu_ctl.scala 727:116] + wire _T_529 = ~take_nmi; // @[el2_dec_tlu_ctl.scala 775:21] + wire _T_530 = take_ext_int & _T_529; // @[el2_dec_tlu_ctl.scala 775:19] + wire _T_533 = take_timer_int & _T_529; // @[el2_dec_tlu_ctl.scala 776:21] + wire _T_536 = take_soft_int & _T_529; // @[el2_dec_tlu_ctl.scala 777:20] + wire _T_539 = take_int_timer0_int & _T_529; // @[el2_dec_tlu_ctl.scala 778:26] + wire _T_542 = take_int_timer1_int & _T_529; // @[el2_dec_tlu_ctl.scala 779:26] + wire _T_545 = take_ce_int & _T_529; // @[el2_dec_tlu_ctl.scala 780:18] + wire _T_548 = illegal_r & _T_529; // @[el2_dec_tlu_ctl.scala 781:16] + wire _T_551 = ecall_r & _T_529; // @[el2_dec_tlu_ctl.scala 782:15] + wire _T_554 = inst_acc_r & _T_529; // @[el2_dec_tlu_ctl.scala 783:18] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 784:16] + wire _T_558 = _T_556 & _T_529; // @[el2_dec_tlu_ctl.scala 784:36] + wire _T_560 = ~lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 785:21] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[el2_dec_tlu_ctl.scala 785:19] + wire _T_563 = _T_561 & _T_529; // @[el2_dec_tlu_ctl.scala 785:35] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[el2_dec_tlu_ctl.scala 786:20] + wire _T_568 = _T_566 & _T_529; // @[el2_dec_tlu_ctl.scala 786:36] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 787:19] + wire _T_572 = _T_570 & _T_529; // @[el2_dec_tlu_ctl.scala 787:34] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 788:20] + wire _T_576 = _T_574 & _T_529; // @[el2_dec_tlu_ctl.scala 788:35] + wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_581 = _T_539 ? 5'h1d : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_582 = _T_542 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_583 = _T_545 ? 5'h1e : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_584 = _T_548 ? 5'h2 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_585 = _T_551 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_586 = _T_554 ? 5'h1 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_587 = _T_558 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_588 = _T_563 ? 5'h4 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_589 = _T_568 ? 5'h5 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_590 = _T_572 ? 5'h6 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_591 = _T_576 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_592 = _T_578 | _T_579; // @[Mux.scala 27:72] + wire [4:0] _T_593 = _T_592 | _T_580; // @[Mux.scala 27:72] + wire [4:0] _T_594 = _T_593 | _T_581; // @[Mux.scala 27:72] + wire [4:0] _T_595 = _T_594 | _T_582; // @[Mux.scala 27:72] + wire [4:0] _T_596 = _T_595 | _T_583; // @[Mux.scala 27:72] + wire [4:0] _T_597 = _T_596 | _T_584; // @[Mux.scala 27:72] + wire [4:0] _T_598 = _T_597 | _T_585; // @[Mux.scala 27:72] + wire [4:0] _T_599 = _T_598 | _T_586; // @[Mux.scala 27:72] + wire [4:0] _T_600 = _T_599 | _T_587; // @[Mux.scala 27:72] + wire [4:0] _T_601 = _T_600 | _T_588; // @[Mux.scala 27:72] + wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] + wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] + wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 813:51] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 813:73] + wire int_timer_stalled = _T_642 | mret_r; // @[el2_dec_tlu_ctl.scala 813:97] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[el2_dec_tlu_ctl.scala 815:71] + wire _T_644 = int_timer0_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 815:48] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 815:120] + wire _T_647 = _T_645 & _T_207; // @[el2_dec_tlu_ctl.scala 815:144] + wire _T_649 = _T_647 & _T_209; // @[el2_dec_tlu_ctl.scala 815:165] + wire _T_651 = _T_649 & _T_152; // @[el2_dec_tlu_ctl.scala 815:187] + wire _T_654 = int_timer1_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 816:48] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 816:120] + wire _T_657 = _T_655 & _T_207; // @[el2_dec_tlu_ctl.scala 816:144] + wire _T_659 = _T_657 & _T_209; // @[el2_dec_tlu_ctl.scala 816:165] + wire _T_661 = _T_659 & _T_152; // @[el2_dec_tlu_ctl.scala 816:187] + reg take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 825:58] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 830:42] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 349:41 el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[el2_dec_tlu_ctl.scala 861:60] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[el2_dec_tlu_ctl.scala 861:27] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[el2_dec_tlu_ctl.scala 862:35] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 862:47] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 862:93] + wire _T_783 = _T_780 | _T_782; // @[el2_dec_tlu_ctl.scala 862:73] + wire _T_785 = rfpc_i0_r & _T_743; // @[el2_dec_tlu_ctl.scala 862:128] + wire sel_npc_r = _T_783 | _T_785; // @[el2_dec_tlu_ctl.scala 862:115] + wire _T_798 = interrupt_valid_r | mret_r; // @[el2_dec_tlu_ctl.scala 866:42] + wire _T_799 = _T_798 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 866:51] + wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73] + wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85] + wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21] + wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39] + wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69] + wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44] + wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 873:46] + wire _T_823 = _T_821 & _T_207; // @[el2_dec_tlu_ctl.scala 873:91] + wire _T_825 = _T_823 & _T_816; // @[el2_dec_tlu_ctl.scala 873:112] + wire _T_830 = _T_529 & mret_r; // @[el2_dec_tlu_ctl.scala 874:16] + wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] + wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] + wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 343:41 el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] + wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] + wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72] + wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72] + wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] + wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] + wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] + reg [30:0] tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 879:58] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 886:44] + wire _T_855 = _T_854 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 886:67] + reg i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 889:81] + wire _T_860 = ~illegal_r; // @[el2_dec_tlu_ctl.scala 892:119] + reg i0_valid_wb; // @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 893:81] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1094:44] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 1094:69] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1099:57] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1099:75] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1099:94] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1099:117] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1099:138] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1099:160] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1099:181] + wire _T_881 = ~_T_880; // @[el2_dec_tlu_ctl.scala 1099:38] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1099:203] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_883 = csr_pkt_legal & _T_882; // @[el2_dec_tlu_ctl.scala 1099:35] + wire _T_884 = ~fast_int_meicpct; // @[el2_dec_tlu_ctl.scala 1099:225] + wire valid_csr = _T_883 & _T_884; // @[el2_dec_tlu_ctl.scala 1099:223] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[el2_dec_tlu_ctl.scala 1101:48] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1101:109] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1101:131] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1101:152] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1101:174] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1101:195] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[el2_dec_tlu_ctl.scala 1101:84] + wire _T_894 = ~_T_893; // @[el2_dec_tlu_ctl.scala 1101:61] + el2_dec_timer_ctl int_timers ( // @[el2_dec_tlu_ctl.scala 355:24] + .clock(int_timers_clock), + .reset(int_timers_reset), + .io_free_clk(int_timers_io_free_clk), + .io_scan_mode(int_timers_io_scan_mode), + .io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r), + .io_csr_mitctl0(int_timers_io_csr_mitctl0), + .io_csr_mitctl1(int_timers_io_csr_mitctl1), + .io_csr_mitb0(int_timers_io_csr_mitb0), + .io_csr_mitb1(int_timers_io_csr_mitb1), + .io_csr_mitcnt0(int_timers_io_csr_mitcnt0), + .io_csr_mitcnt1(int_timers_io_csr_mitcnt1), + .io_dec_pause_state(int_timers_io_dec_pause_state), + .io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted), + .io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers), + .io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d), + .io_dec_timer_read_d(int_timers_io_dec_timer_read_d), + .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) + ); + rvclkhdr rvclkhdr ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + csr_tlu csr ( // @[el2_dec_tlu_ctl.scala 897:17] + .clock(csr_clock), + .reset(csr_reset), + .io_free_clk(csr_io_free_clk), + .io_active_clk(csr_io_active_clk), + .io_scan_mode(csr_io_scan_mode), + .io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r), + .io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r), + .io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d), + .io_dec_i0_decode_d(csr_io_dec_i0_decode_d), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), + .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_(csr_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_(csr_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_(csr_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_(csr_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2), + .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn), + .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any), + .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any), + .io_lsu_store_stall_any(csr_io_lsu_store_stall_any), + .io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall), + .io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall), + .io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall), + .io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp), + .io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded), + .io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned), + .io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4), + .io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit), + .io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1), + .io_dec_csr_wen_r(csr_io_dec_csr_wen_r), + .io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3), + .io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted), + .io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write), + .io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read), + .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), + .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), + .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), + .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), + .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), + .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), + .io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d), + .io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable), + .io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r), + .io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn), + .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data), + .io_dec_tlu_meipt(csr_io_dec_tlu_meipt), + .io_pic_pl(csr_io_pic_pl), + .io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl), + .io_dec_tlu_meihap(csr_io_dec_tlu_meihap), + .io_pic_claimid(csr_io_pic_claimid), + .io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error), + .io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any), + .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), + .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), + .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty), + .io_dec_illegal_inst(csr_io_dec_illegal_inst), + .io_lsu_error_pkt_r_mscause(csr_io_lsu_error_pkt_r_mscause), + .io_mexintpend(csr_io_mexintpend), + .io_exu_npc_r(csr_io_exu_npc_r), + .io_mpc_reset_run_req(csr_io_mpc_reset_run_req), + .io_rst_vec(csr_io_rst_vec), + .io_core_id(csr_io_core_id), + .io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d), + .io_dec_timer_read_d(csr_io_dec_timer_read_d), + .io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod), + .io_rfpc_i0_r(csr_io_rfpc_i0_r), + .io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r), + .io_fw_halt_req(csr_io_fw_halt_req), + .io_mstatus(csr_io_mstatus), + .io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r), + .io_mret_r(csr_io_mret_r), + .io_mstatus_mie_ns(csr_io_mstatus_mie_ns), + .io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f), + .io_dcsr(csr_io_dcsr), + .io_mtvec(csr_io_mtvec), + .io_mip(csr_io_mip), + .io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse), + .io_timer_int_sync(csr_io_timer_int_sync), + .io_soft_int_sync(csr_io_soft_int_sync), + .io_mie_ns(csr_io_mie_ns), + .io_csr_wr_clk(csr_io_csr_wr_clk), + .io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r), + .io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted), + .io_lsu_fir_error(csr_io_lsu_fir_error), + .io_npc_r(csr_io_npc_r), + .io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1), + .io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1), + .io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1), + .io_npc_r_d1(csr_io_npc_r_d1), + .io_reset_delayed(csr_io_reset_delayed), + .io_mepc(csr_io_mepc), + .io_interrupt_valid_r(csr_io_interrupt_valid_r), + .io_i0_exception_valid_r(csr_io_i0_exception_valid_r), + .io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r), + .io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r), + .io_e4e5_int_clk(csr_io_e4e5_int_clk), + .io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r), + .io_inst_acc_r(csr_io_inst_acc_r), + .io_inst_acc_second_r(csr_io_inst_acc_second_r), + .io_take_nmi(csr_io_take_nmi), + .io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r), + .io_exc_cause_r(csr_io_exc_cause_r), + .io_i0_valid_wb(csr_io_i0_valid_wb), + .io_exc_or_int_valid_r_d1(csr_io_exc_or_int_valid_r_d1), + .io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1), + .io_clk_override(csr_io_clk_override), + .io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1), + .io_lsu_i0_exc_r_d1(csr_io_lsu_i0_exc_r_d1), + .io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type), + .io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type), + .io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt), + .io_ebreak_r(csr_io_ebreak_r), + .io_ecall_r(csr_io_ecall_r), + .io_illegal_r(csr_io_illegal_r), + .io_mdseac_locked_ns(csr_io_mdseac_locked_ns), + .io_mdseac_locked_f(csr_io_mdseac_locked_f), + .io_nmi_int_detected_f(csr_io_nmi_int_detected_f), + .io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2), + .io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1), + .io_ic_perr_r_d1(csr_io_ic_perr_r_d1), + .io_iccm_sbecc_r_d1(csr_io_iccm_sbecc_r_d1), + .io_lsu_single_ecc_error_r_d1(csr_io_lsu_single_ecc_error_r_d1), + .io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f), + .io_lsu_idle_any_f(csr_io_lsu_idle_any_f), + .io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f), + .io_dbg_tlu_halted(csr_io_dbg_tlu_halted), + .io_debug_halt_req_f(csr_io_debug_halt_req_f), + .io_force_halt(csr_io_force_halt), + .io_take_ext_int_start(csr_io_take_ext_int_start), + .io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1), + .io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1), + .io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f), + .io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1), + .io_debug_halt_req(csr_io_debug_halt_req), + .io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write), + .io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f), + .io_enter_debug_halt_req(csr_io_enter_debug_halt_req), + .io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode), + .io_request_debug_mode_done(csr_io_request_debug_mode_done), + .io_request_debug_mode_r(csr_io_request_debug_mode_r), + .io_dpc(csr_io_dpc), + .io_update_hit_bit_r(csr_io_update_hit_bit_r), + .io_take_timer_int(csr_io_take_timer_int), + .io_take_int_timer0_int(csr_io_take_int_timer0_int), + .io_take_int_timer1_int(csr_io_take_int_timer1_int), + .io_take_ext_int(csr_io_take_ext_int), + .io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r), + .io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r), + .io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r), + .io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1), + .io_mtdata1_t_0(csr_io_mtdata1_t_0), + .io_mtdata1_t_1(csr_io_mtdata1_t_1), + .io_mtdata1_t_2(csr_io_mtdata1_t_2), + .io_mtdata1_t_3(csr_io_mtdata1_t_3) + ); + el2_dec_decode_csr_read csr_read ( // @[el2_dec_tlu_ctl.scala 1090:22] + .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), + .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst), + .io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0), + .io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1), + .io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0), + .io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1), + .io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0), + .io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1), + .io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct), + .io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1), + .io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago), + .io_csr_pkt_presync(csr_read_io_csr_pkt_presync), + .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), + .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) + ); + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 568:23] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[el2_dec_tlu_ctl.scala 569:23] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 550:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[el2_dec_tlu_ctl.scala 551:41] + assign io_dec_tlu_resume_ack = _T_190; // @[el2_dec_tlu_ctl.scala 534:41] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 549:41] + assign io_dec_tlu_flush_noredir_r = _T_205 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 555:30] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[el2_dec_tlu_ctl.scala 449:41] + assign io_dec_tlu_flush_leak_one_r = _T_233 & _T_234; // @[el2_dec_tlu_ctl.scala 564:31] + assign io_dec_tlu_flush_err_r = io_dec_tlu_flush_lower_r & _T_433; // @[el2_dec_tlu_ctl.scala 565:26] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] + assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_ = csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_ = csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_ = csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_ = csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_o_cpu_halt_status = _T_353; // @[el2_dec_tlu_ctl.scala 654:41] + assign io_o_cpu_halt_ack = _T_354; // @[el2_dec_tlu_ctl.scala 655:49] + assign io_o_cpu_run_ack = _T_355; // @[el2_dec_tlu_ctl.scala 656:49] + assign io_o_debug_mode_status = debug_mode_status; // @[el2_dec_tlu_ctl.scala 677:26] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 474:25] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 475:25] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 476:25] + assign io_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 955:44] + assign io_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 957:44] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] + assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] + assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49] + assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41] + assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49] + assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] + assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 415:33] + assign io_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 882:33] + assign io_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[el2_dec_tlu_ctl.scala 883:33] + assign io_dec_tlu_fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 753:24] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 979:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[el2_dec_tlu_ctl.scala 560:28] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[el2_dec_tlu_ctl.scala 1094:25] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1095:25] + assign io_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 980:40] + assign io_dec_tlu_force_halt = _T_33; // @[el2_dec_tlu_ctl.scala 411:41] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 965:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 966:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 967:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 968:40] + assign io_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 985:40] + assign io_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 983:40] + assign io_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 984:40] + assign io_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 982:40] + assign io_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 981:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 978:40] + assign io_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 986:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 969:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 970:40] + assign io_dec_tlu_ifu_clk_override = csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 971:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 972:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 973:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 974:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 975:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 976:40] + assign int_timers_clock = clock; + assign int_timers_reset = reset; + assign int_timers_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 356:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 357:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 358:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 360:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 361:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 362:49] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 363:49] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 364:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 365:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 366:49] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 367:49] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 368:41] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 369:41] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[el2_dec_tlu_ctl.scala 370:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[el2_lib.scala 476:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign csr_clock = clock; + assign csr_reset = reset; + assign csr_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 898:44] + assign csr_io_active_clk = io_active_clk; // @[el2_dec_tlu_ctl.scala 899:44] + assign csr_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 900:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 901:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 902:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 903:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 904:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 905:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 906:44] + assign csr_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 907:44] + assign csr_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 908:44] + assign csr_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 909:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 910:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 911:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 912:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 913:44] + assign csr_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 914:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 916:44] + assign csr_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 917:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 918:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 919:44] + assign csr_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 920:44] + assign csr_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 921:44] + assign csr_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 922:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 923:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 924:44] + assign csr_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 925:44] + assign csr_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 926:44] + assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44] + assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44] + assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44] + assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44] + assign csr_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 935:44] + assign csr_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 936:44] + assign csr_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 937:44] + assign csr_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 938:44] + assign csr_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 939:44] + assign csr_io_pic_pl = io_pic_pl; // @[el2_dec_tlu_ctl.scala 940:44] + assign csr_io_pic_claimid = io_pic_claimid; // @[el2_dec_tlu_ctl.scala 941:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 942:44] + assign csr_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 943:44] + assign csr_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 944:44] + assign csr_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 945:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 946:44 el2_dec_tlu_ctl.scala 987:44] + assign csr_io_lsu_error_pkt_r_mscause = io_lsu_error_pkt_r_mscause; // @[el2_dec_tlu_ctl.scala 947:44 el2_dec_tlu_ctl.scala 988:44] + assign csr_io_mexintpend = io_mexintpend; // @[el2_dec_tlu_ctl.scala 948:44 el2_dec_tlu_ctl.scala 989:44] + assign csr_io_exu_npc_r = io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 949:44 el2_dec_tlu_ctl.scala 990:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 950:44 el2_dec_tlu_ctl.scala 991:44] + assign csr_io_rst_vec = io_rst_vec; // @[el2_dec_tlu_ctl.scala 951:44 el2_dec_tlu_ctl.scala 992:44] + assign csr_io_core_id = io_core_id; // @[el2_dec_tlu_ctl.scala 952:44 el2_dec_tlu_ctl.scala 993:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 953:44 el2_dec_tlu_ctl.scala 994:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 954:44 el2_dec_tlu_ctl.scala 995:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 998:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 999:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1000:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 1001:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1002:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 1003:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 1004:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[el2_dec_tlu_ctl.scala 1005:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[el2_dec_tlu_ctl.scala 1006:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[el2_dec_tlu_ctl.scala 1007:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 1008:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1009:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1010:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1011:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1012:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 1013:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 1014:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 1015:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 1016:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1017:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 1018:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[el2_dec_tlu_ctl.scala 1019:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1020:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] + assign csr_io_lsu_error_pkt_addr_r = {{31'd0}, io_lsu_error_pkt_r_addr}; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1028:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 1029:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1030:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 1031:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[el2_dec_tlu_ctl.scala 1033:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[el2_dec_tlu_ctl.scala 1034:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 1035:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 1036:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 1037:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 1038:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1039:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1040:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1041:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1042:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 1043:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1044:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 1045:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 1046:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 1047:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1048:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 1049:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 1050:51] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 1051:47] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 1052:43] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 1053:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 1054:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1055:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 1056:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 1057:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[el2_dec_tlu_ctl.scala 1058:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1059:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 1060:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[el2_dec_tlu_ctl.scala 1061:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[el2_dec_tlu_ctl.scala 1062:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 1063:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 1064:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 1065:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 1066:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 1067:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1068:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 1069:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 1070:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 1071:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 1072:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1091:31] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_halt_state_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + mpc_halt_state_f = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_8 = _RAND_2[6:0]; + _RAND_3 = {1{`RANDOM}}; + syncro_ff = _RAND_3[6:0]; + _RAND_4 = {1{`RANDOM}}; + lsu_exc_valid_r_d1 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + e5_valid = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + debug_mode_status = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + i_cpu_run_req_d1_raw = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + nmi_int_delayed = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + mdseac_locked_f = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + nmi_int_detected_f = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + take_nmi_r_d1 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + take_ext_int_start_d3 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + int_timer0_int_hold_f = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + int_timer1_int_hold_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + i_cpu_halt_req_d1 = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + dbg_halt_req_held = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + ext_int_freeze_d1 = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + reset_detect = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + reset_detected = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + dcsr_single_step_done_f = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + trigger_hit_dmode_r_d1 = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ebreak_to_debug_mode_r_d1 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + debug_halt_req_f = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + lsu_idle_any_f = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ifu_miss_state_idle_f = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + debug_halt_req_d1 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + dec_tlu_flush_noredir_r_d1 = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + dec_tlu_flush_pause_r_d1 = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + take_ext_int_start_d1 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + halt_taken_f = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + dbg_tlu_halted_f = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + pmu_fw_tlu_halted_f = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + interrupt_valid_r_d1 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + debug_resume_req_f = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + dcsr_single_step_running_f = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + pmu_fw_halt_req_f = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + internal_pmu_fw_halt_mode_f = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + tlu_flush_lower_r_d1 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + ic_perr_r_d1 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + iccm_sbecc_r_d1 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + request_debug_mode_r_d1 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + iccm_repair_state_d1 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + dec_pause_state_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + dec_tlu_wr_pause_r_d1 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + exc_or_int_valid_r_d1 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + pause_expired_wb = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + lsu_pmu_load_external_r = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + lsu_pmu_store_external_r = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_32 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + internal_dbg_halt_mode_f2 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_33 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + nmi_lsu_load_type_f = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + nmi_lsu_store_type_f = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + mpc_debug_halt_req_sync_f = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + mpc_debug_run_req_sync_f = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + mpc_run_state_f = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + debug_brkpt_status_f = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mpc_debug_halt_ack_f = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mpc_debug_run_ack_f = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + dbg_run_state_f = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + _T_65 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + request_debug_mode_done_f = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + _T_190 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + _T_353 = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + _T_354 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + _T_355 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + lsu_single_ecc_error_r_d1 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + lsu_i0_exc_r_d1 = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + take_ext_int_start_d2 = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + tlu_flush_path_r_d1 = _RAND_70[30:0]; + _RAND_71 = {1{`RANDOM}}; + i0_exception_valid_r_d1 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + i0_valid_wb = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + trigger_hit_r_d1 = _RAND_73[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dbg_halt_state_f = 1'h0; + end + if (reset) begin + mpc_halt_state_f = 1'h0; + end + if (reset) begin + _T_8 = 7'h0; + end + if (reset) begin + syncro_ff = 7'h0; + end + if (reset) begin + lsu_exc_valid_r_d1 = 1'h0; + end + if (reset) begin + e5_valid = 1'h0; + end + if (reset) begin + debug_mode_status = 1'h0; + end + if (reset) begin + i_cpu_run_req_d1_raw = 1'h0; + end + if (reset) begin + nmi_int_delayed = 1'h0; + end + if (reset) begin + mdseac_locked_f = 1'h0; + end + if (reset) begin + nmi_int_detected_f = 1'h0; + end + if (reset) begin + take_nmi_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d3 = 1'h0; + end + if (reset) begin + int_timer0_int_hold_f = 1'h0; + end + if (reset) begin + int_timer1_int_hold_f = 1'h0; + end + if (reset) begin + i_cpu_halt_req_d1 = 1'h0; + end + if (reset) begin + dbg_halt_req_held = 1'h0; + end + if (reset) begin + ext_int_freeze_d1 = 1'h0; + end + if (reset) begin + reset_detect = 1'h0; + end + if (reset) begin + reset_detected = 1'h0; + end + if (reset) begin + dcsr_single_step_done_f = 1'h0; + end + if (reset) begin + trigger_hit_dmode_r_d1 = 1'h0; + end + if (reset) begin + ebreak_to_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + debug_halt_req_f = 1'h0; + end + if (reset) begin + lsu_idle_any_f = 1'h0; + end + if (reset) begin + ifu_miss_state_idle_f = 1'h0; + end + if (reset) begin + debug_halt_req_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_noredir_r_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_pause_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d1 = 1'h0; + end + if (reset) begin + halt_taken_f = 1'h0; + end + if (reset) begin + dbg_tlu_halted_f = 1'h0; + end + if (reset) begin + pmu_fw_tlu_halted_f = 1'h0; + end + if (reset) begin + interrupt_valid_r_d1 = 1'h0; + end + if (reset) begin + debug_resume_req_f = 1'h0; + end + if (reset) begin + dcsr_single_step_running_f = 1'h0; + end + if (reset) begin + pmu_fw_halt_req_f = 1'h0; + end + if (reset) begin + internal_pmu_fw_halt_mode_f = 1'h0; + end + if (reset) begin + tlu_flush_lower_r_d1 = 1'h0; + end + if (reset) begin + ic_perr_r_d1 = 1'h0; + end + if (reset) begin + iccm_sbecc_r_d1 = 1'h0; + end + if (reset) begin + request_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + iccm_repair_state_d1 = 1'h0; + end + if (reset) begin + dec_pause_state_f = 1'h0; + end + if (reset) begin + dec_tlu_wr_pause_r_d1 = 1'h0; + end + if (reset) begin + exc_or_int_valid_r_d1 = 1'h0; + end + if (reset) begin + pause_expired_wb = 1'h0; + end + if (reset) begin + lsu_pmu_load_external_r = 1'h0; + end + if (reset) begin + lsu_pmu_store_external_r = 1'h0; + end + if (reset) begin + _T_32 = 1'h0; + end + if (reset) begin + internal_dbg_halt_mode_f2 = 1'h0; + end + if (reset) begin + _T_33 = 1'h0; + end + if (reset) begin + nmi_lsu_load_type_f = 1'h0; + end + if (reset) begin + nmi_lsu_store_type_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_req_sync_f = 1'h0; + end + if (reset) begin + mpc_debug_run_req_sync_f = 1'h0; + end + if (reset) begin + mpc_run_state_f = 1'h0; + end + if (reset) begin + debug_brkpt_status_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_ack_f = 1'h0; + end + if (reset) begin + mpc_debug_run_ack_f = 1'h0; + end + if (reset) begin + dbg_run_state_f = 1'h0; + end + if (reset) begin + _T_65 = 1'h0; + end + if (reset) begin + request_debug_mode_done_f = 1'h0; + end + if (reset) begin + _T_190 = 1'h0; + end + if (reset) begin + _T_353 = 1'h0; + end + if (reset) begin + _T_354 = 1'h0; + end + if (reset) begin + _T_355 = 1'h0; + end + if (reset) begin + lsu_single_ecc_error_r_d1 = 1'h0; + end + if (reset) begin + lsu_i0_exc_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d2 = 1'h0; + end + if (reset) begin + tlu_flush_path_r_d1 = 31'h0; + end + if (reset) begin + i0_exception_valid_r_d1 = 1'h0; + end + if (reset) begin + i0_valid_wb = 1'h0; + end + if (reset) begin + trigger_hit_r_d1 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_state_f <= 1'h0; + end else begin + dbg_halt_state_f <= _T_83 & _T_84; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_halt_state_f <= 1'h0; + end else begin + mpc_halt_state_f <= _T_71 & _T_72; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_8 <= 7'h0; + end else begin + _T_8 <= {_T_6,_T_3}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + syncro_ff <= 7'h0; + end else begin + syncro_ff <= _T_8; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_exc_valid_r_d1 <= 1'h0; + end else begin + lsu_exc_valid_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + e5_valid <= 1'h0; + end else begin + e5_valid <= io_dec_tlu_i0_valid_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_mode_status <= 1'h0; + end else begin + debug_mode_status <= debug_halt_req_ns | _T_160; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_run_req_d1_raw <= 1'h0; + end else begin + i_cpu_run_req_d1_raw <= _T_351 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_delayed <= 1'h0; + end else begin + nmi_int_delayed <= syncro_ff[6]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mdseac_locked_f <= 1'h0; + end else begin + mdseac_locked_f <= csr_io_mdseac_locked_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_detected_f <= 1'h0; + end else begin + nmi_int_detected_f <= _T_42 | _T_44; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + take_nmi_r_d1 <= 1'h0; + end else begin + take_nmi_r_d1 <= _T_756 & _T_760; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d3 <= 1'h0; + end else begin + take_ext_int_start_d3 <= take_ext_int_start_d2; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer0_int_hold_f <= 1'h0; + end else begin + int_timer0_int_hold_f <= _T_644 | _T_651; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer1_int_hold_f <= 1'h0; + end else begin + int_timer1_int_hold_f <= _T_654 | _T_661; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_halt_req_d1 <= 1'h0; + end else begin + i_cpu_halt_req_d1 <= _T_347 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_req_held <= 1'h0; + end else begin + dbg_halt_req_held <= _T_106 & ext_int_freeze_d1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ext_int_freeze_d1 <= 1'h0; + end else begin + ext_int_freeze_d1 <= _T_682 | take_ext_int_start_d3; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detect <= 1'h0; + end else begin + reset_detect <= 1'h1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detected <= 1'h0; + end else begin + reset_detected <= reset_detect; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_done_f <= 1'h0; + end else begin + dcsr_single_step_done_f <= _T_174 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + trigger_hit_dmode_r_d1 <= 1'h0; + end else begin + trigger_hit_dmode_r_d1 <= i0_trigger_hit_raw_r & i0_trigger_action_r; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ebreak_to_debug_mode_r_d1 <= 1'h0; + end else begin + ebreak_to_debug_mode_r_d1 <= _T_519 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_f <= 1'h0; + end else begin + debug_halt_req_f <= enter_debug_halt_req | _T_168; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_idle_any_f <= 1'h0; + end else begin + lsu_idle_any_f <= io_lsu_idle_any; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_miss_state_idle_f <= 1'h0; + end else begin + ifu_miss_state_idle_f <= io_ifu_miss_state_idle; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_d1 <= 1'h0; + end else begin + debug_halt_req_d1 <= _T_114 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_noredir_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_noredir_r_d1 <= io_dec_tlu_flush_noredir_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d1 <= 1'h0; + end else begin + take_ext_int_start_d1 <= ext_int_ready & _T_704; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + halt_taken_f <= 1'h0; + end else begin + halt_taken_f <= _T_135 | _T_141; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_tlu_halted_f <= 1'h0; + end else begin + dbg_tlu_halted_f <= _T_164 | _T_166; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_tlu_halted_f <= 1'h0; + end else begin + pmu_fw_tlu_halted_f <= _T_377 & _T_378; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + interrupt_valid_r_d1 <= 1'h0; + end else begin + interrupt_valid_r_d1 <= _T_766 | take_int_timer1_int; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_resume_req_f <= 1'h0; + end else begin + debug_resume_req_f <= _T_165 & _T_121; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_running_f <= 1'h0; + end else begin + dcsr_single_step_running_f <= _T_177 | _T_179; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_halt_req_f <= 1'h0; + end else begin + pmu_fw_halt_req_f <= _T_363 & _T_378; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_pmu_fw_halt_mode_f <= 1'h0; + end else begin + internal_pmu_fw_halt_mode_f <= pmu_fw_halt_req_ns | _T_369; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + tlu_flush_lower_r_d1 <= 1'h0; + end else begin + tlu_flush_lower_r_d1 <= _T_801 | take_ext_int_start; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_perr_r_d1 <= 1'h0; + end else begin + ic_perr_r_d1 <= _T_499 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_sbecc_r_d1 <= 1'h0; + end else begin + iccm_sbecc_r_d1 <= _T_506 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_r_d1 <= 1'h0; + end else begin + request_debug_mode_r_d1 <= _T_180 | _T_182; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_repair_state_d1 <= 1'h0; + end else begin + iccm_repair_state_d1 <= iccm_sbecc_r_d1 | _T_442; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_pause_state_f <= 1'h0; + end else begin + dec_pause_state_f <= io_dec_pause_state; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_wr_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + exc_or_int_valid_r_d1 <= 1'h0; + end else begin + exc_or_int_valid_r_d1 <= _T_855 | mepc_trigger_hit_sel_pc_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + pause_expired_wb <= 1'h0; + end else begin + pause_expired_wb <= _T_227 & _T_228; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_load_external_r <= 1'h0; + end else begin + lsu_pmu_load_external_r <= io_lsu_pmu_load_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_store_external_r <= 1'h0; + end else begin + lsu_pmu_store_external_r <= io_lsu_pmu_store_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_32 <= 1'h0; + end else begin + _T_32 <= _T_427 | i0_trigger_hit_raw_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_dbg_halt_mode_f2 <= 1'h0; + end else begin + internal_dbg_halt_mode_f2 <= debug_mode_status; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_33 <= 1'h0; + end else begin + _T_33 <= csr_io_force_halt; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_load_type_f <= 1'h0; + end else begin + nmi_lsu_load_type_f <= _T_50 | _T_52; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_store_type_f <= 1'h0; + end else begin + nmi_lsu_store_type_f <= _T_58 | _T_60; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_req_sync_f <= 1'h0; + end else begin + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync_raw & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_req_sync_f <= 1'h0; + end else begin + mpc_debug_run_req_sync_f <= syncro_ff[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_run_state_f <= 1'h0; + end else begin + mpc_run_state_f <= _T_76 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_brkpt_status_f <= 1'h0; + end else begin + debug_brkpt_status_f <= _T_92 & _T_94; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_ack_f <= 1'h0; + end else begin + mpc_debug_halt_ack_f <= _T_97 & core_empty; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_ack_f <= 1'h0; + end else begin + mpc_debug_run_ack_f <= _T_102 | _T_103; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_run_state_f <= 1'h0; + end else begin + dbg_run_state_f <= _T_86 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_65 <= 1'h0; + end else begin + _T_65 <= _T & mpc_halt_state_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_done_f <= 1'h0; + end else begin + request_debug_mode_done_f <= _T_183 & _T_136; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_190 <= 1'h0; + end else begin + _T_190 <= _T_170 & dbg_run_state_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_353 <= 1'h0; + end else begin + _T_353 <= _T_376 | _T_386; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_354 <= 1'h0; + end else begin + _T_354 <= i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_355 <= 1'h0; + end else begin + _T_355 <= _T_388 | _T_389; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_single_ecc_error_r_d1 <= 1'h0; + end else begin + lsu_single_ecc_error_r_d1 <= io_lsu_single_ecc_error_incr; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_i0_exc_r_d1 <= 1'h0; + end else begin + lsu_i0_exc_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d2 <= 1'h0; + end else begin + take_ext_int_start_d2 <= take_ext_int_start_d1; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + tlu_flush_path_r_d1 <= 31'h0; + end else if (take_reset) begin + tlu_flush_path_r_d1 <= io_rst_vec; + end else begin + tlu_flush_path_r_d1 <= _T_852; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_exception_valid_r_d1 <= 1'h0; + end else begin + i0_exception_valid_r_d1 <= _T_527 & _T_528; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_valid_wb <= 1'h0; + end else begin + i0_valid_wb <= tlu_i0_commit_cmt & _T_860; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + trigger_hit_r_d1 <= 1'h0; + end else begin + trigger_hit_r_d1 <= |i0_trigger_chain_masked_r; + end + end +endmodule +module el2_dec_trigger( + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input [30:0] io_dec_i0_pc_d, + output [3:0] io_dec_i0_trigger_match_d +); + wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63] + wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127] + wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63] + wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127] + wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63] + wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127] + wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63] + wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127] + wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] + wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 232:45] + wire _T_152 = ~_T_151; // @[el2_lib.scala 232:39] + wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 232:37] + wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 233:52] + wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 233:41] + wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 235:41] + wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 235:78] + wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 235:23] + wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 235:41] + wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 235:78] + wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 235:23] + wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 235:41] + wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 235:78] + wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 235:23] + wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 235:41] + wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 235:78] + wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 235:23] + wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 235:41] + wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 235:78] + wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 235:23] + wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 235:41] + wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 235:78] + wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 235:23] + wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 235:41] + wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 235:78] + wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 235:23] + wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 235:41] + wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 235:78] + wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 235:23] + wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 235:41] + wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 235:78] + wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 235:23] + wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 235:41] + wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 235:78] + wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 235:23] + wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 235:41] + wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 235:78] + wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 235:23] + wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 235:41] + wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 235:78] + wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 235:23] + wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 235:41] + wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 235:78] + wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 235:23] + wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 235:41] + wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 235:78] + wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 235:23] + wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 235:41] + wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 235:78] + wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 235:23] + wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 235:41] + wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 235:78] + wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 235:23] + wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 235:41] + wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 235:78] + wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 235:23] + wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 235:41] + wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 235:78] + wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 235:23] + wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 235:41] + wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 235:78] + wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 235:23] + wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 235:41] + wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 235:78] + wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 235:23] + wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 235:41] + wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 235:78] + wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 235:23] + wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 235:41] + wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 235:78] + wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 235:23] + wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 235:41] + wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 235:78] + wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 235:23] + wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 235:41] + wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 235:78] + wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 235:23] + wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 235:41] + wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 235:78] + wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 235:23] + wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 235:41] + wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 235:78] + wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 235:23] + wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 235:41] + wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 235:78] + wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 235:23] + wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 235:41] + wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 235:78] + wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 235:23] + wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 235:41] + wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 235:78] + wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 235:23] + wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 235:41] + wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 235:78] + wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 235:23] + wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 235:41] + wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 235:78] + wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 235:23] + wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 236:14] + wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 236:14] + wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 236:14] + wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109] + wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] + wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 232:45] + wire _T_411 = ~_T_410; // @[el2_lib.scala 232:39] + wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 232:37] + wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 233:52] + wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 233:41] + wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 235:41] + wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 235:78] + wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 235:23] + wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 235:41] + wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 235:78] + wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 235:23] + wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 235:41] + wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 235:78] + wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 235:23] + wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 235:41] + wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 235:78] + wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 235:23] + wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 235:41] + wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 235:78] + wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 235:23] + wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 235:41] + wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 235:78] + wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 235:23] + wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 235:41] + wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 235:78] + wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 235:23] + wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 235:41] + wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 235:78] + wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 235:23] + wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 235:41] + wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 235:78] + wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 235:23] + wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 235:41] + wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 235:78] + wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 235:23] + wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 235:41] + wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 235:78] + wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 235:23] + wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 235:41] + wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 235:78] + wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 235:23] + wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 235:41] + wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 235:78] + wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 235:23] + wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 235:41] + wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 235:78] + wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 235:23] + wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 235:41] + wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 235:78] + wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 235:23] + wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 235:41] + wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 235:78] + wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 235:23] + wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 235:41] + wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 235:78] + wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 235:23] + wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 235:41] + wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 235:78] + wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 235:23] + wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 235:41] + wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 235:78] + wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 235:23] + wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 235:41] + wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 235:78] + wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 235:23] + wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 235:41] + wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 235:78] + wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 235:23] + wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 235:41] + wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 235:78] + wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 235:23] + wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 235:41] + wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 235:78] + wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 235:23] + wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 235:41] + wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 235:78] + wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 235:23] + wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 235:41] + wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 235:78] + wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 235:23] + wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 235:41] + wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 235:78] + wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 235:23] + wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 235:41] + wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 235:78] + wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 235:23] + wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 235:41] + wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 235:78] + wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 235:23] + wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 235:41] + wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 235:78] + wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 235:23] + wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 235:41] + wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 235:78] + wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 235:23] + wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 235:41] + wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 235:78] + wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 235:23] + wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 236:14] + wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 236:14] + wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 236:14] + wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109] + wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] + wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 232:45] + wire _T_670 = ~_T_669; // @[el2_lib.scala 232:39] + wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 232:37] + wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 233:52] + wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 233:41] + wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 235:41] + wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 235:78] + wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 235:23] + wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 235:41] + wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 235:78] + wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 235:23] + wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 235:41] + wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 235:78] + wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 235:23] + wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 235:41] + wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 235:78] + wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 235:23] + wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 235:41] + wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 235:78] + wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 235:23] + wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 235:41] + wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 235:78] + wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 235:23] + wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 235:41] + wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 235:78] + wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 235:23] + wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 235:41] + wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 235:78] + wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 235:23] + wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 235:41] + wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 235:78] + wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 235:23] + wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 235:41] + wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 235:78] + wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 235:23] + wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 235:41] + wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 235:78] + wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 235:23] + wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 235:41] + wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 235:78] + wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 235:23] + wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 235:41] + wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 235:78] + wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 235:23] + wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 235:41] + wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 235:78] + wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 235:23] + wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 235:41] + wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 235:78] + wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 235:23] + wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 235:41] + wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 235:78] + wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 235:23] + wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 235:41] + wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 235:78] + wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 235:23] + wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 235:41] + wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 235:78] + wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 235:23] + wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 235:41] + wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 235:78] + wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 235:23] + wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 235:41] + wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 235:78] + wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 235:23] + wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 235:41] + wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 235:78] + wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 235:23] + wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 235:41] + wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 235:78] + wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 235:23] + wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 235:41] + wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 235:78] + wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 235:23] + wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 235:41] + wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 235:78] + wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 235:23] + wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 235:41] + wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 235:78] + wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 235:23] + wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 235:41] + wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 235:78] + wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 235:23] + wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 235:41] + wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 235:78] + wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 235:23] + wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 235:41] + wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 235:78] + wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 235:23] + wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 235:41] + wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 235:78] + wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 235:23] + wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 235:41] + wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 235:78] + wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 235:23] + wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 235:41] + wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 235:78] + wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 235:23] + wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 236:14] + wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 236:14] + wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 236:14] + wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109] + wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] + wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 232:45] + wire _T_929 = ~_T_928; // @[el2_lib.scala 232:39] + wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 232:37] + wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 233:52] + wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 233:41] + wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 235:41] + wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 235:78] + wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 235:23] + wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 235:41] + wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 235:78] + wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 235:23] + wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 235:41] + wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 235:78] + wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 235:23] + wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 235:41] + wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 235:78] + wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 235:23] + wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 235:41] + wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 235:78] + wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 235:23] + wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 235:41] + wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 235:78] + wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 235:23] + wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 235:41] + wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 235:78] + wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 235:23] + wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 235:41] + wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 235:78] + wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 235:23] + wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 235:41] + wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 235:78] + wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 235:23] + wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 235:78] + wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 235:23] + wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 235:78] + wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 235:23] + wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 235:78] + wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 235:23] + wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 235:78] + wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 235:23] + wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 235:78] + wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 235:23] + wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 235:78] + wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 235:23] + wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 235:78] + wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 235:23] + wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 235:78] + wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 235:23] + wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 235:78] + wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 235:23] + wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 235:78] + wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 235:23] + wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 235:78] + wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 235:23] + wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 235:78] + wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 235:23] + wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 235:78] + wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 235:23] + wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 235:78] + wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 235:23] + wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 235:78] + wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 235:23] + wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 235:78] + wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 235:23] + wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 235:78] + wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 235:23] + wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 235:78] + wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 235:23] + wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 235:78] + wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 235:23] + wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 235:78] + wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 235:23] + wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 235:78] + wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 235:23] + wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 235:78] + wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 235:23] + wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 236:14] + wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 236:14] + wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 236:14] + wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109] + wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29] +endmodule +module el2_dec( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_lsu_fastint_stall_any, + output io_dec_extint_stall, + output io_dec_i0_decode_d, + output io_dec_pause_state_cg, + input [31:0] io_rst_vec, + input io_nmi_int, + input [31:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [31:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + input io_exu_pmu_i0_br_misp, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_pc4, + input io_lsu_nonblock_load_valid_m, + input [1:0] io_lsu_nonblock_load_tag_m, + input io_lsu_nonblock_load_inv_r, + input [1:0] io_lsu_nonblock_load_inv_tag_r, + input io_lsu_nonblock_load_data_valid, + input io_lsu_nonblock_load_data_error, + input [1:0] io_lsu_nonblock_load_data_tag, + input [31:0] io_lsu_nonblock_load_data, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_error, + input io_lsu_pmu_bus_busy, + input io_lsu_pmu_misaligned_m, + input io_lsu_pmu_load_external_m, + input io_lsu_pmu_store_external_m, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input [31:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_ifu_pmu_instr_aligned, + input io_ifu_pmu_fetch_stall, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_ifu_pmu_bus_trxn, + input io_ifu_ic_error_start, + input io_ifu_iccm_rd_ecc_single_err, + input [3:0] io_lsu_trigger_match_m, + input io_dbg_cmd_valid, + input io_dbg_cmd_write, + input [1:0] io_dbg_cmd_type, + input [31:0] io_dbg_cmd_addr, + input [1:0] io_dbg_cmd_wrdata, + input io_ifu_i0_icaf, + input [1:0] io_ifu_i0_icaf_type, + input io_ifu_i0_icaf_f1, + input io_ifu_i0_dbecc, + input io_lsu_idle_any, + input io_i0_brp_valid, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input io_i0_brp_bank, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, + input [8:0] io_ifu_i0_bp_index, + input [7:0] io_ifu_i0_bp_fghr, + input [4:0] io_ifu_i0_bp_btag, + input io_lsu_error_pkt_r_exc_valid, + input io_lsu_error_pkt_r_single_ecc_error, + input io_lsu_error_pkt_r_inst_type, + input io_lsu_error_pkt_r_exc_type, + input io_lsu_error_pkt_r_mscause, + input io_lsu_error_pkt_r_addr, + input io_lsu_single_ecc_error_incr, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + input [31:0] io_lsu_imprecise_error_addr_any, + input [31:0] io_exu_div_result, + input io_exu_div_wren, + input [31:0] io_exu_csr_rs1_x, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_iccm_dma_sb_error, + input io_exu_flush_final, + input [31:0] io_exu_npc_r, + input [31:0] io_exu_i0_result_x, + input io_ifu_i0_valid, + input [31:0] io_ifu_i0_instr, + input [31:0] io_ifu_i0_pc, + input io_ifu_i0_pc4, + input [31:0] io_exu_i0_pc_x, + input io_mexintpend, + input io_timer_int, + input io_soft_int, + input [7:0] io_pic_claimid, + input [3:0] io_pic_pl, + input io_mhwakeup, + output [3:0] io_dec_tlu_meicurpl, + output [3:0] io_dec_tlu_meipt, + input [69:0] io_ifu_ic_debug_rd_data, + input io_ifu_ic_debug_rd_data_valid, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_ifu_miss_state_idle, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_flush_noredir_r, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_leak_one_r, + output io_dec_tlu_flush_err_r, + output [31:0] io_dec_tlu_meihap, + output io_dec_debug_wdata_rs1_d, + output [31:0] io_dec_dbg_rddata, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + output io_dec_tlu_force_halt, + input [1:0] io_exu_i0_br_hist_r, + input io_exu_i0_br_error_r, + input io_exu_i0_br_start_error_r, + input io_exu_i0_br_valid_r, + input io_exu_i0_br_mp_r, + input io_exu_i0_br_middle_r, + input io_exu_i0_br_way_r, + output io_dec_i0_rs1_en_d, + output io_dec_i0_rs2_en_d, + output [31:0] io_gpr_i0_rs1_d, + output [31:0] io_gpr_i0_rs2_d, + output [31:0] io_dec_i0_immed_d, + output [12:0] io_dec_i0_br_immed_d, + output io_i0_ap_land, + output io_i0_ap_lor, + output io_i0_ap_lxor, + output io_i0_ap_sll, + output io_i0_ap_srl, + output io_i0_ap_sra, + output io_i0_ap_beq, + output io_i0_ap_bne, + output io_i0_ap_blt, + output io_i0_ap_bge, + output io_i0_ap_add, + output io_i0_ap_sub, + output io_i0_ap_slt, + output io_i0_ap_unsign, + output io_i0_ap_jal, + output io_i0_ap_predict_t, + output io_i0_ap_predict_nt, + output io_i0_ap_csr_write, + output io_i0_ap_csr_imm, + output io_dec_i0_alu_decode_d, + output io_dec_i0_select_pc_d, + output [31:0] io_dec_i0_pc_d, + output [1:0] io_dec_i0_rs1_bypass_en_d, + output [1:0] io_dec_i0_rs2_bypass_en_d, + output [31:0] io_dec_i0_rs1_bypass_data_d, + output [31:0] io_dec_i0_rs2_bypass_data_d, + output io_lsu_p_fast_int, + output io_lsu_p_by, + output io_lsu_p_half, + output io_lsu_p_word, + output io_lsu_p_dword, + output io_lsu_p_load, + output io_lsu_p_store, + output io_lsu_p_unsign, + output io_lsu_p_dma, + output io_lsu_p_store_data_bypass_d, + output io_lsu_p_load_ldst_bypass_d, + output io_lsu_p_store_data_bypass_m, + output io_lsu_p_valid, + output io_mul_p_valid, + output io_mul_p_rs1_sign, + output io_mul_p_rs2_sign, + output io_mul_p_low, + output io_mul_p_bext, + output io_mul_p_bdep, + output io_mul_p_clmul, + output io_mul_p_clmulh, + output io_mul_p_clmulr, + output io_mul_p_grev, + output io_mul_p_shfl, + output io_mul_p_unshfl, + output io_mul_p_crc32_b, + output io_mul_p_crc32_h, + output io_mul_p_crc32_w, + output io_mul_p_crc32c_b, + output io_mul_p_crc32c_h, + output io_mul_p_crc32c_w, + output io_mul_p_bfp, + output io_div_p_valid, + output io_div_p_unsign, + output io_div_p_rem, + output io_dec_div_cancel, + output [11:0] io_dec_lsu_offset_d, + output io_dec_csr_ren_d, + output io_dec_tlu_flush_lower_r, + output [31:0] io_dec_tlu_flush_path_r, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_fence_i_r, + output [31:0] io_pred_correct_npc_x, + output io_dec_tlu_br0_r_pkt_valid, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_i0_predict_p_d_misp, + output io_dec_i0_predict_p_d_ataken, + output io_dec_i0_predict_p_d_boffset, + output io_dec_i0_predict_p_d_pc4, + output [1:0] io_dec_i0_predict_p_d_hist, + output [11:0] io_dec_i0_predict_p_d_toffset, + output io_dec_i0_predict_p_d_valid, + output io_dec_i0_predict_p_d_br_error, + output io_dec_i0_predict_p_d_br_start_error, + output [30:0] io_dec_i0_predict_p_d_prett, + output io_dec_i0_predict_p_d_pcall, + output io_dec_i0_predict_p_d_pret, + output io_dec_i0_predict_p_d_pja, + output io_dec_i0_predict_p_d_way, + output [7:0] io_i0_predict_fghr_d, + output [8:0] io_i0_predict_index_d, + output [4:0] io_i0_predict_btag_d, + output io_dec_lsu_valid_raw_d, + output [31:0] io_dec_tlu_mrac_ff, + output [1:0] io_dec_data_en, + output [1:0] io_dec_ctl_en, + input [15:0] io_ifu_i0_cinst, + output io_dec_tlu_external_ldfwd_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_wb_coalescing_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output io_dec_tlu_i0_commit_cmt, + input io_scan_mode +); + wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 352:24] + wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 352:24] + wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 352:24] + wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 352:24] + wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 352:24] + wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 352:24] + wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 352:24] + wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 352:24] + wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 352:24] + wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 352:24] + wire instbuff_io_i0_brp_way; // @[el2_dec.scala 352:24] + wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 352:24] + wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 352:24] + wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 352:24] + wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 352:24] + wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 352:24] + wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 352:24] + wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 352:24] + wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 352:24] + wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 352:24] + wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 352:24] + wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 352:24] + wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:24] + wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 352:24] + wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 352:24] + wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 352:24] + wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 352:24] + wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 352:24] + wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 352:24] + wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 352:24] + wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 352:24] + wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 352:24] + wire decode_clock; // @[el2_dec.scala 353:22] + wire decode_reset; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 353:22] + wire decode_io_dec_extint_stall; // @[el2_dec.scala 353:22] + wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 353:22] + wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 353:22] + wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 353:22] + wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 353:22] + wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 353:22] + wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 353:22] + wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 353:22] + wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 353:22] + wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 353:22] + wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 353:22] + wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 353:22] + wire decode_io_lsu_idle_any; // @[el2_dec.scala 353:22] + wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 353:22] + wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 353:22] + wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 353:22] + wire decode_io_exu_div_wren; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 353:22] + wire decode_io_exu_flush_final; // @[el2_dec.scala 353:22] + wire [30:0] decode_io_exu_i0_pc_x; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 353:22] + wire decode_io_free_clk; // @[el2_dec.scala 353:22] + wire decode_io_active_clk; // @[el2_dec.scala 353:22] + wire decode_io_clk_override; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_land; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_lor; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_lxor; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_sll; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_srl; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_sra; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_beq; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_bne; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_blt; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_bge; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_add; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_sub; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_slt; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_unsign; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_jal; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 353:22] + wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_fast_int; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_by; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_half; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_word; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_load; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_store; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_unsign; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_store_data_bypass_d; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_load_ldst_bypass_d; // @[el2_dec.scala 353:22] + wire decode_io_lsu_p_valid; // @[el2_dec.scala 353:22] + wire decode_io_mul_p_valid; // @[el2_dec.scala 353:22] + wire decode_io_mul_p_rs1_sign; // @[el2_dec.scala 353:22] + wire decode_io_mul_p_rs2_sign; // @[el2_dec.scala 353:22] + wire decode_io_mul_p_low; // @[el2_dec.scala 353:22] + wire decode_io_div_p_valid; // @[el2_dec.scala 353:22] + wire decode_io_div_p_unsign; // @[el2_dec.scala 353:22] + wire decode_io_div_p_rem; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 353:22] + wire decode_io_dec_div_cancel; // @[el2_dec.scala 353:22] + wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 353:22] + wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 353:22] + wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 353:22] + wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 353:22] + wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 353:22] + wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 353:22] + wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_pc4; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_i0_predict_p_d_hist; // @[el2_dec.scala 353:22] + wire [11:0] decode_io_dec_i0_predict_p_d_toffset; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_br_error; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_br_start_error; // @[el2_dec.scala 353:22] + wire [30:0] decode_io_dec_i0_predict_p_d_prett; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_pcall; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_pret; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_pja; // @[el2_dec.scala 353:22] + wire decode_io_dec_i0_predict_p_d_way; // @[el2_dec.scala 353:22] + wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 353:22] + wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 353:22] + wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 353:22] + wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 353:22] + wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 353:22] + wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 353:22] + wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 353:22] + wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 353:22] + wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 353:22] + wire decode_io_dec_pause_state; // @[el2_dec.scala 353:22] + wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 353:22] + wire decode_io_dec_div_active; // @[el2_dec.scala 353:22] + wire decode_io_scan_mode; // @[el2_dec.scala 353:22] + wire gpr_clock; // @[el2_dec.scala 354:19] + wire gpr_reset; // @[el2_dec.scala 354:19] + wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 354:19] + wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 354:19] + wire gpr_io_wen0; // @[el2_dec.scala 354:19] + wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 354:19] + wire [31:0] gpr_io_wd0; // @[el2_dec.scala 354:19] + wire gpr_io_wen1; // @[el2_dec.scala 354:19] + wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 354:19] + wire [31:0] gpr_io_wd1; // @[el2_dec.scala 354:19] + wire gpr_io_wen2; // @[el2_dec.scala 354:19] + wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 354:19] + wire [31:0] gpr_io_wd2; // @[el2_dec.scala 354:19] + wire [31:0] gpr_io_rd0; // @[el2_dec.scala 354:19] + wire [31:0] gpr_io_rd1; // @[el2_dec.scala 354:19] + wire gpr_io_scan_mode; // @[el2_dec.scala 354:19] + wire tlu_clock; // @[el2_dec.scala 355:19] + wire tlu_reset; // @[el2_dec.scala 355:19] + wire tlu_io_active_clk; // @[el2_dec.scala 355:19] + wire tlu_io_free_clk; // @[el2_dec.scala 355:19] + wire tlu_io_scan_mode; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 355:19] + wire tlu_io_nmi_int; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 355:19] + wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 355:19] + wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 355:19] + wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 355:19] + wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 355:19] + wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 355:19] + wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 355:19] + wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 355:19] + wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 355:19] + wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 355:19] + wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 355:19] + wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 355:19] + wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 355:19] + wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 355:19] + wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 355:19] + wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 355:19] + wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 355:19] + wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_exc_valid; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_single_ecc_error; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_inst_type; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_exc_type; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_mscause; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_error_pkt_r_addr; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 355:19] + wire tlu_io_dec_pause_state; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 355:19] + wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 355:19] + wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 355:19] + wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 355:19] + wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 355:19] + wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 355:19] + wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 355:19] + wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 355:19] + wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 355:19] + wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 355:19] + wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 355:19] + wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 355:19] + wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 355:19] + wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 355:19] + wire tlu_io_dbg_halt_req; // @[el2_dec.scala 355:19] + wire tlu_io_dbg_resume_req; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 355:19] + wire tlu_io_lsu_idle_any; // @[el2_dec.scala 355:19] + wire tlu_io_dec_div_active; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 355:19] + wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 355:19] + wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 355:19] + wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 355:19] + wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 355:19] + wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 355:19] + wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 355:19] + wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 355:19] + wire tlu_io_mhwakeup; // @[el2_dec.scala 355:19] + wire tlu_io_mexintpend; // @[el2_dec.scala 355:19] + wire tlu_io_timer_int; // @[el2_dec.scala 355:19] + wire tlu_io_soft_int; // @[el2_dec.scala 355:19] + wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 355:19] + wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 355:19] + wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 355:19] + wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 355:19] + wire [27:0] tlu_io_core_id; // @[el2_dec.scala 355:19] + wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 355:19] + wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 355:19] + wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 355:19] + wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 355:19] + wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 355:19] + wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 355:19] + wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 355:19] + wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 355:19] + wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 355:19] + wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 355:19] + wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 355:19] + wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 355:19] + wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_ifu_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_bus_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 355:19] + wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 355:19] + wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 356:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 356:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 356:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 356:27] + wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 356:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 356:27] + wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 356:27] + wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 356:27] + el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 352:24] + .io_dbg_cmd_valid(instbuff_io_dbg_cmd_valid), + .io_dbg_cmd_write(instbuff_io_dbg_cmd_write), + .io_dbg_cmd_type(instbuff_io_dbg_cmd_type), + .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr), + .io_i0_brp_valid(instbuff_io_i0_brp_valid), + .io_i0_brp_toffset(instbuff_io_i0_brp_toffset), + .io_i0_brp_hist(instbuff_io_i0_brp_hist), + .io_i0_brp_br_error(instbuff_io_i0_brp_br_error), + .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error), + .io_i0_brp_prett(instbuff_io_i0_brp_prett), + .io_i0_brp_way(instbuff_io_i0_brp_way), + .io_i0_brp_ret(instbuff_io_i0_brp_ret), + .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index), + .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr), + .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag), + .io_ifu_i0_valid(instbuff_io_ifu_i0_valid), + .io_ifu_i0_icaf(instbuff_io_ifu_i0_icaf), + .io_ifu_i0_icaf_type(instbuff_io_ifu_i0_icaf_type), + .io_ifu_i0_icaf_f1(instbuff_io_ifu_i0_icaf_f1), + .io_ifu_i0_dbecc(instbuff_io_ifu_i0_dbecc), + .io_ifu_i0_instr(instbuff_io_ifu_i0_instr), + .io_ifu_i0_pc(instbuff_io_ifu_i0_pc), + .io_dec_ib0_valid_d(instbuff_io_dec_ib0_valid_d), + .io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d), + .io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d), + .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d), + .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), + .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret), + .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index), + .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr), + .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag), + .io_dec_i0_icaf_d(instbuff_io_dec_i0_icaf_d), + .io_dec_i0_icaf_f1_d(instbuff_io_dec_i0_icaf_f1_d), + .io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d), + .io_dec_debug_wdata_rs1_d(instbuff_io_dec_debug_wdata_rs1_d), + .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d) + ); + el2_dec_decode_ctl decode ( // @[el2_dec.scala 353:22] + .clock(decode_clock), + .reset(decode_reset), + .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), + .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt), + .io_dec_extint_stall(decode_io_dec_extint_stall), + .io_ifu_i0_cinst(decode_io_ifu_i0_cinst), + .io_lsu_nonblock_load_valid_m(decode_io_lsu_nonblock_load_valid_m), + .io_lsu_nonblock_load_tag_m(decode_io_lsu_nonblock_load_tag_m), + .io_lsu_nonblock_load_inv_r(decode_io_lsu_nonblock_load_inv_r), + .io_lsu_nonblock_load_inv_tag_r(decode_io_lsu_nonblock_load_inv_tag_r), + .io_lsu_nonblock_load_data_valid(decode_io_lsu_nonblock_load_data_valid), + .io_lsu_nonblock_load_data_error(decode_io_lsu_nonblock_load_data_error), + .io_lsu_nonblock_load_data_tag(decode_io_lsu_nonblock_load_data_tag), + .io_lsu_nonblock_load_data(decode_io_lsu_nonblock_load_data), + .io_dec_i0_trigger_match_d(decode_io_dec_i0_trigger_match_d), + .io_dec_tlu_wr_pause_r(decode_io_dec_tlu_wr_pause_r), + .io_dec_tlu_pipelining_disable(decode_io_dec_tlu_pipelining_disable), + .io_lsu_trigger_match_m(decode_io_lsu_trigger_match_m), + .io_lsu_pmu_misaligned_m(decode_io_lsu_pmu_misaligned_m), + .io_dec_tlu_debug_stall(decode_io_dec_tlu_debug_stall), + .io_dec_tlu_flush_leak_one_r(decode_io_dec_tlu_flush_leak_one_r), + .io_dec_debug_fence_d(decode_io_dec_debug_fence_d), + .io_dbg_cmd_wrdata(decode_io_dbg_cmd_wrdata), + .io_dec_i0_icaf_d(decode_io_dec_i0_icaf_d), + .io_dec_i0_icaf_f1_d(decode_io_dec_i0_icaf_f1_d), + .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d), + .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d), + .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid), + .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(decode_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret), + .io_dec_i0_bp_index(decode_io_dec_i0_bp_index), + .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr), + .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag), + .io_lsu_idle_any(decode_io_lsu_idle_any), + .io_lsu_load_stall_any(decode_io_lsu_load_stall_any), + .io_lsu_store_stall_any(decode_io_lsu_store_stall_any), + .io_dma_dccm_stall_any(decode_io_dma_dccm_stall_any), + .io_exu_div_wren(decode_io_exu_div_wren), + .io_dec_tlu_i0_kill_writeb_wb(decode_io_dec_tlu_i0_kill_writeb_wb), + .io_dec_tlu_flush_lower_wb(decode_io_dec_tlu_flush_lower_wb), + .io_dec_tlu_i0_kill_writeb_r(decode_io_dec_tlu_i0_kill_writeb_r), + .io_dec_tlu_flush_lower_r(decode_io_dec_tlu_flush_lower_r), + .io_dec_tlu_flush_pause_r(decode_io_dec_tlu_flush_pause_r), + .io_dec_tlu_presync_d(decode_io_dec_tlu_presync_d), + .io_dec_tlu_postsync_d(decode_io_dec_tlu_postsync_d), + .io_dec_i0_pc4_d(decode_io_dec_i0_pc4_d), + .io_dec_csr_rddata_d(decode_io_dec_csr_rddata_d), + .io_dec_csr_legal_d(decode_io_dec_csr_legal_d), + .io_exu_csr_rs1_x(decode_io_exu_csr_rs1_x), + .io_lsu_result_m(decode_io_lsu_result_m), + .io_lsu_result_corr_r(decode_io_lsu_result_corr_r), + .io_exu_flush_final(decode_io_exu_flush_final), + .io_exu_i0_pc_x(decode_io_exu_i0_pc_x), + .io_dec_i0_instr_d(decode_io_dec_i0_instr_d), + .io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d), + .io_exu_i0_result_x(decode_io_exu_i0_result_x), + .io_free_clk(decode_io_free_clk), + .io_active_clk(decode_io_active_clk), + .io_clk_override(decode_io_clk_override), + .io_dec_i0_rs1_en_d(decode_io_dec_i0_rs1_en_d), + .io_dec_i0_rs2_en_d(decode_io_dec_i0_rs2_en_d), + .io_dec_i0_rs1_d(decode_io_dec_i0_rs1_d), + .io_dec_i0_rs2_d(decode_io_dec_i0_rs2_d), + .io_dec_i0_immed_d(decode_io_dec_i0_immed_d), + .io_dec_i0_br_immed_d(decode_io_dec_i0_br_immed_d), + .io_i0_ap_land(decode_io_i0_ap_land), + .io_i0_ap_lor(decode_io_i0_ap_lor), + .io_i0_ap_lxor(decode_io_i0_ap_lxor), + .io_i0_ap_sll(decode_io_i0_ap_sll), + .io_i0_ap_srl(decode_io_i0_ap_srl), + .io_i0_ap_sra(decode_io_i0_ap_sra), + .io_i0_ap_beq(decode_io_i0_ap_beq), + .io_i0_ap_bne(decode_io_i0_ap_bne), + .io_i0_ap_blt(decode_io_i0_ap_blt), + .io_i0_ap_bge(decode_io_i0_ap_bge), + .io_i0_ap_add(decode_io_i0_ap_add), + .io_i0_ap_sub(decode_io_i0_ap_sub), + .io_i0_ap_slt(decode_io_i0_ap_slt), + .io_i0_ap_unsign(decode_io_i0_ap_unsign), + .io_i0_ap_jal(decode_io_i0_ap_jal), + .io_i0_ap_predict_t(decode_io_i0_ap_predict_t), + .io_i0_ap_predict_nt(decode_io_i0_ap_predict_nt), + .io_i0_ap_csr_write(decode_io_i0_ap_csr_write), + .io_i0_ap_csr_imm(decode_io_i0_ap_csr_imm), + .io_dec_i0_decode_d(decode_io_dec_i0_decode_d), + .io_dec_i0_alu_decode_d(decode_io_dec_i0_alu_decode_d), + .io_dec_i0_rs1_bypass_data_d(decode_io_dec_i0_rs1_bypass_data_d), + .io_dec_i0_rs2_bypass_data_d(decode_io_dec_i0_rs2_bypass_data_d), + .io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r), + .io_dec_i0_wen_r(decode_io_dec_i0_wen_r), + .io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r), + .io_dec_i0_select_pc_d(decode_io_dec_i0_select_pc_d), + .io_dec_i0_rs1_bypass_en_d(decode_io_dec_i0_rs1_bypass_en_d), + .io_dec_i0_rs2_bypass_en_d(decode_io_dec_i0_rs2_bypass_en_d), + .io_lsu_p_fast_int(decode_io_lsu_p_fast_int), + .io_lsu_p_by(decode_io_lsu_p_by), + .io_lsu_p_half(decode_io_lsu_p_half), + .io_lsu_p_word(decode_io_lsu_p_word), + .io_lsu_p_load(decode_io_lsu_p_load), + .io_lsu_p_store(decode_io_lsu_p_store), + .io_lsu_p_unsign(decode_io_lsu_p_unsign), + .io_lsu_p_store_data_bypass_d(decode_io_lsu_p_store_data_bypass_d), + .io_lsu_p_load_ldst_bypass_d(decode_io_lsu_p_load_ldst_bypass_d), + .io_lsu_p_valid(decode_io_lsu_p_valid), + .io_mul_p_valid(decode_io_mul_p_valid), + .io_mul_p_rs1_sign(decode_io_mul_p_rs1_sign), + .io_mul_p_rs2_sign(decode_io_mul_p_rs2_sign), + .io_mul_p_low(decode_io_mul_p_low), + .io_div_p_valid(decode_io_div_p_valid), + .io_div_p_unsign(decode_io_div_p_unsign), + .io_div_p_rem(decode_io_div_p_rem), + .io_div_waddr_wb(decode_io_div_waddr_wb), + .io_dec_div_cancel(decode_io_dec_div_cancel), + .io_dec_lsu_valid_raw_d(decode_io_dec_lsu_valid_raw_d), + .io_dec_lsu_offset_d(decode_io_dec_lsu_offset_d), + .io_dec_csr_ren_d(decode_io_dec_csr_ren_d), + .io_dec_csr_wen_unq_d(decode_io_dec_csr_wen_unq_d), + .io_dec_csr_any_unq_d(decode_io_dec_csr_any_unq_d), + .io_dec_csr_rdaddr_d(decode_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_r(decode_io_dec_csr_wen_r), + .io_dec_csr_wraddr_r(decode_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(decode_io_dec_csr_wrdata_r), + .io_dec_csr_stall_int_ff(decode_io_dec_csr_stall_int_ff), + .io_dec_tlu_i0_valid_r(decode_io_dec_tlu_i0_valid_r), + .io_dec_tlu_packet_r_legal(decode_io_dec_tlu_packet_r_legal), + .io_dec_tlu_packet_r_icaf(decode_io_dec_tlu_packet_r_icaf), + .io_dec_tlu_packet_r_icaf_f1(decode_io_dec_tlu_packet_r_icaf_f1), + .io_dec_tlu_packet_r_icaf_type(decode_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_fence_i(decode_io_dec_tlu_packet_r_fence_i), + .io_dec_tlu_packet_r_i0trigger(decode_io_dec_tlu_packet_r_i0trigger), + .io_dec_tlu_packet_r_pmu_i0_itype(decode_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(decode_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(decode_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(decode_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_dec_tlu_i0_pc_r(decode_io_dec_tlu_i0_pc_r), + .io_dec_illegal_inst(decode_io_dec_illegal_inst), + .io_pred_correct_npc_x(decode_io_pred_correct_npc_x), + .io_dec_i0_predict_p_d_pc4(decode_io_dec_i0_predict_p_d_pc4), + .io_dec_i0_predict_p_d_hist(decode_io_dec_i0_predict_p_d_hist), + .io_dec_i0_predict_p_d_toffset(decode_io_dec_i0_predict_p_d_toffset), + .io_dec_i0_predict_p_d_valid(decode_io_dec_i0_predict_p_d_valid), + .io_dec_i0_predict_p_d_br_error(decode_io_dec_i0_predict_p_d_br_error), + .io_dec_i0_predict_p_d_br_start_error(decode_io_dec_i0_predict_p_d_br_start_error), + .io_dec_i0_predict_p_d_prett(decode_io_dec_i0_predict_p_d_prett), + .io_dec_i0_predict_p_d_pcall(decode_io_dec_i0_predict_p_d_pcall), + .io_dec_i0_predict_p_d_pret(decode_io_dec_i0_predict_p_d_pret), + .io_dec_i0_predict_p_d_pja(decode_io_dec_i0_predict_p_d_pja), + .io_dec_i0_predict_p_d_way(decode_io_dec_i0_predict_p_d_way), + .io_i0_predict_fghr_d(decode_io_i0_predict_fghr_d), + .io_i0_predict_index_d(decode_io_i0_predict_index_d), + .io_i0_predict_btag_d(decode_io_i0_predict_btag_d), + .io_dec_data_en(decode_io_dec_data_en), + .io_dec_ctl_en(decode_io_dec_ctl_en), + .io_dec_pmu_instr_decoded(decode_io_dec_pmu_instr_decoded), + .io_dec_pmu_decode_stall(decode_io_dec_pmu_decode_stall), + .io_dec_pmu_presync_stall(decode_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(decode_io_dec_pmu_postsync_stall), + .io_dec_nonblock_load_wen(decode_io_dec_nonblock_load_wen), + .io_dec_nonblock_load_waddr(decode_io_dec_nonblock_load_waddr), + .io_dec_pause_state(decode_io_dec_pause_state), + .io_dec_pause_state_cg(decode_io_dec_pause_state_cg), + .io_dec_div_active(decode_io_dec_div_active), + .io_scan_mode(decode_io_scan_mode) + ); + el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 354:19] + .clock(gpr_clock), + .reset(gpr_reset), + .io_raddr0(gpr_io_raddr0), + .io_raddr1(gpr_io_raddr1), + .io_wen0(gpr_io_wen0), + .io_waddr0(gpr_io_waddr0), + .io_wd0(gpr_io_wd0), + .io_wen1(gpr_io_wen1), + .io_waddr1(gpr_io_waddr1), + .io_wd1(gpr_io_wd1), + .io_wen2(gpr_io_wen2), + .io_waddr2(gpr_io_waddr2), + .io_wd2(gpr_io_wd2), + .io_rd0(gpr_io_rd0), + .io_rd1(gpr_io_rd1), + .io_scan_mode(gpr_io_scan_mode) + ); + el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 355:19] + .clock(tlu_clock), + .reset(tlu_reset), + .io_active_clk(tlu_io_active_clk), + .io_free_clk(tlu_io_free_clk), + .io_scan_mode(tlu_io_scan_mode), + .io_rst_vec(tlu_io_rst_vec), + .io_nmi_int(tlu_io_nmi_int), + .io_nmi_vec(tlu_io_nmi_vec), + .io_i_cpu_halt_req(tlu_io_i_cpu_halt_req), + .io_i_cpu_run_req(tlu_io_i_cpu_run_req), + .io_lsu_fastint_stall_any(tlu_io_lsu_fastint_stall_any), + .io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned), + .io_ifu_pmu_fetch_stall(tlu_io_ifu_pmu_fetch_stall), + .io_ifu_pmu_ic_miss(tlu_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(tlu_io_ifu_pmu_ic_hit), + .io_ifu_pmu_bus_error(tlu_io_ifu_pmu_bus_error), + .io_ifu_pmu_bus_busy(tlu_io_ifu_pmu_bus_busy), + .io_ifu_pmu_bus_trxn(tlu_io_ifu_pmu_bus_trxn), + .io_dec_pmu_instr_decoded(tlu_io_dec_pmu_instr_decoded), + .io_dec_pmu_decode_stall(tlu_io_dec_pmu_decode_stall), + .io_dec_pmu_presync_stall(tlu_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(tlu_io_dec_pmu_postsync_stall), + .io_lsu_store_stall_any(tlu_io_lsu_store_stall_any), + .io_dma_dccm_stall_any(tlu_io_dma_dccm_stall_any), + .io_dma_iccm_stall_any(tlu_io_dma_iccm_stall_any), + .io_exu_pmu_i0_br_misp(tlu_io_exu_pmu_i0_br_misp), + .io_exu_pmu_i0_br_ataken(tlu_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_pc4(tlu_io_exu_pmu_i0_pc4), + .io_lsu_pmu_bus_trxn(tlu_io_lsu_pmu_bus_trxn), + .io_lsu_pmu_bus_misaligned(tlu_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_error(tlu_io_lsu_pmu_bus_error), + .io_lsu_pmu_bus_busy(tlu_io_lsu_pmu_bus_busy), + .io_lsu_pmu_load_external_m(tlu_io_lsu_pmu_load_external_m), + .io_lsu_pmu_store_external_m(tlu_io_lsu_pmu_store_external_m), + .io_dma_pmu_dccm_read(tlu_io_dma_pmu_dccm_read), + .io_dma_pmu_dccm_write(tlu_io_dma_pmu_dccm_write), + .io_dma_pmu_any_read(tlu_io_dma_pmu_any_read), + .io_dma_pmu_any_write(tlu_io_dma_pmu_any_write), + .io_lsu_fir_addr(tlu_io_lsu_fir_addr), + .io_lsu_fir_error(tlu_io_lsu_fir_error), + .io_iccm_dma_sb_error(tlu_io_iccm_dma_sb_error), + .io_lsu_error_pkt_r_exc_valid(tlu_io_lsu_error_pkt_r_exc_valid), + .io_lsu_error_pkt_r_single_ecc_error(tlu_io_lsu_error_pkt_r_single_ecc_error), + .io_lsu_error_pkt_r_inst_type(tlu_io_lsu_error_pkt_r_inst_type), + .io_lsu_error_pkt_r_exc_type(tlu_io_lsu_error_pkt_r_exc_type), + .io_lsu_error_pkt_r_mscause(tlu_io_lsu_error_pkt_r_mscause), + .io_lsu_error_pkt_r_addr(tlu_io_lsu_error_pkt_r_addr), + .io_lsu_single_ecc_error_incr(tlu_io_lsu_single_ecc_error_incr), + .io_dec_pause_state(tlu_io_dec_pause_state), + .io_lsu_imprecise_error_store_any(tlu_io_lsu_imprecise_error_store_any), + .io_lsu_imprecise_error_load_any(tlu_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_addr_any(tlu_io_lsu_imprecise_error_addr_any), + .io_dec_csr_wen_unq_d(tlu_io_dec_csr_wen_unq_d), + .io_dec_csr_any_unq_d(tlu_io_dec_csr_any_unq_d), + .io_dec_csr_rdaddr_d(tlu_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_r(tlu_io_dec_csr_wen_r), + .io_dec_csr_wraddr_r(tlu_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(tlu_io_dec_csr_wrdata_r), + .io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff), + .io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r), + .io_exu_npc_r(tlu_io_exu_npc_r), + .io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r), + .io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal), + .io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf), + .io_dec_tlu_packet_r_icaf_f1(tlu_io_dec_tlu_packet_r_icaf_f1), + .io_dec_tlu_packet_r_icaf_type(tlu_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_fence_i(tlu_io_dec_tlu_packet_r_fence_i), + .io_dec_tlu_packet_r_i0trigger(tlu_io_dec_tlu_packet_r_i0trigger), + .io_dec_tlu_packet_r_pmu_i0_itype(tlu_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(tlu_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_dec_illegal_inst(tlu_io_dec_illegal_inst), + .io_dec_i0_decode_d(tlu_io_dec_i0_decode_d), + .io_exu_i0_br_hist_r(tlu_io_exu_i0_br_hist_r), + .io_exu_i0_br_error_r(tlu_io_exu_i0_br_error_r), + .io_exu_i0_br_start_error_r(tlu_io_exu_i0_br_start_error_r), + .io_exu_i0_br_valid_r(tlu_io_exu_i0_br_valid_r), + .io_exu_i0_br_mp_r(tlu_io_exu_i0_br_mp_r), + .io_exu_i0_br_middle_r(tlu_io_exu_i0_br_middle_r), + .io_exu_i0_br_way_r(tlu_io_exu_i0_br_way_r), + .io_dec_dbg_cmd_done(tlu_io_dec_dbg_cmd_done), + .io_dec_dbg_cmd_fail(tlu_io_dec_dbg_cmd_fail), + .io_dec_tlu_dbg_halted(tlu_io_dec_tlu_dbg_halted), + .io_dec_tlu_debug_mode(tlu_io_dec_tlu_debug_mode), + .io_dec_tlu_resume_ack(tlu_io_dec_tlu_resume_ack), + .io_dec_tlu_debug_stall(tlu_io_dec_tlu_debug_stall), + .io_dec_tlu_flush_noredir_r(tlu_io_dec_tlu_flush_noredir_r), + .io_dec_tlu_mpc_halted_only(tlu_io_dec_tlu_mpc_halted_only), + .io_dec_tlu_flush_leak_one_r(tlu_io_dec_tlu_flush_leak_one_r), + .io_dec_tlu_flush_err_r(tlu_io_dec_tlu_flush_err_r), + .io_dec_tlu_flush_extint(tlu_io_dec_tlu_flush_extint), + .io_dec_tlu_meihap(tlu_io_dec_tlu_meihap), + .io_dbg_halt_req(tlu_io_dbg_halt_req), + .io_dbg_resume_req(tlu_io_dbg_resume_req), + .io_ifu_miss_state_idle(tlu_io_ifu_miss_state_idle), + .io_lsu_idle_any(tlu_io_lsu_idle_any), + .io_dec_div_active(tlu_io_dec_div_active), + .io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_(tlu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_(tlu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_(tlu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_(tlu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(tlu_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(tlu_io_trigger_pkt_any_3_tdata2), + .io_ifu_ic_error_start(tlu_io_ifu_ic_error_start), + .io_ifu_iccm_rd_ecc_single_err(tlu_io_ifu_iccm_rd_ecc_single_err), + .io_ifu_ic_debug_rd_data(tlu_io_ifu_ic_debug_rd_data), + .io_ifu_ic_debug_rd_data_valid(tlu_io_ifu_ic_debug_rd_data_valid), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_pic_claimid(tlu_io_pic_claimid), + .io_pic_pl(tlu_io_pic_pl), + .io_mhwakeup(tlu_io_mhwakeup), + .io_mexintpend(tlu_io_mexintpend), + .io_timer_int(tlu_io_timer_int), + .io_soft_int(tlu_io_soft_int), + .io_o_cpu_halt_status(tlu_io_o_cpu_halt_status), + .io_o_cpu_halt_ack(tlu_io_o_cpu_halt_ack), + .io_o_cpu_run_ack(tlu_io_o_cpu_run_ack), + .io_o_debug_mode_status(tlu_io_o_debug_mode_status), + .io_core_id(tlu_io_core_id), + .io_mpc_debug_halt_req(tlu_io_mpc_debug_halt_req), + .io_mpc_debug_run_req(tlu_io_mpc_debug_run_req), + .io_mpc_reset_run_req(tlu_io_mpc_reset_run_req), + .io_mpc_debug_halt_ack(tlu_io_mpc_debug_halt_ack), + .io_mpc_debug_run_ack(tlu_io_mpc_debug_run_ack), + .io_debug_brkpt_status(tlu_io_debug_brkpt_status), + .io_dec_tlu_meicurpl(tlu_io_dec_tlu_meicurpl), + .io_dec_tlu_meipt(tlu_io_dec_tlu_meipt), + .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), + .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), + .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid), + .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle), + .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), + .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), + .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt), + .io_dec_tlu_i0_kill_writeb_r(tlu_io_dec_tlu_i0_kill_writeb_r), + .io_dec_tlu_flush_lower_r(tlu_io_dec_tlu_flush_lower_r), + .io_dec_tlu_flush_path_r(tlu_io_dec_tlu_flush_path_r), + .io_dec_tlu_fence_i_r(tlu_io_dec_tlu_fence_i_r), + .io_dec_tlu_wr_pause_r(tlu_io_dec_tlu_wr_pause_r), + .io_dec_tlu_flush_pause_r(tlu_io_dec_tlu_flush_pause_r), + .io_dec_tlu_presync_d(tlu_io_dec_tlu_presync_d), + .io_dec_tlu_postsync_d(tlu_io_dec_tlu_postsync_d), + .io_dec_tlu_mrac_ff(tlu_io_dec_tlu_mrac_ff), + .io_dec_tlu_force_halt(tlu_io_dec_tlu_force_halt), + .io_dec_tlu_perfcnt0(tlu_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(tlu_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(tlu_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(tlu_io_dec_tlu_perfcnt3), + .io_dec_tlu_external_ldfwd_disable(tlu_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_sideeffect_posted_disable(tlu_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(tlu_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_bpred_disable(tlu_io_dec_tlu_bpred_disable), + .io_dec_tlu_wb_coalescing_disable(tlu_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable), + .io_dec_tlu_dma_qos_prty(tlu_io_dec_tlu_dma_qos_prty), + .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(tlu_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override) + ); + el2_dec_trigger dec_trigger ( // @[el2_dec.scala 356:27] + .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_(dec_trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_(dec_trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_(dec_trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_(dec_trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2), + .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d), + .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) + ); + assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 468:40] + assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 478:40] + assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 521:40] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 654:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 655:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 656:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 657:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 658:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 659:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 660:29] + assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 661:29] + assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 662:29] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 653:29] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 653:29] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 653:29] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 653:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 642:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 643:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 644:28] + assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 646:34] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 647:34] + assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 648:34] + assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 649:34] + assign io_dec_tlu_meihap = {{2'd0}, tlu_io_dec_tlu_meihap}; // @[el2_dec.scala 651:29] + assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 392:38] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 709:21] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 640:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 641:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 652:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 652:29] + assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 678:29] + assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 471:40] + assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 472:40] + assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 544:19] + assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 545:19] + assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 475:40] + assign io_dec_i0_br_immed_d = {{1'd0}, decode_io_dec_i0_br_immed_d}; // @[el2_dec.scala 476:40] + assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 477:40] + assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 477:40] + assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 477:40] + assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 477:40] + assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 477:40] + assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 477:40] + assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 477:40] + assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 477:40] + assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 477:40] + assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 477:40] + assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 477:40] + assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 477:40] + assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 477:40] + assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 477:40] + assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 477:40] + assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 477:40] + assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 477:40] + assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 477:40] + assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 477:40] + assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 479:40] + assign io_dec_i0_select_pc_d = decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 485:40] + assign io_dec_i0_pc_d = 32'h0; // @[el2_dec.scala 272:18] + assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 486:40] + assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 487:40] + assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 480:40] + assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 481:40] + assign io_lsu_p_fast_int = decode_io_lsu_p_fast_int; // @[el2_dec.scala 488:40] + assign io_lsu_p_by = decode_io_lsu_p_by; // @[el2_dec.scala 488:40] + assign io_lsu_p_half = decode_io_lsu_p_half; // @[el2_dec.scala 488:40] + assign io_lsu_p_word = decode_io_lsu_p_word; // @[el2_dec.scala 488:40] + assign io_lsu_p_dword = 1'h0; // @[el2_dec.scala 488:40] + assign io_lsu_p_load = decode_io_lsu_p_load; // @[el2_dec.scala 488:40] + assign io_lsu_p_store = decode_io_lsu_p_store; // @[el2_dec.scala 488:40] + assign io_lsu_p_unsign = decode_io_lsu_p_unsign; // @[el2_dec.scala 488:40] + assign io_lsu_p_dma = 1'h0; // @[el2_dec.scala 488:40] + assign io_lsu_p_store_data_bypass_d = decode_io_lsu_p_store_data_bypass_d; // @[el2_dec.scala 488:40] + assign io_lsu_p_load_ldst_bypass_d = decode_io_lsu_p_load_ldst_bypass_d; // @[el2_dec.scala 488:40] + assign io_lsu_p_store_data_bypass_m = 1'h0; // @[el2_dec.scala 488:40] + assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 488:40] + assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 489:40] + assign io_mul_p_rs1_sign = decode_io_mul_p_rs1_sign; // @[el2_dec.scala 489:40] + assign io_mul_p_rs2_sign = decode_io_mul_p_rs2_sign; // @[el2_dec.scala 489:40] + assign io_mul_p_low = decode_io_mul_p_low; // @[el2_dec.scala 489:40] + assign io_mul_p_bext = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_bdep = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_clmul = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_clmulh = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_clmulr = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_grev = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_shfl = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_unshfl = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32_b = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32_h = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32_w = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32c_b = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32c_h = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_crc32c_w = 1'h0; // @[el2_dec.scala 489:40] + assign io_mul_p_bfp = 1'h0; // @[el2_dec.scala 489:40] + assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 490:40] + assign io_div_p_unsign = decode_io_div_p_unsign; // @[el2_dec.scala 490:40] + assign io_div_p_rem = decode_io_div_p_rem; // @[el2_dec.scala 490:40] + assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 492:40] + assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 494:40] + assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 495:40] + assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 670:34] + assign io_dec_tlu_flush_path_r = {{1'd0}, tlu_io_dec_tlu_flush_path_r}; // @[el2_dec.scala 671:34] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 669:34] + assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 672:34] + assign io_pred_correct_npc_x = {{1'd0}, decode_io_pred_correct_npc_x}; // @[el2_dec.scala 507:40] + assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 665:42] + assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 665:42] + assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 665:42] + assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 665:42] + assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 665:42] + assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 665:42] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 679:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 680:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 681:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 682:29] + assign io_dec_i0_predict_p_d_misp = 1'h0; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_ataken = 1'h0; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_boffset = 1'h0; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_pc4 = decode_io_dec_i0_predict_p_d_pc4; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_hist = decode_io_dec_i0_predict_p_d_hist; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_toffset = decode_io_dec_i0_predict_p_d_toffset; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_br_error = decode_io_dec_i0_predict_p_d_br_error; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_br_start_error = decode_io_dec_i0_predict_p_d_br_start_error; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_prett = decode_io_dec_i0_predict_p_d_prett; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_pcall = decode_io_dec_i0_predict_p_d_pcall; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_pret = decode_io_dec_i0_predict_p_d_pret; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_pja = decode_io_dec_i0_predict_p_d_pja; // @[el2_dec.scala 508:40] + assign io_dec_i0_predict_p_d_way = decode_io_dec_i0_predict_p_d_way; // @[el2_dec.scala 508:40] + assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 509:40] + assign io_i0_predict_index_d = {{1'd0}, decode_io_i0_predict_index_d}; // @[el2_dec.scala 510:40] + assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 511:40] + assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 493:40] + assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 677:29] + assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 512:40] + assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 513:40] + assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 688:43] + assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 689:43] + assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 690:43] + assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 691:43] + assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 692:43] + assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 694:35] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 695:35] + assign io_dec_tlu_ifu_clk_override = tlu_io_dec_tlu_ifu_clk_override; // @[el2_dec.scala 697:36] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 698:36] + assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[el2_dec.scala 699:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 700:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 701:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 702:36] + assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 668:34] + assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 363:45] + assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 364:45] + assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 365:45] + assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 366:45] + assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 367:55] + assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 367:55] + assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index[7:0]; // @[el2_dec.scala 368:35] + assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 369:35] + assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 370:35] + assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 372:35] + assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 373:35] + assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 374:35] + assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 375:35] + assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 376:35] + assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 377:35] + assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc[30:0]; // @[el2_dec.scala 378:35] + assign decode_clock = clock; + assign decode_reset = reset; + assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 409:48 el2_dec.scala 650:37] + assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 410:48] + assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 411:48] + assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 412:48] + assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 413:48] + assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 414:48] + assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 415:48] + assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 416:48] + assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 417:48] + assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 418:48] + assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 419:48] + assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 420:48] + assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 421:48 el2_dec.scala 673:35] + assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 422:48] + assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 423:48] + assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 424:48] + assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 425:48 el2_dec.scala 645:36] + assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 426:48] + assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 393:38 el2_dec.scala 427:48] + assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 428:48] + assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 389:38 el2_dec.scala 429:48] + assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 390:38 el2_dec.scala 430:48] + assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 381:38 el2_dec.scala 431:48] + assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 391:38 el2_dec.scala 432:48] + assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 385:38 el2_dec.scala 433:48] + assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] + assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 387:38 el2_dec.scala 435:48] + assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 388:38 el2_dec.scala 436:48] + assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 438:48] + assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 439:48] + assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 440:48] + assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 441:48] + assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 442:48] + assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 443:48 el2_dec.scala 666:42] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 444:48 el2_dec.scala 667:42] + assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 445:48] + assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 446:48] + assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 447:48 el2_dec.scala 674:35] + assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 448:48 el2_dec.scala 675:35] + assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 449:48 el2_dec.scala 676:35] + assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc_d[0]; // @[el2_dec.scala 384:38 el2_dec.scala 450:48] + assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 451:48 el2_dec.scala 663:33] + assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 452:48 el2_dec.scala 664:33] + assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 453:48] + assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 454:48] + assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 455:48] + assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 456:48] + assign decode_io_exu_i0_pc_x = io_exu_i0_pc_x[30:0]; // @[el2_dec.scala 457:48] + assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 382:38 el2_dec.scala 458:48] + assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 380:38 el2_dec.scala 459:48] + assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 460:48] + assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 462:48] + assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 463:48] + assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 464:48] + assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 466:48] + assign gpr_clock = clock; + assign gpr_reset = reset; + assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 473:40 el2_dec.scala 529:23] + assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 474:40 el2_dec.scala 530:23] + assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 483:40 el2_dec.scala 531:23] + assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 482:40 el2_dec.scala 532:23] + assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 484:40 el2_dec.scala 533:23] + assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 534:23] + assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 535:23] + assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 536:23] + assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 537:23] + assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 491:40 el2_dec.scala 538:23] + assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 539:23] + assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 542:23] + assign tlu_clock = clock; + assign tlu_reset = reset; + assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 554:45] + assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 555:45] + assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 557:45] + assign tlu_io_rst_vec = io_rst_vec[30:0]; // @[el2_dec.scala 558:45] + assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 559:45] + assign tlu_io_nmi_vec = io_nmi_vec[30:0]; // @[el2_dec.scala 560:45] + assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 561:45] + assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 562:45] + assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 563:45] + assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 564:45] + assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 565:45] + assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 566:45] + assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 567:45] + assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 568:45] + assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 569:45] + assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 570:45] + assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 571:45] + assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 572:45] + assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 573:45] + assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 514:40 el2_dec.scala 515:40 el2_dec.scala 516:40 el2_dec.scala 517:40 el2_dec.scala 518:40 el2_dec.scala 519:40 el2_dec.scala 520:40 el2_dec.scala 574:45] + assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 575:45] + assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 576:45] + assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 577:45] + assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 578:45] + assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 579:45] + assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 580:45] + assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 581:45] + assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 582:45] + assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 583:45] + assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 584:45] + assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 585:45] + assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 586:45] + assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 587:45] + assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 588:45] + assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 589:45] + assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 590:45] + assign tlu_io_lsu_fir_addr = io_lsu_fir_addr[30:0]; // @[el2_dec.scala 591:45] + assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 592:45] + assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 593:45] + assign tlu_io_lsu_error_pkt_r_exc_valid = io_lsu_error_pkt_r_exc_valid; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_error_pkt_r_single_ecc_error = io_lsu_error_pkt_r_single_ecc_error; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_error_pkt_r_inst_type = io_lsu_error_pkt_r_inst_type; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_error_pkt_r_exc_type = io_lsu_error_pkt_r_exc_type; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_error_pkt_r_mscause = io_lsu_error_pkt_r_mscause; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_error_pkt_r_addr = io_lsu_error_pkt_r_addr; // @[el2_dec.scala 594:45] + assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 595:45] + assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 596:45] + assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 597:45] + assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 598:45] + assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 599:45] + assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 496:40 el2_dec.scala 600:45] + assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 497:40 el2_dec.scala 601:45] + assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 498:40 el2_dec.scala 602:45] + assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 499:40 el2_dec.scala 603:45] + assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 500:40 el2_dec.scala 604:45] + assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 501:40 el2_dec.scala 605:45] + assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 502:40 el2_dec.scala 606:45] + assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 503:40 el2_dec.scala 607:45] + assign tlu_io_exu_npc_r = io_exu_npc_r[30:0]; // @[el2_dec.scala 608:45] + assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 505:40 el2_dec.scala 609:45] + assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 504:40 el2_dec.scala 610:45] + assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 506:40 el2_dec.scala 611:45] + assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 612:45] + assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 613:45] + assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 614:45] + assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 615:45] + assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 616:45] + assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 617:45] + assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 618:45] + assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 619:45] + assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 620:45] + assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 621:45] + assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 622:45] + assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 623:45] + assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 522:40 el2_dec.scala 624:45] + assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 625:45] + assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 626:45] + assign tlu_io_ifu_ic_debug_rd_data = {{1'd0}, io_ifu_ic_debug_rd_data}; // @[el2_dec.scala 627:45] + assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 628:45] + assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 629:45] + assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 630:45] + assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 631:45] + assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 632:45] + assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 633:45] + assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 634:45] + assign tlu_io_core_id = io_core_id[27:0]; // @[el2_dec.scala 635:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 636:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 637:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 638:45] + assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 400:34] + assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 400:34] + assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 399:30] +endmodule diff --git a/el2_dec_decode_ctl.anno.json b/el2_dec_decode_ctl.anno.json new file mode 100644 index 00000000..516262af --- /dev/null +++ b/el2_dec_decode_ctl.anno.json @@ -0,0 +1,1492 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_pmu_decode_stall", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_decode_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_load_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dma_dccm_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_store_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_csr_any_unq_d", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_alu_decode_d", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_csr_legal_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_predict_p_d_valid", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_decode_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_csr_legal_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_load_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dma_dccm_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_store_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_pred_correct_npc_x", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_exu_i0_pc_x" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_csr_write", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_add", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_predict_p_d_pja", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + 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] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_slt", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_bypass_data_d", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data", + 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"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_nonblock_load_wen", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_nonblock_load_waddr", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_i0_kill_writeb_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_wb" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_predict_p_d_pret", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_predict_t", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ctl_en", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_clk_override", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_decode_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_load_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dma_dccm_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_store_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_decode_ctl.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_decode_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_decode_ctl.fir b/el2_dec_decode_ctl.fir new file mode 100644 index 00000000..99e07259 --- /dev/null +++ b/el2_dec_decode_ctl.fir @@ -0,0 +1,5032 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_decode_ctl : + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_dec_ctl : + input clock : Clock + input reset : Reset + output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] + node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] + node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] + node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] + node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] + node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] + node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] + node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] + node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] + node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] + node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] + node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] + node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] + node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] + node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] + node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] + node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] + node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] + node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] + node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] + node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] + node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] + node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] + node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] + node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] + io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] + node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] + node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] + node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] + node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] + node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] + io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] + node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] + node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] + node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] + node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] + node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] + node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] + node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] + node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] + node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] + node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] + node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] + node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] + node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] + io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] + node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] + node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] + node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] + node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] + node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] + node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] + node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] + node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] + node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] + node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] + io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] + node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] + node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] + node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] + io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] + node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] + node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] + node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] + node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] + node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] + node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] + node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] + io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] + node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] + node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] + node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] + node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] + node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] + node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] + node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] + node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] + node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] + node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] + node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] + io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] + node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] + node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] + io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] + node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] + node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] + io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] + node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] + node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] + io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] + node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] + node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] + node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] + node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] + node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] + node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] + node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] + node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] + node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] + node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] + node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] + node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] + node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] + io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] + node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] + node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] + node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] + node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] + node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] + node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] + node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] + node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] + node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] + node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] + node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] + node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] + node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] + node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] + node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] + io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] + node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] + node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] + node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] + node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] + node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] + node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] + node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] + node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] + node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] + io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] + node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] + node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] + node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] + node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] + node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] + node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] + node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] + node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] + node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] + node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] + node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] + node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] + node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] + node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] + node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] + node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] + node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] + node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] + io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] + node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] + node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] + node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] + node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] + node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] + node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] + node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] + node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] + node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] + io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] + node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] + node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] + node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] + node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] + io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] + node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] + node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] + node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] + node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] + io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] + node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] + node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] + node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] + node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] + node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] + io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] + node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] + node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] + node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] + node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] + node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] + node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] + node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] + node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] + node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] + node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] + node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] + io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] + node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] + node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] + node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] + node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] + node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] + node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] + node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] + node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] + node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] + node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] + node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] + node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] + node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] + node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] + node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] + node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] + node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] + node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] + node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] + node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] + node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] + node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] + node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] + io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] + node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] + node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] + io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] + node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] + node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] + node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] + node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] + io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] + node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] + node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] + node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] + node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] + io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] + node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] + node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] + node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] + node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] + io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] + node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] + node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] + node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] + node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] + io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] + node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] + io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] + node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] + node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] + node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] + node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] + io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] + node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] + node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] + node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] + io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] + node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] + node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] + io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] + node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] + node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] + node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] + node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] + node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] + node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] + node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] + node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] + node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] + node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] + node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] + node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] + node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] + node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] + node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] + node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] + node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] + io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] + node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] + node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] + node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] + node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] + node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] + node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] + node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] + node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] + node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] + node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] + node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] + node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] + node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] + node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] + node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] + node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] + node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] + node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] + node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] + node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] + node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] + node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] + io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] + node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] + node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] + io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] + node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] + node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] + node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] + node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] + node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] + node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] + node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] + node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] + node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] + node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] + node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] + node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] + node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] + node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] + node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] + node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] + node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] + io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] + node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] + node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] + node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] + node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] + node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] + node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] + node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] + node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] + node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] + node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] + node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] + node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] + node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] + node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] + io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] + node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] + node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] + node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] + io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] + node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] + node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] + node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] + io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] + node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] + node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] + io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] + node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] + node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] + node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] + io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] + node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] + node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] + node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] + node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] + node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] + node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] + node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] + node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] + node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] + node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] + io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] + node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] + node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] + node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] + node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] + io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] + node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] + node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] + node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] + node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] + io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] + node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] + node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] + node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] + io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] + node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] + node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] + node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] + node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] + io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] + node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] + io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] + node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] + node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] + io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] + node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] + node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] + node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] + node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] + node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] + node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] + node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] + node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] + node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] + node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] + io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] + node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] + node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] + node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] + node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] + node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] + node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] + node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] + node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] + node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] + node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] + node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] + node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] + node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] + node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] + node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] + node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] + node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] + node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] + node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] + node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] + node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] + node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] + node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] + node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] + node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] + node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] + node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] + node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] + node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] + node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] + node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] + node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] + node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] + node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] + node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] + node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] + node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] + node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] + node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] + io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] + node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] + node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] + node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] + node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] + node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] + node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] + node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] + node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] + node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] + node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] + node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] + node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] + node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] + node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] + node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] + node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] + node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] + node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] + node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] + node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] + node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] + node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] + node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] + node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] + node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] + node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] + node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] + node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] + node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] + node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] + node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] + node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] + node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] + node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] + node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] + node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] + node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] + node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] + node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] + node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] + node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] + io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] + node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] + node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] + node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] + node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] + node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] + node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] + node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] + node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] + node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] + node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] + node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] + node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] + node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] + node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] + node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] + node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] + node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] + node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] + node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] + node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] + node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] + node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] + node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] + node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] + node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] + node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] + node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] + node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] + node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] + node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] + node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] + node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] + node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] + node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] + node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] + node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] + node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] + node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] + node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] + node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] + node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] + node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] + node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] + node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] + node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] + node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] + node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] + node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] + node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] + node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] + node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] + node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] + node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] + node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] + node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] + node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] + node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] + node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] + node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] + node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] + node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] + node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] + node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] + node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] + node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] + node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] + node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] + node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] + node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] + node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] + node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] + node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] + node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] + node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] + node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] + node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] + node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] + node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] + node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] + node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] + node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] + node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] + node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] + node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] + node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] + node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] + node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] + node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] + node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] + node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] + node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] + node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] + node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] + node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] + node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] + node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] + node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] + node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] + node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] + node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] + node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] + node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] + node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] + node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] + node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] + node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] + node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] + node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] + node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] + node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] + node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] + node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] + node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] + node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] + node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] + node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] + node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] + node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] + node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] + node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] + node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] + node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] + node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] + node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] + node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] + node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] + node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] + node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] + node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] + node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] + node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] + node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] + node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] + node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] + node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] + node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] + node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] + node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] + node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] + node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] + node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] + node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] + node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] + node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] + node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] + node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] + node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] + node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] + node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] + node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] + node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] + node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] + node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] + node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] + node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] + node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] + node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] + node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] + node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] + node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] + node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] + node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] + node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] + node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] + node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] + node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] + node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] + node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] + node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] + node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] + node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] + node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] + node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] + node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] + node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] + node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] + node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] + node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] + node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] + node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] + node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] + node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] + node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] + node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] + node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] + node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] + node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] + node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] + node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] + node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] + node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] + node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] + node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] + node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] + node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] + node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] + node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] + node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] + node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] + node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] + node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] + node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] + node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] + node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] + node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] + node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] + node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] + node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] + node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] + node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] + node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] + node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] + node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] + node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] + node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] + node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] + node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] + node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] + node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] + node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] + node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] + node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] + node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] + node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] + node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] + node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] + node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] + node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] + node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] + node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] + node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] + node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] + node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] + node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] + node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] + node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] + node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] + node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] + node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] + node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] + node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] + node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] + node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] + node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] + node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] + node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] + node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] + node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] + node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] + node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] + node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] + node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] + node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] + node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] + node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] + node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] + node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] + node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] + node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] + node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] + node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] + node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] + node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] + node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] + node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] + node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] + node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] + node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] + node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] + node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] + node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] + io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_decode_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + + wire _T : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>} @[el2_dec_decode_ctl.scala 126:27] + _T.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.unshfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.shfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.grev <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulh <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bdep <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bext <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + io.mul_p.bfp <= _T.bfp @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_w <= _T.crc32c_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_h <= _T.crc32c_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_b <= _T.crc32c_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_w <= _T.crc32_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_h <= _T.crc32_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_b <= _T.crc32_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.unshfl <= _T.unshfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.shfl <= _T.shfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.grev <= _T.grev @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulr <= _T.clmulr @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulh <= _T.clmulh @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmul <= _T.clmul @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bdep <= _T.bdep @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bext <= _T.bext @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.low <= _T.low @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs2_sign <= _T.rs2_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs1_sign <= _T.rs1_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.valid <= _T.valid @[el2_dec_decode_ctl.scala 126:12] + wire leak1_i1_stall_in : UInt<1> + leak1_i1_stall_in <= UInt<1>("h00") + wire leak1_i0_stall_in : UInt<1> + leak1_i0_stall_in <= UInt<1>("h00") + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 130:17] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 131:17] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 132:17] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] + wire i0_rs1_depth_d : UInt<2> + i0_rs1_depth_d <= UInt<1>("h00") + wire i0_rs2_depth_d : UInt<2> + i0_rs2_depth_d <= UInt<1>("h00") + wire cam_wen : UInt<4> + cam_wen <= UInt<1>("h00") + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam_write : UInt<1> + cam_write <= UInt<1>("h00") + wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] + wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] + wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] + wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] + wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] + wire i0_rs1bypass : UInt<3> + i0_rs1bypass <= UInt<1>("h00") + wire i0_rs2bypass : UInt<3> + i0_rs2bypass <= UInt<1>("h00") + wire illegal_lockout : UInt<1> + illegal_lockout <= UInt<1>("h00") + wire postsync_stall : UInt<1> + postsync_stall <= UInt<1>("h00") + wire ps_stall_in : UInt<1> + ps_stall_in <= UInt<1>("h00") + wire i0_pipe_en : UInt<4> + i0_pipe_en <= UInt<1>("h00") + wire i0_load_block_d : UInt<1> + i0_load_block_d <= UInt<1>("h00") + wire load_ldst_bypass_d : UInt<1> + load_ldst_bypass_d <= UInt<1>("h00") + wire store_data_bypass_d : UInt<1> + store_data_bypass_d <= UInt<1>("h00") + wire store_data_bypass_m : UInt<1> + store_data_bypass_m <= UInt<1>("h00") + wire tlu_wr_pause_r1 : UInt<1> + tlu_wr_pause_r1 <= UInt<1>("h00") + wire tlu_wr_pause_r2 : UInt<1> + tlu_wr_pause_r2 <= UInt<1>("h00") + wire leak1_i1_stall : UInt<1> + leak1_i1_stall <= UInt<1>("h00") + wire leak1_i0_stall : UInt<1> + leak1_i0_stall <= UInt<1>("h00") + wire pause_stall : UInt<1> + pause_stall <= UInt<1>("h00") + wire flush_final_r : UInt<1> + flush_final_r <= UInt<1>("h00") + wire illegal_lockout_in : UInt<1> + illegal_lockout_in <= UInt<1>("h00") + wire lsu_idle : UInt<1> + lsu_idle <= UInt<1>("h00") + wire pause_state_in : UInt<1> + pause_state_in <= UInt<1>("h00") + wire leak1_mode : UInt<1> + leak1_mode <= UInt<1>("h00") + wire i0_pcall : UInt<1> + i0_pcall <= UInt<1>("h00") + wire i0_pja : UInt<1> + i0_pja <= UInt<1>("h00") + wire i0_pret : UInt<1> + i0_pret <= UInt<1>("h00") + wire i0_legal_decode_d : UInt<1> + i0_legal_decode_d <= UInt<1>("h00") + wire i0_pcall_raw : UInt<1> + i0_pcall_raw <= UInt<1>("h00") + wire i0_pja_raw : UInt<1> + i0_pja_raw <= UInt<1>("h00") + wire i0_pret_raw : UInt<1> + i0_pret_raw <= UInt<1>("h00") + wire i0_br_offset : UInt<12> + i0_br_offset <= UInt<1>("h00") + wire i0_csr_write_only_d : UInt<1> + i0_csr_write_only_d <= UInt<1>("h00") + wire i0_jal : UInt<1> + i0_jal <= UInt<1>("h00") + wire i0_wen_r : UInt<1> + i0_wen_r <= UInt<1>("h00") + wire i0_x_ctl_en : UInt<1> + i0_x_ctl_en <= UInt<1>("h00") + wire i0_r_ctl_en : UInt<1> + i0_r_ctl_en <= UInt<1>("h00") + wire i0_wb_ctl_en : UInt<1> + i0_wb_ctl_en <= UInt<1>("h00") + wire i0_x_data_en : UInt<1> + i0_x_data_en <= UInt<1>("h00") + wire i0_r_data_en : UInt<1> + i0_r_data_en <= UInt<1>("h00") + wire i0_wb_data_en : UInt<1> + i0_wb_data_en <= UInt<1>("h00") + wire i0_wb1_data_en : UInt<1> + i0_wb1_data_en <= UInt<1>("h00") + wire i0_nonblock_load_stall : UInt<1> + i0_nonblock_load_stall <= UInt<1>("h00") + wire csr_read : UInt<1> + csr_read <= UInt<1>("h00") + wire lsu_decode_d : UInt<1> + lsu_decode_d <= UInt<1>("h00") + wire mul_decode_d : UInt<1> + mul_decode_d <= UInt<1>("h00") + wire div_decode_d : UInt<1> + div_decode_d <= UInt<1>("h00") + wire write_csr_data : UInt<32> + write_csr_data <= UInt<1>("h00") + wire i0_result_corr_r : UInt<32> + i0_result_corr_r <= UInt<1>("h00") + wire presync_stall : UInt<1> + presync_stall <= UInt<1>("h00") + wire i0_nonblock_div_stall : UInt<1> + i0_nonblock_div_stall <= UInt<1>("h00") + wire debug_fence : UInt<1> + debug_fence <= UInt<1>("h00") + wire i0_immed_d : UInt<32> + i0_immed_d <= UInt<1>("h00") + wire i0_result_x : UInt<32> + i0_result_x <= UInt<1>("h00") + wire i0_result_r : UInt<32> + i0_result_r <= UInt<1>("h00") + node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[el2_dec_decode_ctl.scala 211:51] + node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[el2_dec_decode_ctl.scala 212:32] + node _T_3 = or(_T_1, _T_2) @[el2_dec_decode_ctl.scala 211:73] + node _T_4 = xor(io.dec_tlu_flush_extint, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 213:32] + node _T_5 = or(_T_3, _T_4) @[el2_dec_decode_ctl.scala 212:56] + node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[el2_dec_decode_ctl.scala 214:32] + node _T_7 = or(_T_5, _T_6) @[el2_dec_decode_ctl.scala 213:56] + node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[el2_dec_decode_ctl.scala 215:32] + node _T_9 = or(_T_7, _T_8) @[el2_dec_decode_ctl.scala 214:56] + node _T_10 = xor(pause_state_in, pause_stall) @[el2_dec_decode_ctl.scala 216:32] + node _T_11 = or(_T_9, _T_10) @[el2_dec_decode_ctl.scala 215:56] + node _T_12 = xor(ps_stall_in, postsync_stall) @[el2_dec_decode_ctl.scala 217:32] + node _T_13 = or(_T_11, _T_12) @[el2_dec_decode_ctl.scala 216:56] + node _T_14 = xor(io.exu_flush_final, flush_final_r) @[el2_dec_decode_ctl.scala 218:32] + node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56] + node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32] + node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56] + inst data_gated_cgc of rvclkhdr @[el2_dec_decode_ctl.scala 221:29] + data_gated_cgc.clock <= clock + data_gated_cgc.reset <= reset + data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 222:31] + data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 223:31] + data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 224:31] + node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 229:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 229:60] + io.dec_i0_predict_p_d.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 230:38] + io.dec_i0_predict_p_d.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:38] + io.dec_i0_predict_p_d.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:38] + io.dec_i0_predict_p_d.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 233:38] + io.dec_i0_predict_p_d.pja <= i0_pja @[el2_dec_decode_ctl.scala 234:38] + io.dec_i0_predict_p_d.pret <= i0_pret @[el2_dec_decode_ctl.scala 235:38] + io.dec_i0_predict_p_d.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 236:38] + io.dec_i0_predict_p_d.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 237:38] + io.dec_i0_predict_p_d.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 238:38] + node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 239:55] + io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 239:38] + node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 240:75] + node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 240:90] + node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 240:103] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:56] + node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 240:54] + node _T_23 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 243:67] + node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 243:47] + node _T_25 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 243:96] + node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 243:71] + node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:116] + node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 243:114] + node _T_28 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 244:47] + node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:69] + node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 244:67] + node _T_30 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 245:57] + node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 245:74] + node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 245:96] + node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 246:67] + node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 246:89] + node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 246:87] + io.dec_i0_predict_p_d.br_error <= _T_34 @[el2_dec_decode_ctl.scala 246:51] + node _T_35 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:84] + node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:106] + node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 247:104] + io.dec_i0_predict_p_d.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 247:51] + io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 248:32] + io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 249:32] + node _T_38 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 250:47] + node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 250:81] + node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 250:79] + io.dec_i0_predict_p_d.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 251:44] + io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 252:32] + io.dec_i0_predict_p_d.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 253:51] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 259:36] + i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 262:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 262:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 262:9] + i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 262:9] + i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 262:9] + i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 262:9] + i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 262:9] + i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 262:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 262:9] + i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 262:9] + i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 262:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 262:9] + i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 262:9] + i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 262:9] + i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 262:9] + i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 262:9] + i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 262:9] + i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 262:9] + i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 262:9] + i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 262:9] + i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 262:9] + i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 262:9] + i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 262:9] + i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 262:9] + i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 262:9] + i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 262:9] + i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 262:9] + i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 262:9] + i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 262:9] + i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 262:9] + i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 262:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 262:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 262:9] + i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 262:9] + node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 263:25] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 263:43] + when _T_41 : @[el2_dec_decode_ctl.scala 263:50] + wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 264:35] + _T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + _T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 264:35] + i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 264:20] + i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 264:20] + i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 264:20] + i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 264:20] + i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 264:20] + i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 264:20] + i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 264:20] + i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 264:20] + i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 264:20] + i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 264:20] + i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 264:20] + i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 264:20] + i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 264:20] + i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 264:20] + i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 264:20] + i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 264:20] + i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 264:20] + i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 264:20] + i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 264:20] + i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 264:20] + i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 264:20] + i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 264:20] + i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 264:20] + i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 264:20] + i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 264:20] + i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 264:20] + i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 264:20] + i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 264:20] + i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 264:20] + i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 264:20] + i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 264:20] + i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] + i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] + i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20] + i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20] + i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20] + skip @[el2_dec_decode_ctl.scala 263:50] + io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 274:25] + node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 277:38] + node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 277:49] + node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 277:58] + node _T_45 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 279:46] + node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 279:50] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 279:26] + node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 279:66] + node _T_48 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:46] + node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:50] + node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 280:66] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 281:20] + io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 283:26] + io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 284:26] + io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 286:20] + io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 287:20] + io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 288:20] + io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 289:20] + io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 290:20] + io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 291:20] + io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 292:20] + io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 293:20] + io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 294:20] + io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 295:20] + io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 296:20] + io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 297:20] + io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 298:20] + io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 299:20] + io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 300:22] + io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 301:22] + io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 302:22] + node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 306:158] + node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 306:126] + node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 306:158] + node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 306:126] + node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 306:126] + node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 306:158] + node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 306:78] + node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 306:126] + node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 306:126] + node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 306:120] + node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 306:129] + node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 306:126] + node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 306:137] + node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 306:158] + node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72] + node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] + node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72] + wire _T_87 : UInt<4> @[Mux.scala 27:72] + _T_87 <= _T_86 @[Mux.scala 27:72] + cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 306:11] + cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 308:25] + node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 309:54] + node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 312:59] + node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 314:63] + node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 315:60] + node _T_88 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 317:43] + node nonblock_load_rd = mux(_T_88, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 317:31] + node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 321:116] + reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_89 : @[Reg.scala 28:19] + nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 322:56] + node _T_90 = eq(cam_inv_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 324:45] + node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 324:26] + node _T_93 = eq(cam_data_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 325:45] + node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 325:27] + wire _T_96 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_96.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[0].rd <= _T_96.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].tag <= _T_96.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].wb <= _T_96.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 326:14] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 327:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 327:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 327:11] + cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_97 : @[el2_dec_decode_ctl.scala 329:39] + cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 332:17] + node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_99 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_102 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 337:64] + node _T_104 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 337:95] + node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 337:44] + when _T_106 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 342:44] + node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 342:95] + when _T_111 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_112 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_112.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 350:47] + _T_113.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 350:47] + _T_113.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 350:47] + _T_113.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 350:47] + _T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[0].rd <= _T_113.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].tag <= _T_113.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].wb <= _T_113.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 351:28] + node _T_116 = eq(cam_inv_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 324:45] + node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 324:26] + node _T_119 = eq(cam_data_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 325:45] + node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 325:27] + wire _T_122 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_122.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[1].rd <= _T_122.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].tag <= _T_122.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].wb <= _T_122.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 326:14] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 327:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 327:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 327:11] + cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_123 : @[el2_dec_decode_ctl.scala 329:39] + cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 332:17] + node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_125 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_128 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 337:64] + node _T_130 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 337:95] + node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 337:44] + when _T_132 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 342:44] + node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 342:95] + when _T_137 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_138 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_138.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 350:47] + _T_139.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 350:47] + _T_139.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 350:47] + _T_139.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 350:47] + _T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[1].rd <= _T_139.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].tag <= _T_139.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].wb <= _T_139.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 351:28] + node _T_142 = eq(cam_inv_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 324:45] + node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 324:26] + node _T_145 = eq(cam_data_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 325:45] + node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 325:27] + wire _T_148 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_148.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[2].rd <= _T_148.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].tag <= _T_148.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].wb <= _T_148.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 326:14] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 327:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 327:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 327:11] + cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_149 : @[el2_dec_decode_ctl.scala 329:39] + cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 332:17] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_151 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_154 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 337:64] + node _T_156 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 337:95] + node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 337:44] + when _T_158 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 342:44] + node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 342:95] + when _T_163 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_164 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_164.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 350:47] + _T_165.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 350:47] + _T_165.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 350:47] + _T_165.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 350:47] + _T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[2].rd <= _T_165.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].tag <= _T_165.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].wb <= _T_165.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 351:28] + node _T_168 = eq(cam_inv_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 324:66] + node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 324:45] + node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 324:82] + cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 324:26] + node _T_171 = eq(cam_data_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 325:67] + node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 325:45] + node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 325:83] + cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 325:27] + wire _T_174 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 326:28] + _T_174.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + _T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 326:28] + cam_in[3].rd <= _T_174.rd @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].tag <= _T_174.tag @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].wb <= _T_174.wb @[el2_dec_decode_ctl.scala 326:14] + cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 326:14] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 327:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 327:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 327:11] + cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 327:11] + node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 329:32] + when _T_175 : @[el2_dec_decode_ctl.scala 329:39] + cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 330:20] + skip @[el2_dec_decode_ctl.scala 329:39] + node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 332:17] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 332:21] + when _T_177 : @[el2_dec_decode_ctl.scala 332:28] + cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 333:27] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 334:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 335:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 336:27] + skip @[el2_dec_decode_ctl.scala 332:28] + else : @[el2_dec_decode_ctl.scala 337:116] + node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 337:37] + node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 337:57] + node _T_180 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 337:80] + node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 337:64] + node _T_182 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 337:108] + node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 337:95] + node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 337:44] + when _T_184 : @[el2_dec_decode_ctl.scala 337:116] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 338:23] + skip @[el2_dec_decode_ctl.scala 337:116] + else : @[el2_dec_decode_ctl.scala 339:16] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 340:22] + cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 340:22] + skip @[el2_dec_decode_ctl.scala 339:16] + node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:37] + node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 342:79] + node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 342:44] + node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 342:110] + node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 342:95] + when _T_189 : @[el2_dec_decode_ctl.scala 342:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 343:20] + skip @[el2_dec_decode_ctl.scala 342:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 346:32] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:23] + skip @[el2_dec_decode_ctl.scala 346:32] + wire _T_190 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 350:70] + _T_190.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + _T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 350:70] + reg _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 350:47] + _T_191.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 350:47] + _T_191.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 350:47] + _T_191.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 350:47] + _T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 350:47] + cam_raw[3].rd <= _T_191.rd @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].tag <= _T_191.tag @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].wb <= _T_191.wb @[el2_dec_decode_ctl.scala 350:15] + cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 350:15] + node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 351:46] + node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 351:66] + nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 351:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 354:29] + node _T_194 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 356:44] + node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 356:76] + node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 357:95] + node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 357:95] + node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 357:95] + node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 357:99] + node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 357:64] + node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 357:109] + node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 357:106] + io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 357:28] + node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 358:54] + node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 358:66] + node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 358:97] + node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 358:137] + node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 358:149] + node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 358:180] + node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 358:118] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 360:26] + node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_210 = and(_T_209, cam[0].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_212 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 362:136] + node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_215 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 362:197] + node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, cam[1].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_221 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 362:136] + node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_224 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 362:197] + node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_228 = and(_T_227, cam[2].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_230 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 362:136] + node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_233 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 362:197] + node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_237 = and(_T_236, cam[3].rd) @[el2_dec_decode_ctl.scala 362:88] + node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 362:121] + node _T_239 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 362:149] + node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 362:136] + node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 362:182] + node _T_242 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 362:210] + node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 362:197] + node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 363:69] + node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 363:69] + node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 363:69] + node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 363:102] + node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 363:102] + node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 363:102] + node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 363:134] + node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 363:134] + node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 363:134] + io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 364:29] + node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 365:38] + node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 365:51] + i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 365:25] + node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 374:34] + node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 374:32] + node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 386:16] + node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 386:30] + node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 387:6] + node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16] + node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 387:30] + node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:18] + node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 388:16] + node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 388:30] + node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16] + node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16] + node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 378:49] + d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 378:21] + inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 395:22] + i0_dec.clock <= clock + i0_dec.reset <= reset + i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 396:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 397:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 397:12] + reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 399:45] + _T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 399:45] + lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 399:11] + node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 402:73] + node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 402:71] + node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 402:53] + leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 402:21] + reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 403:56] + _T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 403:56] + leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 403:21] + leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 404:14] + node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 405:45] + node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 405:83] + node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 405:81] + node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 405:63] + leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 405:21] + reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 406:56] + _T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 406:56] + leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 406:21] + node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 410:29] + node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 410:36] + node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 410:46] + node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 410:53] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58] + node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58] + node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 411:46] + node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 411:51] + node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 411:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 411:79] + node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 411:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 411:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 411:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 412:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 412:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 412:98] + node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 412:89] + node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 412:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98] + node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 413:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 413:67] + node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 413:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 414:38] + i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 414:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38] + i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 415:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 416:38] + i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 416:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38] + i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 417:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 418:41] + node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 418:55] + node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 418:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 418:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 418:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 418:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 418:113] + node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] + node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] + node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] + node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 418:26] + i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 418:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 420:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 420:65] + node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 420:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 420:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 420:111] + node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 420:101] + node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 420:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 421:32] + i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 421:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32] + i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 422:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:35] + node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 423:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:52] + node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 423:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 423:67] + node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 423:65] + i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 423:15] + io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 426:21] + io.div_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 427:21] + io.div_p.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 428:21] + io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 430:21] + io.mul_p.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 431:21] + io.mul_p.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 432:21] + io.mul_p.low <= i0_dp.low @[el2_dec_decode_ctl.scala 433:21] + reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 435:58] + _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 435:58] + io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 435:23] + wire _T_340 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_dec_decode_ctl.scala 437:27] + _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + _T_340.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 437:27] + io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store_data_bypass_m <= _T_340.store_data_bypass_m @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.load_ldst_bypass_d <= _T_340.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store_data_bypass_d <= _T_340.store_data_bypass_d @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.dma <= _T_340.dma @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.unsign <= _T_340.unsign @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.store <= _T_340.store @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.load <= _T_340.load @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.dword <= _T_340.dword @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.word <= _T_340.word @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.half <= _T_340.half @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.by <= _T_340.by @[el2_dec_decode_ctl.scala 437:12] + io.lsu_p.fast_int <= _T_340.fast_int @[el2_dec_decode_ctl.scala 437:12] + when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 438:29] + io.lsu_p.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 439:24] + io.lsu_p.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:24] + io.lsu_p.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:24] + io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:24] + skip @[el2_dec_decode_ctl.scala 438:29] + else : @[el2_dec_decode_ctl.scala 443:15] + io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 444:35] + io.lsu_p.load <= i0_dp.load @[el2_dec_decode_ctl.scala 445:35] + io.lsu_p.store <= i0_dp.store @[el2_dec_decode_ctl.scala 446:35] + io.lsu_p.by <= i0_dp.by @[el2_dec_decode_ctl.scala 447:35] + io.lsu_p.half <= i0_dp.half @[el2_dec_decode_ctl.scala 448:35] + io.lsu_p.word <= i0_dp.word @[el2_dec_decode_ctl.scala 449:35] + io.lsu_p.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 450:35] + io.lsu_p.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 451:35] + io.lsu_p.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 452:35] + io.lsu_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 453:35] + skip @[el2_dec_decode_ctl.scala 443:15] + io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 457:21] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 458:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 458:36] + csr_read <= _T_342 @[el2_dec_decode_ctl.scala 458:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 460:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 460:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 461:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 461:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 462:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59] + node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 463:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 465:41] + node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 465:39] + i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 465:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 466:42] + node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 466:58] + io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 466:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 469:30] + io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 469:24] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 470:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 474:48] + io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 474:20] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 477:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 477:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 477:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 477:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 477:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 477:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 477:117] + io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 477:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 479:52] + csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 479:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:51] + csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 480:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51] + csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 481:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:53] + csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 482:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:51] + csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 483:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 486:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 486:48] + inst rvclkhdr of rvclkhdr_1 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_363 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + csrimm_x <= _T_362 @[el2_lib.scala 491:16] + node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:62] + inst rvclkhdr_1 of rvclkhdr_2 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 491:16] + node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 490:15] + wire _T_366 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58] + node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58] + node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58] + node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58] + node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58] + node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58] + node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58] + node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58] + node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58] + node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58] + node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58] + node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58] + node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58] + node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58] + node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58] + node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58] + node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58] + node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] + node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] + node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] + node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 490:53] + node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] + node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 491:5] + node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] + wire csr_mask_x : UInt<32> @[Mux.scala 27:72] + csr_mask_x <= _T_399 @[Mux.scala 27:72] + node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 494:38] + node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 494:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 495:35] + node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72] + node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] + wire write_csr_data_x : UInt @[Mux.scala 27:72] + write_csr_data_x <= _T_407 @[Mux.scala 27:72] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 498:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 498:47] + node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 498:109] + node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 498:91] + node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 498:76] + node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 499:44] + node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:61] + node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 499:59] + pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 499:18] + reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 500:50] + _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 500:50] + pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 500:15] + io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 501:22] + reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 502:29] + _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 502:29] + tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 502:19] + reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29] + _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 503:29] + tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 503:19] + node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 505:44] + node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 505:64] + node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 505:61] + node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 505:41] + io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 505:25] + node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 508:59] + node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 508:59] + node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 509:8] + node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 508:30] + node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 510:34] + node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 510:46] + node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 510:61] + node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 510:75] + node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 510:99] + inst rvclkhdr_2 of rvclkhdr_3 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_429 <= write_csr_data_in @[el2_lib.scala 491:16] + write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 511:18] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 517:44] + node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 517:30] + io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 517:24] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 519:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 519:53] + node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 521:67] + node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 521:48] + node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 522:67] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 522:48] + node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 523:40] + debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 523:21] + node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 526:34] + node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 526:57] + node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 526:73] + node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 526:91] + node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 529:36] + node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 529:60] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 529:104] + node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 529:112] + node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 529:99] + node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 529:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 531:34] + io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 532:24] + node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 533:40] + node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 533:51] + node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 533:37] + wire _T_446 : UInt<1>[16] @[el2_lib.scala 161:48] + _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_447 = cat(_T_446[0], _T_446[1]) @[Cat.scala 29:58] + node _T_448 = cat(_T_447, _T_446[2]) @[Cat.scala 29:58] + node _T_449 = cat(_T_448, _T_446[3]) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_446[4]) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_446[5]) @[Cat.scala 29:58] + node _T_452 = cat(_T_451, _T_446[6]) @[Cat.scala 29:58] + node _T_453 = cat(_T_452, _T_446[7]) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_446[8]) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_446[9]) @[Cat.scala 29:58] + node _T_456 = cat(_T_455, _T_446[10]) @[Cat.scala 29:58] + node _T_457 = cat(_T_456, _T_446[11]) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_446[12]) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_446[13]) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 534:27] + node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 537:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 537:47] + node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:44] + node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 538:42] + inst rvclkhdr_3 of rvclkhdr_4 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_465 <= i0_inst_d @[el2_lib.scala 491:16] + io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 539:23] + node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 540:40] + node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 540:61] + node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 540:59] + illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 540:22] + reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 541:54] + _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 541:54] + illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 541:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 542:42] + node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 544:40] + node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 544:59] + node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 544:81] + node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 544:95] + node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 545:20] + node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 545:45] + node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 545:62] + node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 546:19] + node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 546:36] + node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 546:34] + node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 545:79] + node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 546:47] + node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 546:72] + node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 547:21] + node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 547:45] + node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 549:65] + node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 549:39] + node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:63] + node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 550:38] + node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 551:38] + node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 551:57] + node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:46] + node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 555:44] + node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:63] + node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 555:61] + node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 555:91] + node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 555:89] + io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 555:22] + node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46] + node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 556:44] + node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63] + node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 556:61] + node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91] + node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 556:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 557:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 560:28] + node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 561:51] + node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 561:49] + io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 561:27] + node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 562:47] + io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 562:29] + node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:46] + io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 563:29] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 567:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 568:31] + node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 570:37] + presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 570:22] + reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 571:53] + _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 571:53] + postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 571:18] + node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 573:56] + node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 573:54] + node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 573:39] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 573:88] + node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 573:69] + ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 573:15] + node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 575:50] + io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 575:26] + node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 577:40] + lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 577:16] + node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 578:40] + mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 578:16] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 579:40] + div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 579:16] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 581:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 581:45] + io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 581:29] + d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 584:26] + node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 585:40] + d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 585:26] + node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:50] + d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 586:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 587:26] + node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 589:44] + node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 589:61] + d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 589:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 592:26] + d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 593:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26] + wire _T_519 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[2] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[3] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58] + node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58] + node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58] + node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 596:56] + d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 596:26] + node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 599:33] + inst rvclkhdr_4 of rvclkhdr_5 @[el2_lib.scala 495:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 498:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 501:33] + _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_525.i0trigger <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_525.fence_i <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.icaf_type <= UInt<2>("h00") @[el2_lib.scala 501:33] + _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 501:33] + reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 501:16] + _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 501:16] + _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 501:16] + _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 501:16] + _T_526.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 501:16] + _T_526.i0trigger <= d_t.i0trigger @[el2_lib.scala 501:16] + _T_526.fence_i <= d_t.fence_i @[el2_lib.scala 501:16] + _T_526.icaf_type <= d_t.icaf_type @[el2_lib.scala 501:16] + _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 501:16] + _T_526.icaf <= d_t.icaf @[el2_lib.scala 501:16] + _T_526.legal <= d_t.legal @[el2_lib.scala 501:16] + x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 599:7] + x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 599:7] + x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 599:7] + x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 599:7] + x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 599:7] + x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 599:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 601:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 601:10] + x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 601:10] + x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 601:10] + x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 601:10] + x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 601:10] + wire _T_527 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58] + node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58] + node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58] + node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 602:39] + node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 602:37] + x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 602:20] + node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 604:36] + inst rvclkhdr_5 of rvclkhdr_6 @[el2_lib.scala 495:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 498:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 501:33] + _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_534.i0trigger <= UInt<4>("h00") @[el2_lib.scala 501:33] + _T_534.fence_i <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.icaf_type <= UInt<2>("h00") @[el2_lib.scala 501:33] + _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 501:33] + reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 501:16] + _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 501:16] + _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 501:16] + _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 501:16] + _T_535.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 501:16] + _T_535.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 501:16] + _T_535.fence_i <= x_t_in.fence_i @[el2_lib.scala 501:16] + _T_535.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 501:16] + _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 501:16] + _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 501:16] + _T_535.legal <= x_t_in.legal @[el2_lib.scala 501:16] + r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 604:7] + r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 604:7] + r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 604:7] + r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 604:7] + r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 604:7] + r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 604:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 605:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 605:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 606:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 608:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 608:10] + r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 608:10] + r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 608:10] + r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 608:10] + r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 608:10] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 610:56] + wire _T_537 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_537[0] <= _T_536 @[el2_lib.scala 161:48] + _T_537[1] <= _T_536 @[el2_lib.scala 161:48] + _T_537[2] <= _T_536 @[el2_lib.scala 161:48] + _T_537[3] <= _T_536 @[el2_lib.scala 161:48] + node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] + node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] + node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 610:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 610:95] + r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 610:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 611:33] + node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 613:35] + when _T_543 : @[el2_dec_decode_ctl.scala 613:43] + wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 613:66] + r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 613:51] + r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 613:51] + r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 613:51] + r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 613:51] + r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 613:51] + r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 613:51] + skip @[el2_dec_decode_ctl.scala 613:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 615:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 615:39] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 616:53] + io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 616:39] + reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 619:52] + _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 619:52] + flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 619:17] + node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:46] + node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 621:44] + node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:60] + node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 621:58] + node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 621:88] + node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 621:86] + io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 621:22] + node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 623:16] + i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 623:11] + node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 624:16] + i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 624:11] + node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 625:16] + i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 625:11] + node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 627:49] + node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 627:38] + io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 627:24] + node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49] + node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 628:38] + io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 628:24] + node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:48] + node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 629:37] + io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 630:19] + io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 631:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 633:38] + node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 634:27] + node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38] + node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 638:5] + node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72] + wire _T_566 : UInt<32> @[Mux.scala 27:72] + _T_566 <= _T_565 @[Mux.scala 27:72] + io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 636:21] + node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 641:38] + wire _T_568 : UInt<1>[20] @[el2_lib.scala 161:48] + _T_568[0] <= _T_567 @[el2_lib.scala 161:48] + _T_568[1] <= _T_567 @[el2_lib.scala 161:48] + _T_568[2] <= _T_567 @[el2_lib.scala 161:48] + _T_568[3] <= _T_567 @[el2_lib.scala 161:48] + _T_568[4] <= _T_567 @[el2_lib.scala 161:48] + _T_568[5] <= _T_567 @[el2_lib.scala 161:48] + _T_568[6] <= _T_567 @[el2_lib.scala 161:48] + _T_568[7] <= _T_567 @[el2_lib.scala 161:48] + _T_568[8] <= _T_567 @[el2_lib.scala 161:48] + _T_568[9] <= _T_567 @[el2_lib.scala 161:48] + _T_568[10] <= _T_567 @[el2_lib.scala 161:48] + _T_568[11] <= _T_567 @[el2_lib.scala 161:48] + _T_568[12] <= _T_567 @[el2_lib.scala 161:48] + _T_568[13] <= _T_567 @[el2_lib.scala 161:48] + _T_568[14] <= _T_567 @[el2_lib.scala 161:48] + _T_568[15] <= _T_567 @[el2_lib.scala 161:48] + _T_568[16] <= _T_567 @[el2_lib.scala 161:48] + _T_568[17] <= _T_567 @[el2_lib.scala 161:48] + _T_568[18] <= _T_567 @[el2_lib.scala 161:48] + _T_568[19] <= _T_567 @[el2_lib.scala 161:48] + node _T_569 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58] + node _T_570 = cat(_T_569, _T_568[2]) @[Cat.scala 29:58] + node _T_571 = cat(_T_570, _T_568[3]) @[Cat.scala 29:58] + node _T_572 = cat(_T_571, _T_568[4]) @[Cat.scala 29:58] + node _T_573 = cat(_T_572, _T_568[5]) @[Cat.scala 29:58] + node _T_574 = cat(_T_573, _T_568[6]) @[Cat.scala 29:58] + node _T_575 = cat(_T_574, _T_568[7]) @[Cat.scala 29:58] + node _T_576 = cat(_T_575, _T_568[8]) @[Cat.scala 29:58] + node _T_577 = cat(_T_576, _T_568[9]) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_568[10]) @[Cat.scala 29:58] + node _T_579 = cat(_T_578, _T_568[11]) @[Cat.scala 29:58] + node _T_580 = cat(_T_579, _T_568[12]) @[Cat.scala 29:58] + node _T_581 = cat(_T_580, _T_568[13]) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_568[14]) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_568[15]) @[Cat.scala 29:58] + node _T_584 = cat(_T_583, _T_568[16]) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58] + node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58] + node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 641:46] + node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58] + wire _T_590 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_591 = cat(_T_590[0], _T_590[1]) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_590[2]) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_590[3]) @[Cat.scala 29:58] + node _T_594 = cat(_T_593, _T_590[4]) @[Cat.scala 29:58] + node _T_595 = cat(_T_594, _T_590[5]) @[Cat.scala 29:58] + node _T_596 = cat(_T_595, _T_590[6]) @[Cat.scala 29:58] + node _T_597 = cat(_T_596, _T_590[7]) @[Cat.scala 29:58] + node _T_598 = cat(_T_597, _T_590[8]) @[Cat.scala 29:58] + node _T_599 = cat(_T_598, _T_590[9]) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_590[10]) @[Cat.scala 29:58] + node _T_601 = cat(_T_600, _T_590[11]) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_590[12]) @[Cat.scala 29:58] + node _T_603 = cat(_T_602, _T_590[13]) @[Cat.scala 29:58] + node _T_604 = cat(_T_603, _T_590[14]) @[Cat.scala 29:58] + node _T_605 = cat(_T_604, _T_590[15]) @[Cat.scala 29:58] + node _T_606 = cat(_T_605, _T_590[16]) @[Cat.scala 29:58] + node _T_607 = cat(_T_606, _T_590[17]) @[Cat.scala 29:58] + node _T_608 = cat(_T_607, _T_590[18]) @[Cat.scala 29:58] + node _T_609 = cat(_T_608, _T_590[19]) @[Cat.scala 29:58] + node _T_610 = cat(_T_609, _T_590[20]) @[Cat.scala 29:58] + node _T_611 = cat(_T_610, _T_590[21]) @[Cat.scala 29:58] + node _T_612 = cat(_T_611, _T_590[22]) @[Cat.scala 29:58] + node _T_613 = cat(_T_612, _T_590[23]) @[Cat.scala 29:58] + node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58] + node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58] + node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 642:43] + node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58] + node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 643:38] + wire _T_620 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_620[0] <= _T_619 @[el2_lib.scala 161:48] + _T_620[1] <= _T_619 @[el2_lib.scala 161:48] + _T_620[2] <= _T_619 @[el2_lib.scala 161:48] + _T_620[3] <= _T_619 @[el2_lib.scala 161:48] + _T_620[4] <= _T_619 @[el2_lib.scala 161:48] + _T_620[5] <= _T_619 @[el2_lib.scala 161:48] + _T_620[6] <= _T_619 @[el2_lib.scala 161:48] + _T_620[7] <= _T_619 @[el2_lib.scala 161:48] + _T_620[8] <= _T_619 @[el2_lib.scala 161:48] + _T_620[9] <= _T_619 @[el2_lib.scala 161:48] + _T_620[10] <= _T_619 @[el2_lib.scala 161:48] + _T_620[11] <= _T_619 @[el2_lib.scala 161:48] + node _T_621 = cat(_T_620[0], _T_620[1]) @[Cat.scala 29:58] + node _T_622 = cat(_T_621, _T_620[2]) @[Cat.scala 29:58] + node _T_623 = cat(_T_622, _T_620[3]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_620[4]) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_620[5]) @[Cat.scala 29:58] + node _T_626 = cat(_T_625, _T_620[6]) @[Cat.scala 29:58] + node _T_627 = cat(_T_626, _T_620[7]) @[Cat.scala 29:58] + node _T_628 = cat(_T_627, _T_620[8]) @[Cat.scala 29:58] + node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58] + node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58] + node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 643:46] + node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 643:56] + node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 643:63] + node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58] + node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58] + node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58] + node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 644:30] + wire _T_640 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58] + node _T_644 = cat(_T_643, _T_640[4]) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_640[5]) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_640[6]) @[Cat.scala 29:58] + node _T_647 = cat(_T_646, _T_640[7]) @[Cat.scala 29:58] + node _T_648 = cat(_T_647, _T_640[8]) @[Cat.scala 29:58] + node _T_649 = cat(_T_648, _T_640[9]) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58] + node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58] + node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58] + node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 645:26] + node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 645:43] + wire _T_655 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_656 = cat(_T_655[0], _T_655[1]) @[Cat.scala 29:58] + node _T_657 = cat(_T_656, _T_655[2]) @[Cat.scala 29:58] + node _T_658 = cat(_T_657, _T_655[3]) @[Cat.scala 29:58] + node _T_659 = cat(_T_658, _T_655[4]) @[Cat.scala 29:58] + node _T_660 = cat(_T_659, _T_655[5]) @[Cat.scala 29:58] + node _T_661 = cat(_T_660, _T_655[6]) @[Cat.scala 29:58] + node _T_662 = cat(_T_661, _T_655[7]) @[Cat.scala 29:58] + node _T_663 = cat(_T_662, _T_655[8]) @[Cat.scala 29:58] + node _T_664 = cat(_T_663, _T_655[9]) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_655[10]) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_655[11]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_655[12]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_655[13]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_655[14]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_655[15]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_655[16]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_655[17]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_655[18]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_655[19]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_655[20]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_655[21]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_655[22]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_655[23]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58] + node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 645:72] + node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58] + node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_686 = mux(i0_jalimm20, _T_638, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_687 = mux(i0_uiimm20, _T_652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_688 = mux(_T_654, _T_683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_689 = or(_T_684, _T_685) @[Mux.scala 27:72] + node _T_690 = or(_T_689, _T_686) @[Mux.scala 27:72] + node _T_691 = or(_T_690, _T_687) @[Mux.scala 27:72] + node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72] + wire _T_693 : UInt<32> @[Mux.scala 27:72] + _T_693 <= _T_692 @[Mux.scala 27:72] + i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 640:14] + node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 647:46] + i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 647:24] + node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 649:44] + i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 649:29] + node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44] + i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 650:29] + node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44] + i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 651:29] + node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 653:71] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_698 : @[Reg.scala 16:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_699 : @[Reg.scala 16:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 655:83] + reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 655:72] + _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 655:72] + node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58] + i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 655:14] + node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 657:43] + node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 657:49] + node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 657:53] + i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 657:29] + node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 658:43] + node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 658:49] + node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 658:53] + i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 658:29] + node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 659:43] + node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 659:49] + node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 659:53] + i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 659:29] + node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 660:44] + node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 660:50] + i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 660:29] + node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 661:44] + node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 661:50] + i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 661:29] + node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 662:44] + node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 662:50] + i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 662:29] + node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 663:44] + node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 663:50] + i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 663:29] + node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 665:27] + node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 666:27] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 668:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 669:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 670:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 672:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 672:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 673:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 674:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 676:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 676:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 677:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 677:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 678:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 678:29] + node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 680:34] + inst rvclkhdr_6 of rvclkhdr_7 @[el2_lib.scala 495:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 498:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 501:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 501:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 501:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 501:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 501:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 501:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 501:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 501:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 501:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 501:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 680:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 680:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 680:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 680:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 680:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 680:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 680:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 680:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 680:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 681:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 682:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 682:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 682:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 682:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 683:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 683:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 683:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 683:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 683:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 684:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 684:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 684:22] + node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 686:36] + inst rvclkhdr_7 of rvclkhdr_8 @[el2_lib.scala 495:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 498:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 501:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 501:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 501:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 501:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 501:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 501:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 501:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 501:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 501:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 501:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 686:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 686:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 686:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 686:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 686:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 686:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 686:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 686:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 686:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 687:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 687:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 687:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 688:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 690:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 691:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 691:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 692:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 692:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 693:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 693:22] + node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 695:37] + inst rvclkhdr_8 of rvclkhdr_9 @[el2_lib.scala 495:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 497:18] + rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 498:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 499:24] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 501:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 501:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 501:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 501:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 501:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 501:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 501:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 501:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 501:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 501:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 501:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 501:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 501:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 501:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 695:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 695:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 695:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 695:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 695:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 695:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 695:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 695:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 695:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 697:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 698:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 698:40] + i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 698:25] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:49] + node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 699:47] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 699:63] + io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 699:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 700:26] + node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 702:57] + inst rvclkhdr_9 of rvclkhdr_10 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_result_r_raw <= i0_result_x @[el2_lib.scala 491:16] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 708:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 708:56] + node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 708:32] + i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 708:26] + i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 709:26] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 713:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 713:51] + node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 713:27] + i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 713:21] + node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 714:54] + node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 714:52] + node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 714:66] + wire _T_770 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_771 = cat(_T_770[0], _T_770[1]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_770[2]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_770[3]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_770[4]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_770[5]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_770[6]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_770[7]) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, _T_770[8]) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58] + node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58] + node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 714:30] + io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 714:24] + wire last_br_immed_d : UInt<12> + last_br_immed_d <= UInt<1>("h00") + node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 716:48] + wire _T_784 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_785 = cat(_T_784[0], _T_784[1]) @[Cat.scala 29:58] + node _T_786 = cat(_T_785, _T_784[2]) @[Cat.scala 29:58] + node _T_787 = cat(_T_786, _T_784[3]) @[Cat.scala 29:58] + node _T_788 = cat(_T_787, _T_784[4]) @[Cat.scala 29:58] + node _T_789 = cat(_T_788, _T_784[5]) @[Cat.scala 29:58] + node _T_790 = cat(_T_789, _T_784[6]) @[Cat.scala 29:58] + node _T_791 = cat(_T_790, _T_784[7]) @[Cat.scala 29:58] + node _T_792 = cat(_T_791, _T_784[8]) @[Cat.scala 29:58] + node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58] + node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 716:25] + last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 716:19] + wire last_br_immed_x : UInt<12> + last_br_immed_x <= UInt<1>("h00") + node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 718:58] + inst rvclkhdr_10 of rvclkhdr_11 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_798 <= last_br_immed_d @[el2_lib.scala 491:16] + last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 718:19] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 722:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 722:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 724:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 724:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 724:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 725:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 725:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 724:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 726:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 726:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 725:59] + node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 730:51] + node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 731:26] + node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 731:24] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 731:51] + node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 731:39] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 731:72] + node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 730:65] + node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 733:53] + io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 733:29] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 734:55] + node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 736:62] + node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 736:60] + node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 736:81] + node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 736:79] + node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 736:39] + reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 738:54] + _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 738:54] + io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 738:21] + node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 741:49] + node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 741:88] + node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 741:69] + node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:25] + node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 742:64] + node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 742:45] + node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 741:102] + i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 741:26] + node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 744:59] + reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_829 : @[Reg.scala 28:19] + _T_830 <= i0r.rd @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 744:19] + node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 751:34] + node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 751:57] + inst rvclkhdr_11 of rvclkhdr_12 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + div_inst <= _T_831 @[el2_lib.scala 491:16] + node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 752:49] + inst rvclkhdr_12 of rvclkhdr_13 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_x <= i0_inst_d @[el2_lib.scala 491:16] + node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49] + inst rvclkhdr_13 of rvclkhdr_14 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_r <= i0_inst_x @[el2_lib.scala 491:16] + node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 755:50] + inst rvclkhdr_14 of rvclkhdr_15 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_inst_wb <= i0_inst_r @[el2_lib.scala 491:16] + node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:53] + inst rvclkhdr_15 of rvclkhdr_16 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_837 <= i0_inst_wb @[el2_lib.scala 491:16] + io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 756:22] + node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53] + inst rvclkhdr_16 of rvclkhdr_17 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 491:16] + node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 759:49] + inst rvclkhdr_17 of rvclkhdr_18 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_840 <= i0_pc_wb @[el2_lib.scala 491:16] + io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 759:20] + node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:56] + inst rvclkhdr_18 of rvclkhdr_19 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 491:16] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 762:27] + node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 206:24] + node _T_845 = bits(_T_843, 12, 1) @[el2_lib.scala 206:40] + node _T_846 = add(_T_844, _T_845) @[el2_lib.scala 206:31] + node _T_847 = bits(_T_842, 31, 13) @[el2_lib.scala 207:20] + node _T_848 = add(_T_847, UInt<1>("h01")) @[el2_lib.scala 207:27] + node _T_849 = tail(_T_848, 1) @[el2_lib.scala 207:27] + node _T_850 = bits(_T_842, 31, 13) @[el2_lib.scala 208:20] + node _T_851 = sub(_T_850, UInt<1>("h01")) @[el2_lib.scala 208:27] + node _T_852 = tail(_T_851, 1) @[el2_lib.scala 208:27] + node _T_853 = bits(_T_843, 12, 12) @[el2_lib.scala 209:22] + node _T_854 = bits(_T_846, 12, 12) @[el2_lib.scala 210:39] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_lib.scala 210:28] + node _T_856 = xor(_T_853, _T_855) @[el2_lib.scala 210:26] + node _T_857 = bits(_T_856, 0, 0) @[el2_lib.scala 210:64] + node _T_858 = bits(_T_842, 31, 13) @[el2_lib.scala 210:76] + node _T_859 = eq(_T_853, UInt<1>("h00")) @[el2_lib.scala 211:20] + node _T_860 = bits(_T_846, 12, 12) @[el2_lib.scala 211:39] + node _T_861 = and(_T_859, _T_860) @[el2_lib.scala 211:26] + node _T_862 = bits(_T_861, 0, 0) @[el2_lib.scala 211:64] + node _T_863 = bits(_T_846, 12, 12) @[el2_lib.scala 212:39] + node _T_864 = eq(_T_863, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_865 = and(_T_853, _T_864) @[el2_lib.scala 212:26] + node _T_866 = bits(_T_865, 0, 0) @[el2_lib.scala 212:64] + node _T_867 = mux(_T_857, _T_858, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_868 = mux(_T_862, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_869 = mux(_T_866, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_870 = or(_T_867, _T_868) @[Mux.scala 27:72] + node _T_871 = or(_T_870, _T_869) @[Mux.scala 27:72] + wire _T_872 : UInt<19> @[Mux.scala 27:72] + _T_872 <= _T_871 @[Mux.scala 27:72] + node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 212:94] + node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 767:51] + io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 767:25] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 771:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 772:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 774:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 774:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 774:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 775:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 775:58] + node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 777:44] + node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 777:81] + wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 777:109] + _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 777:109] + node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 777:61] + node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 777:24] + i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 777:18] + i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 777:18] + i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 777:18] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:83] + node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 778:63] + node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 778:24] + i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 778:18] + node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44] + node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:81] + wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 779:109] + _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 779:109] + node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 779:61] + node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 779:24] + i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 779:18] + i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 779:18] + i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 779:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:83] + node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 780:63] + node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 780:24] + i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 780:18] + i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 790:21] + node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 791:43] + node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 791:74] + node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 791:58] + node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 791:78] + load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 791:27] + node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:59] + node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 792:43] + node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 792:63] + store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 792:25] + store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 793:25] + node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 797:62] + node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 797:119] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 797:89] + node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 799:62] + node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 799:119] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 799:89] + node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 802:41] + node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 802:66] + node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 802:45] + node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 802:104] + node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 802:108] + node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 802:149] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 802:175] + node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 802:196] + node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 802:153] + node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58] + node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58] + i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 802:18] + node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 804:41] + node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 804:67] + node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 804:45] + node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 804:105] + node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 804:109] + node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 804:149] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 804:175] + node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 804:196] + node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 804:153] + node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58] + i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 804:18] + node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 806:54] + node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 806:71] + node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 806:89] + node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 806:75] + node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 806:109] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 806:96] + node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 806:113] + node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 806:93] + node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58] + io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 806:34] + node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54] + node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71] + node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89] + node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 807:75] + node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96] + node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113] + node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 807:93] + node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58] + io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 807:34] + node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 810:17] + node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 810:21] + node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 811:17] + node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 811:21] + node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 812:19] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 812:6] + node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:38] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 812:25] + node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 812:23] + node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 812:42] + node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 812:78] + node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_967 = or(_T_964, _T_965) @[Mux.scala 27:72] + node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72] + wire _T_969 : UInt<32> @[Mux.scala 27:72] + _T_969 <= _T_968 @[Mux.scala 27:72] + io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 809:31] + node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 815:17] + node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 815:21] + node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 816:17] + node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 816:21] + node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 817:19] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:6] + node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:38] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:25] + node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 817:23] + node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 817:42] + node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 817:78] + node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_984 = or(_T_981, _T_982) @[Mux.scala 27:72] + node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72] + wire _T_986 : UInt<32> @[Mux.scala 27:72] + _T_986 <= _T_985 @[Mux.scala 27:72] + io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 814:31] + node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 819:68] + node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 819:50] + node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:89] + node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 819:87] + node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:114] + node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 819:112] + node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 819:131] + io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 819:26] + node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 821:6] + node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 821:27] + node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 821:39] + node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 821:53] + node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 821:70] + node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27] + node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 822:39] + node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 822:54] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 822:74] + node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 822:84] + node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58] + node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72] + wire _T_1009 : UInt<12> @[Mux.scala 27:72] + _T_1009 <= _T_1008 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 820:23] + diff --git a/el2_dec_decode_ctl.v b/el2_dec_decode_ctl.v index 926f89bf..4569b81d 100644 --- a/el2_dec_decode_ctl.v +++ b/el2_dec_decode_ctl.v @@ -1,43 +1,29 @@ -module TEC_RV_ICG( - ( - input logic SE, EN, CK, - output Q - ); - logic en_ff; - logic enable; - assign enable = EN | SE; - always @(CK, enable) begin - if(!CK) - en_ff = enable; - end - assign Q = CK & en_ff; -endmodule module rvclkhdr( output io_l1clk, input io_clk, input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 330:24] - wire clkhdr_CK; // @[beh_lib.scala 330:24] - wire clkhdr_EN; // @[beh_lib.scala 330:24] - wire clkhdr_SE; // @[beh_lib.scala 330:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 330:24] + wire clkhdr_Q; // @[el2_lib.scala 465:26] + wire clkhdr_CK; // @[el2_lib.scala 465:26] + wire clkhdr_EN; // @[el2_lib.scala 465:26] + wire clkhdr_SE; // @[el2_lib.scala 465:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 331:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 332:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 333:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 334:16] + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18] endmodule module el2_dec_dec_ctl( input [31:0] io_ins, output io_out_alu, - output io_out_rs2, output io_out_rs1, + output io_out_rs2, output io_out_imm12, output io_out_rd, output io_out_shimm5, @@ -86,655 +72,654 @@ module el2_dec_dec_ctl( output io_out_pm_alu, output io_out_legal ); - wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 20:27] - wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 20:42] - wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:53] - wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 20:39] - wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 20:68] - wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:78] - wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 21:43] - wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 21:70] - wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 22:29] - wire _T_48 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_49 = _T_48 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_50 = _T_43 | _T_49; // @[el2_dec_dec_ctl.scala 22:56] - wire _T_56 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_57 = _T_56 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_58 = _T_50 | _T_57; // @[el2_dec_dec_ctl.scala 23:29] - wire _T_63 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_64 = _T_63 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_65 = _T_58 | _T_64; // @[el2_dec_dec_ctl.scala 23:55] - wire _T_71 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_72 = _T_71 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_73 = _T_65 | _T_72; // @[el2_dec_dec_ctl.scala 24:29] - wire _T_78 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_79 = _T_78 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_80 = _T_73 | _T_79; // @[el2_dec_dec_ctl.scala 24:55] - wire _T_86 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_87 = _T_86 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_88 = _T_80 | _T_87; // @[el2_dec_dec_ctl.scala 25:29] - wire _T_93 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_94 = _T_93 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_95 = _T_88 | _T_94; // @[el2_dec_dec_ctl.scala 25:55] - wire _T_97 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_99 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_100 = _T_97 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_101 = _T_95 | _T_100; // @[el2_dec_dec_ctl.scala 26:29] - wire _T_103 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_106 = _T_103 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_113 = io_ins[5] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_114 = _T_113 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_120 = _T_103 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_121 = _T_120 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_129 = _T_100 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_136 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_137 = _T_136 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_138 = _T_137 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_139 = _T_129 | _T_138; // @[el2_dec_dec_ctl.scala 28:42] - wire _T_143 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_146 = _T_16 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_147 = _T_146 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_148 = _T_147 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_149 = _T_139 | _T_148; // @[el2_dec_dec_ctl.scala 28:70] - wire _T_157 = _T_143 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_158 = _T_157 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_159 = _T_158 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_165 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 30:28] - wire _T_168 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 30:55] - wire _T_169 = _T_165 | _T_168; // @[el2_dec_dec_ctl.scala 30:42] - wire _T_180 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_181 = _T_180 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_182 = _T_181 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_186 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 32:29] - wire _T_189 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 32:53] - wire _T_195 = _T_9 & _T_99; // @[el2_dec_dec_ctl.scala 33:28] - wire _T_197 = _T_195 & io_ins[2]; // @[el2_dec_dec_ctl.scala 33:41] - wire _T_208 = _T_9 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_223 = _T_103 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_235 = _T_19 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_236 = _T_235 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_237 = _T_236 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_245 = _T_237 | _T_197; // @[el2_dec_dec_ctl.scala 37:49] - wire _T_247 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_261 = _T_247 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_262 = _T_261 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_263 = _T_262 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_264 = _T_263 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_265 = _T_264 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_266 = _T_265 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_267 = _T_266 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_278 = io_ins[30] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_279 = _T_278 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_280 = _T_279 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_281 = _T_280 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_282 = _T_281 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_293 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_294 = _T_293 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_295 = _T_294 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_296 = _T_295 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_297 = _T_296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_298 = _T_282 | _T_297; // @[el2_dec_dec_ctl.scala 39:49] - wire _T_307 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_308 = _T_307 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_309 = _T_308 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_310 = _T_309 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_311 = _T_298 | _T_310; // @[el2_dec_dec_ctl.scala 39:85] - wire _T_317 = io_ins[6] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_318 = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_327 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_328 = _T_327 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_329 = _T_328 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_330 = _T_329 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_340 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_341 = _T_340 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_342 = _T_341 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_343 = _T_342 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_344 = _T_343 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_349 = _T_103 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_362 = _T_341 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_363 = _T_362 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_364 = _T_363 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_365 = _T_349 | _T_364; // @[el2_dec_dec_ctl.scala 42:37] - wire _T_369 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_370 = _T_369 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_371 = _T_365 | _T_370; // @[el2_dec_dec_ctl.scala 42:74] - wire _T_381 = _T_371 | _T_148; // @[el2_dec_dec_ctl.scala 43:26] - wire _T_391 = _T_327 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_392 = _T_391 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_393 = _T_392 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_406 = _T_340 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_407 = _T_406 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_408 = _T_407 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_409 = _T_408 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_420 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_421 = _T_420 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_422 = _T_421 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_423 = _T_422 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_424 = _T_423 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_439 = _T_293 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_440 = _T_439 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_441 = _T_440 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_442 = _T_441 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_453 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_454 = _T_453 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_455 = _T_454 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_456 = _T_455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_472 = _T_261 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_473 = _T_472 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_474 = _T_473 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_475 = _T_474 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_476 = _T_475 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_515 = _T_307 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_516 = _T_515 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_517 = _T_516 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_524 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_525 = _T_524 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_526 = _T_525 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_527 = _T_517 | _T_526; // @[el2_dec_dec_ctl.scala 50:51] - wire _T_533 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_534 = _T_533 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_535 = _T_527 | _T_534; // @[el2_dec_dec_ctl.scala 50:79] - wire _T_548 = _T_294 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_549 = _T_548 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_550 = _T_549 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_551 = _T_535 | _T_550; // @[el2_dec_dec_ctl.scala 51:29] - wire _T_560 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_561 = _T_560 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_562 = _T_561 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_563 = _T_562 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_564 = _T_563 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_582 = _T_14 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_583 = _T_582 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_584 = _T_583 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_594 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_595 = _T_594 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_596 = _T_595 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_605 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_606 = _T_605 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_607 = _T_606 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_617 = io_ins[14] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_618 = _T_617 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_619 = _T_618 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_635 = _T_146 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_636 = _T_635 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_645 = io_ins[12] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_646 = _T_645 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_653 = io_ins[13] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_659 = _T_524 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_663 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_664 = _T_663 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_665 = _T_659 | _T_664; // @[el2_dec_dec_ctl.scala 62:44] - wire _T_669 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_670 = _T_669 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_671 = _T_665 | _T_670; // @[el2_dec_dec_ctl.scala 62:67] - wire _T_675 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_676 = _T_675 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_677 = _T_671 | _T_676; // @[el2_dec_dec_ctl.scala 63:26] - wire _T_681 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_682 = _T_681 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_683 = _T_677 | _T_682; // @[el2_dec_dec_ctl.scala 63:49] - wire _T_687 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_688 = _T_687 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_696 = _T_93 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_697 = _T_696 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_698 = _T_697 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_705 = _T_78 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_706 = _T_705 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_707 = _T_706 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_708 = _T_698 | _T_707; // @[el2_dec_dec_ctl.scala 65:49] - wire _T_715 = _T_63 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_716 = _T_715 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_717 = _T_716 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_718 = _T_708 | _T_717; // @[el2_dec_dec_ctl.scala 65:79] - wire _T_724 = io_ins[18] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_725 = _T_724 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_726 = _T_725 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_727 = _T_718 | _T_726; // @[el2_dec_dec_ctl.scala 66:33] - wire _T_733 = io_ins[19] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_734 = _T_733 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_735 = _T_734 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_743 = _T_180 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_751 = _T_420 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_752 = _T_751 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_757 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_758 = _T_757 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_759 = _T_758 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_760 = _T_752 | _T_759; // @[el2_dec_dec_ctl.scala 69:47] - wire _T_765 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_766 = _T_765 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_767 = _T_766 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_768 = _T_760 | _T_767; // @[el2_dec_dec_ctl.scala 69:74] - wire _T_773 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_774 = _T_773 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_775 = _T_774 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_776 = _T_768 | _T_775; // @[el2_dec_dec_ctl.scala 70:30] - wire _T_781 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_782 = _T_781 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_783 = _T_782 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_784 = _T_776 | _T_783; // @[el2_dec_dec_ctl.scala 70:57] - wire _T_789 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_790 = _T_789 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_791 = _T_790 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_798 = io_ins[15] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_799 = _T_798 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_800 = _T_799 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_806 = io_ins[16] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_807 = _T_806 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_808 = _T_807 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_809 = _T_800 | _T_808; // @[el2_dec_dec_ctl.scala 72:47] - wire _T_815 = io_ins[17] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_816 = _T_815 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_817 = _T_816 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_818 = _T_809 | _T_817; // @[el2_dec_dec_ctl.scala 72:75] - wire _T_827 = _T_818 | _T_726; // @[el2_dec_dec_ctl.scala 73:31] - wire _T_838 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_846 = _T_838 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_847 = _T_846 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_848 = _T_847 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_849 = _T_848 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_852 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_854 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_861 = _T_852 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_862 = _T_861 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_863 = _T_862 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_864 = _T_863 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_873 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_874 = _T_873 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_875 = _T_874 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_886 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_887 = _T_886 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_888 = _T_887 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_889 = _T_888 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_904 = _T_886 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_905 = _T_904 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_906 = _T_905 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_907 = _T_906 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_908 = _T_907 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_909 = _T_908 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_922 = _T_886 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_923 = _T_922 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_924 = _T_923 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_925 = _T_924 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_926 = _T_925 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_958 = _T_922 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_959 = _T_958 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_960 = _T_959 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_970 = _T_560 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_971 = _T_970 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_982 = _T_560 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_983 = _T_982 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_984 = _T_983 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_989 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_994 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_995 = _T_994 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1003 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1004 = _T_1003 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1005 = _T_1004 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1006 = _T_1005 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1010 = _T_1006 | _T_189; // @[el2_dec_dec_ctl.scala 87:51] - wire _T_1016 = _T_4 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1017 = _T_1016 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1018 = _T_1010 | _T_1017; // @[el2_dec_dec_ctl.scala 87:72] - wire _T_1034 = _T_86 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1035 = _T_1034 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1036 = _T_989 | _T_1035; // @[el2_dec_dec_ctl.scala 89:41] - wire _T_1043 = _T_71 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1044 = _T_1043 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1045 = _T_1036 | _T_1044; // @[el2_dec_dec_ctl.scala 89:68] - wire _T_1052 = _T_56 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1053 = _T_1052 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1054 = _T_1045 | _T_1053; // @[el2_dec_dec_ctl.scala 90:30] - wire _T_1061 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1062 = _T_1061 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1063 = _T_1054 | _T_1062; // @[el2_dec_dec_ctl.scala 90:57] - wire _T_1070 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1071 = _T_1070 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1072 = _T_1063 | _T_1071; // @[el2_dec_dec_ctl.scala 91:31] - wire _T_1078 = _T_93 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1079 = _T_1078 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1080 = _T_1072 | _T_1079; // @[el2_dec_dec_ctl.scala 91:59] - wire _T_1086 = _T_78 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1087 = _T_1086 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1088 = _T_1080 | _T_1087; // @[el2_dec_dec_ctl.scala 92:30] - wire _T_1094 = _T_63 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1095 = _T_1094 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1096 = _T_1088 | _T_1095; // @[el2_dec_dec_ctl.scala 92:57] - wire _T_1102 = _T_48 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1103 = _T_1102 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1104 = _T_1096 | _T_1103; // @[el2_dec_dec_ctl.scala 93:30] - wire _T_1110 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1111 = _T_1110 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1127 = _T_838 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1128 = _T_1127 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1129 = _T_1128 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1130 = _T_1129 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1131 = _T_995 | _T_1130; // @[el2_dec_dec_ctl.scala 95:45] - wire _T_1140 = _T_1131 | _T_1035; // @[el2_dec_dec_ctl.scala 95:78] - wire _T_1149 = _T_1140 | _T_1044; // @[el2_dec_dec_ctl.scala 96:30] - wire _T_1158 = _T_1149 | _T_1053; // @[el2_dec_dec_ctl.scala 96:57] - wire _T_1167 = _T_1158 | _T_1062; // @[el2_dec_dec_ctl.scala 97:30] - wire _T_1176 = _T_1167 | _T_1071; // @[el2_dec_dec_ctl.scala 97:58] - wire _T_1184 = _T_1176 | _T_1079; // @[el2_dec_dec_ctl.scala 98:31] - wire _T_1192 = _T_1184 | _T_1087; // @[el2_dec_dec_ctl.scala 98:58] - wire _T_1200 = _T_1192 | _T_1095; // @[el2_dec_dec_ctl.scala 99:30] - wire _T_1208 = _T_1200 | _T_1103; // @[el2_dec_dec_ctl.scala 99:57] - wire _T_1218 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1224 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1226 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1230 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1232 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1239 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1241 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1243 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1245 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1247 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1251 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1253 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1255 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1257 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1259 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1269 = _T_1218 & _T_247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1270 = _T_1269 & io_ins[29]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1271 = _T_1270 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1272 = _T_1271 & _T_1224; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1273 = _T_1272 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1274 = _T_1273 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1275 = _T_1274 & _T_1230; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1276 = _T_1275 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1277 = _T_1276 & _T_838; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1278 = _T_1277 & io_ins[21]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1279 = _T_1278 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1280 = _T_1279 & _T_1239; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1281 = _T_1280 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1282 = _T_1281 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1283 = _T_1282 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1284 = _T_1283 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1285 = _T_1284 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1286 = _T_1285 & _T_1251; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1287 = _T_1286 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1288 = _T_1287 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1289 = _T_1288 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1290 = _T_1289 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1291 = _T_1290 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1292 = _T_1291 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1293 = _T_1292 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1294 = _T_1293 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1295 = _T_1294 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1296 = _T_1295 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1297 = _T_1296 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1303 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1351 = _T_1269 & _T_1303; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1352 = _T_1351 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1353 = _T_1352 & _T_1224; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1354 = _T_1353 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1355 = _T_1354 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1356 = _T_1355 & _T_1230; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1357 = _T_1356 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1358 = _T_1357 & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1359 = _T_1358 & _T_852; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1360 = _T_1359 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1361 = _T_1360 & _T_1239; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1362 = _T_1361 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1363 = _T_1362 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1364 = _T_1363 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1365 = _T_1364 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1366 = _T_1365 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1367 = _T_1366 & _T_1251; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1368 = _T_1367 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1369 = _T_1368 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1370 = _T_1369 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1371 = _T_1370 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1372 = _T_1371 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1373 = _T_1372 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1374 = _T_1373 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1375 = _T_1374 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1376 = _T_1375 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1377 = _T_1376 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1378 = _T_1377 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1379 = _T_1297 | _T_1378; // @[el2_dec_dec_ctl.scala 101:136] - wire _T_1387 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 15:46] - wire _T_1434 = _T_1351 & _T_1387; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1435 = _T_1434 & _T_1224; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1436 = _T_1435 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1437 = _T_1436 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1438 = _T_1437 & _T_1230; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1439 = _T_1438 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1440 = _T_1439 & _T_838; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1441 = _T_1440 & _T_852; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1442 = _T_1441 & _T_1239; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1443 = _T_1442 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1444 = _T_1443 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1445 = _T_1444 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1446 = _T_1445 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1447 = _T_1446 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1448 = _T_1447 & _T_1251; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1449 = _T_1448 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1450 = _T_1449 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1451 = _T_1450 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1452 = _T_1451 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1453 = _T_1452 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1454 = _T_1453 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1455 = _T_1454 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1456 = _T_1455 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1457 = _T_1456 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1458 = _T_1457 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1459 = _T_1379 | _T_1458; // @[el2_dec_dec_ctl.scala 102:122] - wire _T_1487 = _T_1437 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1488 = _T_1487 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1489 = _T_1488 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1490 = _T_1489 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1491 = _T_1490 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1492 = _T_1459 | _T_1491; // @[el2_dec_dec_ctl.scala 103:119] - wire _T_1519 = _T_1218 & _T_1303; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1520 = _T_1519 & _T_1387; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1521 = _T_1520 & _T_1224; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1522 = _T_1521 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1523 = _T_1522 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1524 = _T_1523 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1525 = _T_1524 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1526 = _T_1525 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1527 = _T_1526 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1528 = _T_1527 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1529 = _T_1528 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1530 = _T_1529 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1531 = _T_1530 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1532 = _T_1492 | _T_1531; // @[el2_dec_dec_ctl.scala 104:60] - wire _T_1561 = _T_1523 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1562 = _T_1561 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1563 = _T_1562 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1564 = _T_1563 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1565 = _T_1564 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1566 = _T_1565 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1567 = _T_1566 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1568 = _T_1567 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1569 = _T_1532 | _T_1568; // @[el2_dec_dec_ctl.scala 105:69] - wire _T_1595 = _T_1436 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1596 = _T_1595 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1597 = _T_1596 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1598 = _T_1597 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1599 = _T_1598 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1600 = _T_1599 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1601 = _T_1569 | _T_1600; // @[el2_dec_dec_ctl.scala 106:66] - wire _T_1618 = _T_235 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1619 = _T_1618 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1620 = _T_1619 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1621 = _T_1620 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1622 = _T_1621 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1623 = _T_1622 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1624 = _T_1601 | _T_1623; // @[el2_dec_dec_ctl.scala 107:58] - wire _T_1636 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1637 = _T_1636 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1638 = _T_1637 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1639 = _T_1638 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1640 = _T_1639 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1641 = _T_1640 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1642 = _T_1641 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1643 = _T_1624 | _T_1642; // @[el2_dec_dec_ctl.scala 108:46] - wire _T_1655 = _T_143 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1656 = _T_1655 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1657 = _T_1656 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1658 = _T_1657 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1659 = _T_1658 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1660 = _T_1659 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1661 = _T_1643 | _T_1660; // @[el2_dec_dec_ctl.scala 109:40] - wire _T_1676 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1677 = _T_1676 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1678 = _T_1677 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1679 = _T_1678 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1680 = _T_1679 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1681 = _T_1680 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1682 = _T_1661 | _T_1681; // @[el2_dec_dec_ctl.scala 110:39] - wire _T_1693 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1694 = _T_1693 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1695 = _T_1694 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1696 = _T_1695 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1697 = _T_1696 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1698 = _T_1697 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1699 = _T_1698 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1700 = _T_1682 | _T_1699; // @[el2_dec_dec_ctl.scala 111:43] - wire _T_1769 = _T_1441 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1770 = _T_1769 & _T_1239; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1771 = _T_1770 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1772 = _T_1771 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1773 = _T_1772 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1774 = _T_1773 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1775 = _T_1774 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1776 = _T_1775 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1777 = _T_1776 & _T_1251; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1778 = _T_1777 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1779 = _T_1778 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1780 = _T_1779 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1781 = _T_1780 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1782 = _T_1781 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1783 = _T_1782 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1784 = _T_1783 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1785 = _T_1784 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1786 = _T_1785 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1787 = _T_1786 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1788 = _T_1787 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1789 = _T_1700 | _T_1788; // @[el2_dec_dec_ctl.scala 112:39] - wire _T_1837 = _T_1434 & _T_1239; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1838 = _T_1837 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1839 = _T_1838 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1840 = _T_1839 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1841 = _T_1840 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1842 = _T_1841 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1843 = _T_1842 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1844 = _T_1843 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1845 = _T_1844 & _T_1251; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1846 = _T_1845 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1847 = _T_1846 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1848 = _T_1847 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1849 = _T_1848 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1850 = _T_1849 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1851 = _T_1850 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1852 = _T_1851 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1853 = _T_1852 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1854 = _T_1853 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1855 = _T_1854 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1856 = _T_1855 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1857 = _T_1789 | _T_1856; // @[el2_dec_dec_ctl.scala 113:130] - wire _T_1869 = _T_524 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1870 = _T_1869 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1871 = _T_1870 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1872 = _T_1871 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1873 = _T_1872 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1874 = _T_1873 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1875 = _T_1857 | _T_1874; // @[el2_dec_dec_ctl.scala 114:102] - wire _T_1890 = _T_16 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1891 = _T_1890 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1892 = _T_1891 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1893 = _T_1892 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1894 = _T_1893 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1895 = _T_1894 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1896 = _T_1895 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1897 = _T_1875 | _T_1896; // @[el2_dec_dec_ctl.scala 115:39] - wire _T_1906 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1907 = _T_1906 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1908 = _T_1907 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1909 = _T_1908 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1910 = _T_1909 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1911 = _T_1910 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1912 = _T_1897 | _T_1911; // @[el2_dec_dec_ctl.scala 116:43] - wire _T_1924 = _T_653 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1925 = _T_1924 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1926 = _T_1925 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1927 = _T_1926 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1928 = _T_1927 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1929 = _T_1912 | _T_1928; // @[el2_dec_dec_ctl.scala 117:35] - wire _T_1945 = _T_582 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1946 = _T_1945 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1947 = _T_1946 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1948 = _T_1947 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1949 = _T_1948 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1950 = _T_1949 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1951 = _T_1929 | _T_1950; // @[el2_dec_dec_ctl.scala 118:38] - wire _T_1960 = _T_103 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1961 = _T_1960 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1962 = _T_1961 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1963 = _T_1962 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] - wire _T_1964 = _T_1963 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] - assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 20:14] - assign io_out_rs2 = _T_114 | _T_121; // @[el2_dec_dec_ctl.scala 27:14] - assign io_out_rs1 = _T_101 | _T_106; // @[el2_dec_dec_ctl.scala 21:14] - assign io_out_imm12 = _T_149 | _T_159; // @[el2_dec_dec_ctl.scala 28:16] - assign io_out_rd = _T_169 | io_ins[4]; // @[el2_dec_dec_ctl.scala 30:13] - assign io_out_shimm5 = _T_182 & _T_18; // @[el2_dec_dec_ctl.scala 31:17] - assign io_out_imm20 = _T_186 | _T_189; // @[el2_dec_dec_ctl.scala 32:16] - assign io_out_pc = _T_197 | _T_186; // @[el2_dec_dec_ctl.scala 33:13] - assign io_out_load = _T_208 & _T_18; // @[el2_dec_dec_ctl.scala 34:15] - assign io_out_store = _T_120 & _T_97; // @[el2_dec_dec_ctl.scala 35:16] - assign io_out_lsu = _T_223 & _T_18; // @[el2_dec_dec_ctl.scala 36:14] - assign io_out_add = _T_245 | _T_267; // @[el2_dec_dec_ctl.scala 37:14] - assign io_out_sub = _T_311 | _T_318; // @[el2_dec_dec_ctl.scala 39:14] - assign io_out_land = _T_330 | _T_344; // @[el2_dec_dec_ctl.scala 41:15] - assign io_out_lor = _T_381 | _T_393; // @[el2_dec_dec_ctl.scala 42:14] - assign io_out_lxor = _T_409 | _T_424; // @[el2_dec_dec_ctl.scala 45:15] - assign io_out_sll = _T_442 & _T_18; // @[el2_dec_dec_ctl.scala 46:14] - assign io_out_sra = _T_456 & _T_18; // @[el2_dec_dec_ctl.scala 47:14] - assign io_out_srl = _T_476 & _T_18; // @[el2_dec_dec_ctl.scala 48:14] - assign io_out_slt = _T_297 | _T_310; // @[el2_dec_dec_ctl.scala 49:14] - assign io_out_unsign = _T_551 | _T_564; // @[el2_dec_dec_ctl.scala 50:17] - assign io_out_condbr = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 53:17] - assign io_out_beq = _T_584 & _T_18; // @[el2_dec_dec_ctl.scala 54:14] - assign io_out_bne = _T_596 & _T_18; // @[el2_dec_dec_ctl.scala 55:14] - assign io_out_bge = _T_607 & _T_18; // @[el2_dec_dec_ctl.scala 56:14] - assign io_out_blt = _T_619 & _T_18; // @[el2_dec_dec_ctl.scala 57:14] - assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 58:14] - assign io_out_by = _T_636 & _T_18; // @[el2_dec_dec_ctl.scala 59:13] - assign io_out_half = _T_646 & _T_18; // @[el2_dec_dec_ctl.scala 60:15] - assign io_out_word = _T_653 & _T_97; // @[el2_dec_dec_ctl.scala 61:15] - assign io_out_csr_read = _T_683 | _T_688; // @[el2_dec_dec_ctl.scala 62:19] - assign io_out_csr_clr = _T_727 | _T_735; // @[el2_dec_dec_ctl.scala 65:18] - assign io_out_csr_set = _T_827 | _T_735; // @[el2_dec_dec_ctl.scala 72:18] - assign io_out_csr_write = _T_743 & io_ins[4]; // @[el2_dec_dec_ctl.scala 68:20] - assign io_out_csr_imm = _T_784 | _T_791; // @[el2_dec_dec_ctl.scala 69:18] - assign io_out_presync = _T_1104 | _T_1111; // @[el2_dec_dec_ctl.scala 89:18] - assign io_out_postsync = _T_1208 | _T_1111; // @[el2_dec_dec_ctl.scala 95:19] - assign io_out_ebreak = _T_849 & io_ins[4]; // @[el2_dec_dec_ctl.scala 75:17] - assign io_out_ecall = _T_864 & io_ins[4]; // @[el2_dec_dec_ctl.scala 76:16] - assign io_out_mret = _T_875 & io_ins[4]; // @[el2_dec_dec_ctl.scala 77:15] - assign io_out_mul = _T_889 & _T_18; // @[el2_dec_dec_ctl.scala 78:14] - assign io_out_rs1_sign = _T_909 | _T_926; // @[el2_dec_dec_ctl.scala 79:19] - assign io_out_rs2_sign = _T_925 & _T_18; // @[el2_dec_dec_ctl.scala 81:19] - assign io_out_low = _T_960 & _T_18; // @[el2_dec_dec_ctl.scala 82:14] - assign io_out_div = _T_971 & _T_18; // @[el2_dec_dec_ctl.scala 83:14] - assign io_out_rem = _T_984 & _T_18; // @[el2_dec_dec_ctl.scala 84:14] - assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 85:16] - assign io_out_fence_i = _T_994 & io_ins[3]; // @[el2_dec_dec_ctl.scala 86:18] - assign io_out_pm_alu = _T_1018 | _T_11; // @[el2_dec_dec_ctl.scala 87:17] - assign io_out_legal = _T_1951 | _T_1964; // @[el2_dec_dec_ctl.scala 101:16] + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] + wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] + wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] + wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] + wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] + wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] + wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] + wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] + wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] + wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] + wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] + wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] + wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] + wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] + wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] + wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] + wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] + wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] + wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] + wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] + wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] + wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] + wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] + wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] + wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] + wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] + wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] + wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] + wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] + wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] + wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] + wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] + wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] + wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] + wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] + wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] + wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] + wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] + wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] + wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] + wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] + wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] + wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] + wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] + wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] + wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] + wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] + wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] + wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] + wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] + wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] + wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] + wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] + wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] + wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] + wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] + wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] + wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] + wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] + wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] + wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] + wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] + wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] + wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] + wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] + wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] + wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] + wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] + wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] + wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] + wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] + wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] + wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] + wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] + wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] + wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] + wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] + wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] + wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] + wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] + wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] + wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] + wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] + wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] + wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] + wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] + wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] + wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] + wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] + wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] + wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] + wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] + assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] + assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] + assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] + assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] + assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] + assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] + assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] + assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] + assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] + assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] + assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] + assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] + assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] + assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] + assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] + assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] + assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] + assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] + assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] + assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] + assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] + assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] + assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] + assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] + assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] + assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] + assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] + assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] + assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] + assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] + assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] + assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] + assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] + assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] + assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] + assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] + assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] + assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] + assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] + assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] + assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] + assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] + assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] + assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] + assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] + assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] + assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] endmodule module el2_dec_decode_ctl( input clock, @@ -746,12 +731,12 @@ module el2_dec_decode_ctl( output [31:0] io_dec_i0_inst_wb1, output [30:0] io_dec_i0_pc_wb1, input io_lsu_nonblock_load_valid_m, - input [2:0] io_lsu_nonblock_load_tag_m, + input [1:0] io_lsu_nonblock_load_tag_m, input io_lsu_nonblock_load_inv_r, - input [2:0] io_lsu_nonblock_load_inv_tag_r, + input [1:0] io_lsu_nonblock_load_inv_tag_r, input io_lsu_nonblock_load_data_valid, input io_lsu_nonblock_load_data_error, - input [2:0] io_lsu_nonblock_load_data_tag, + input [1:0] io_lsu_nonblock_load_data_tag, input [31:0] io_lsu_nonblock_load_data, input [3:0] io_dec_i0_trigger_match_d, input io_dec_tlu_wr_pause_r, @@ -1028,203 +1013,203 @@ module el2_dec_decode_ctl( wire data_gated_cgc_io_clk; // @[el2_dec_decode_ctl.scala 221:29] wire data_gated_cgc_io_en; // @[el2_dec_decode_ctl.scala 221:29] wire data_gated_cgc_io_scan_mode; // @[el2_dec_decode_ctl.scala 221:29] - wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 396:24] - wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 396:24] - wire rvclkhdr_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_1_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_1_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_2_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_2_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_3_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_3_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_3_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_3_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_4_io_l1clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_4_io_clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_4_io_en; // @[beh_lib.scala 360:21] - wire rvclkhdr_4_io_scan_mode; // @[beh_lib.scala 360:21] - wire rvclkhdr_5_io_l1clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_5_io_clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_5_io_en; // @[beh_lib.scala 360:21] - wire rvclkhdr_5_io_scan_mode; // @[beh_lib.scala 360:21] - wire rvclkhdr_6_io_l1clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_6_io_clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_6_io_en; // @[beh_lib.scala 360:21] - wire rvclkhdr_6_io_scan_mode; // @[beh_lib.scala 360:21] - wire rvclkhdr_7_io_l1clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_7_io_clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_7_io_en; // @[beh_lib.scala 360:21] - wire rvclkhdr_7_io_scan_mode; // @[beh_lib.scala 360:21] - wire rvclkhdr_8_io_l1clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_8_io_clk; // @[beh_lib.scala 360:21] - wire rvclkhdr_8_io_en; // @[beh_lib.scala 360:21] - wire rvclkhdr_8_io_scan_mode; // @[beh_lib.scala 360:21] - wire rvclkhdr_9_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_9_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_9_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_9_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_10_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_10_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_10_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_10_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_11_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_11_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_11_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_11_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_12_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_12_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_12_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_12_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_13_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_13_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_13_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_13_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_14_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_14_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_14_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_14_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_15_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_15_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_15_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_15_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_16_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_16_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_16_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_16_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_17_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_17_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_17_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_17_io_scan_mode; // @[beh_lib.scala 350:21] - wire rvclkhdr_18_io_l1clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_18_io_clk; // @[beh_lib.scala 350:21] - wire rvclkhdr_18_io_en; // @[beh_lib.scala 350:21] - wire rvclkhdr_18_io_scan_mode; // @[beh_lib.scala 350:21] - reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 503:29] + wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 395:22] + wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 395:22] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 495:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 495:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 502:29] wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51] - reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 504:29] - wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:50] + reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 503:29] + wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32] wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73] - wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:50] - wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:74] - reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 404:56] - wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 403:73] - wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 403:71] - wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 403:53] - wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:50] - wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:74] - wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 406:45] - reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 407:56] - wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 406:81] - wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 406:63] - wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:50] - wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:74] - reg pause_stall; // @[el2_dec_decode_ctl.scala 501:50] - wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 500:44] - wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 499:49] - wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 499:47] - reg [31:0] write_csr_data; // @[beh_lib.scala 356:14] - wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 499:109] - wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 499:91] - wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 499:76] - wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 500:61] - wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 500:59] - wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:50] - wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:74] + wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32] + wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56] + reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 403:56] + wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 402:73] + wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 402:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 402:53] + wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32] + wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56] + wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 405:45] + reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 406:56] + wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 405:81] + wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 405:63] + wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32] + wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56] + reg pause_stall; // @[el2_dec_decode_ctl.scala 500:50] + wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 499:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 498:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 498:47] + reg [31:0] write_csr_data; // @[el2_lib.scala 491:16] + wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 498:109] + wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 498:91] + wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 498:76] + wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 499:61] + wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 499:59] + wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32] + wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56] wire _T_17 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 229:62] wire i0_brp_valid = io_dec_i0_brp_valid & _T_17; // @[el2_dec_decode_ctl.scala 229:60] - wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire [20:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] - wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 412:79] - wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 412:112] - wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 412:33] - wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 413:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 626:16] - wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 413:76] - wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 413:98] - wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 413:89] - wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 413:65] - wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] + wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 411:79] + wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 411:112] + wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 411:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 412:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 625:16] + wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 412:76] + wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 412:98] + wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 412:89] + wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 412:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 414:38] wire _T_19 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 240:75] - wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 414:67] - wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 414:65] - wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] + wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 413:67] + wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 413:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 416:38] wire _T_20 = _T_19 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 240:90] - wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 421:37] - wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 421:65] - wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 421:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 624:16] - wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 421:89] - wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 421:111] - wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 421:101] - wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 421:79] - wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 420:37] + wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 420:65] + wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 420:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 623:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 420:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 420:111] + wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 420:101] + wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 420:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 421:32] wire _T_21 = _T_20 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:103] wire _T_22 = ~_T_21; // @[el2_dec_decode_ctl.scala 240:56] wire i0_notbr_error = i0_brp_valid & _T_22; // @[el2_dec_decode_ctl.scala 240:54] wire _T_30 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 245:57] wire _T_24 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 243:47] - wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 419:41] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 418:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] - wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 419:26] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 418:26] wire _T_25 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 243:96] wire _T_26 = _T_24 & _T_25; // @[el2_dec_decode_ctl.scala 243:71] wire _T_27 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 243:116] @@ -1237,194 +1222,196 @@ module el2_dec_decode_ctl( wire i0_br_error_all = _T_38 & _T_17; // @[el2_dec_decode_ctl.scala 250:79] wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 259:36] wire _T_40 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 263:25] - wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_postsync = _T_40 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 263:50] - wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 530:36] - wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 522:48] - wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 530:60] - wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 529:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 521:48] + wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 529:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_csr_write = _T_40 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 263:50] - wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 461:42] - wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 461:40] - wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 460:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 460:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_csr_read = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 263:50] - wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 466:41] - wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 466:39] - wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 530:112] - wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 530:99] - wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 530:76] - wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 465:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 465:39] + wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 529:112] + wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 529:99] + wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 529:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_legal = _T_40 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 263:50] - wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:34] - wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 534:40] - wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 534:51] - wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 534:37] - wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 574:56] - wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 574:54] - wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 574:39] - reg postsync_stall; // @[el2_dec_decode_ctl.scala 572:53] - reg x_d_i0valid; // @[beh_lib.scala 366:14] - wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 574:88] - wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 574:69] - wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:50] - wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:74] - reg flush_final_r; // @[el2_dec_decode_ctl.scala 620:52] - wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:50] - wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:74] - wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 538:47] - reg illegal_lockout; // @[el2_dec_decode_ctl.scala 542:54] - wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 541:40] - wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 541:61] - wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 541:59] - wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:50] - wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 648:46] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 531:34] + wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 533:40] + wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 533:51] + wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 533:37] + wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 573:56] + wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 573:54] + wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 573:39] + reg postsync_stall; // @[el2_dec_decode_ctl.scala 571:53] + reg x_d_i0valid; // @[el2_lib.scala 501:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 573:88] + wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 573:69] + wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] + wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] + reg flush_final_r; // @[el2_dec_decode_ctl.scala 619:52] + wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32] + wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56] + wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 537:47] + reg illegal_lockout; // @[el2_dec_decode_ctl.scala 541:54] + wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 540:40] + wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 540:61] + wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 540:59] + wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 647:46] wire _T_32 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 246:67] wire _T_35 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 247:84] - wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_pm_alu = _T_40 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_fence_i = _T_40 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_fence = _T_40 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_div = _T_40 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_mul = _T_40 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_mret = _T_40 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_ecall = _T_40 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_ebreak = _T_40 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_presync = _T_40 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_csr_set = _T_40 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_csr_clr = _T_40 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_word = _T_40 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_half = _T_40 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_by = _T_40 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 263:50] wire i0_dp_jal = _T_40 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_condbr = _T_40 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_lsu = _T_40 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_store = _T_40 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_load = _T_40 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_imm20 = _T_40 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_shimm5 = _T_40 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_rd = _T_40 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 263:50] wire i0_dp_imm12 = _T_40 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] - wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_rs2 = _T_40 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:14] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] + wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 263:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 397:12] wire i0_dp_alu = _T_40 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 263:50] - wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 416:38] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] wire _T_43 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 277:38] - wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 418:38] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] wire _T_44 = _T_43 | i0_pja; // @[el2_dec_decode_ctl.scala 277:49] - wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 423:32] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] wire i0_predict_br = _T_44 | i0_pret; // @[el2_dec_decode_ctl.scala 277:58] wire _T_46 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 279:50] wire _T_47 = ~_T_46; // @[el2_dec_decode_ctl.scala 279:26] wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 281:20] wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 314:63] reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 350:47] - wire _T_93 = io_lsu_nonblock_load_data_tag == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_93 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 325:67] wire _T_94 = cam_data_reset & _T_93; // @[el2_dec_decode_ctl.scala 325:45] reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 350:47] wire cam_data_reset_val_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 325:83] wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 329:39] - wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 306:79] + wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 306:78] reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 350:47] - wire _T_119 = io_lsu_nonblock_load_data_tag == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_119 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 325:67] wire _T_120 = cam_data_reset & _T_119; // @[el2_dec_decode_ctl.scala 325:45] reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 350:47] wire cam_data_reset_val_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 325:83] wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 329:39] - wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 306:79] - wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 306:127] - wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 306:159] + wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 306:126] + wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 306:158] reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 350:47] - wire _T_145 = io_lsu_nonblock_load_data_tag == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_145 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 325:67] wire _T_146 = cam_data_reset & _T_145; // @[el2_dec_decode_ctl.scala 325:45] reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 350:47] wire cam_data_reset_val_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 325:83] wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 329:39] - wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 306:79] - wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 306:127] - wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 306:127] - wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 306:159] + wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 306:126] + wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 306:126] + wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 306:158] reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 350:47] - wire _T_171 = io_lsu_nonblock_load_data_tag == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 325:67] + wire _T_171 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 325:67] wire _T_172 = cam_data_reset & _T_171; // @[el2_dec_decode_ctl.scala 325:45] reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 350:47] wire cam_data_reset_val_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 325:83] wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 329:39] - wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 306:79] - wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 306:127] - wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 306:127] - wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 306:159] + wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 306:78] + wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 306:126] + wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 306:126] + wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 306:158] wire _T_80 = _T_50 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] wire [1:0] _T_81 = _T_56 ? _T_58 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_82 = _T_65 ? _T_67 : 3'h0; // @[Mux.scala 27:72] wire [3:0] _T_83 = _T_77 ? _T_79 : 4'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_123 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] - wire [1:0] _T_84 = _GEN_123 | _T_81; // @[Mux.scala 27:72] - wire [2:0] _GEN_124 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] - wire [2:0] _T_85 = _GEN_124 | _T_82; // @[Mux.scala 27:72] - wire [3:0] _GEN_125 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] - wire [3:0] cam_wen = _GEN_125 | _T_83; // @[Mux.scala 27:72] - reg x_d_i0load; // @[beh_lib.scala 366:14] - reg [4:0] x_d_i0rd; // @[beh_lib.scala 366:14] + wire [1:0] _GEN_127 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] + wire [1:0] _T_84 = _GEN_127 | _T_81; // @[Mux.scala 27:72] + wire [2:0] _GEN_128 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] + wire [2:0] _T_85 = _GEN_128 | _T_82; // @[Mux.scala 27:72] + wire [3:0] _GEN_129 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_129 | _T_83; // @[Mux.scala 27:72] + reg x_d_i0load; // @[el2_lib.scala 501:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 501:16] wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 317:31] - reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 656:72] + reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 655:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] - wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 659:49] - wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 659:53] + wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 658:49] + wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_i0load; // @[beh_lib.scala 366:14] + reg r_d_i0load; // @[el2_lib.scala 501:16] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 322:56] - wire _T_90 = io_lsu_nonblock_load_inv_tag_r == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_90 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 324:66] wire _T_91 = io_lsu_nonblock_load_inv_r & _T_90; // @[el2_dec_decode_ctl.scala 324:45] wire cam_inv_reset_val_0 = _T_91 & cam_0_valid; // @[el2_dec_decode_ctl.scala 324:82] - reg r_d_i0v; // @[beh_lib.scala 366:14] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 691:41] - wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 691:39] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 699:42] - wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 699:40] - reg [4:0] r_d_i0rd; // @[beh_lib.scala 366:14] + reg r_d_i0v; // @[el2_lib.scala 501:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 690:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 690:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 698:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 698:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 501:16] reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 350:47] wire _T_102 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 337:80] wire _T_103 = i0_wen_r & _T_102; // @[el2_dec_decode_ctl.scala 337:64] @@ -1438,7 +1425,7 @@ module el2_dec_decode_ctl( wire _T_109 = nonblock_load_valid_m_delay & _T_90; // @[el2_dec_decode_ctl.scala 342:44] wire _T_111 = _T_109 & cam_0_valid; // @[el2_dec_decode_ctl.scala 342:95] wire nonblock_load_write_0 = _T_93 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 351:66] - wire _T_116 = io_lsu_nonblock_load_inv_tag_r == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_116 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 324:66] wire _T_117 = io_lsu_nonblock_load_inv_r & _T_116; // @[el2_dec_decode_ctl.scala 324:45] wire cam_inv_reset_val_1 = _T_117 & cam_1_valid; // @[el2_dec_decode_ctl.scala 324:82] reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 350:47] @@ -1454,7 +1441,7 @@ module el2_dec_decode_ctl( wire _T_135 = nonblock_load_valid_m_delay & _T_116; // @[el2_dec_decode_ctl.scala 342:44] wire _T_137 = _T_135 & cam_1_valid; // @[el2_dec_decode_ctl.scala 342:95] wire nonblock_load_write_1 = _T_119 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 351:66] - wire _T_142 = io_lsu_nonblock_load_inv_tag_r == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_142 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 324:66] wire _T_143 = io_lsu_nonblock_load_inv_r & _T_142; // @[el2_dec_decode_ctl.scala 324:45] wire cam_inv_reset_val_2 = _T_143 & cam_2_valid; // @[el2_dec_decode_ctl.scala 324:82] reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 350:47] @@ -1470,7 +1457,7 @@ module el2_dec_decode_ctl( wire _T_161 = nonblock_load_valid_m_delay & _T_142; // @[el2_dec_decode_ctl.scala 342:44] wire _T_163 = _T_161 & cam_2_valid; // @[el2_dec_decode_ctl.scala 342:95] wire nonblock_load_write_2 = _T_145 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 351:66] - wire _T_168 = io_lsu_nonblock_load_inv_tag_r == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 324:66] + wire _T_168 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 324:66] wire _T_169 = io_lsu_nonblock_load_inv_r & _T_168; // @[el2_dec_decode_ctl.scala 324:45] wire cam_inv_reset_val_3 = _T_169 & cam_3_valid; // @[el2_dec_decode_ctl.scala 324:82] reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 350:47] @@ -1496,7 +1483,7 @@ module el2_dec_decode_ctl( wire _T_202 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 358:54] wire _T_203 = _T_202 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 358:66] wire _T_204 = _T_203 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 358:97] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 625:16] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 624:16] wire _T_205 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 358:137] wire _T_206 = _T_205 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 358:149] wire _T_207 = _T_206 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 358:180] @@ -1545,197 +1532,197 @@ module el2_dec_decode_ctl( wire i0_nonblock_load_stall = _T_250 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 365:51] wire _T_252 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 374:34] wire [3:0] _T_254 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire _T_255 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 384:18] - wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 459:36] - wire _T_256 = csr_read & _T_255; // @[el2_dec_decode_ctl.scala 384:16] - wire _T_258 = ~csr_read; // @[el2_dec_decode_ctl.scala 385:6] - wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 385:16] - wire _T_261 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 386:16] - wire [3:0] _T_263 = i0_dp_jal ? 4'he : 4'h0; // @[Mux.scala 98:16] - wire [3:0] _T_264 = i0_dp_condbr ? 4'hd : _T_263; // @[Mux.scala 98:16] - wire [3:0] _T_265 = i0_dp_mret ? 4'hc : _T_264; // @[Mux.scala 98:16] - wire [3:0] _T_266 = i0_dp_fence_i ? 4'hb : _T_265; // @[Mux.scala 98:16] - wire [3:0] _T_267 = i0_dp_fence ? 4'ha : _T_266; // @[Mux.scala 98:16] - wire [3:0] _T_268 = i0_dp_ecall ? 4'h9 : _T_267; // @[Mux.scala 98:16] - wire [3:0] _T_269 = i0_dp_ebreak ? 4'h8 : _T_268; // @[Mux.scala 98:16] - wire [3:0] _T_270 = _T_261 ? 4'h7 : _T_269; // @[Mux.scala 98:16] - wire [3:0] _T_271 = _T_259 ? 4'h6 : _T_270; // @[Mux.scala 98:16] - wire [3:0] _T_272 = _T_256 ? 4'h5 : _T_271; // @[Mux.scala 98:16] - wire [3:0] _T_273 = i0_dp_pm_alu ? 4'h4 : _T_272; // @[Mux.scala 98:16] - wire [3:0] _T_274 = i0_dp_store ? 4'h3 : _T_273; // @[Mux.scala 98:16] - wire [3:0] _T_275 = i0_dp_load ? 4'h2 : _T_274; // @[Mux.scala 98:16] - wire [3:0] _T_276 = i0_dp_mul ? 4'h1 : _T_275; // @[Mux.scala 98:16] - reg lsu_idle; // @[el2_dec_decode_ctl.scala 400:45] - wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 424:35] - wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 424:32] - wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 424:52] - wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 424:50] - wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 424:67] - reg _T_339; // @[el2_dec_decode_ctl.scala 436:58] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 578:40] - wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 792:47] - reg x_d_i0v; // @[beh_lib.scala 366:14] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:70] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 772:58] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 773:48] - wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 773:70] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 773:58] - wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 779:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 779:24] - wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:62] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 458:36] + wire _T_255 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 386:16] + wire _T_257 = ~csr_read; // @[el2_dec_decode_ctl.scala 387:6] + wire _T_258 = _T_257 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 387:16] + wire _T_260 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 388:18] + wire _T_261 = csr_read & _T_260; // @[el2_dec_decode_ctl.scala 388:16] + wire [3:0] _T_263 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_264 = i0_dp_load ? 4'h2 : _T_263; // @[Mux.scala 98:16] + wire [3:0] _T_265 = i0_dp_store ? 4'h3 : _T_264; // @[Mux.scala 98:16] + wire [3:0] _T_266 = i0_dp_pm_alu ? 4'h4 : _T_265; // @[Mux.scala 98:16] + wire [3:0] _T_267 = _T_261 ? 4'h5 : _T_266; // @[Mux.scala 98:16] + wire [3:0] _T_268 = _T_258 ? 4'h6 : _T_267; // @[Mux.scala 98:16] + wire [3:0] _T_269 = _T_255 ? 4'h7 : _T_268; // @[Mux.scala 98:16] + wire [3:0] _T_270 = i0_dp_ebreak ? 4'h8 : _T_269; // @[Mux.scala 98:16] + wire [3:0] _T_271 = i0_dp_ecall ? 4'h9 : _T_270; // @[Mux.scala 98:16] + wire [3:0] _T_272 = i0_dp_fence ? 4'ha : _T_271; // @[Mux.scala 98:16] + wire [3:0] _T_273 = i0_dp_fence_i ? 4'hb : _T_272; // @[Mux.scala 98:16] + wire [3:0] _T_274 = i0_dp_mret ? 4'hc : _T_273; // @[Mux.scala 98:16] + wire [3:0] _T_275 = i0_dp_condbr ? 4'hd : _T_274; // @[Mux.scala 98:16] + wire [3:0] _T_276 = i0_dp_jal ? 4'he : _T_275; // @[Mux.scala 98:16] + reg lsu_idle; // @[el2_dec_decode_ctl.scala 399:45] + wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 423:35] + wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 423:32] + wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 423:52] + wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 423:50] + wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 423:67] + reg _T_339; // @[el2_dec_decode_ctl.scala 435:58] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 577:40] + wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 791:43] + reg x_d_i0v; // @[el2_lib.scala 501:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 772:58] + wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 778:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 778:24] + wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 791:58] reg i0_x_c_load; // @[Reg.scala 15:16] reg i0_r_c_load; // @[Reg.scala 15:16] - wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 778:24] - wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 792:82] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 775:48] - wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:70] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 775:58] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 776:48] - wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 776:70] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 776:58] - wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 781:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 781:24] - wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 793:47] - wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 780:24] - wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 793:67] - wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 467:42] - reg r_d_csrwen; // @[beh_lib.scala 366:14] - reg r_d_i0valid; // @[beh_lib.scala 366:14] - wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 475:34] - reg [11:0] r_d_csrwaddr; // @[beh_lib.scala 366:14] - wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 478:45] - wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 478:75] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 478:59] - wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 478:90] - wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 478:103] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 478:119] - reg csr_read_x; // @[el2_dec_decode_ctl.scala 480:52] - reg csr_clr_x; // @[el2_dec_decode_ctl.scala 481:51] - reg csr_set_x; // @[el2_dec_decode_ctl.scala 482:51] - reg csr_write_x; // @[el2_dec_decode_ctl.scala 483:53] - reg csr_imm_x; // @[el2_dec_decode_ctl.scala 484:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] - reg [4:0] csrimm_x; // @[beh_lib.scala 356:14] - reg [31:0] csr_rddata_x; // @[beh_lib.scala 356:14] + wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 777:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 777:24] + wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 791:78] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 774:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 774:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 774:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 775:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 775:58] + wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 780:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 780:24] + wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:43] + wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 779:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 779:24] + wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 792:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 466:42] + reg r_d_csrwen; // @[el2_lib.scala 501:16] + reg r_d_i0valid; // @[el2_lib.scala 501:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 501:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 477:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 477:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 477:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 477:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 477:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 477:119] + reg csr_read_x; // @[el2_dec_decode_ctl.scala 479:52] + reg csr_clr_x; // @[el2_dec_decode_ctl.scala 480:51] + reg csr_set_x; // @[el2_dec_decode_ctl.scala 481:51] + reg csr_write_x; // @[el2_dec_decode_ctl.scala 482:53] + reg csr_imm_x; // @[el2_dec_decode_ctl.scala 483:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 660:50] + reg [4:0] csrimm_x; // @[el2_lib.scala 491:16] + reg [31:0] csr_rddata_x; // @[el2_lib.scala 491:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] - wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 492:25] + wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 491:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] - wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 495:56] - wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 495:53] - wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 496:53] + wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 494:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 494:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 495:35] wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] - wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 506:44] - wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 506:64] - wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 506:61] - wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 509:59] - wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 511:34] - wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 511:46] - wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 511:61] - wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 511:75] - reg r_d_csrwonly; // @[beh_lib.scala 366:14] - wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 714:37] - reg [31:0] i0_result_r_raw; // @[beh_lib.scala 356:14] - wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 714:27] - reg x_d_csrwonly; // @[beh_lib.scala 366:14] - wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 520:38] - reg wbd_csrwonly; // @[beh_lib.scala 366:14] - wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 520:53] - wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 523:48] - wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 524:40] - wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 527:34] - wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 527:57] - wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 527:73] - wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 527:91] + wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 505:44] + wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 505:64] + wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 505:61] + wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 508:59] + wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 510:34] + wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 510:46] + wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 510:61] + wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 510:75] + reg r_d_csrwonly; // @[el2_lib.scala 501:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 713:37] + reg [31:0] i0_result_r_raw; // @[el2_lib.scala 491:16] + wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 713:27] + reg x_d_csrwonly; // @[el2_lib.scala 501:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 519:38] + reg wbd_csrwonly; // @[el2_lib.scala 501:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 519:53] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 522:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 523:40] + wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 526:34] + wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 526:57] + wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 526:73] + wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 526:91] wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 539:44] - reg [31:0] _T_465; // @[beh_lib.scala 356:14] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 543:42] - wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 545:40] - wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 545:59] - wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 545:81] - wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 545:95] - wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 546:20] - wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 546:45] - wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 568:41] - wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 569:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 571:37] - wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 546:62] - wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 547:19] - wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 547:36] - wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 547:34] - wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 546:79] - wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 547:47] - wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:49] - wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 742:88] - wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 742:69] - wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 743:52] - wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 743:91] - wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 743:72] - wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 742:102] - wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 548:21] - wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 548:45] - wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:65] - wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 550:39] - wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 551:63] - wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 551:38] - wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 552:38] - wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 552:57] - wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 556:46] - wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 556:44] - wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] - wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 557:46] - wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 557:44] - wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 557:61] - wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 557:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 558:46] - wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 562:51] - wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 590:44] + wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 538:44] + reg [31:0] _T_465; // @[el2_lib.scala 491:16] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 542:42] + wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 544:40] + wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 544:59] + wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 544:81] + wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 544:95] + wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 545:20] + wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 545:45] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 567:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 568:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 570:37] + wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 545:62] + wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 546:19] + wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 546:36] + wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 546:34] + wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 545:79] + wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 546:47] + wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 741:49] + wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 741:88] + wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 741:69] + wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:25] + wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 742:64] + wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 742:45] + wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 741:102] + wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 547:21] + wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 547:45] + wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 549:65] + wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 549:39] + wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:63] + wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 550:38] + wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 551:38] + wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 551:57] + wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 555:46] + wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 555:44] + wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 555:61] + wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 556:46] + wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 556:44] + wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] + wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 556:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 557:46] + wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:51] + wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 589:44] wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 658:49] - wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] - reg x_t_legal; // @[beh_lib.scala 366:14] - reg x_t_icaf; // @[beh_lib.scala 366:14] - reg x_t_icaf_f1; // @[beh_lib.scala 366:14] - reg [1:0] x_t_icaf_type; // @[beh_lib.scala 366:14] - reg x_t_fence_i; // @[beh_lib.scala 366:14] - reg [3:0] x_t_i0trigger; // @[beh_lib.scala 366:14] - reg [3:0] x_t_pmu_i0_itype; // @[beh_lib.scala 366:14] - reg x_t_pmu_i0_br_unpred; // @[beh_lib.scala 366:14] + wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 657:49] + wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 657:53] + reg x_t_legal; // @[el2_lib.scala 501:16] + reg x_t_icaf; // @[el2_lib.scala 501:16] + reg x_t_icaf_f1; // @[el2_lib.scala 501:16] + reg [1:0] x_t_icaf_type; // @[el2_lib.scala 501:16] + reg x_t_fence_i; // @[el2_lib.scala 501:16] + reg [3:0] x_t_i0trigger; // @[el2_lib.scala 501:16] + reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 501:16] + reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 501:16] wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 603:39] - reg r_t_legal; // @[beh_lib.scala 366:14] - reg r_t_icaf; // @[beh_lib.scala 366:14] - reg r_t_icaf_f1; // @[beh_lib.scala 366:14] - reg [1:0] r_t_icaf_type; // @[beh_lib.scala 366:14] - reg r_t_fence_i; // @[beh_lib.scala 366:14] - reg [3:0] r_t_i0trigger; // @[beh_lib.scala 366:14] - reg [3:0] r_t_pmu_i0_itype; // @[beh_lib.scala 366:14] - reg r_t_pmu_i0_br_unpred; // @[beh_lib.scala 366:14] - reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 606:36] - reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 607:37] - reg r_d_i0store; // @[beh_lib.scala 366:14] - wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 611:56] + wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 602:39] + reg r_t_legal; // @[el2_lib.scala 501:16] + reg r_t_icaf; // @[el2_lib.scala 501:16] + reg r_t_icaf_f1; // @[el2_lib.scala 501:16] + reg [1:0] r_t_icaf_type; // @[el2_lib.scala 501:16] + reg r_t_fence_i; // @[el2_lib.scala 501:16] + reg [3:0] r_t_i0trigger; // @[el2_lib.scala 501:16] + reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 501:16] + reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 501:16] + reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 605:36] + reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 606:37] + reg r_d_i0store; // @[el2_lib.scala 501:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 610:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 611:72] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 611:95] - reg r_d_i0div; // @[beh_lib.scala 366:14] - wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 617:53] - wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] - wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 629:49] - wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 630:48] - wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 630:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] - wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 635:27] - wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 635:38] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 610:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 610:95] + reg r_d_i0div; // @[el2_lib.scala 501:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 616:53] + wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 627:49] + wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] + wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 629:48] + wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 629:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 633:38] + wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 634:27] + wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] @@ -1750,138 +1737,138 @@ module el2_dec_decode_ctl( wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72] - wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 646:40] + wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 645:26] wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72] wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 652:44] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 649:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] reg i0_x_c_mul; // @[Reg.scala 15:16] reg i0_x_c_alu; // @[Reg.scala 15:16] reg i0_r_c_mul; // @[Reg.scala 15:16] reg i0_r_c_alu; // @[Reg.scala 15:16] - wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 660:49] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 662:50] - reg x_d_i0store; // @[beh_lib.scala 366:14] - reg x_d_i0div; // @[beh_lib.scala 366:14] - reg x_d_csrwen; // @[beh_lib.scala 366:14] - reg [11:0] x_d_csrwaddr; // @[beh_lib.scala 366:14] - wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 684:37] - wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 685:37] - wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 700:49] - wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 700:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 700:65] - wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 709:45] - wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 715:52] + wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 659:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] + reg x_d_i0store; // @[el2_lib.scala 501:16] + reg x_d_i0div; // @[el2_lib.scala 501:16] + reg x_d_csrwen; // @[el2_lib.scala 501:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 501:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 683:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 684:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 699:49] + wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 699:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 699:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 708:42] + wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 714:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] - reg [11:0] last_br_immed_x; // @[beh_lib.scala 356:14] - wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 723:40] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 723:55] - wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 725:69] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 725:57] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:30] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 725:86] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 727:30] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 727:57] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 726:59] - wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 731:51] - wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 732:26] - wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 732:24] - wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 732:51] - wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 732:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 732:72] - wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 731:65] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 735:55] - wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 737:62] - wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 737:60] - wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 737:81] - wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 737:79] - reg _T_821; // @[el2_dec_decode_ctl.scala 739:54] + reg [11:0] last_br_immed_x; // @[el2_lib.scala 491:16] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 722:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 722:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 724:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 724:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 725:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 724:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 726:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 725:59] + wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 730:51] + wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 731:26] + wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 731:24] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 731:51] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 731:39] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 731:72] + wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 730:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 734:55] + wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 736:62] + wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 736:60] + wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 736:81] + wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 736:79] + reg _T_821; // @[el2_dec_decode_ctl.scala 738:54] reg [4:0] _T_830; // @[Reg.scala 27:20] - reg [31:0] i0_inst_x; // @[beh_lib.scala 356:14] - reg [31:0] i0_inst_r; // @[beh_lib.scala 356:14] - reg [31:0] i0_inst_wb; // @[beh_lib.scala 356:14] - reg [31:0] _T_837; // @[beh_lib.scala 356:14] - reg [30:0] i0_pc_wb; // @[beh_lib.scala 356:14] - reg [30:0] _T_840; // @[beh_lib.scala 356:14] - reg [30:0] dec_i0_pc_r; // @[beh_lib.scala 356:14] + reg [31:0] i0_inst_x; // @[el2_lib.scala 491:16] + reg [31:0] i0_inst_r; // @[el2_lib.scala 491:16] + reg [31:0] i0_inst_wb; // @[el2_lib.scala 491:16] + reg [31:0] _T_837; // @[el2_lib.scala 491:16] + reg [30:0] i0_pc_wb; // @[el2_lib.scala 491:16] + reg [30:0] _T_840; // @[el2_lib.scala 491:16] + reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 491:16] wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 310:31] - wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 311:27] - wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 312:27] - wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 314:27] - wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 314:25] - wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 315:8] - wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 315:14] - wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 316:13] + wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 206:31] + wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 207:27] + wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 208:27] + wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 210:28] + wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 210:26] + wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 211:20] + wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 211:26] + wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 212:26] wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72] wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72] wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 778:61] - wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 778:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 778:24] - wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 780:61] - wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 780:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 780:24] - wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 798:62] - wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 798:119] - wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 798:89] - wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 800:62] - wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 800:119] - wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 800:89] - wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 803:69] - wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 803:48] - wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:111] - wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:199] - wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 803:156] + wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 777:61] + wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 777:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 777:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 777:24] + wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 779:61] + wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 779:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 779:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 779:24] + wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 797:62] + wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 797:119] + wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 797:89] + wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 799:62] + wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 799:119] + wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 799:89] + wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 802:66] + wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 802:45] + wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 802:108] + wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 802:196] + wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 802:153] wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58] - wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 805:70] - wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 805:48] - wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:112] - wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:199] - wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 805:156] + wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 804:67] + wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 804:45] + wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 804:109] + wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 804:196] + wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 804:153] wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58] - wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 807:78] - wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 807:99] - wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:116] - wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 807:96] - wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 808:78] - wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 808:99] - wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 808:116] - wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 808:96] - wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 813:30] - wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 813:49] - wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 813:47] - wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 813:66] + wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 806:75] + wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 806:96] + wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 806:113] + wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 806:93] + wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 807:75] + wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 807:96] + wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:113] + wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 807:93] + wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 812:6] + wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 812:25] + wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 812:23] + wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 812:42] wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72] - wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 818:31] - wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 818:50] - wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 818:48] - wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 818:67] + wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 817:6] + wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 817:25] + wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 817:23] + wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 817:42] wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72] - wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 820:68] - wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 820:50] - wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 820:89] - wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 820:87] - wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 820:112] - wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 822:6] - wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 822:27] - wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 822:39] - wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 823:39] + wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 819:68] + wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 819:50] + wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 819:89] + wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 819:87] + wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 819:112] + wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 821:6] + wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 821:27] + wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 821:39] + wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 822:39] wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72] @@ -1891,11 +1878,11 @@ module el2_dec_decode_ctl( .io_en(data_gated_cgc_io_en), .io_scan_mode(data_gated_cgc_io_scan_mode) ); - el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 396:24] + el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 395:22] .io_ins(i0_dec_io_ins), .io_out_alu(i0_dec_io_out_alu), - .io_out_rs2(i0_dec_io_out_rs2), .io_out_rs1(i0_dec_io_out_rs1), + .io_out_rs2(i0_dec_io_out_rs2), .io_out_imm12(i0_dec_io_out_imm12), .io_out_rd(i0_dec_io_out_rd), .io_out_shimm5(i0_dec_io_out_shimm5), @@ -1944,129 +1931,129 @@ module el2_dec_decode_ctl( .io_out_pm_alu(i0_dec_io_out_pm_alu), .io_out_legal(i0_dec_io_out_legal) ); - rvclkhdr rvclkhdr ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[beh_lib.scala 360:21] + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 495:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[beh_lib.scala 360:21] + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 495:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[beh_lib.scala 360:21] + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 495:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[beh_lib.scala 360:21] + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 495:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[beh_lib.scala 360:21] + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 495:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[beh_lib.scala 350:21] + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 436:23] - assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 757:22] - assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 760:20] - assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 628:24] - assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 629:24] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 631:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 632:19] - assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 637:21] - assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 715:24] + assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 435:23] + assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 756:22] + assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 759:20] + assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 627:24] + assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 628:24] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 630:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 631:19] + assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 636:21] + assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 714:24] assign io_i0_ap_land = _T_40 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 288:20] assign io_i0_ap_lor = _T_40 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 289:20] assign io_i0_ap_lxor = _T_40 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 290:20] @@ -2086,33 +2073,33 @@ module el2_dec_decode_ctl( assign io_i0_ap_predict_nt = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 283:26] assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 300:22] assign io_i0_ap_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 301:22] - assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 556:22 el2_dec_decode_ctl.scala 622:22] - assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 576:26] - assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 810:34] - assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 815:34] - assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 698:27] - assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 700:32] - assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 701:26] + assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 555:22 el2_dec_decode_ctl.scala 621:22] + assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 575:26] + assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 809:31] + assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 814:31] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 697:27] + assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 699:32] + assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 700:26] assign io_dec_i0_select_pc_d = _T_40 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 274:25] - assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 807:37] - assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 808:37] - assign io_lsu_p_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 442:30] - assign io_lsu_p_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 448:41] - assign io_lsu_p_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 449:41] - assign io_lsu_p_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 441:30 el2_dec_decode_ctl.scala 450:41] - assign io_lsu_p_dword = 1'h0; // @[el2_dec_decode_ctl.scala 438:11] - assign io_lsu_p_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 440:30 el2_dec_decode_ctl.scala 446:41] - assign io_lsu_p_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 447:41] - assign io_lsu_p_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 454:41] - assign io_lsu_p_dma = 1'h0; // @[el2_dec_decode_ctl.scala 438:11] - assign io_lsu_p_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 452:41] - assign io_lsu_p_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 451:41] - assign io_lsu_p_store_data_bypass_m = 1'h0; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 453:41] - assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 438:11 el2_dec_decode_ctl.scala 443:30 el2_dec_decode_ctl.scala 445:41] - assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] - assign io_mul_p_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:21] - assign io_mul_p_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:21] - assign io_mul_p_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 434:21] + assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 806:34] + assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 807:34] + assign io_lsu_p_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 441:24] + assign io_lsu_p_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 447:35] + assign io_lsu_p_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 448:35] + assign io_lsu_p_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 440:24 el2_dec_decode_ctl.scala 449:35] + assign io_lsu_p_dword = 1'h0; // @[el2_dec_decode_ctl.scala 437:12] + assign io_lsu_p_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 439:24 el2_dec_decode_ctl.scala 445:35] + assign io_lsu_p_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 446:35] + assign io_lsu_p_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 453:35] + assign io_lsu_p_dma = 1'h0; // @[el2_dec_decode_ctl.scala 437:12] + assign io_lsu_p_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 451:35] + assign io_lsu_p_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 450:35] + assign io_lsu_p_store_data_bypass_m = 1'h0; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 452:35] + assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 437:12 el2_dec_decode_ctl.scala 442:24 el2_dec_decode_ctl.scala 444:35] + assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 430:21] + assign io_mul_p_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] + assign io_mul_p_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:21] + assign io_mul_p_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:21] assign io_mul_p_bext = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] assign io_mul_p_bdep = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] assign io_mul_p_clmul = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] @@ -2128,35 +2115,35 @@ module el2_dec_decode_ctl( assign io_mul_p_crc32c_h = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] assign io_mul_p_crc32c_w = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] assign io_mul_p_bfp = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] - assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 427:21] - assign io_div_p_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 428:21] - assign io_div_p_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 429:21] - assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 745:19] - assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 734:29] - assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 820:26] - assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 821:23] - assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 458:21] - assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 467:24] - assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 533:24] - assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 470:24] - assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 475:20] - assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 471:23] - assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 518:24] - assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 478:27] - assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 582:30] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 616:39 el2_dec_decode_ctl.scala 617:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 763:27] - assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 540:23] - assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 768:25] + assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 426:21] + assign io_div_p_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 427:21] + assign io_div_p_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 428:21] + assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 744:19] + assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 733:29] + assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 819:26] + assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 820:23] + assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 457:21] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 466:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 469:24] + assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 474:20] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 470:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 517:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 477:27] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 581:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 615:39 el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 615:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 762:27] + assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 539:23] + assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 767:25] assign io_dec_i0_predict_p_d_misp = 1'h0; // @[el2_dec_decode_ctl.scala 230:38] assign io_dec_i0_predict_p_d_ataken = 1'h0; // @[el2_dec_decode_ctl.scala 231:38] assign io_dec_i0_predict_p_d_boffset = 1'h0; // @[el2_dec_decode_ctl.scala 232:38] @@ -2174,78 +2161,78 @@ module el2_dec_decode_ctl( assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 252:32] assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 248:32] assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 249:32] - assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 666:27] - assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 667:27] - assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 562:27] - assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 564:29] - assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 563:29] + assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 665:27] + assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 666:27] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 560:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 561:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 563:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 562:29] assign io_dec_nonblock_load_wen = _T_199 & _T_200; // @[el2_dec_decode_ctl.scala 357:28] assign io_dec_nonblock_load_waddr = _T_245 | _T_237; // @[el2_dec_decode_ctl.scala 354:29 el2_dec_decode_ctl.scala 364:29] - assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 502:22] - assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 506:25] - assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 739:21] + assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 501:22] + assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 505:25] + assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 738:21] assign data_gated_cgc_io_clk = clock; // @[el2_dec_decode_ctl.scala 224:31] assign data_gated_cgc_io_en = _T_15 | _T_16; // @[el2_dec_decode_ctl.scala 222:31] assign data_gated_cgc_io_scan_mode = io_scan_mode; // @[el2_dec_decode_ctl.scala 223:31] - assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 397:18] - assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[beh_lib.scala 353:15] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_3_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[beh_lib.scala 353:15] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_4_io_clk = clock; // @[beh_lib.scala 362:16] - assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[beh_lib.scala 363:15] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[beh_lib.scala 364:22] - assign rvclkhdr_5_io_clk = clock; // @[beh_lib.scala 362:16] - assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[beh_lib.scala 363:15] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[beh_lib.scala 364:22] - assign rvclkhdr_6_io_clk = clock; // @[beh_lib.scala 362:16] - assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[beh_lib.scala 363:15] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[beh_lib.scala 364:22] - assign rvclkhdr_7_io_clk = clock; // @[beh_lib.scala 362:16] - assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[beh_lib.scala 363:15] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[beh_lib.scala 364:22] - assign rvclkhdr_8_io_clk = clock; // @[beh_lib.scala 362:16] - assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[beh_lib.scala 363:15] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[beh_lib.scala 364:22] - assign rvclkhdr_9_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_10_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_11_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[beh_lib.scala 353:15] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_12_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_13_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_14_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_15_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_16_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_17_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] - assign rvclkhdr_18_io_clk = clock; // @[beh_lib.scala 352:16] - assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[beh_lib.scala 353:15] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[beh_lib.scala 354:22] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 396:16] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 497:18] + assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 498:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 499:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2823,7 +2810,7 @@ end // initial if (reset) begin cam_raw_0_tag <= 3'h0; end else if (cam_wen[0]) begin - cam_raw_0_tag <= io_lsu_nonblock_load_tag_m; + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_106) begin cam_raw_0_tag <= 3'h0; end @@ -2841,7 +2828,7 @@ end // initial if (reset) begin cam_raw_1_tag <= 3'h0; end else if (cam_wen[1]) begin - cam_raw_1_tag <= io_lsu_nonblock_load_tag_m; + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_132) begin cam_raw_1_tag <= 3'h0; end @@ -2859,7 +2846,7 @@ end // initial if (reset) begin cam_raw_2_tag <= 3'h0; end else if (cam_wen[2]) begin - cam_raw_2_tag <= io_lsu_nonblock_load_tag_m; + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_158) begin cam_raw_2_tag <= 3'h0; end @@ -2877,7 +2864,7 @@ end // initial if (reset) begin cam_raw_3_tag <= 3'h0; end else if (cam_wen[3]) begin - cam_raw_3_tag <= io_lsu_nonblock_load_tag_m; + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_184) begin cam_raw_3_tag <= 3'h0; end @@ -3397,4 +3384,3 @@ end // initial end end endmodule - diff --git a/el2_dec_gpr_ctl.anno.json b/el2_dec_gpr_ctl.anno.json new file mode 100644 index 00000000..33d139f2 --- /dev/null +++ b/el2_dec_gpr_ctl.anno.json @@ -0,0 +1,37 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1", + "sources":[ + "~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0", + "sources":[ + "~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_gpr_ctl.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_gpr_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_gpr_ctl.fir b/el2_dec_gpr_ctl.fir new file mode 100644 index 00000000..0fd1bbfe --- /dev/null +++ b/el2_dec_gpr_ctl.fir @@ -0,0 +1,2074 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_gpr_ctl : + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_26 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_27 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_28 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_29 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_30 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_gpr_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} + + wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 11:30] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 12:30] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 13:22] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 14:22] + wire gpr_wr_en : UInt<32> @[el2_dec_gpr_ctl.scala 15:22] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 16:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 18:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 19:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 21:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 22:9] + node _T = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_1 = cat(w0v[2], _T) @[Cat.scala 29:58] + node _T_2 = cat(w0v[3], _T_1) @[Cat.scala 29:58] + node _T_3 = cat(w0v[4], _T_2) @[Cat.scala 29:58] + node _T_4 = cat(w0v[5], _T_3) @[Cat.scala 29:58] + node _T_5 = cat(w0v[6], _T_4) @[Cat.scala 29:58] + node _T_6 = cat(w0v[7], _T_5) @[Cat.scala 29:58] + node _T_7 = cat(w0v[8], _T_6) @[Cat.scala 29:58] + node _T_8 = cat(w0v[9], _T_7) @[Cat.scala 29:58] + node _T_9 = cat(w0v[10], _T_8) @[Cat.scala 29:58] + node _T_10 = cat(w0v[11], _T_9) @[Cat.scala 29:58] + node _T_11 = cat(w0v[12], _T_10) @[Cat.scala 29:58] + node _T_12 = cat(w0v[13], _T_11) @[Cat.scala 29:58] + node _T_13 = cat(w0v[14], _T_12) @[Cat.scala 29:58] + node _T_14 = cat(w0v[15], _T_13) @[Cat.scala 29:58] + node _T_15 = cat(w0v[16], _T_14) @[Cat.scala 29:58] + node _T_16 = cat(w0v[17], _T_15) @[Cat.scala 29:58] + node _T_17 = cat(w0v[18], _T_16) @[Cat.scala 29:58] + node _T_18 = cat(w0v[19], _T_17) @[Cat.scala 29:58] + node _T_19 = cat(w0v[20], _T_18) @[Cat.scala 29:58] + node _T_20 = cat(w0v[21], _T_19) @[Cat.scala 29:58] + node _T_21 = cat(w0v[22], _T_20) @[Cat.scala 29:58] + node _T_22 = cat(w0v[23], _T_21) @[Cat.scala 29:58] + node _T_23 = cat(w0v[24], _T_22) @[Cat.scala 29:58] + node _T_24 = cat(w0v[25], _T_23) @[Cat.scala 29:58] + node _T_25 = cat(w0v[26], _T_24) @[Cat.scala 29:58] + node _T_26 = cat(w0v[27], _T_25) @[Cat.scala 29:58] + node _T_27 = cat(w0v[28], _T_26) @[Cat.scala 29:58] + node _T_28 = cat(w0v[29], _T_27) @[Cat.scala 29:58] + node _T_29 = cat(w0v[30], _T_28) @[Cat.scala 29:58] + node _T_30 = cat(w0v[31], _T_29) @[Cat.scala 29:58] + node _T_31 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_32 = cat(w1v[2], _T_31) @[Cat.scala 29:58] + node _T_33 = cat(w1v[3], _T_32) @[Cat.scala 29:58] + node _T_34 = cat(w1v[4], _T_33) @[Cat.scala 29:58] + node _T_35 = cat(w1v[5], _T_34) @[Cat.scala 29:58] + node _T_36 = cat(w1v[6], _T_35) @[Cat.scala 29:58] + node _T_37 = cat(w1v[7], _T_36) @[Cat.scala 29:58] + node _T_38 = cat(w1v[8], _T_37) @[Cat.scala 29:58] + node _T_39 = cat(w1v[9], _T_38) @[Cat.scala 29:58] + node _T_40 = cat(w1v[10], _T_39) @[Cat.scala 29:58] + node _T_41 = cat(w1v[11], _T_40) @[Cat.scala 29:58] + node _T_42 = cat(w1v[12], _T_41) @[Cat.scala 29:58] + node _T_43 = cat(w1v[13], _T_42) @[Cat.scala 29:58] + node _T_44 = cat(w1v[14], _T_43) @[Cat.scala 29:58] + node _T_45 = cat(w1v[15], _T_44) @[Cat.scala 29:58] + node _T_46 = cat(w1v[16], _T_45) @[Cat.scala 29:58] + node _T_47 = cat(w1v[17], _T_46) @[Cat.scala 29:58] + node _T_48 = cat(w1v[18], _T_47) @[Cat.scala 29:58] + node _T_49 = cat(w1v[19], _T_48) @[Cat.scala 29:58] + node _T_50 = cat(w1v[20], _T_49) @[Cat.scala 29:58] + node _T_51 = cat(w1v[21], _T_50) @[Cat.scala 29:58] + node _T_52 = cat(w1v[22], _T_51) @[Cat.scala 29:58] + node _T_53 = cat(w1v[23], _T_52) @[Cat.scala 29:58] + node _T_54 = cat(w1v[24], _T_53) @[Cat.scala 29:58] + node _T_55 = cat(w1v[25], _T_54) @[Cat.scala 29:58] + node _T_56 = cat(w1v[26], _T_55) @[Cat.scala 29:58] + node _T_57 = cat(w1v[27], _T_56) @[Cat.scala 29:58] + node _T_58 = cat(w1v[28], _T_57) @[Cat.scala 29:58] + node _T_59 = cat(w1v[29], _T_58) @[Cat.scala 29:58] + node _T_60 = cat(w1v[30], _T_59) @[Cat.scala 29:58] + node _T_61 = cat(w1v[31], _T_60) @[Cat.scala 29:58] + node _T_62 = or(_T_30, _T_61) @[el2_dec_gpr_ctl.scala 23:51] + node _T_63 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_64 = cat(w2v[2], _T_63) @[Cat.scala 29:58] + node _T_65 = cat(w2v[3], _T_64) @[Cat.scala 29:58] + node _T_66 = cat(w2v[4], _T_65) @[Cat.scala 29:58] + node _T_67 = cat(w2v[5], _T_66) @[Cat.scala 29:58] + node _T_68 = cat(w2v[6], _T_67) @[Cat.scala 29:58] + node _T_69 = cat(w2v[7], _T_68) @[Cat.scala 29:58] + node _T_70 = cat(w2v[8], _T_69) @[Cat.scala 29:58] + node _T_71 = cat(w2v[9], _T_70) @[Cat.scala 29:58] + node _T_72 = cat(w2v[10], _T_71) @[Cat.scala 29:58] + node _T_73 = cat(w2v[11], _T_72) @[Cat.scala 29:58] + node _T_74 = cat(w2v[12], _T_73) @[Cat.scala 29:58] + node _T_75 = cat(w2v[13], _T_74) @[Cat.scala 29:58] + node _T_76 = cat(w2v[14], _T_75) @[Cat.scala 29:58] + node _T_77 = cat(w2v[15], _T_76) @[Cat.scala 29:58] + node _T_78 = cat(w2v[16], _T_77) @[Cat.scala 29:58] + node _T_79 = cat(w2v[17], _T_78) @[Cat.scala 29:58] + node _T_80 = cat(w2v[18], _T_79) @[Cat.scala 29:58] + node _T_81 = cat(w2v[19], _T_80) @[Cat.scala 29:58] + node _T_82 = cat(w2v[20], _T_81) @[Cat.scala 29:58] + node _T_83 = cat(w2v[21], _T_82) @[Cat.scala 29:58] + node _T_84 = cat(w2v[22], _T_83) @[Cat.scala 29:58] + node _T_85 = cat(w2v[23], _T_84) @[Cat.scala 29:58] + node _T_86 = cat(w2v[24], _T_85) @[Cat.scala 29:58] + node _T_87 = cat(w2v[25], _T_86) @[Cat.scala 29:58] + node _T_88 = cat(w2v[26], _T_87) @[Cat.scala 29:58] + node _T_89 = cat(w2v[27], _T_88) @[Cat.scala 29:58] + node _T_90 = cat(w2v[28], _T_89) @[Cat.scala 29:58] + node _T_91 = cat(w2v[29], _T_90) @[Cat.scala 29:58] + node _T_92 = cat(w2v[30], _T_91) @[Cat.scala 29:58] + node _T_93 = cat(w2v[31], _T_92) @[Cat.scala 29:58] + node _T_94 = or(_T_62, _T_93) @[el2_dec_gpr_ctl.scala 23:89] + gpr_wr_en <= _T_94 @[el2_dec_gpr_ctl.scala 23:12] + node _T_95 = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_96 = and(io.wen0, _T_95) @[el2_dec_gpr_ctl.scala 26:28] + w0v[1] <= _T_96 @[el2_dec_gpr_ctl.scala 26:16] + node _T_97 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_98 = and(io.wen1, _T_97) @[el2_dec_gpr_ctl.scala 27:28] + w1v[1] <= _T_98 @[el2_dec_gpr_ctl.scala 27:16] + node _T_99 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_100 = and(io.wen2, _T_99) @[el2_dec_gpr_ctl.scala 28:28] + w2v[1] <= _T_100 @[el2_dec_gpr_ctl.scala 28:16] + node _T_101 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_103 = and(_T_102, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_104 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_106 = and(_T_105, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_107 = or(_T_103, _T_106) @[el2_dec_gpr_ctl.scala 29:47] + node _T_108 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_110 = and(_T_109, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_111 = or(_T_107, _T_110) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[1] <= _T_111 @[el2_dec_gpr_ctl.scala 29:16] + node _T_112 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_113 = and(io.wen0, _T_112) @[el2_dec_gpr_ctl.scala 26:28] + w0v[2] <= _T_113 @[el2_dec_gpr_ctl.scala 26:16] + node _T_114 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_115 = and(io.wen1, _T_114) @[el2_dec_gpr_ctl.scala 27:28] + w1v[2] <= _T_115 @[el2_dec_gpr_ctl.scala 27:16] + node _T_116 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_117 = and(io.wen2, _T_116) @[el2_dec_gpr_ctl.scala 28:28] + w2v[2] <= _T_117 @[el2_dec_gpr_ctl.scala 28:16] + node _T_118 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_119 = mux(_T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_120 = and(_T_119, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_121 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_122 = mux(_T_121, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_123 = and(_T_122, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_124 = or(_T_120, _T_123) @[el2_dec_gpr_ctl.scala 29:47] + node _T_125 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_128 = or(_T_124, _T_127) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[2] <= _T_128 @[el2_dec_gpr_ctl.scala 29:16] + node _T_129 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_130 = and(io.wen0, _T_129) @[el2_dec_gpr_ctl.scala 26:28] + w0v[3] <= _T_130 @[el2_dec_gpr_ctl.scala 26:16] + node _T_131 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_132 = and(io.wen1, _T_131) @[el2_dec_gpr_ctl.scala 27:28] + w1v[3] <= _T_132 @[el2_dec_gpr_ctl.scala 27:16] + node _T_133 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_134 = and(io.wen2, _T_133) @[el2_dec_gpr_ctl.scala 28:28] + w2v[3] <= _T_134 @[el2_dec_gpr_ctl.scala 28:16] + node _T_135 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_136 = mux(_T_135, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_137 = and(_T_136, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_138 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_139 = mux(_T_138, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_140 = and(_T_139, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_141 = or(_T_137, _T_140) @[el2_dec_gpr_ctl.scala 29:47] + node _T_142 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(_T_143, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_145 = or(_T_141, _T_144) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[3] <= _T_145 @[el2_dec_gpr_ctl.scala 29:16] + node _T_146 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_147 = and(io.wen0, _T_146) @[el2_dec_gpr_ctl.scala 26:28] + w0v[4] <= _T_147 @[el2_dec_gpr_ctl.scala 26:16] + node _T_148 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_149 = and(io.wen1, _T_148) @[el2_dec_gpr_ctl.scala 27:28] + w1v[4] <= _T_149 @[el2_dec_gpr_ctl.scala 27:16] + node _T_150 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_151 = and(io.wen2, _T_150) @[el2_dec_gpr_ctl.scala 28:28] + w2v[4] <= _T_151 @[el2_dec_gpr_ctl.scala 28:16] + node _T_152 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_153 = mux(_T_152, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_154 = and(_T_153, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_155 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_156 = mux(_T_155, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_157 = and(_T_156, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_158 = or(_T_154, _T_157) @[el2_dec_gpr_ctl.scala 29:47] + node _T_159 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_161 = and(_T_160, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_162 = or(_T_158, _T_161) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[4] <= _T_162 @[el2_dec_gpr_ctl.scala 29:16] + node _T_163 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_164 = and(io.wen0, _T_163) @[el2_dec_gpr_ctl.scala 26:28] + w0v[5] <= _T_164 @[el2_dec_gpr_ctl.scala 26:16] + node _T_165 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_166 = and(io.wen1, _T_165) @[el2_dec_gpr_ctl.scala 27:28] + w1v[5] <= _T_166 @[el2_dec_gpr_ctl.scala 27:16] + node _T_167 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_168 = and(io.wen2, _T_167) @[el2_dec_gpr_ctl.scala 28:28] + w2v[5] <= _T_168 @[el2_dec_gpr_ctl.scala 28:16] + node _T_169 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_171 = and(_T_170, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_172 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(_T_173, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_175 = or(_T_171, _T_174) @[el2_dec_gpr_ctl.scala 29:47] + node _T_176 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_178 = and(_T_177, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_179 = or(_T_175, _T_178) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[5] <= _T_179 @[el2_dec_gpr_ctl.scala 29:16] + node _T_180 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_181 = and(io.wen0, _T_180) @[el2_dec_gpr_ctl.scala 26:28] + w0v[6] <= _T_181 @[el2_dec_gpr_ctl.scala 26:16] + node _T_182 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_183 = and(io.wen1, _T_182) @[el2_dec_gpr_ctl.scala 27:28] + w1v[6] <= _T_183 @[el2_dec_gpr_ctl.scala 27:16] + node _T_184 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_185 = and(io.wen2, _T_184) @[el2_dec_gpr_ctl.scala 28:28] + w2v[6] <= _T_185 @[el2_dec_gpr_ctl.scala 28:16] + node _T_186 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_187 = mux(_T_186, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_188 = and(_T_187, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_189 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_191 = and(_T_190, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_192 = or(_T_188, _T_191) @[el2_dec_gpr_ctl.scala 29:47] + node _T_193 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_196 = or(_T_192, _T_195) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[6] <= _T_196 @[el2_dec_gpr_ctl.scala 29:16] + node _T_197 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_198 = and(io.wen0, _T_197) @[el2_dec_gpr_ctl.scala 26:28] + w0v[7] <= _T_198 @[el2_dec_gpr_ctl.scala 26:16] + node _T_199 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_200 = and(io.wen1, _T_199) @[el2_dec_gpr_ctl.scala 27:28] + w1v[7] <= _T_200 @[el2_dec_gpr_ctl.scala 27:16] + node _T_201 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_202 = and(io.wen2, _T_201) @[el2_dec_gpr_ctl.scala 28:28] + w2v[7] <= _T_202 @[el2_dec_gpr_ctl.scala 28:16] + node _T_203 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_204 = mux(_T_203, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_205 = and(_T_204, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_206 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_208 = and(_T_207, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_209 = or(_T_205, _T_208) @[el2_dec_gpr_ctl.scala 29:47] + node _T_210 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_212 = and(_T_211, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_213 = or(_T_209, _T_212) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[7] <= _T_213 @[el2_dec_gpr_ctl.scala 29:16] + node _T_214 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_215 = and(io.wen0, _T_214) @[el2_dec_gpr_ctl.scala 26:28] + w0v[8] <= _T_215 @[el2_dec_gpr_ctl.scala 26:16] + node _T_216 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_217 = and(io.wen1, _T_216) @[el2_dec_gpr_ctl.scala 27:28] + w1v[8] <= _T_217 @[el2_dec_gpr_ctl.scala 27:16] + node _T_218 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_219 = and(io.wen2, _T_218) @[el2_dec_gpr_ctl.scala 28:28] + w2v[8] <= _T_219 @[el2_dec_gpr_ctl.scala 28:16] + node _T_220 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_222 = and(_T_221, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_223 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_225 = and(_T_224, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_226 = or(_T_222, _T_225) @[el2_dec_gpr_ctl.scala 29:47] + node _T_227 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_230 = or(_T_226, _T_229) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[8] <= _T_230 @[el2_dec_gpr_ctl.scala 29:16] + node _T_231 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_232 = and(io.wen0, _T_231) @[el2_dec_gpr_ctl.scala 26:28] + w0v[9] <= _T_232 @[el2_dec_gpr_ctl.scala 26:16] + node _T_233 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_234 = and(io.wen1, _T_233) @[el2_dec_gpr_ctl.scala 27:28] + w1v[9] <= _T_234 @[el2_dec_gpr_ctl.scala 27:16] + node _T_235 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_236 = and(io.wen2, _T_235) @[el2_dec_gpr_ctl.scala 28:28] + w2v[9] <= _T_236 @[el2_dec_gpr_ctl.scala 28:16] + node _T_237 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_238 = mux(_T_237, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_239 = and(_T_238, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_240 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_242 = and(_T_241, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_243 = or(_T_239, _T_242) @[el2_dec_gpr_ctl.scala 29:47] + node _T_244 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_246 = and(_T_245, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_247 = or(_T_243, _T_246) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[9] <= _T_247 @[el2_dec_gpr_ctl.scala 29:16] + node _T_248 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_249 = and(io.wen0, _T_248) @[el2_dec_gpr_ctl.scala 26:28] + w0v[10] <= _T_249 @[el2_dec_gpr_ctl.scala 26:16] + node _T_250 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_251 = and(io.wen1, _T_250) @[el2_dec_gpr_ctl.scala 27:28] + w1v[10] <= _T_251 @[el2_dec_gpr_ctl.scala 27:16] + node _T_252 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_253 = and(io.wen2, _T_252) @[el2_dec_gpr_ctl.scala 28:28] + w2v[10] <= _T_253 @[el2_dec_gpr_ctl.scala 28:16] + node _T_254 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_256 = and(_T_255, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_257 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_258 = mux(_T_257, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_259 = and(_T_258, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_260 = or(_T_256, _T_259) @[el2_dec_gpr_ctl.scala 29:47] + node _T_261 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_263 = and(_T_262, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_264 = or(_T_260, _T_263) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[10] <= _T_264 @[el2_dec_gpr_ctl.scala 29:16] + node _T_265 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_266 = and(io.wen0, _T_265) @[el2_dec_gpr_ctl.scala 26:28] + w0v[11] <= _T_266 @[el2_dec_gpr_ctl.scala 26:16] + node _T_267 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_268 = and(io.wen1, _T_267) @[el2_dec_gpr_ctl.scala 27:28] + w1v[11] <= _T_268 @[el2_dec_gpr_ctl.scala 27:16] + node _T_269 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_270 = and(io.wen2, _T_269) @[el2_dec_gpr_ctl.scala 28:28] + w2v[11] <= _T_270 @[el2_dec_gpr_ctl.scala 28:16] + node _T_271 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_273 = and(_T_272, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_274 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_276 = and(_T_275, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_277 = or(_T_273, _T_276) @[el2_dec_gpr_ctl.scala 29:47] + node _T_278 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_281 = or(_T_277, _T_280) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[11] <= _T_281 @[el2_dec_gpr_ctl.scala 29:16] + node _T_282 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_283 = and(io.wen0, _T_282) @[el2_dec_gpr_ctl.scala 26:28] + w0v[12] <= _T_283 @[el2_dec_gpr_ctl.scala 26:16] + node _T_284 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_285 = and(io.wen1, _T_284) @[el2_dec_gpr_ctl.scala 27:28] + w1v[12] <= _T_285 @[el2_dec_gpr_ctl.scala 27:16] + node _T_286 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_287 = and(io.wen2, _T_286) @[el2_dec_gpr_ctl.scala 28:28] + w2v[12] <= _T_287 @[el2_dec_gpr_ctl.scala 28:16] + node _T_288 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_291 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_293 = and(_T_292, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_294 = or(_T_290, _T_293) @[el2_dec_gpr_ctl.scala 29:47] + node _T_295 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_297 = and(_T_296, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_298 = or(_T_294, _T_297) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[12] <= _T_298 @[el2_dec_gpr_ctl.scala 29:16] + node _T_299 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_300 = and(io.wen0, _T_299) @[el2_dec_gpr_ctl.scala 26:28] + w0v[13] <= _T_300 @[el2_dec_gpr_ctl.scala 26:16] + node _T_301 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_302 = and(io.wen1, _T_301) @[el2_dec_gpr_ctl.scala 27:28] + w1v[13] <= _T_302 @[el2_dec_gpr_ctl.scala 27:16] + node _T_303 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_304 = and(io.wen2, _T_303) @[el2_dec_gpr_ctl.scala 28:28] + w2v[13] <= _T_304 @[el2_dec_gpr_ctl.scala 28:16] + node _T_305 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_307 = and(_T_306, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_308 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_309 = mux(_T_308, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_310 = and(_T_309, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_311 = or(_T_307, _T_310) @[el2_dec_gpr_ctl.scala 29:47] + node _T_312 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_314 = and(_T_313, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_315 = or(_T_311, _T_314) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[13] <= _T_315 @[el2_dec_gpr_ctl.scala 29:16] + node _T_316 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_317 = and(io.wen0, _T_316) @[el2_dec_gpr_ctl.scala 26:28] + w0v[14] <= _T_317 @[el2_dec_gpr_ctl.scala 26:16] + node _T_318 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_319 = and(io.wen1, _T_318) @[el2_dec_gpr_ctl.scala 27:28] + w1v[14] <= _T_319 @[el2_dec_gpr_ctl.scala 27:16] + node _T_320 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_321 = and(io.wen2, _T_320) @[el2_dec_gpr_ctl.scala 28:28] + w2v[14] <= _T_321 @[el2_dec_gpr_ctl.scala 28:16] + node _T_322 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_323 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_324 = and(_T_323, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_325 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_326 = mux(_T_325, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_327 = and(_T_326, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_328 = or(_T_324, _T_327) @[el2_dec_gpr_ctl.scala 29:47] + node _T_329 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_331 = and(_T_330, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_332 = or(_T_328, _T_331) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[14] <= _T_332 @[el2_dec_gpr_ctl.scala 29:16] + node _T_333 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_334 = and(io.wen0, _T_333) @[el2_dec_gpr_ctl.scala 26:28] + w0v[15] <= _T_334 @[el2_dec_gpr_ctl.scala 26:16] + node _T_335 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_336 = and(io.wen1, _T_335) @[el2_dec_gpr_ctl.scala 27:28] + w1v[15] <= _T_336 @[el2_dec_gpr_ctl.scala 27:16] + node _T_337 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_338 = and(io.wen2, _T_337) @[el2_dec_gpr_ctl.scala 28:28] + w2v[15] <= _T_338 @[el2_dec_gpr_ctl.scala 28:16] + node _T_339 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_340 = mux(_T_339, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_341 = and(_T_340, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_342 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_343 = mux(_T_342, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_344 = and(_T_343, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_345 = or(_T_341, _T_344) @[el2_dec_gpr_ctl.scala 29:47] + node _T_346 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_348 = and(_T_347, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_349 = or(_T_345, _T_348) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[15] <= _T_349 @[el2_dec_gpr_ctl.scala 29:16] + node _T_350 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_351 = and(io.wen0, _T_350) @[el2_dec_gpr_ctl.scala 26:28] + w0v[16] <= _T_351 @[el2_dec_gpr_ctl.scala 26:16] + node _T_352 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_353 = and(io.wen1, _T_352) @[el2_dec_gpr_ctl.scala 27:28] + w1v[16] <= _T_353 @[el2_dec_gpr_ctl.scala 27:16] + node _T_354 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_355 = and(io.wen2, _T_354) @[el2_dec_gpr_ctl.scala 28:28] + w2v[16] <= _T_355 @[el2_dec_gpr_ctl.scala 28:16] + node _T_356 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_357 = mux(_T_356, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_358 = and(_T_357, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_359 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_360 = mux(_T_359, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_361 = and(_T_360, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_362 = or(_T_358, _T_361) @[el2_dec_gpr_ctl.scala 29:47] + node _T_363 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_366 = or(_T_362, _T_365) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[16] <= _T_366 @[el2_dec_gpr_ctl.scala 29:16] + node _T_367 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_368 = and(io.wen0, _T_367) @[el2_dec_gpr_ctl.scala 26:28] + w0v[17] <= _T_368 @[el2_dec_gpr_ctl.scala 26:16] + node _T_369 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_370 = and(io.wen1, _T_369) @[el2_dec_gpr_ctl.scala 27:28] + w1v[17] <= _T_370 @[el2_dec_gpr_ctl.scala 27:16] + node _T_371 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_372 = and(io.wen2, _T_371) @[el2_dec_gpr_ctl.scala 28:28] + w2v[17] <= _T_372 @[el2_dec_gpr_ctl.scala 28:16] + node _T_373 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_374 = mux(_T_373, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_375 = and(_T_374, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_376 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_377 = mux(_T_376, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_378 = and(_T_377, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_379 = or(_T_375, _T_378) @[el2_dec_gpr_ctl.scala 29:47] + node _T_380 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_382 = and(_T_381, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_383 = or(_T_379, _T_382) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[17] <= _T_383 @[el2_dec_gpr_ctl.scala 29:16] + node _T_384 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_385 = and(io.wen0, _T_384) @[el2_dec_gpr_ctl.scala 26:28] + w0v[18] <= _T_385 @[el2_dec_gpr_ctl.scala 26:16] + node _T_386 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_387 = and(io.wen1, _T_386) @[el2_dec_gpr_ctl.scala 27:28] + w1v[18] <= _T_387 @[el2_dec_gpr_ctl.scala 27:16] + node _T_388 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_389 = and(io.wen2, _T_388) @[el2_dec_gpr_ctl.scala 28:28] + w2v[18] <= _T_389 @[el2_dec_gpr_ctl.scala 28:16] + node _T_390 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_391 = mux(_T_390, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_392 = and(_T_391, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_393 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_394 = mux(_T_393, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_395 = and(_T_394, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_396 = or(_T_392, _T_395) @[el2_dec_gpr_ctl.scala 29:47] + node _T_397 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_399 = and(_T_398, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_400 = or(_T_396, _T_399) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[18] <= _T_400 @[el2_dec_gpr_ctl.scala 29:16] + node _T_401 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_402 = and(io.wen0, _T_401) @[el2_dec_gpr_ctl.scala 26:28] + w0v[19] <= _T_402 @[el2_dec_gpr_ctl.scala 26:16] + node _T_403 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_404 = and(io.wen1, _T_403) @[el2_dec_gpr_ctl.scala 27:28] + w1v[19] <= _T_404 @[el2_dec_gpr_ctl.scala 27:16] + node _T_405 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_406 = and(io.wen2, _T_405) @[el2_dec_gpr_ctl.scala 28:28] + w2v[19] <= _T_406 @[el2_dec_gpr_ctl.scala 28:16] + node _T_407 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_409 = and(_T_408, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_410 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_411 = mux(_T_410, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_412 = and(_T_411, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_413 = or(_T_409, _T_412) @[el2_dec_gpr_ctl.scala 29:47] + node _T_414 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_417 = or(_T_413, _T_416) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[19] <= _T_417 @[el2_dec_gpr_ctl.scala 29:16] + node _T_418 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_419 = and(io.wen0, _T_418) @[el2_dec_gpr_ctl.scala 26:28] + w0v[20] <= _T_419 @[el2_dec_gpr_ctl.scala 26:16] + node _T_420 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_421 = and(io.wen1, _T_420) @[el2_dec_gpr_ctl.scala 27:28] + w1v[20] <= _T_421 @[el2_dec_gpr_ctl.scala 27:16] + node _T_422 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_423 = and(io.wen2, _T_422) @[el2_dec_gpr_ctl.scala 28:28] + w2v[20] <= _T_423 @[el2_dec_gpr_ctl.scala 28:16] + node _T_424 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_426 = and(_T_425, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_427 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_428 = mux(_T_427, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_429 = and(_T_428, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_430 = or(_T_426, _T_429) @[el2_dec_gpr_ctl.scala 29:47] + node _T_431 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_433 = and(_T_432, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_434 = or(_T_430, _T_433) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[20] <= _T_434 @[el2_dec_gpr_ctl.scala 29:16] + node _T_435 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_436 = and(io.wen0, _T_435) @[el2_dec_gpr_ctl.scala 26:28] + w0v[21] <= _T_436 @[el2_dec_gpr_ctl.scala 26:16] + node _T_437 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_438 = and(io.wen1, _T_437) @[el2_dec_gpr_ctl.scala 27:28] + w1v[21] <= _T_438 @[el2_dec_gpr_ctl.scala 27:16] + node _T_439 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_440 = and(io.wen2, _T_439) @[el2_dec_gpr_ctl.scala 28:28] + w2v[21] <= _T_440 @[el2_dec_gpr_ctl.scala 28:16] + node _T_441 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_442 = mux(_T_441, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_443 = and(_T_442, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_444 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_446 = and(_T_445, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_447 = or(_T_443, _T_446) @[el2_dec_gpr_ctl.scala 29:47] + node _T_448 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_451 = or(_T_447, _T_450) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[21] <= _T_451 @[el2_dec_gpr_ctl.scala 29:16] + node _T_452 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_453 = and(io.wen0, _T_452) @[el2_dec_gpr_ctl.scala 26:28] + w0v[22] <= _T_453 @[el2_dec_gpr_ctl.scala 26:16] + node _T_454 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_455 = and(io.wen1, _T_454) @[el2_dec_gpr_ctl.scala 27:28] + w1v[22] <= _T_455 @[el2_dec_gpr_ctl.scala 27:16] + node _T_456 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_457 = and(io.wen2, _T_456) @[el2_dec_gpr_ctl.scala 28:28] + w2v[22] <= _T_457 @[el2_dec_gpr_ctl.scala 28:16] + node _T_458 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(_T_459, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_461 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_462 = mux(_T_461, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_463 = and(_T_462, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_464 = or(_T_460, _T_463) @[el2_dec_gpr_ctl.scala 29:47] + node _T_465 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_467 = and(_T_466, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_468 = or(_T_464, _T_467) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[22] <= _T_468 @[el2_dec_gpr_ctl.scala 29:16] + node _T_469 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_470 = and(io.wen0, _T_469) @[el2_dec_gpr_ctl.scala 26:28] + w0v[23] <= _T_470 @[el2_dec_gpr_ctl.scala 26:16] + node _T_471 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_472 = and(io.wen1, _T_471) @[el2_dec_gpr_ctl.scala 27:28] + w1v[23] <= _T_472 @[el2_dec_gpr_ctl.scala 27:16] + node _T_473 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_474 = and(io.wen2, _T_473) @[el2_dec_gpr_ctl.scala 28:28] + w2v[23] <= _T_474 @[el2_dec_gpr_ctl.scala 28:16] + node _T_475 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(_T_476, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_478 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_480 = and(_T_479, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_481 = or(_T_477, _T_480) @[el2_dec_gpr_ctl.scala 29:47] + node _T_482 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_484 = and(_T_483, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_485 = or(_T_481, _T_484) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[23] <= _T_485 @[el2_dec_gpr_ctl.scala 29:16] + node _T_486 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_487 = and(io.wen0, _T_486) @[el2_dec_gpr_ctl.scala 26:28] + w0v[24] <= _T_487 @[el2_dec_gpr_ctl.scala 26:16] + node _T_488 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_489 = and(io.wen1, _T_488) @[el2_dec_gpr_ctl.scala 27:28] + w1v[24] <= _T_489 @[el2_dec_gpr_ctl.scala 27:16] + node _T_490 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_491 = and(io.wen2, _T_490) @[el2_dec_gpr_ctl.scala 28:28] + w2v[24] <= _T_491 @[el2_dec_gpr_ctl.scala 28:16] + node _T_492 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_493 = mux(_T_492, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_494 = and(_T_493, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_495 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_496 = mux(_T_495, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_497 = and(_T_496, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_498 = or(_T_494, _T_497) @[el2_dec_gpr_ctl.scala 29:47] + node _T_499 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_501 = and(_T_500, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_502 = or(_T_498, _T_501) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[24] <= _T_502 @[el2_dec_gpr_ctl.scala 29:16] + node _T_503 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_504 = and(io.wen0, _T_503) @[el2_dec_gpr_ctl.scala 26:28] + w0v[25] <= _T_504 @[el2_dec_gpr_ctl.scala 26:16] + node _T_505 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_506 = and(io.wen1, _T_505) @[el2_dec_gpr_ctl.scala 27:28] + w1v[25] <= _T_506 @[el2_dec_gpr_ctl.scala 27:16] + node _T_507 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_508 = and(io.wen2, _T_507) @[el2_dec_gpr_ctl.scala 28:28] + w2v[25] <= _T_508 @[el2_dec_gpr_ctl.scala 28:16] + node _T_509 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_510 = mux(_T_509, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_511 = and(_T_510, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_512 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_513 = mux(_T_512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_514 = and(_T_513, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_515 = or(_T_511, _T_514) @[el2_dec_gpr_ctl.scala 29:47] + node _T_516 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(_T_517, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_519 = or(_T_515, _T_518) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[25] <= _T_519 @[el2_dec_gpr_ctl.scala 29:16] + node _T_520 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_521 = and(io.wen0, _T_520) @[el2_dec_gpr_ctl.scala 26:28] + w0v[26] <= _T_521 @[el2_dec_gpr_ctl.scala 26:16] + node _T_522 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_523 = and(io.wen1, _T_522) @[el2_dec_gpr_ctl.scala 27:28] + w1v[26] <= _T_523 @[el2_dec_gpr_ctl.scala 27:16] + node _T_524 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_525 = and(io.wen2, _T_524) @[el2_dec_gpr_ctl.scala 28:28] + w2v[26] <= _T_525 @[el2_dec_gpr_ctl.scala 28:16] + node _T_526 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(_T_527, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_529 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_531 = and(_T_530, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_532 = or(_T_528, _T_531) @[el2_dec_gpr_ctl.scala 29:47] + node _T_533 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_534 = mux(_T_533, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_535 = and(_T_534, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_536 = or(_T_532, _T_535) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[26] <= _T_536 @[el2_dec_gpr_ctl.scala 29:16] + node _T_537 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_538 = and(io.wen0, _T_537) @[el2_dec_gpr_ctl.scala 26:28] + w0v[27] <= _T_538 @[el2_dec_gpr_ctl.scala 26:16] + node _T_539 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_540 = and(io.wen1, _T_539) @[el2_dec_gpr_ctl.scala 27:28] + w1v[27] <= _T_540 @[el2_dec_gpr_ctl.scala 27:16] + node _T_541 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_542 = and(io.wen2, _T_541) @[el2_dec_gpr_ctl.scala 28:28] + w2v[27] <= _T_542 @[el2_dec_gpr_ctl.scala 28:16] + node _T_543 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_545 = and(_T_544, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_546 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_548 = and(_T_547, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_549 = or(_T_545, _T_548) @[el2_dec_gpr_ctl.scala 29:47] + node _T_550 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_552 = and(_T_551, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_553 = or(_T_549, _T_552) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[27] <= _T_553 @[el2_dec_gpr_ctl.scala 29:16] + node _T_554 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_555 = and(io.wen0, _T_554) @[el2_dec_gpr_ctl.scala 26:28] + w0v[28] <= _T_555 @[el2_dec_gpr_ctl.scala 26:16] + node _T_556 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_557 = and(io.wen1, _T_556) @[el2_dec_gpr_ctl.scala 27:28] + w1v[28] <= _T_557 @[el2_dec_gpr_ctl.scala 27:16] + node _T_558 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_559 = and(io.wen2, _T_558) @[el2_dec_gpr_ctl.scala 28:28] + w2v[28] <= _T_559 @[el2_dec_gpr_ctl.scala 28:16] + node _T_560 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_562 = and(_T_561, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_563 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_564 = mux(_T_563, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_565 = and(_T_564, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_566 = or(_T_562, _T_565) @[el2_dec_gpr_ctl.scala 29:47] + node _T_567 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_569 = and(_T_568, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_570 = or(_T_566, _T_569) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[28] <= _T_570 @[el2_dec_gpr_ctl.scala 29:16] + node _T_571 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_572 = and(io.wen0, _T_571) @[el2_dec_gpr_ctl.scala 26:28] + w0v[29] <= _T_572 @[el2_dec_gpr_ctl.scala 26:16] + node _T_573 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_574 = and(io.wen1, _T_573) @[el2_dec_gpr_ctl.scala 27:28] + w1v[29] <= _T_574 @[el2_dec_gpr_ctl.scala 27:16] + node _T_575 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_576 = and(io.wen2, _T_575) @[el2_dec_gpr_ctl.scala 28:28] + w2v[29] <= _T_576 @[el2_dec_gpr_ctl.scala 28:16] + node _T_577 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_579 = and(_T_578, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_580 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_582 = and(_T_581, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_583 = or(_T_579, _T_582) @[el2_dec_gpr_ctl.scala 29:47] + node _T_584 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_585 = mux(_T_584, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_586 = and(_T_585, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_587 = or(_T_583, _T_586) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[29] <= _T_587 @[el2_dec_gpr_ctl.scala 29:16] + node _T_588 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_589 = and(io.wen0, _T_588) @[el2_dec_gpr_ctl.scala 26:28] + w0v[30] <= _T_589 @[el2_dec_gpr_ctl.scala 26:16] + node _T_590 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_591 = and(io.wen1, _T_590) @[el2_dec_gpr_ctl.scala 27:28] + w1v[30] <= _T_591 @[el2_dec_gpr_ctl.scala 27:16] + node _T_592 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_593 = and(io.wen2, _T_592) @[el2_dec_gpr_ctl.scala 28:28] + w2v[30] <= _T_593 @[el2_dec_gpr_ctl.scala 28:16] + node _T_594 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_595 = mux(_T_594, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_596 = and(_T_595, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_597 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_600 = or(_T_596, _T_599) @[el2_dec_gpr_ctl.scala 29:47] + node _T_601 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_602 = mux(_T_601, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_603 = and(_T_602, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_604 = or(_T_600, _T_603) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[30] <= _T_604 @[el2_dec_gpr_ctl.scala 29:16] + node _T_605 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 26:40] + node _T_606 = and(io.wen0, _T_605) @[el2_dec_gpr_ctl.scala 26:28] + w0v[31] <= _T_606 @[el2_dec_gpr_ctl.scala 26:16] + node _T_607 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 27:40] + node _T_608 = and(io.wen1, _T_607) @[el2_dec_gpr_ctl.scala 27:28] + w1v[31] <= _T_608 @[el2_dec_gpr_ctl.scala 27:16] + node _T_609 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 28:40] + node _T_610 = and(io.wen2, _T_609) @[el2_dec_gpr_ctl.scala 28:28] + w2v[31] <= _T_610 @[el2_dec_gpr_ctl.scala 28:16] + node _T_611 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_612 = mux(_T_611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_613 = and(_T_612, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] + node _T_614 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_615 = mux(_T_614, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_616 = and(_T_615, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] + node _T_617 = or(_T_613, _T_616) @[el2_dec_gpr_ctl.scala 29:47] + node _T_618 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_620 = and(_T_619, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] + node _T_621 = or(_T_617, _T_620) @[el2_dec_gpr_ctl.scala 29:76] + gpr_in[31] <= _T_621 @[el2_dec_gpr_ctl.scala 29:16] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_622 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_623 <= gpr_in[1] @[el2_lib.scala 491:16] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 33:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_624 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_625 <= gpr_in[2] @[el2_lib.scala 491:16] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 33:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_626 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_627 <= gpr_in[3] @[el2_lib.scala 491:16] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 33:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_628 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_629 <= gpr_in[4] @[el2_lib.scala 491:16] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 33:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 485:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_4.io.en <= _T_630 @[el2_lib.scala 488:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_631 <= gpr_in[5] @[el2_lib.scala 491:16] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 33:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 485:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_5.io.en <= _T_632 @[el2_lib.scala 488:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_633 <= gpr_in[6] @[el2_lib.scala 491:16] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 33:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 485:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_6.io.en <= _T_634 @[el2_lib.scala 488:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_635 <= gpr_in[7] @[el2_lib.scala 491:16] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 33:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 485:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_7.io.en <= _T_636 @[el2_lib.scala 488:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_637 <= gpr_in[8] @[el2_lib.scala 491:16] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 33:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 485:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_8.io.en <= _T_638 @[el2_lib.scala 488:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_639 <= gpr_in[9] @[el2_lib.scala 491:16] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 33:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_640 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_641 <= gpr_in[10] @[el2_lib.scala 491:16] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 33:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_642 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_643 <= gpr_in[11] @[el2_lib.scala 491:16] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 33:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_644 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_645 <= gpr_in[12] @[el2_lib.scala 491:16] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 33:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_646 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_647 <= gpr_in[13] @[el2_lib.scala 491:16] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 33:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_648 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_649 <= gpr_in[14] @[el2_lib.scala 491:16] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 33:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_650 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_651 <= gpr_in[15] @[el2_lib.scala 491:16] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 33:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_652 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_653 <= gpr_in[16] @[el2_lib.scala 491:16] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 33:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_654 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_655 <= gpr_in[17] @[el2_lib.scala 491:16] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 33:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_656 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_657 <= gpr_in[18] @[el2_lib.scala 491:16] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 33:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_658 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_659 <= gpr_in[19] @[el2_lib.scala 491:16] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 33:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 485:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_19.io.en <= _T_660 @[el2_lib.scala 488:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_661 <= gpr_in[20] @[el2_lib.scala 491:16] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 33:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 485:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_20.io.en <= _T_662 @[el2_lib.scala 488:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_663 <= gpr_in[21] @[el2_lib.scala 491:16] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 33:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 485:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_21.io.en <= _T_664 @[el2_lib.scala 488:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_665 <= gpr_in[22] @[el2_lib.scala 491:16] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 33:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 485:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_22.io.en <= _T_666 @[el2_lib.scala 488:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_667 <= gpr_in[23] @[el2_lib.scala 491:16] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 33:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 485:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_23.io.en <= _T_668 @[el2_lib.scala 488:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_669 <= gpr_in[24] @[el2_lib.scala 491:16] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 33:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 485:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_24.io.en <= _T_670 @[el2_lib.scala 488:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_671 <= gpr_in[25] @[el2_lib.scala 491:16] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 33:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 485:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_25.io.en <= _T_672 @[el2_lib.scala 488:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_673 <= gpr_in[26] @[el2_lib.scala 491:16] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 33:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 485:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_26.io.en <= _T_674 @[el2_lib.scala 488:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_675 <= gpr_in[27] @[el2_lib.scala 491:16] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 33:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 485:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_27.io.en <= _T_676 @[el2_lib.scala 488:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_677 <= gpr_in[28] @[el2_lib.scala 491:16] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 33:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 485:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_28.io.en <= _T_678 @[el2_lib.scala 488:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_679 <= gpr_in[29] @[el2_lib.scala 491:16] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 33:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 485:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_29.io.en <= _T_680 @[el2_lib.scala 488:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_681 <= gpr_in[30] @[el2_lib.scala 491:16] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 33:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 33:43] + inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 485:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_30.io.en <= _T_682 @[el2_lib.scala 488:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_683 <= gpr_in[31] @[el2_lib.scala 491:16] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 33:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72] + node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72] + node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72] + node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72] + node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72] + node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72] + node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72] + node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72] + node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72] + node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72] + node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72] + node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72] + node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72] + node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72] + node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72] + node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72] + node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72] + node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72] + node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72] + node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72] + node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72] + node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72] + node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72] + node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72] + node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] + wire _T_807 : UInt<32> @[Mux.scala 27:72] + _T_807 <= _T_806 @[Mux.scala 27:72] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 36:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72] + node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72] + node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72] + node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72] + node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72] + node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72] + node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72] + node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72] + node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72] + node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72] + node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72] + node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72] + node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72] + node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72] + node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72] + node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72] + node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72] + node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72] + node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72] + node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] + wire _T_931 : UInt<32> @[Mux.scala 27:72] + _T_931 <= _T_930 @[Mux.scala 27:72] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 37:9] + diff --git a/el2_dec_gpr_ctl.v b/el2_dec_gpr_ctl.v new file mode 100644 index 00000000..e9696eb7 --- /dev/null +++ b/el2_dec_gpr_ctl.v @@ -0,0 +1,1522 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 465:26] + wire clkhdr_CK; // @[el2_lib.scala 465:26] + wire clkhdr_EN; // @[el2_lib.scala 465:26] + wire clkhdr_SE; // @[el2_lib.scala 465:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18] +endmodule +module el2_dec_gpr_ctl( + input clock, + input reset, + input [4:0] io_raddr0, + input [4:0] io_raddr1, + input io_wen0, + input [4:0] io_waddr0, + input [31:0] io_wd0, + input io_wen1, + input [4:0] io_waddr1, + input [31:0] io_wd1, + input io_wen2, + input [4:0] io_waddr2, + input [31:0] io_wd2, + output [31:0] io_rd0, + output [31:0] io_rd1, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 485:23] + wire _T_95 = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_1 = io_wen0 & _T_95; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_112 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_2 = io_wen0 & _T_112; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_129 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_3 = io_wen0 & _T_129; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_146 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_4 = io_wen0 & _T_146; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_163 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_5 = io_wen0 & _T_163; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_180 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_6 = io_wen0 & _T_180; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_197 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_7 = io_wen0 & _T_197; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_214 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_8 = io_wen0 & _T_214; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_231 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_9 = io_wen0 & _T_231; // @[el2_dec_gpr_ctl.scala 26:28] + wire [9:0] _T_8 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_248 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_10 = io_wen0 & _T_248; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_265 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_11 = io_wen0 & _T_265; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_282 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_12 = io_wen0 & _T_282; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_299 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_13 = io_wen0 & _T_299; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_316 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_14 = io_wen0 & _T_316; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_333 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_15 = io_wen0 & _T_333; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_350 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_16 = io_wen0 & _T_350; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_367 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_17 = io_wen0 & _T_367; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_384 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_18 = io_wen0 & _T_384; // @[el2_dec_gpr_ctl.scala 26:28] + wire [18:0] _T_17 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_8}; // @[Cat.scala 29:58] + wire _T_401 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_19 = io_wen0 & _T_401; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_418 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_20 = io_wen0 & _T_418; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_435 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_21 = io_wen0 & _T_435; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_452 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_22 = io_wen0 & _T_452; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_469 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_23 = io_wen0 & _T_469; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_486 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_24 = io_wen0 & _T_486; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_503 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_25 = io_wen0 & _T_503; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_520 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_26 = io_wen0 & _T_520; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_537 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_27 = io_wen0 & _T_537; // @[el2_dec_gpr_ctl.scala 26:28] + wire [27:0] _T_26 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_17}; // @[Cat.scala 29:58] + wire _T_554 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_28 = io_wen0 & _T_554; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_571 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_29 = io_wen0 & _T_571; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_588 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_30 = io_wen0 & _T_588; // @[el2_dec_gpr_ctl.scala 26:28] + wire _T_605 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 26:40] + wire w0v_31 = io_wen0 & _T_605; // @[el2_dec_gpr_ctl.scala 26:28] + wire [31:0] _T_30 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_26}; // @[Cat.scala 29:58] + wire _T_97 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_1 = io_wen1 & _T_97; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_114 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_2 = io_wen1 & _T_114; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_131 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_3 = io_wen1 & _T_131; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_148 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_4 = io_wen1 & _T_148; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_165 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_5 = io_wen1 & _T_165; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_182 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_6 = io_wen1 & _T_182; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_199 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_7 = io_wen1 & _T_199; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_216 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_8 = io_wen1 & _T_216; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_233 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_9 = io_wen1 & _T_233; // @[el2_dec_gpr_ctl.scala 27:28] + wire [9:0] _T_39 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_250 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_10 = io_wen1 & _T_250; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_267 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_11 = io_wen1 & _T_267; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_284 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_12 = io_wen1 & _T_284; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_301 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_13 = io_wen1 & _T_301; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_318 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_14 = io_wen1 & _T_318; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_335 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_15 = io_wen1 & _T_335; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_352 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_16 = io_wen1 & _T_352; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_369 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_17 = io_wen1 & _T_369; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_386 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_18 = io_wen1 & _T_386; // @[el2_dec_gpr_ctl.scala 27:28] + wire [18:0] _T_48 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_39}; // @[Cat.scala 29:58] + wire _T_403 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_19 = io_wen1 & _T_403; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_420 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_20 = io_wen1 & _T_420; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_437 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_21 = io_wen1 & _T_437; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_454 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_22 = io_wen1 & _T_454; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_471 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_23 = io_wen1 & _T_471; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_488 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_24 = io_wen1 & _T_488; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_505 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_25 = io_wen1 & _T_505; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_522 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_26 = io_wen1 & _T_522; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_539 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_27 = io_wen1 & _T_539; // @[el2_dec_gpr_ctl.scala 27:28] + wire [27:0] _T_57 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_48}; // @[Cat.scala 29:58] + wire _T_556 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_28 = io_wen1 & _T_556; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_573 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_29 = io_wen1 & _T_573; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_590 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_30 = io_wen1 & _T_590; // @[el2_dec_gpr_ctl.scala 27:28] + wire _T_607 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 27:40] + wire w1v_31 = io_wen1 & _T_607; // @[el2_dec_gpr_ctl.scala 27:28] + wire [31:0] _T_61 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_57}; // @[Cat.scala 29:58] + wire [31:0] _T_62 = _T_30 | _T_61; // @[el2_dec_gpr_ctl.scala 23:51] + wire _T_99 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_1 = io_wen2 & _T_99; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_116 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_2 = io_wen2 & _T_116; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_133 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_3 = io_wen2 & _T_133; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_150 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_4 = io_wen2 & _T_150; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_167 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_5 = io_wen2 & _T_167; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_184 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_6 = io_wen2 & _T_184; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_201 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_7 = io_wen2 & _T_201; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_218 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_8 = io_wen2 & _T_218; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_235 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_9 = io_wen2 & _T_235; // @[el2_dec_gpr_ctl.scala 28:28] + wire [9:0] _T_71 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire _T_252 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_10 = io_wen2 & _T_252; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_269 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_11 = io_wen2 & _T_269; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_286 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_12 = io_wen2 & _T_286; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_303 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_13 = io_wen2 & _T_303; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_320 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_14 = io_wen2 & _T_320; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_337 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_15 = io_wen2 & _T_337; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_354 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_16 = io_wen2 & _T_354; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_371 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_17 = io_wen2 & _T_371; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_388 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_18 = io_wen2 & _T_388; // @[el2_dec_gpr_ctl.scala 28:28] + wire [18:0] _T_80 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_71}; // @[Cat.scala 29:58] + wire _T_405 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_19 = io_wen2 & _T_405; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_422 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_20 = io_wen2 & _T_422; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_439 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_21 = io_wen2 & _T_439; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_456 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_22 = io_wen2 & _T_456; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_473 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_23 = io_wen2 & _T_473; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_490 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_24 = io_wen2 & _T_490; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_507 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_25 = io_wen2 & _T_507; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_524 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_26 = io_wen2 & _T_524; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_541 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_27 = io_wen2 & _T_541; // @[el2_dec_gpr_ctl.scala 28:28] + wire [27:0] _T_89 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_80}; // @[Cat.scala 29:58] + wire _T_558 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_28 = io_wen2 & _T_558; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_575 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_29 = io_wen2 & _T_575; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_592 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_30 = io_wen2 & _T_592; // @[el2_dec_gpr_ctl.scala 28:28] + wire _T_609 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 28:40] + wire w2v_31 = io_wen2 & _T_609; // @[el2_dec_gpr_ctl.scala 28:28] + wire [31:0] _T_93 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_89}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_62 | _T_93; // @[el2_dec_gpr_ctl.scala 23:89] + wire [31:0] _T_102 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_103 = _T_102 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_105 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_106 = _T_105 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_107 = _T_103 | _T_106; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_109 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_119 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_120 = _T_119 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_122 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_123 = _T_122 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_124 = _T_120 | _T_123; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_126 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_136 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_137 = _T_136 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_139 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_140 = _T_139 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_141 = _T_137 | _T_140; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_143 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_153 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_154 = _T_153 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_156 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_157 = _T_156 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_158 = _T_154 | _T_157; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_160 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_170 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_171 = _T_170 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_173 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_174 = _T_173 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_175 = _T_171 | _T_174; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_177 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_187 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_188 = _T_187 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_190 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_191 = _T_190 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_192 = _T_188 | _T_191; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_194 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_204 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_205 = _T_204 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_207 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_208 = _T_207 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_209 = _T_205 | _T_208; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_211 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_221 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_222 = _T_221 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_224 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_225 = _T_224 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_226 = _T_222 | _T_225; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_228 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_238 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_239 = _T_238 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_241 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_242 = _T_241 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_243 = _T_239 | _T_242; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_245 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_255 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_256 = _T_255 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_258 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_259 = _T_258 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_260 = _T_256 | _T_259; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_262 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_272 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_273 = _T_272 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_275 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_276 = _T_275 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_277 = _T_273 | _T_276; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_279 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_289 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_290 = _T_289 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_292 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_293 = _T_292 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_294 = _T_290 | _T_293; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_296 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_306 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_307 = _T_306 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_309 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_310 = _T_309 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_311 = _T_307 | _T_310; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_313 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_323 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_324 = _T_323 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_326 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_327 = _T_326 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_328 = _T_324 | _T_327; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_330 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_340 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_341 = _T_340 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_343 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_344 = _T_343 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_345 = _T_341 | _T_344; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_347 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_357 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_358 = _T_357 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_360 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_361 = _T_360 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_362 = _T_358 | _T_361; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_364 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_374 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_375 = _T_374 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_377 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_378 = _T_377 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_379 = _T_375 | _T_378; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_381 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_391 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_392 = _T_391 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_394 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_395 = _T_394 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_396 = _T_392 | _T_395; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_398 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_408 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_409 = _T_408 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_411 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_412 = _T_411 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_413 = _T_409 | _T_412; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_415 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_425 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_426 = _T_425 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_428 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_429 = _T_428 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_430 = _T_426 | _T_429; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_432 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_442 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_443 = _T_442 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_445 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_446 = _T_445 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_447 = _T_443 | _T_446; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_449 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_459 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_460 = _T_459 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_462 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_463 = _T_462 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_464 = _T_460 | _T_463; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_466 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_476 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_477 = _T_476 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_479 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_480 = _T_479 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_481 = _T_477 | _T_480; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_483 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_493 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_494 = _T_493 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_496 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_497 = _T_496 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_498 = _T_494 | _T_497; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_500 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_510 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_511 = _T_510 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_513 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_514 = _T_513 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_515 = _T_511 | _T_514; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_517 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_527 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_528 = _T_527 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_530 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_531 = _T_530 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_532 = _T_528 | _T_531; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_534 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_535 = _T_534 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_544 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_545 = _T_544 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_547 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_548 = _T_547 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_549 = _T_545 | _T_548; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_551 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_552 = _T_551 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_561 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_562 = _T_561 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_564 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_565 = _T_564 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_566 = _T_562 | _T_565; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_568 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_569 = _T_568 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_578 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_579 = _T_578 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_581 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_582 = _T_581 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_583 = _T_579 | _T_582; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_585 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_586 = _T_585 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_595 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_596 = _T_595 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_598 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_599 = _T_598 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_600 = _T_596 | _T_599; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_602 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_603 = _T_602 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire [31:0] _T_612 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_613 = _T_612 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] + wire [31:0] _T_615 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_616 = _T_615 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] + wire [31:0] _T_617 = _T_613 | _T_616; // @[el2_dec_gpr_ctl.scala 29:47] + wire [31:0] _T_619 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_620 = _T_619 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + reg [31:0] gpr_out_1; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_2; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_3; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_4; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_5; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_6; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_7; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_8; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_9; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_10; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_11; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_12; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_13; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_14; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_15; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_16; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_17; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_18; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_19; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_20; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_21; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_22; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_23; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_24; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_25; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_26; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_27; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_28; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_29; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_30; // @[el2_lib.scala 491:16] + reg [31:0] gpr_out_31; // @[el2_lib.scala 491:16] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:49] + wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72] + wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72] + wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72] + wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72] + wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72] + wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72] + wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72] + wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72] + wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72] + wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72] + wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72] + wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72] + wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72] + wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72] + wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72] + wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72] + wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72] + wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72] + wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72] + wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72] + wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72] + wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72] + wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] + wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] + wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:49] + wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72] + wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72] + wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72] + wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72] + wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72] + wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72] + wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72] + wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72] + wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72] + wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72] + wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72] + wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72] + wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72] + wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72] + wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72] + wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72] + wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72] + wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72] + wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72] + wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72] + wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72] + wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72] + wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72] + wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 21:9 el2_dec_gpr_ctl.scala 36:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 22:9 el2_dec_gpr_ctl.scala 37:9] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[el2_lib.scala 488:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[el2_lib.scala 488:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[el2_lib.scala 488:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[el2_lib.scala 488:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[el2_lib.scala 488:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[el2_lib.scala 488:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[el2_lib.scala 488:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[el2_lib.scala 488:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[el2_lib.scala 488:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[el2_lib.scala 488:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[el2_lib.scala 488:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[el2_lib.scala 488:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[el2_lib.scala 488:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[el2_lib.scala 488:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[el2_lib.scala 488:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[el2_lib.scala 488:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[el2_lib.scala 488:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + gpr_out_1 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + gpr_out_2 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + gpr_out_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + gpr_out_4 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + gpr_out_5 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + gpr_out_6 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + gpr_out_7 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + gpr_out_8 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + gpr_out_9 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + gpr_out_10 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + gpr_out_11 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + gpr_out_12 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + gpr_out_13 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + gpr_out_14 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + gpr_out_15 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + gpr_out_16 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + gpr_out_17 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + gpr_out_18 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + gpr_out_19 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + gpr_out_20 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + gpr_out_21 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + gpr_out_22 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + gpr_out_23 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + gpr_out_24 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + gpr_out_25 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + gpr_out_26 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + gpr_out_27 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + gpr_out_28 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + gpr_out_29 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + gpr_out_30 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + gpr_out_31 = _RAND_30[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + gpr_out_1 = 32'h0; + end + if (reset) begin + gpr_out_2 = 32'h0; + end + if (reset) begin + gpr_out_3 = 32'h0; + end + if (reset) begin + gpr_out_4 = 32'h0; + end + if (reset) begin + gpr_out_5 = 32'h0; + end + if (reset) begin + gpr_out_6 = 32'h0; + end + if (reset) begin + gpr_out_7 = 32'h0; + end + if (reset) begin + gpr_out_8 = 32'h0; + end + if (reset) begin + gpr_out_9 = 32'h0; + end + if (reset) begin + gpr_out_10 = 32'h0; + end + if (reset) begin + gpr_out_11 = 32'h0; + end + if (reset) begin + gpr_out_12 = 32'h0; + end + if (reset) begin + gpr_out_13 = 32'h0; + end + if (reset) begin + gpr_out_14 = 32'h0; + end + if (reset) begin + gpr_out_15 = 32'h0; + end + if (reset) begin + gpr_out_16 = 32'h0; + end + if (reset) begin + gpr_out_17 = 32'h0; + end + if (reset) begin + gpr_out_18 = 32'h0; + end + if (reset) begin + gpr_out_19 = 32'h0; + end + if (reset) begin + gpr_out_20 = 32'h0; + end + if (reset) begin + gpr_out_21 = 32'h0; + end + if (reset) begin + gpr_out_22 = 32'h0; + end + if (reset) begin + gpr_out_23 = 32'h0; + end + if (reset) begin + gpr_out_24 = 32'h0; + end + if (reset) begin + gpr_out_25 = 32'h0; + end + if (reset) begin + gpr_out_26 = 32'h0; + end + if (reset) begin + gpr_out_27 = 32'h0; + end + if (reset) begin + gpr_out_28 = 32'h0; + end + if (reset) begin + gpr_out_29 = 32'h0; + end + if (reset) begin + gpr_out_30 = 32'h0; + end + if (reset) begin + gpr_out_31 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_1 <= 32'h0; + end else begin + gpr_out_1 <= _T_107 | _T_110; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_2 <= 32'h0; + end else begin + gpr_out_2 <= _T_124 | _T_127; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_3 <= 32'h0; + end else begin + gpr_out_3 <= _T_141 | _T_144; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_4 <= 32'h0; + end else begin + gpr_out_4 <= _T_158 | _T_161; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_5 <= 32'h0; + end else begin + gpr_out_5 <= _T_175 | _T_178; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_6 <= 32'h0; + end else begin + gpr_out_6 <= _T_192 | _T_195; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_7 <= 32'h0; + end else begin + gpr_out_7 <= _T_209 | _T_212; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_8 <= 32'h0; + end else begin + gpr_out_8 <= _T_226 | _T_229; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_9 <= 32'h0; + end else begin + gpr_out_9 <= _T_243 | _T_246; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_10 <= 32'h0; + end else begin + gpr_out_10 <= _T_260 | _T_263; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_11 <= 32'h0; + end else begin + gpr_out_11 <= _T_277 | _T_280; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_12 <= 32'h0; + end else begin + gpr_out_12 <= _T_294 | _T_297; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_13 <= 32'h0; + end else begin + gpr_out_13 <= _T_311 | _T_314; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_14 <= 32'h0; + end else begin + gpr_out_14 <= _T_328 | _T_331; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_15 <= 32'h0; + end else begin + gpr_out_15 <= _T_345 | _T_348; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_16 <= 32'h0; + end else begin + gpr_out_16 <= _T_362 | _T_365; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_17 <= 32'h0; + end else begin + gpr_out_17 <= _T_379 | _T_382; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_18 <= 32'h0; + end else begin + gpr_out_18 <= _T_396 | _T_399; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_19 <= 32'h0; + end else begin + gpr_out_19 <= _T_413 | _T_416; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_20 <= 32'h0; + end else begin + gpr_out_20 <= _T_430 | _T_433; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_21 <= 32'h0; + end else begin + gpr_out_21 <= _T_447 | _T_450; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_22 <= 32'h0; + end else begin + gpr_out_22 <= _T_464 | _T_467; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_23 <= 32'h0; + end else begin + gpr_out_23 <= _T_481 | _T_484; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_24 <= 32'h0; + end else begin + gpr_out_24 <= _T_498 | _T_501; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_25 <= 32'h0; + end else begin + gpr_out_25 <= _T_515 | _T_518; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_26 <= 32'h0; + end else begin + gpr_out_26 <= _T_532 | _T_535; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_27 <= 32'h0; + end else begin + gpr_out_27 <= _T_549 | _T_552; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_28 <= 32'h0; + end else begin + gpr_out_28 <= _T_566 | _T_569; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_29 <= 32'h0; + end else begin + gpr_out_29 <= _T_583 | _T_586; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_30 <= 32'h0; + end else begin + gpr_out_30 <= _T_600 | _T_603; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + gpr_out_31 <= 32'h0; + end else begin + gpr_out_31 <= _T_617 | _T_620; + end + end +endmodule diff --git a/el2_dec_ib_ctl.anno.json b/el2_dec_ib_ctl.anno.json new file mode 100644 index 00000000..75a87d80 --- /dev/null +++ b/el2_dec_ib_ctl.anno.json @@ -0,0 +1,183 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_ret", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_ret" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_dbecc_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_dbecc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_br_error", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_br_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_toffset", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_f1_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_f1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_btag", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_btag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_way", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_way" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc4_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc4" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_hist", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_ib0_valid_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_instr_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_instr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_br_start_error", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_br_start_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_fghr", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_fghr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_prett", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bank", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bank" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_index", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_type_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_valid", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_fence_d", + "sources":[ + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr", + "~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_ib_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_ib_ctl.fir b/el2_dec_ib_ctl.fir new file mode 100644 index 00000000..fee63b0a --- /dev/null +++ b/el2_dec_ib_ctl.fir @@ -0,0 +1,71 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_ib_ctl : + module el2_dec_ib_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31] + io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20] + node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21] + node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20] + node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21] + node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] + ib0_debug_in <= _T_23 @[Mux.scala 27:72] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22] + diff --git a/el2_dec_ib_ctl.v b/el2_dec_ib_ctl.v new file mode 100644 index 00000000..bb4981d0 --- /dev/null +++ b/el2_dec_ib_ctl.v @@ -0,0 +1,98 @@ +module el2_dec_ib_ctl( + input clock, + input reset, + input io_dbg_cmd_valid, + input io_dbg_cmd_write, + input [1:0] io_dbg_cmd_type, + input [31:0] io_dbg_cmd_addr, + input io_i0_brp_valid, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input io_i0_brp_bank, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, + input [7:0] io_ifu_i0_bp_index, + input [7:0] io_ifu_i0_bp_fghr, + input [4:0] io_ifu_i0_bp_btag, + input io_ifu_i0_pc4, + input io_ifu_i0_valid, + input io_ifu_i0_icaf, + input [1:0] io_ifu_i0_icaf_type, + input io_ifu_i0_icaf_f1, + input io_ifu_i0_dbecc, + input [31:0] io_ifu_i0_instr, + input [30:0] io_ifu_i0_pc, + output io_dec_ib0_valid_d, + output [1:0] io_dec_i0_icaf_type_d, + output [31:0] io_dec_i0_instr_d, + output [30:0] io_dec_i0_pc_d, + output io_dec_i0_pc4_d, + output io_dec_i0_brp_valid, + output [11:0] io_dec_i0_brp_toffset, + output [1:0] io_dec_i0_brp_hist, + output io_dec_i0_brp_br_error, + output io_dec_i0_brp_br_start_error, + output io_dec_i0_brp_bank, + output [30:0] io_dec_i0_brp_prett, + output io_dec_i0_brp_way, + output io_dec_i0_brp_ret, + output [7:0] io_dec_i0_bp_index, + output [7:0] io_dec_i0_bp_fghr, + output [4:0] io_dec_i0_bp_btag, + output io_dec_i0_icaf_d, + output io_dec_i0_icaf_f1_d, + output io_dec_i0_dbecc_d, + output io_dec_debug_wdata_rs1_d, + output io_dec_debug_fence_d +); + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40] + wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] + wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] + wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] + wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_bank = io_i0_brp_bank; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 49:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24] +endmodule diff --git a/el2_dec_tlu_ctl.anno.json b/el2_dec_tlu_ctl.anno.json new file mode 100644 index 00000000..eceaf22a --- /dev/null +++ b/el2_dec_tlu_ctl.anno.json @@ -0,0 +1,508 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_hist", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_core_id", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_fence_i_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt2", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_leak_one_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt1", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_br_error", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_path_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_npc_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_middle", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_middle_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_way", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_commit_cmt", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_br_start_error", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid", + "sources":[ + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r", + "~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_tlu_ctl.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_tlu_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_tlu_ctl.fir b/el2_dec_tlu_ctl.fir new file mode 100644 index 00000000..2320e158 --- /dev/null +++ b/el2_dec_tlu_ctl.fir @@ -0,0 +1,8034 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_tlu_ctl : + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module el2_dec_timer_ctl : + input clock : Clock + input reset : Reset + output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} + + wire mitctl1 : UInt<4> @[el2_dec_tlu_ctl.scala 2745:19] + wire mitctl0 : UInt<3> @[el2_dec_tlu_ctl.scala 2746:19] + wire mitb1 : UInt<32> @[el2_dec_tlu_ctl.scala 2747:19] + wire mitb0 : UInt<32> @[el2_dec_tlu_ctl.scala 2748:19] + wire mitcnt1 : UInt<32> @[el2_dec_tlu_ctl.scala 2749:19] + wire mitcnt0 : UInt<32> @[el2_dec_tlu_ctl.scala 2750:19] + node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] + node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] + io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] + io.dec_timer_t1_pulse <= mit1_match_ns @[el2_dec_tlu_ctl.scala 2756:25] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[el2_dec_tlu_ctl.scala 2763:66] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[el2_dec_tlu_ctl.scala 2763:43] + node _T_1 = bits(mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2765:31] + node _T_2 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2765:50] + node _T_3 = bits(mitctl0, 2, 2) @[el2_dec_tlu_ctl.scala 2765:79] + node _T_4 = or(_T_2, _T_3) @[el2_dec_tlu_ctl.scala 2765:70] + node _T_5 = and(_T_1, _T_4) @[el2_dec_tlu_ctl.scala 2765:47] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2765:106] + node _T_7 = bits(mitctl0, 1, 1) @[el2_dec_tlu_ctl.scala 2765:141] + node _T_8 = or(_T_6, _T_7) @[el2_dec_tlu_ctl.scala 2765:132] + node _T_9 = and(_T_5, _T_8) @[el2_dec_tlu_ctl.scala 2765:103] + node _T_10 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2765:167] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[el2_dec_tlu_ctl.scala 2765:165] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2766:29] + node mitcnt0_inc = tail(_T_11, 1) @[el2_dec_tlu_ctl.scala 2766:29] + node _T_12 = bits(mit0_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2767:38] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:60] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:77] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:94] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_17 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_18 <= mitcnt0_ns @[el2_lib.scala 491:16] + mitcnt0 <= _T_18 @[el2_dec_tlu_ctl.scala 2768:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[el2_dec_tlu_ctl.scala 2775:66] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[el2_dec_tlu_ctl.scala 2775:43] + node _T_20 = bits(mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2777:31] + node _T_21 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 2777:50] + node _T_22 = bits(mitctl1, 2, 2) @[el2_dec_tlu_ctl.scala 2777:79] + node _T_23 = or(_T_21, _T_22) @[el2_dec_tlu_ctl.scala 2777:70] + node _T_24 = and(_T_20, _T_23) @[el2_dec_tlu_ctl.scala 2777:47] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2777:106] + node _T_26 = bits(mitctl1, 1, 1) @[el2_dec_tlu_ctl.scala 2777:141] + node _T_27 = or(_T_25, _T_26) @[el2_dec_tlu_ctl.scala 2777:132] + node _T_28 = and(_T_24, _T_27) @[el2_dec_tlu_ctl.scala 2777:103] + node _T_29 = not(io.internal_dbg_halt_timers) @[el2_dec_tlu_ctl.scala 2777:167] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[el2_dec_tlu_ctl.scala 2777:165] + node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_31 = bits(mitctl1, 3, 3) @[el2_dec_tlu_ctl.scala 2780:62] + node _T_32 = not(_T_31) @[el2_dec_tlu_ctl.scala 2780:54] + node _T_33 = or(_T_32, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2780:66] + node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] + node _T_35 = add(mitcnt1, _T_34) @[el2_dec_tlu_ctl.scala 2780:29] + node mitcnt1_inc = tail(_T_35, 1) @[el2_dec_tlu_ctl.scala 2780:29] + node _T_36 = bits(mit1_match_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2781:39] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2781:69] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[el2_dec_tlu_ctl.scala 2781:55] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[el2_dec_tlu_ctl.scala 2781:24] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[el2_dec_tlu_ctl.scala 2782:52] + node _T_40 = or(_T_39, mit1_match_ns) @[el2_dec_tlu_ctl.scala 2782:69] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_tlu_ctl.scala 2782:86] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_42 <= mitcnt1_ns @[el2_lib.scala 491:16] + mitcnt1 <= _T_42 @[el2_dec_tlu_ctl.scala 2782:17] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[el2_dec_tlu_ctl.scala 2789:64] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[el2_dec_tlu_ctl.scala 2789:41] + node _T_44 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2790:30] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2790:63] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mitb0_b <= _T_44 @[el2_lib.scala 491:16] + node _T_46 = not(mitb0_b) @[el2_dec_tlu_ctl.scala 2791:14] + mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:24] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mitb1_b <= _T_48 @[el2_lib.scala 491:16] + node _T_50 = not(mitb1_b) @[el2_dec_tlu_ctl.scala 2800:12] + mitb1 <= _T_50 @[el2_dec_tlu_ctl.scala 2800:9] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[el2_dec_tlu_ctl.scala 2811:66] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[el2_dec_tlu_ctl.scala 2811:43] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2812:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[el2_dec_tlu_ctl.scala 2812:72] + node _T_54 = bits(mitctl0, 2, 0) @[el2_dec_tlu_ctl.scala 2812:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[el2_dec_tlu_ctl.scala 2812:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2814:35] + node mitctl0_0_b_ns = not(_T_55) @[el2_dec_tlu_ctl.scala 2814:24] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2815:54] + mitctl0_0_b <= mitctl0_0_b_ns @[el2_dec_tlu_ctl.scala 2815:54] + node _T_56 = bits(mitctl0_ns, 2, 1) @[el2_dec_tlu_ctl.scala 2816:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2816:67] + _T_57 <= _T_56 @[el2_dec_tlu_ctl.scala 2816:67] + node _T_58 = not(mitctl0_0_b) @[el2_dec_tlu_ctl.scala 2816:90] + node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] + mitctl0 <= _T_59 @[el2_dec_tlu_ctl.scala 2816:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[el2_dec_tlu_ctl.scala 2826:65] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[el2_dec_tlu_ctl.scala 2826:43] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2827:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2827:71] + node _T_63 = bits(mitctl1, 3, 0) @[el2_dec_tlu_ctl.scala 2827:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[el2_dec_tlu_ctl.scala 2827:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[el2_dec_tlu_ctl.scala 2828:34] + node mitctl1_0_b_ns = not(_T_64) @[el2_dec_tlu_ctl.scala 2828:23] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2829:49] + mitctl1_0_b <= mitctl1_0_b_ns @[el2_dec_tlu_ctl.scala 2829:49] + node _T_65 = bits(mitctl1_ns, 3, 1) @[el2_dec_tlu_ctl.scala 2830:57] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2830:46] + _T_66 <= _T_65 @[el2_dec_tlu_ctl.scala 2830:46] + node _T_67 = not(mitctl1_0_b) @[el2_dec_tlu_ctl.scala 2830:69] + node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] + mitctl1 <= _T_68 @[el2_dec_tlu_ctl.scala 2830:10] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[el2_dec_tlu_ctl.scala 2832:43] + node _T_70 = or(_T_69, io.csr_mitb1) @[el2_dec_tlu_ctl.scala 2832:60] + node _T_71 = or(_T_70, io.csr_mitb0) @[el2_dec_tlu_ctl.scala 2832:75] + node _T_72 = or(_T_71, io.csr_mitctl0) @[el2_dec_tlu_ctl.scala 2832:90] + node _T_73 = or(_T_72, io.csr_mitctl1) @[el2_dec_tlu_ctl.scala 2832:107] + io.dec_timer_read_d <= _T_73 @[el2_dec_tlu_ctl.scala 2832:25] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[el2_dec_tlu_ctl.scala 2834:20] + node _T_75 = bits(mitcnt0, 31, 0) @[el2_dec_tlu_ctl.scala 2834:39] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[el2_dec_tlu_ctl.scala 2835:20] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[el2_dec_tlu_ctl.scala 2836:18] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[el2_dec_tlu_ctl.scala 2837:18] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[el2_dec_tlu_ctl.scala 2838:20] + node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] + node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[el2_dec_tlu_ctl.scala 2839:20] + node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] + node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_86 = mux(_T_76, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_87 = mux(_T_77, mitb0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_88 = mux(_T_78, mitb1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_89 = mux(_T_79, _T_81, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_90 = mux(_T_82, _T_84, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_91 = or(_T_85, _T_86) @[Mux.scala 27:72] + node _T_92 = or(_T_91, _T_87) @[Mux.scala 27:72] + node _T_93 = or(_T_92, _T_88) @[Mux.scala 27:72] + node _T_94 = or(_T_93, _T_89) @[Mux.scala 27:72] + node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] + wire _T_96 : UInt<32> @[Mux.scala 27:72] + _T_96 <= _T_95 @[Mux.scala 27:72] + io.dec_timer_rddata_d <= _T_96 @[el2_dec_tlu_ctl.scala 2833:33] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_26 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_27 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_28 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_29 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_30 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_31 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_32 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_33 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_34 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_35 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_36 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_37 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_38 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_39 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_40 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_41 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + extmodule TEC_RV_ICG_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_42 @[el2_lib.scala 465:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14] + clkhdr.CK <= io.clk @[el2_lib.scala 467:18] + clkhdr.EN <= io.en @[el2_lib.scala 468:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18] + + module csr_tlu : + input clock : Clock + input reset : Reset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + + wire miccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1454:41] + wire mice_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1455:41] + wire mdccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1456:41] + wire pc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 1457:41] + wire mpmc_b_ns : UInt<1> @[el2_dec_tlu_ctl.scala 1458:41] + wire mpmc_b : UInt<1> @[el2_dec_tlu_ctl.scala 1459:41] + wire wr_mcycleh_r : UInt<1> + wr_mcycleh_r <= UInt<1>("h00") + wire mcycleh : UInt<32> + mcycleh <= UInt<1>("h00") + wire minstretl_inc : UInt<33> + minstretl_inc <= UInt<1>("h00") + wire wr_minstreth_r : UInt<1> + wr_minstreth_r <= UInt<1>("h00") + wire minstretl : UInt<32> + minstretl <= UInt<1>("h00") + wire minstreth_inc : UInt<32> + minstreth_inc <= UInt<1>("h00") + wire minstreth : UInt<32> + minstreth <= UInt<1>("h00") + wire mfdc_ns : UInt<15> + mfdc_ns <= UInt<1>("h00") + wire mfdc_int : UInt<15> + mfdc_int <= UInt<1>("h00") + wire mhpmc6_incr : UInt<64> + mhpmc6_incr <= UInt<1>("h00") + wire mhpmc5_incr : UInt<64> + mhpmc5_incr <= UInt<1>("h00") + wire mhpmc4_incr : UInt<64> + mhpmc4_incr <= UInt<1>("h00") + wire perfcnt_halted : UInt<1> + perfcnt_halted <= UInt<1>("h00") + wire mhpmc3_incr : UInt<64> + mhpmc3_incr <= UInt<1>("h00") + wire mhpme_vec : UInt<10>[4] @[el2_dec_tlu_ctl.scala 1474:41] + wire mtdata2_t : UInt<32>[4] @[el2_dec_tlu_ctl.scala 1475:65] + wire wr_meicpct_r : UInt<1> + wr_meicpct_r <= UInt<1>("h00") + wire force_halt_ctr_f : UInt<32> + force_halt_ctr_f <= UInt<1>("h00") + wire mdccmect_inc : UInt<27> + mdccmect_inc <= UInt<1>("h00") + wire miccmect_inc : UInt<27> + miccmect_inc <= UInt<1>("h00") + wire fw_halted : UInt<1> + fw_halted <= UInt<1>("h00") + wire micect_inc : UInt<27> + micect_inc <= UInt<1>("h00") + wire mdseac_en : UInt<1> + mdseac_en <= UInt<1>("h00") + wire mie : UInt<6> + mie <= UInt<1>("h00") + wire mcyclel : UInt<32> + mcyclel <= UInt<1>("h00") + wire mscratch : UInt<32> + mscratch <= UInt<1>("h00") + wire mcause : UInt<32> + mcause <= UInt<1>("h00") + wire mscause : UInt<4> + mscause <= UInt<1>("h00") + wire mtval : UInt<32> + mtval <= UInt<1>("h00") + wire meicurpl : UInt<4> + meicurpl <= UInt<1>("h00") + wire meicidpl : UInt<4> + meicidpl <= UInt<1>("h00") + wire meipt : UInt<4> + meipt <= UInt<1>("h00") + wire mfdc : UInt<19> + mfdc <= UInt<1>("h00") + wire mtsel : UInt<2> + mtsel <= UInt<1>("h00") + wire micect : UInt<32> + micect <= UInt<1>("h00") + wire miccmect : UInt<32> + miccmect <= UInt<1>("h00") + wire mdccmect : UInt<32> + mdccmect <= UInt<1>("h00") + wire mhpmc3h : UInt<32> + mhpmc3h <= UInt<1>("h00") + wire mhpmc3 : UInt<32> + mhpmc3 <= UInt<1>("h00") + wire mhpmc4h : UInt<32> + mhpmc4h <= UInt<1>("h00") + wire mhpmc4 : UInt<32> + mhpmc4 <= UInt<1>("h00") + wire mhpmc5h : UInt<32> + mhpmc5h <= UInt<1>("h00") + wire mhpmc5 : UInt<32> + mhpmc5 <= UInt<1>("h00") + wire mhpmc6h : UInt<32> + mhpmc6h <= UInt<1>("h00") + wire mhpmc6 : UInt<32> + mhpmc6 <= UInt<1>("h00") + wire mhpme3 : UInt<10> + mhpme3 <= UInt<1>("h00") + wire mhpme4 : UInt<10> + mhpme4 <= UInt<1>("h00") + wire mhpme5 : UInt<10> + mhpme5 <= UInt<1>("h00") + wire mhpme6 : UInt<10> + mhpme6 <= UInt<1>("h00") + wire mfdht : UInt<6> + mfdht <= UInt<1>("h00") + wire mfdhs : UInt<2> + mfdhs <= UInt<1>("h00") + wire mcountinhibit : UInt<7> + mcountinhibit <= UInt<1>("h00") + wire mpmc : UInt<1> + mpmc <= UInt<1>("h00") + wire dicad1 : UInt<32> + dicad1 <= UInt<1>("h00") + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:46] + node _T_1 = and(io.dec_csr_wen_r, _T) @[el2_dec_tlu_ctl.scala 1530:44] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1530:69] + node _T_3 = and(_T_1, _T_2) @[el2_dec_tlu_ctl.scala 1530:67] + io.dec_csr_wen_r_mod <= _T_3 @[el2_dec_tlu_ctl.scala 1530:24] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1531:65] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[el2_dec_tlu_ctl.scala 1531:72] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[el2_dec_tlu_ctl.scala 1531:43] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1534:29] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[el2_dec_tlu_ctl.scala 1534:40] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:6] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1537:20] + node _T_9 = bits(_T_8, 0, 0) @[el2_dec_tlu_ctl.scala 1537:45] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_11 = bits(_T_10, 0, 0) @[el2_dec_tlu_ctl.scala 1537:69] + node _T_12 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1538:19] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 1538:44] + node _T_14 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1538:77] + node _T_15 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1539:18] + node _T_16 = and(io.mret_r, _T_15) @[el2_dec_tlu_ctl.scala 1539:16] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 1539:42] + node _T_18 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1539:71] + node _T_19 = cat(UInt<1>("h01"), _T_18) @[Cat.scala 29:58] + node _T_20 = bits(set_mie_pmu_fw_halt, 0, 0) @[el2_dec_tlu_ctl.scala 1540:27] + node _T_21 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 1540:51] + node _T_22 = cat(_T_21, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_23 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1541:21] + node _T_24 = and(wr_mstatus_r, _T_23) @[el2_dec_tlu_ctl.scala 1541:19] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 1541:45] + node _T_26 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1541:78] + node _T_27 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1541:102] + node _T_28 = cat(_T_26, _T_27) @[Cat.scala 29:58] + node _T_29 = eq(wr_mstatus_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:6] + node _T_30 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:22] + node _T_31 = and(_T_29, _T_30) @[el2_dec_tlu_ctl.scala 1542:20] + node _T_32 = eq(io.mret_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:47] + node _T_33 = and(_T_31, _T_32) @[el2_dec_tlu_ctl.scala 1542:45] + node _T_34 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1542:60] + node _T_35 = and(_T_33, _T_34) @[el2_dec_tlu_ctl.scala 1542:58] + node _T_36 = bits(_T_35, 0, 0) @[el2_dec_tlu_ctl.scala 1542:82] + node _T_37 = mux(_T_9, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_39 = mux(_T_17, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_20, _T_22, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_25, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_36, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = or(_T_37, _T_38) @[Mux.scala 27:72] + node _T_44 = or(_T_43, _T_39) @[Mux.scala 27:72] + node _T_45 = or(_T_44, _T_40) @[Mux.scala 27:72] + node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72] + wire mstatus_ns : UInt<2> @[Mux.scala 27:72] + mstatus_ns <= _T_47 @[Mux.scala 27:72] + node _T_48 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_49 = bits(_T_48, 0, 0) @[el2_dec_tlu_ctl.scala 1545:34] + node _T_50 = not(io.dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 1545:51] + node _T_51 = bits(io.dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 1545:91] + node _T_52 = or(_T_50, _T_51) @[el2_dec_tlu_ctl.scala 1545:82] + node _T_53 = and(_T_49, _T_52) @[el2_dec_tlu_ctl.scala 1545:48] + io.mstatus_mie_ns <= _T_53 @[el2_dec_tlu_ctl.scala 1545:21] + reg _T_54 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1547:12] + _T_54 <= mstatus_ns @[el2_dec_tlu_ctl.scala 1547:12] + io.mstatus <= _T_54 @[el2_dec_tlu_ctl.scala 1546:14] + node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1556:63] + node _T_56 = eq(_T_55, UInt<12>("h0305")) @[el2_dec_tlu_ctl.scala 1556:70] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_56) @[el2_dec_tlu_ctl.scala 1556:41] + node _T_57 = bits(io.dec_csr_wrdata_r, 31, 2) @[el2_dec_tlu_ctl.scala 1557:41] + node _T_58 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1557:69] + node mtvec_ns = cat(_T_57, _T_58) @[Cat.scala 29:58] + node _T_59 = bits(wr_mtvec_r, 0, 0) @[el2_dec_tlu_ctl.scala 1558:43] + inst rvclkhdr of rvclkhdr_8 @[el2_lib.scala 485:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr.io.en <= _T_59 @[el2_lib.scala 488:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_60 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_60 <= mtvec_ns @[el2_lib.scala 491:16] + io.mtvec <= _T_60 @[el2_dec_tlu_ctl.scala 1558:12] + node _T_61 = or(mdccme_ce_req, miccme_ce_req) @[el2_dec_tlu_ctl.scala 1570:31] + node ce_int = or(_T_61, mice_ce_req) @[el2_dec_tlu_ctl.scala 1570:47] + node _T_62 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, io.soft_int_sync) @[Cat.scala 29:58] + node _T_64 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, io.dec_timer_t1_pulse) @[Cat.scala 29:58] + node mip_ns = cat(_T_65, _T_63) @[Cat.scala 29:58] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1574:12] + _T_66 <= mip_ns @[el2_dec_tlu_ctl.scala 1574:12] + io.mip <= _T_66 @[el2_dec_tlu_ctl.scala 1573:10] + node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1586:61] + node _T_68 = eq(_T_67, UInt<12>("h0304")) @[el2_dec_tlu_ctl.scala 1586:68] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[el2_dec_tlu_ctl.scala 1586:39] + node _T_69 = bits(wr_mie_r, 0, 0) @[el2_dec_tlu_ctl.scala 1587:29] + node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[el2_dec_tlu_ctl.scala 1587:60] + node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1587:89] + node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1587:114] + node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1587:138] + node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58] + node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58] + node _T_77 = mux(_T_69, _T_76, mie) @[el2_dec_tlu_ctl.scala 1587:19] + io.mie_ns <= _T_77 @[el2_dec_tlu_ctl.scala 1587:13] + reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1589:12] + _T_78 <= io.mie_ns @[el2_dec_tlu_ctl.scala 1589:12] + mie <= _T_78 @[el2_dec_tlu_ctl.scala 1588:7] + node _T_79 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1596:64] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[el2_dec_tlu_ctl.scala 1596:55] + node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1598:65] + node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[el2_dec_tlu_ctl.scala 1598:72] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[el2_dec_tlu_ctl.scala 1598:43] + node _T_82 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 1600:81] + node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[el2_dec_tlu_ctl.scala 1600:72] + node _T_84 = or(kill_ebreak_count_r, _T_83) @[el2_dec_tlu_ctl.scala 1600:47] + node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 1600:95] + node _T_86 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 1600:137] + node _T_87 = or(_T_85, _T_86) @[el2_dec_tlu_ctl.scala 1600:122] + node mcyclel_cout_in = not(_T_87) @[el2_dec_tlu_ctl.scala 1600:25] + wire mcyclel_inc : UInt<33> + mcyclel_inc <= UInt<1>("h00") + node _T_88 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] + node _T_89 = add(mcyclel, _T_88) @[el2_dec_tlu_ctl.scala 1604:26] + node _T_90 = tail(_T_89, 1) @[el2_dec_tlu_ctl.scala 1604:26] + mcyclel_inc <= _T_90 @[el2_dec_tlu_ctl.scala 1604:15] + node _T_91 = bits(wr_mcyclel_r, 0, 0) @[el2_dec_tlu_ctl.scala 1605:37] + node mcyclel_ns = mux(_T_91, io.dec_csr_wrdata_r, mcyclel_inc) @[el2_dec_tlu_ctl.scala 1605:23] + node _T_92 = bits(mcyclel_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1606:33] + node mcyclel_cout = bits(_T_92, 0, 0) @[el2_dec_tlu_ctl.scala 1606:38] + node _T_93 = or(wr_mcyclel_r, mcyclel_cout_in) @[el2_dec_tlu_ctl.scala 1607:47] + node _T_94 = bits(_T_93, 0, 0) @[el2_dec_tlu_ctl.scala 1607:73] + inst rvclkhdr_1 of rvclkhdr_9 @[el2_lib.scala 485:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_1.io.en <= _T_94 @[el2_lib.scala 488:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_95 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_95 <= mcyclel_ns @[el2_lib.scala 491:16] + mcyclel <= _T_95 @[el2_dec_tlu_ctl.scala 1607:11] + node _T_96 = eq(wr_mcycleh_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1608:72] + node _T_97 = and(mcyclel_cout, _T_96) @[el2_dec_tlu_ctl.scala 1608:70] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1608:55] + mcyclel_cout_f <= _T_97 @[el2_dec_tlu_ctl.scala 1608:55] + node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1614:62] + node _T_99 = eq(_T_98, UInt<12>("h0b80")) @[el2_dec_tlu_ctl.scala 1614:69] + node _T_100 = and(io.dec_csr_wen_r_mod, _T_99) @[el2_dec_tlu_ctl.scala 1614:40] + wr_mcycleh_r <= _T_100 @[el2_dec_tlu_ctl.scala 1614:16] + node _T_101 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] + node _T_102 = add(mcycleh, _T_101) @[el2_dec_tlu_ctl.scala 1616:29] + node mcycleh_inc = tail(_T_102, 1) @[el2_dec_tlu_ctl.scala 1616:29] + node _T_103 = bits(wr_mcycleh_r, 0, 0) @[el2_dec_tlu_ctl.scala 1617:37] + node mcycleh_ns = mux(_T_103, io.dec_csr_wrdata_r, mcycleh_inc) @[el2_dec_tlu_ctl.scala 1617:23] + node _T_104 = or(wr_mcycleh_r, mcyclel_cout_f) @[el2_dec_tlu_ctl.scala 1619:47] + node _T_105 = bits(_T_104, 0, 0) @[el2_dec_tlu_ctl.scala 1619:65] + inst rvclkhdr_2 of rvclkhdr_10 @[el2_lib.scala 485:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_2.io.en <= _T_105 @[el2_lib.scala 488:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_106 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_106 <= mcycleh_ns @[el2_lib.scala 491:16] + mcycleh <= _T_106 @[el2_dec_tlu_ctl.scala 1619:11] + node _T_107 = or(io.ebreak_r, io.ecall_r) @[el2_dec_tlu_ctl.scala 1633:73] + node _T_108 = or(_T_107, io.ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 1633:86] + node _T_109 = or(_T_108, io.illegal_r) @[el2_dec_tlu_ctl.scala 1633:114] + node _T_110 = bits(mcountinhibit, 2, 2) @[el2_dec_tlu_ctl.scala 1633:144] + node _T_111 = or(_T_109, _T_110) @[el2_dec_tlu_ctl.scala 1633:129] + node _T_112 = bits(_T_111, 0, 0) @[el2_dec_tlu_ctl.scala 1633:149] + node _T_113 = not(_T_112) @[el2_dec_tlu_ctl.scala 1633:59] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_113) @[el2_dec_tlu_ctl.scala 1633:57] + node _T_114 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1635:67] + node _T_115 = eq(_T_114, UInt<12>("h0b02")) @[el2_dec_tlu_ctl.scala 1635:74] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_115) @[el2_dec_tlu_ctl.scala 1635:45] + node _T_116 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] + node _T_117 = add(minstretl, _T_116) @[el2_dec_tlu_ctl.scala 1637:30] + node _T_118 = tail(_T_117, 1) @[el2_dec_tlu_ctl.scala 1637:30] + minstretl_inc <= _T_118 @[el2_dec_tlu_ctl.scala 1637:17] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[el2_dec_tlu_ctl.scala 1638:37] + node _T_119 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[el2_dec_tlu_ctl.scala 1639:53] + node minstret_enable = bits(_T_119, 0, 0) @[el2_dec_tlu_ctl.scala 1639:71] + node _T_120 = bits(wr_minstretl_r, 0, 0) @[el2_dec_tlu_ctl.scala 1641:41] + node minstretl_ns = mux(_T_120, io.dec_csr_wrdata_r, minstretl_inc) @[el2_dec_tlu_ctl.scala 1641:25] + node _T_121 = bits(minstret_enable, 0, 0) @[el2_dec_tlu_ctl.scala 1642:52] + inst rvclkhdr_3 of rvclkhdr_11 @[el2_lib.scala 485:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_3.io.en <= _T_121 @[el2_lib.scala 488:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_122 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_122 <= minstretl_ns @[el2_lib.scala 491:16] + minstretl <= _T_122 @[el2_dec_tlu_ctl.scala 1642:13] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1643:57] + minstret_enable_f <= minstret_enable @[el2_dec_tlu_ctl.scala 1643:57] + node _T_123 = not(wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1644:76] + node _T_124 = and(minstretl_cout, _T_123) @[el2_dec_tlu_ctl.scala 1644:74] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1644:57] + minstretl_cout_f <= _T_124 @[el2_dec_tlu_ctl.scala 1644:57] + node _T_125 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1652:65] + node _T_126 = eq(_T_125, UInt<12>("h0b82")) @[el2_dec_tlu_ctl.scala 1652:72] + node _T_127 = and(io.dec_csr_wen_r_mod, _T_126) @[el2_dec_tlu_ctl.scala 1652:43] + node _T_128 = bits(_T_127, 0, 0) @[el2_dec_tlu_ctl.scala 1652:88] + wr_minstreth_r <= _T_128 @[el2_dec_tlu_ctl.scala 1652:18] + node _T_129 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] + node _T_130 = add(minstreth, _T_129) @[el2_dec_tlu_ctl.scala 1655:30] + node _T_131 = tail(_T_130, 1) @[el2_dec_tlu_ctl.scala 1655:30] + minstreth_inc <= _T_131 @[el2_dec_tlu_ctl.scala 1655:17] + node _T_132 = bits(wr_minstreth_r, 0, 0) @[el2_dec_tlu_ctl.scala 1656:42] + node minstreth_ns = mux(_T_132, io.dec_csr_wrdata_r, minstreth_inc) @[el2_dec_tlu_ctl.scala 1656:26] + node _T_133 = or(minstret_enable_f, wr_minstreth_r) @[el2_dec_tlu_ctl.scala 1658:56] + node _T_134 = bits(_T_133, 0, 0) @[el2_dec_tlu_ctl.scala 1658:74] + inst rvclkhdr_4 of rvclkhdr_12 @[el2_lib.scala 485:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_4.io.en <= _T_134 @[el2_lib.scala 488:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_135 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_135 <= minstreth_ns @[el2_lib.scala 491:16] + minstreth <= _T_135 @[el2_dec_tlu_ctl.scala 1658:13] + node _T_136 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1666:66] + node _T_137 = eq(_T_136, UInt<12>("h0340")) @[el2_dec_tlu_ctl.scala 1666:73] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_137) @[el2_dec_tlu_ctl.scala 1666:44] + node _T_138 = bits(wr_mscratch_r, 0, 0) @[el2_dec_tlu_ctl.scala 1668:56] + inst rvclkhdr_5 of rvclkhdr_13 @[el2_lib.scala 485:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_5.io.en <= _T_138 @[el2_lib.scala 488:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_139 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_139 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mscratch <= _T_139 @[el2_dec_tlu_ctl.scala 1668:12] + node _T_140 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:23] + node _T_141 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1677:48] + node _T_142 = and(_T_140, _T_141) @[el2_dec_tlu_ctl.scala 1677:46] + node sel_exu_npc_r = and(_T_142, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1677:73] + node _T_143 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:25] + node _T_144 = and(_T_143, io.tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 1678:48] + node _T_145 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1678:76] + node sel_flush_npc_r = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 1678:74] + node _T_146 = eq(sel_exu_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:24] + node _T_147 = eq(sel_flush_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1679:41] + node sel_hold_npc_r = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 1679:39] + node _T_148 = bits(sel_exu_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1682:19] + node _T_149 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1683:6] + node _T_150 = and(_T_149, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1683:28] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_tlu_ctl.scala 1683:48] + node _T_152 = bits(sel_flush_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1684:21] + node _T_153 = bits(sel_hold_npc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1685:20] + node _T_154 = mux(_T_148, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_155 = mux(_T_151, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_156 = mux(_T_152, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_157 = mux(_T_153, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_158 = or(_T_154, _T_155) @[Mux.scala 27:72] + node _T_159 = or(_T_158, _T_156) @[Mux.scala 27:72] + node _T_160 = or(_T_159, _T_157) @[Mux.scala 27:72] + wire _T_161 : UInt<31> @[Mux.scala 27:72] + _T_161 <= _T_160 @[Mux.scala 27:72] + io.npc_r <= _T_161 @[el2_dec_tlu_ctl.scala 1681:12] + node _T_162 = or(sel_exu_npc_r, sel_flush_npc_r) @[el2_dec_tlu_ctl.scala 1687:49] + node _T_163 = or(_T_162, io.reset_delayed) @[el2_dec_tlu_ctl.scala 1687:67] + node _T_164 = bits(_T_163, 0, 0) @[el2_dec_tlu_ctl.scala 1687:87] + inst rvclkhdr_6 of rvclkhdr_14 @[el2_lib.scala 485:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_6.io.en <= _T_164 @[el2_lib.scala 488:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_165 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_165 <= io.npc_r @[el2_lib.scala 491:16] + io.npc_r_d1 <= _T_165 @[el2_dec_tlu_ctl.scala 1687:15] + node _T_166 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1690:22] + node _T_167 = and(_T_166, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 1690:45] + node pc0_valid_r = bits(_T_167, 0, 0) @[el2_dec_tlu_ctl.scala 1690:70] + node _T_168 = not(pc0_valid_r) @[el2_dec_tlu_ctl.scala 1694:5] + node _T_169 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_170 = mux(_T_168, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_171 = or(_T_169, _T_170) @[Mux.scala 27:72] + wire pc_r : UInt<31> @[Mux.scala 27:72] + pc_r <= _T_171 @[Mux.scala 27:72] + inst rvclkhdr_7 of rvclkhdr_15 @[el2_lib.scala 485:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 488:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_172 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_172 <= pc_r @[el2_lib.scala 491:16] + pc_r_d1 <= _T_172 @[el2_dec_tlu_ctl.scala 1696:11] + node _T_173 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1698:62] + node _T_174 = eq(_T_173, UInt<12>("h0341")) @[el2_dec_tlu_ctl.scala 1698:69] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_174) @[el2_dec_tlu_ctl.scala 1698:40] + node _T_175 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1701:30] + node _T_176 = or(_T_175, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1701:51] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_tlu_ctl.scala 1701:83] + node _T_178 = bits(io.interrupt_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1702:28] + node _T_179 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1703:18] + node _T_180 = and(wr_mepc_r, _T_179) @[el2_dec_tlu_ctl.scala 1703:16] + node _T_181 = bits(_T_180, 0, 0) @[el2_dec_tlu_ctl.scala 1703:42] + node _T_182 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 1703:107] + node _T_183 = eq(wr_mepc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:6] + node _T_184 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1704:19] + node _T_185 = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 1704:17] + node _T_186 = bits(_T_185, 0, 0) @[el2_dec_tlu_ctl.scala 1704:43] + node _T_187 = mux(_T_177, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = mux(_T_178, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_189 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_186, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = or(_T_187, _T_188) @[Mux.scala 27:72] + node _T_192 = or(_T_191, _T_189) @[Mux.scala 27:72] + node _T_193 = or(_T_192, _T_190) @[Mux.scala 27:72] + wire mepc_ns : UInt<31> @[Mux.scala 27:72] + mepc_ns <= _T_193 @[Mux.scala 27:72] + reg _T_194 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1706:48] + _T_194 <= mepc_ns @[el2_dec_tlu_ctl.scala 1706:48] + io.mepc <= _T_194 @[el2_dec_tlu_ctl.scala 1706:11] + node _T_195 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1713:64] + node _T_196 = eq(_T_195, UInt<12>("h0342")) @[el2_dec_tlu_ctl.scala 1713:71] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_196) @[el2_dec_tlu_ctl.scala 1713:42] + node _T_197 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1714:52] + node mcause_sel_nmi_store = and(_T_197, io.nmi_lsu_store_type) @[el2_dec_tlu_ctl.scala 1714:66] + node _T_198 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1715:51] + node mcause_sel_nmi_load = and(_T_198, io.nmi_lsu_load_type) @[el2_dec_tlu_ctl.scala 1715:65] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[el2_dec_tlu_ctl.scala 1716:50] + node _T_200 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1716:83] + node mcause_sel_nmi_ext = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 1716:64] + node _T_201 = andr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 1722:52] + node _T_202 = bits(io.lsu_fir_error, 1, 1) @[el2_dec_tlu_ctl.scala 1722:75] + node _T_203 = bits(io.lsu_fir_error, 0, 0) @[el2_dec_tlu_ctl.scala 1722:98] + node _T_204 = not(_T_203) @[el2_dec_tlu_ctl.scala 1722:81] + node _T_205 = and(_T_202, _T_204) @[el2_dec_tlu_ctl.scala 1722:79] + node mcause_fir_error_type = cat(_T_201, _T_205) @[Cat.scala 29:58] + node _T_206 = bits(mcause_sel_nmi_store, 0, 0) @[el2_dec_tlu_ctl.scala 1725:26] + node _T_207 = bits(mcause_sel_nmi_load, 0, 0) @[el2_dec_tlu_ctl.scala 1726:25] + node _T_208 = bits(mcause_sel_nmi_ext, 0, 0) @[el2_dec_tlu_ctl.scala 1727:24] + node _T_209 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] + node _T_210 = cat(_T_209, mcause_fir_error_type) @[Cat.scala 29:58] + node _T_211 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1728:30] + node _T_212 = and(io.exc_or_int_valid_r, _T_211) @[el2_dec_tlu_ctl.scala 1728:28] + node _T_213 = bits(_T_212, 0, 0) @[el2_dec_tlu_ctl.scala 1728:44] + node _T_214 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] + node _T_215 = cat(_T_214, io.exc_cause_r) @[Cat.scala 29:58] + node _T_216 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1729:20] + node _T_217 = and(wr_mcause_r, _T_216) @[el2_dec_tlu_ctl.scala 1729:18] + node _T_218 = bits(_T_217, 0, 0) @[el2_dec_tlu_ctl.scala 1729:44] + node _T_219 = not(wr_mcause_r) @[el2_dec_tlu_ctl.scala 1730:6] + node _T_220 = not(io.exc_or_int_valid_r) @[el2_dec_tlu_ctl.scala 1730:21] + node _T_221 = and(_T_219, _T_220) @[el2_dec_tlu_ctl.scala 1730:19] + node _T_222 = bits(_T_221, 0, 0) @[el2_dec_tlu_ctl.scala 1730:45] + node _T_223 = mux(_T_206, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_224 = mux(_T_207, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_225 = mux(_T_208, _T_210, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = mux(_T_218, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_228 = mux(_T_222, mcause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = or(_T_223, _T_224) @[Mux.scala 27:72] + node _T_230 = or(_T_229, _T_225) @[Mux.scala 27:72] + node _T_231 = or(_T_230, _T_226) @[Mux.scala 27:72] + node _T_232 = or(_T_231, _T_227) @[Mux.scala 27:72] + node _T_233 = or(_T_232, _T_228) @[Mux.scala 27:72] + wire mcause_ns : UInt<32> @[Mux.scala 27:72] + mcause_ns <= _T_233 @[Mux.scala 27:72] + reg _T_234 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1732:47] + _T_234 <= mcause_ns @[el2_dec_tlu_ctl.scala 1732:47] + mcause <= _T_234 @[el2_dec_tlu_ctl.scala 1732:10] + node _T_235 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1739:65] + node _T_236 = eq(_T_235, UInt<12>("h07ff")) @[el2_dec_tlu_ctl.scala 1739:72] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_236) @[el2_dec_tlu_ctl.scala 1739:43] + node _T_237 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 1741:57] + node _T_238 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] + node ifu_mscause = mux(_T_237, UInt<4>("h09"), _T_238) @[el2_dec_tlu_ctl.scala 1741:25] + node _T_239 = bits(io.lsu_i0_exc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1744:21] + node _T_240 = bits(io.i0_trigger_hit_r, 0, 0) @[el2_dec_tlu_ctl.scala 1745:25] + node _T_241 = bits(io.ebreak_r, 0, 0) @[el2_dec_tlu_ctl.scala 1746:17] + node _T_242 = bits(io.inst_acc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1747:19] + node _T_243 = mux(_T_239, io.lsu_error_pkt_r.mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_240, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_241, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = mux(_T_242, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_247 = or(_T_243, _T_244) @[Mux.scala 27:72] + node _T_248 = or(_T_247, _T_245) @[Mux.scala 27:72] + node _T_249 = or(_T_248, _T_246) @[Mux.scala 27:72] + wire mscause_type : UInt<4> @[Mux.scala 27:72] + mscause_type <= _T_249 @[Mux.scala 27:72] + node _T_250 = bits(io.exc_or_int_valid_r, 0, 0) @[el2_dec_tlu_ctl.scala 1751:29] + node _T_251 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1752:21] + node _T_252 = and(wr_mscause_r, _T_251) @[el2_dec_tlu_ctl.scala 1752:19] + node _T_253 = bits(_T_252, 0, 0) @[el2_dec_tlu_ctl.scala 1752:45] + node _T_254 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 1752:84] + node _T_255 = eq(wr_mscause_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:6] + node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 1753:22] + node _T_257 = and(_T_255, _T_256) @[el2_dec_tlu_ctl.scala 1753:20] + node _T_258 = bits(_T_257, 0, 0) @[el2_dec_tlu_ctl.scala 1753:46] + node _T_259 = mux(_T_250, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_258, mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72] + wire mscause_ns : UInt<4> @[Mux.scala 27:72] + mscause_ns <= _T_263 @[Mux.scala 27:72] + reg _T_264 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1755:48] + _T_264 <= mscause_ns @[el2_dec_tlu_ctl.scala 1755:48] + mscause <= _T_264 @[el2_dec_tlu_ctl.scala 1755:11] + node _T_265 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1762:63] + node _T_266 = eq(_T_265, UInt<12>("h0343")) @[el2_dec_tlu_ctl.scala 1762:70] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_266) @[el2_dec_tlu_ctl.scala 1762:41] + node _T_267 = not(io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1763:84] + node _T_268 = and(io.inst_acc_r, _T_267) @[el2_dec_tlu_ctl.scala 1763:82] + node _T_269 = or(io.ebreak_r, _T_268) @[el2_dec_tlu_ctl.scala 1763:65] + node _T_270 = or(_T_269, io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1763:107] + node _T_271 = and(io.exc_or_int_valid_r, _T_270) @[el2_dec_tlu_ctl.scala 1763:50] + node _T_272 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1763:141] + node mtval_capture_pc_r = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 1763:139] + node _T_273 = and(io.inst_acc_r, io.inst_acc_second_r) @[el2_dec_tlu_ctl.scala 1764:73] + node _T_274 = and(io.exc_or_int_valid_r, _T_273) @[el2_dec_tlu_ctl.scala 1764:56] + node _T_275 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1764:99] + node mtval_capture_pc_plus2_r = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 1764:97] + node _T_276 = and(io.exc_or_int_valid_r, io.illegal_r) @[el2_dec_tlu_ctl.scala 1765:52] + node _T_277 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1765:69] + node mtval_capture_inst_r = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 1765:67] + node _T_278 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 1766:51] + node _T_279 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1766:74] + node mtval_capture_lsu_r = and(_T_278, _T_279) @[el2_dec_tlu_ctl.scala 1766:72] + node _T_280 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1767:47] + node _T_281 = and(io.exc_or_int_valid_r, _T_280) @[el2_dec_tlu_ctl.scala 1767:45] + node _T_282 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1767:69] + node _T_283 = and(_T_281, _T_282) @[el2_dec_tlu_ctl.scala 1767:67] + node _T_284 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1767:93] + node _T_285 = and(_T_283, _T_284) @[el2_dec_tlu_ctl.scala 1767:91] + node _T_286 = not(io.mepc_trigger_hit_sel_pc_r) @[el2_dec_tlu_ctl.scala 1767:116] + node mtval_clear_r = and(_T_285, _T_286) @[el2_dec_tlu_ctl.scala 1767:114] + node _T_287 = bits(mtval_capture_pc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1771:26] + node _T_288 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_289 = bits(mtval_capture_pc_plus2_r, 0, 0) @[el2_dec_tlu_ctl.scala 1772:32] + node _T_290 = add(pc_r, UInt<31>("h01")) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_291 = tail(_T_290, 1) @[el2_dec_tlu_ctl.scala 1772:84] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = bits(mtval_capture_inst_r, 0, 0) @[el2_dec_tlu_ctl.scala 1773:28] + node _T_294 = bits(mtval_capture_lsu_r, 0, 0) @[el2_dec_tlu_ctl.scala 1774:27] + node _T_295 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1775:19] + node _T_296 = and(wr_mtval_r, _T_295) @[el2_dec_tlu_ctl.scala 1775:17] + node _T_297 = bits(_T_296, 0, 0) @[el2_dec_tlu_ctl.scala 1775:49] + node _T_298 = not(io.take_nmi) @[el2_dec_tlu_ctl.scala 1776:6] + node _T_299 = not(wr_mtval_r) @[el2_dec_tlu_ctl.scala 1776:21] + node _T_300 = and(_T_298, _T_299) @[el2_dec_tlu_ctl.scala 1776:19] + node _T_301 = not(mtval_capture_pc_r) @[el2_dec_tlu_ctl.scala 1776:35] + node _T_302 = and(_T_300, _T_301) @[el2_dec_tlu_ctl.scala 1776:33] + node _T_303 = not(mtval_capture_inst_r) @[el2_dec_tlu_ctl.scala 1776:57] + node _T_304 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 1776:55] + node _T_305 = not(mtval_clear_r) @[el2_dec_tlu_ctl.scala 1776:81] + node _T_306 = and(_T_304, _T_305) @[el2_dec_tlu_ctl.scala 1776:79] + node _T_307 = not(mtval_capture_lsu_r) @[el2_dec_tlu_ctl.scala 1776:98] + node _T_308 = and(_T_306, _T_307) @[el2_dec_tlu_ctl.scala 1776:96] + node _T_309 = bits(_T_308, 0, 0) @[el2_dec_tlu_ctl.scala 1776:120] + node _T_310 = mux(_T_287, _T_288, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_311 = mux(_T_289, _T_292, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_312 = mux(_T_293, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_313 = mux(_T_294, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_314 = mux(_T_297, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_315 = mux(_T_309, mtval, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_316 = or(_T_310, _T_311) @[Mux.scala 27:72] + node _T_317 = or(_T_316, _T_312) @[Mux.scala 27:72] + node _T_318 = or(_T_317, _T_313) @[Mux.scala 27:72] + node _T_319 = or(_T_318, _T_314) @[Mux.scala 27:72] + node _T_320 = or(_T_319, _T_315) @[Mux.scala 27:72] + wire mtval_ns : UInt<32> @[Mux.scala 27:72] + mtval_ns <= _T_320 @[Mux.scala 27:72] + reg _T_321 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1778:47] + _T_321 <= mtval_ns @[el2_dec_tlu_ctl.scala 1778:47] + mtval <= _T_321 @[el2_dec_tlu_ctl.scala 1778:9] + node _T_322 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1793:62] + node _T_323 = eq(_T_322, UInt<12>("h07f8")) @[el2_dec_tlu_ctl.scala 1793:69] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_323) @[el2_dec_tlu_ctl.scala 1793:40] + node _T_324 = bits(io.dec_csr_wrdata_r, 8, 0) @[el2_dec_tlu_ctl.scala 1795:40] + node _T_325 = bits(wr_mcgc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1795:56] + inst rvclkhdr_8 of rvclkhdr_16 @[el2_lib.scala 485:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_8.io.en <= _T_325 @[el2_lib.scala 488:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mcgc <= _T_324 @[el2_lib.scala 491:16] + node _T_326 = bits(mcgc, 8, 8) @[el2_dec_tlu_ctl.scala 1797:39] + io.dec_tlu_misc_clk_override <= _T_326 @[el2_dec_tlu_ctl.scala 1797:32] + node _T_327 = bits(mcgc, 7, 7) @[el2_dec_tlu_ctl.scala 1798:39] + io.dec_tlu_dec_clk_override <= _T_327 @[el2_dec_tlu_ctl.scala 1798:32] + node _T_328 = bits(mcgc, 5, 5) @[el2_dec_tlu_ctl.scala 1799:39] + io.dec_tlu_ifu_clk_override <= _T_328 @[el2_dec_tlu_ctl.scala 1799:32] + node _T_329 = bits(mcgc, 4, 4) @[el2_dec_tlu_ctl.scala 1800:39] + io.dec_tlu_lsu_clk_override <= _T_329 @[el2_dec_tlu_ctl.scala 1800:32] + node _T_330 = bits(mcgc, 3, 3) @[el2_dec_tlu_ctl.scala 1801:39] + io.dec_tlu_bus_clk_override <= _T_330 @[el2_dec_tlu_ctl.scala 1801:32] + node _T_331 = bits(mcgc, 2, 2) @[el2_dec_tlu_ctl.scala 1802:39] + io.dec_tlu_pic_clk_override <= _T_331 @[el2_dec_tlu_ctl.scala 1802:32] + node _T_332 = bits(mcgc, 1, 1) @[el2_dec_tlu_ctl.scala 1803:39] + io.dec_tlu_dccm_clk_override <= _T_332 @[el2_dec_tlu_ctl.scala 1803:32] + node _T_333 = bits(mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 1804:39] + io.dec_tlu_icm_clk_override <= _T_333 @[el2_dec_tlu_ctl.scala 1804:32] + node _T_334 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1823:62] + node _T_335 = eq(_T_334, UInt<12>("h07f9")) @[el2_dec_tlu_ctl.scala 1823:69] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_335) @[el2_dec_tlu_ctl.scala 1823:40] + node _T_336 = bits(wr_mfdc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1827:40] + inst rvclkhdr_9 of rvclkhdr_17 @[el2_lib.scala 485:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_9.io.en <= _T_336 @[el2_lib.scala 488:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_337 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_337 <= mfdc_ns @[el2_lib.scala 491:16] + mfdc_int <= _T_337 @[el2_dec_tlu_ctl.scala 1827:12] + node _T_338 = bits(io.dec_csr_wrdata_r, 18, 16) @[el2_dec_tlu_ctl.scala 1832:40] + node _T_339 = not(_T_338) @[el2_dec_tlu_ctl.scala 1832:20] + node _T_340 = bits(io.dec_csr_wrdata_r, 11, 7) @[el2_dec_tlu_ctl.scala 1832:67] + node _T_341 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1832:95] + node _T_342 = not(_T_341) @[el2_dec_tlu_ctl.scala 1832:75] + node _T_343 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1832:119] + node _T_344 = cat(_T_342, _T_343) @[Cat.scala 29:58] + node _T_345 = cat(_T_339, _T_340) @[Cat.scala 29:58] + node _T_346 = cat(_T_345, _T_344) @[Cat.scala 29:58] + mfdc_ns <= _T_346 @[el2_dec_tlu_ctl.scala 1832:13] + node _T_347 = bits(mfdc_int, 14, 12) @[el2_dec_tlu_ctl.scala 1833:29] + node _T_348 = not(_T_347) @[el2_dec_tlu_ctl.scala 1833:20] + node _T_349 = bits(mfdc_int, 11, 7) @[el2_dec_tlu_ctl.scala 1833:55] + node _T_350 = bits(mfdc_int, 6, 6) @[el2_dec_tlu_ctl.scala 1833:72] + node _T_351 = not(_T_350) @[el2_dec_tlu_ctl.scala 1833:63] + node _T_352 = bits(mfdc_int, 5, 0) @[el2_dec_tlu_ctl.scala 1833:85] + node _T_353 = cat(_T_351, _T_352) @[Cat.scala 29:58] + node _T_354 = cat(_T_348, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_355 = cat(_T_354, _T_349) @[Cat.scala 29:58] + node _T_356 = cat(_T_355, _T_353) @[Cat.scala 29:58] + mfdc <= _T_356 @[el2_dec_tlu_ctl.scala 1833:13] + node _T_357 = bits(mfdc, 18, 16) @[el2_dec_tlu_ctl.scala 1841:47] + io.dec_tlu_dma_qos_prty <= _T_357 @[el2_dec_tlu_ctl.scala 1841:40] + node _T_358 = bits(mfdc, 11, 11) @[el2_dec_tlu_ctl.scala 1842:47] + io.dec_tlu_external_ldfwd_disable <= _T_358 @[el2_dec_tlu_ctl.scala 1842:40] + node _T_359 = bits(mfdc, 8, 8) @[el2_dec_tlu_ctl.scala 1843:47] + io.dec_tlu_core_ecc_disable <= _T_359 @[el2_dec_tlu_ctl.scala 1843:40] + node _T_360 = bits(mfdc, 6, 6) @[el2_dec_tlu_ctl.scala 1844:47] + io.dec_tlu_sideeffect_posted_disable <= _T_360 @[el2_dec_tlu_ctl.scala 1844:40] + node _T_361 = bits(mfdc, 3, 3) @[el2_dec_tlu_ctl.scala 1845:47] + io.dec_tlu_bpred_disable <= _T_361 @[el2_dec_tlu_ctl.scala 1845:40] + node _T_362 = bits(mfdc, 2, 2) @[el2_dec_tlu_ctl.scala 1846:47] + io.dec_tlu_wb_coalescing_disable <= _T_362 @[el2_dec_tlu_ctl.scala 1846:40] + node _T_363 = bits(mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 1847:47] + io.dec_tlu_pipelining_disable <= _T_363 @[el2_dec_tlu_ctl.scala 1847:40] + node _T_364 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1856:71] + node _T_365 = eq(_T_364, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 1856:78] + node _T_366 = and(io.dec_csr_wen_r_mod, _T_365) @[el2_dec_tlu_ctl.scala 1856:49] + node _T_367 = not(io.interrupt_valid_r) @[el2_dec_tlu_ctl.scala 1856:90] + node _T_368 = and(_T_366, _T_367) @[el2_dec_tlu_ctl.scala 1856:88] + node _T_369 = not(io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 1856:114] + node _T_370 = and(_T_368, _T_369) @[el2_dec_tlu_ctl.scala 1856:112] + io.dec_tlu_wr_pause_r <= _T_370 @[el2_dec_tlu_ctl.scala 1856:25] + node _T_371 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1863:62] + node _T_372 = eq(_T_371, UInt<12>("h07c0")) @[el2_dec_tlu_ctl.scala 1863:69] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_372) @[el2_dec_tlu_ctl.scala 1863:40] + node _T_373 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:40] + node _T_374 = bits(io.dec_csr_wrdata_r, 30, 30) @[el2_dec_tlu_ctl.scala 1866:65] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[el2_dec_tlu_ctl.scala 1866:92] + node _T_376 = not(_T_375) @[el2_dec_tlu_ctl.scala 1866:72] + node _T_377 = and(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 1866:70] + node _T_378 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:24] + node _T_379 = bits(io.dec_csr_wrdata_r, 28, 28) @[el2_dec_tlu_ctl.scala 1867:49] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[el2_dec_tlu_ctl.scala 1867:76] + node _T_381 = not(_T_380) @[el2_dec_tlu_ctl.scala 1867:56] + node _T_382 = and(_T_379, _T_381) @[el2_dec_tlu_ctl.scala 1867:54] + node _T_383 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:24] + node _T_384 = bits(io.dec_csr_wrdata_r, 26, 26) @[el2_dec_tlu_ctl.scala 1868:49] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 1868:76] + node _T_386 = not(_T_385) @[el2_dec_tlu_ctl.scala 1868:56] + node _T_387 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 1868:54] + node _T_388 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:24] + node _T_389 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 1869:49] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[el2_dec_tlu_ctl.scala 1869:76] + node _T_391 = not(_T_390) @[el2_dec_tlu_ctl.scala 1869:56] + node _T_392 = and(_T_389, _T_391) @[el2_dec_tlu_ctl.scala 1869:54] + node _T_393 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:24] + node _T_394 = bits(io.dec_csr_wrdata_r, 22, 22) @[el2_dec_tlu_ctl.scala 1870:49] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[el2_dec_tlu_ctl.scala 1870:76] + node _T_396 = not(_T_395) @[el2_dec_tlu_ctl.scala 1870:56] + node _T_397 = and(_T_394, _T_396) @[el2_dec_tlu_ctl.scala 1870:54] + node _T_398 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:24] + node _T_399 = bits(io.dec_csr_wrdata_r, 20, 20) @[el2_dec_tlu_ctl.scala 1871:49] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[el2_dec_tlu_ctl.scala 1871:76] + node _T_401 = not(_T_400) @[el2_dec_tlu_ctl.scala 1871:56] + node _T_402 = and(_T_399, _T_401) @[el2_dec_tlu_ctl.scala 1871:54] + node _T_403 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:24] + node _T_404 = bits(io.dec_csr_wrdata_r, 18, 18) @[el2_dec_tlu_ctl.scala 1872:49] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 1872:76] + node _T_406 = not(_T_405) @[el2_dec_tlu_ctl.scala 1872:56] + node _T_407 = and(_T_404, _T_406) @[el2_dec_tlu_ctl.scala 1872:54] + node _T_408 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:24] + node _T_409 = bits(io.dec_csr_wrdata_r, 16, 16) @[el2_dec_tlu_ctl.scala 1873:49] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[el2_dec_tlu_ctl.scala 1873:76] + node _T_411 = not(_T_410) @[el2_dec_tlu_ctl.scala 1873:56] + node _T_412 = and(_T_409, _T_411) @[el2_dec_tlu_ctl.scala 1873:54] + node _T_413 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:24] + node _T_414 = bits(io.dec_csr_wrdata_r, 14, 14) @[el2_dec_tlu_ctl.scala 1874:49] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 1874:76] + node _T_416 = not(_T_415) @[el2_dec_tlu_ctl.scala 1874:56] + node _T_417 = and(_T_414, _T_416) @[el2_dec_tlu_ctl.scala 1874:54] + node _T_418 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:24] + node _T_419 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 1875:49] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[el2_dec_tlu_ctl.scala 1875:76] + node _T_421 = not(_T_420) @[el2_dec_tlu_ctl.scala 1875:56] + node _T_422 = and(_T_419, _T_421) @[el2_dec_tlu_ctl.scala 1875:54] + node _T_423 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:24] + node _T_424 = bits(io.dec_csr_wrdata_r, 10, 10) @[el2_dec_tlu_ctl.scala 1876:49] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 1876:76] + node _T_426 = not(_T_425) @[el2_dec_tlu_ctl.scala 1876:56] + node _T_427 = and(_T_424, _T_426) @[el2_dec_tlu_ctl.scala 1876:54] + node _T_428 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:24] + node _T_429 = bits(io.dec_csr_wrdata_r, 8, 8) @[el2_dec_tlu_ctl.scala 1877:49] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[el2_dec_tlu_ctl.scala 1877:76] + node _T_431 = not(_T_430) @[el2_dec_tlu_ctl.scala 1877:56] + node _T_432 = and(_T_429, _T_431) @[el2_dec_tlu_ctl.scala 1877:53] + node _T_433 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:24] + node _T_434 = bits(io.dec_csr_wrdata_r, 6, 6) @[el2_dec_tlu_ctl.scala 1878:49] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[el2_dec_tlu_ctl.scala 1878:76] + node _T_436 = not(_T_435) @[el2_dec_tlu_ctl.scala 1878:56] + node _T_437 = and(_T_434, _T_436) @[el2_dec_tlu_ctl.scala 1878:53] + node _T_438 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:24] + node _T_439 = bits(io.dec_csr_wrdata_r, 4, 4) @[el2_dec_tlu_ctl.scala 1879:49] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[el2_dec_tlu_ctl.scala 1879:76] + node _T_441 = not(_T_440) @[el2_dec_tlu_ctl.scala 1879:56] + node _T_442 = and(_T_439, _T_441) @[el2_dec_tlu_ctl.scala 1879:53] + node _T_443 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:24] + node _T_444 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 1880:49] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[el2_dec_tlu_ctl.scala 1880:76] + node _T_446 = not(_T_445) @[el2_dec_tlu_ctl.scala 1880:56] + node _T_447 = and(_T_444, _T_446) @[el2_dec_tlu_ctl.scala 1880:53] + node _T_448 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:24] + node _T_449 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1881:49] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1881:76] + node _T_451 = not(_T_450) @[el2_dec_tlu_ctl.scala 1881:56] + node _T_452 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 1881:53] + node _T_453 = cat(_T_448, _T_452) @[Cat.scala 29:58] + node _T_454 = cat(_T_443, _T_447) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_453) @[Cat.scala 29:58] + node _T_456 = cat(_T_438, _T_442) @[Cat.scala 29:58] + node _T_457 = cat(_T_433, _T_437) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_456) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_455) @[Cat.scala 29:58] + node _T_460 = cat(_T_428, _T_432) @[Cat.scala 29:58] + node _T_461 = cat(_T_423, _T_427) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_418, _T_422) @[Cat.scala 29:58] + node _T_464 = cat(_T_413, _T_417) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_459) @[Cat.scala 29:58] + node _T_468 = cat(_T_408, _T_412) @[Cat.scala 29:58] + node _T_469 = cat(_T_403, _T_407) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_468) @[Cat.scala 29:58] + node _T_471 = cat(_T_398, _T_402) @[Cat.scala 29:58] + node _T_472 = cat(_T_393, _T_397) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_471) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_470) @[Cat.scala 29:58] + node _T_475 = cat(_T_388, _T_392) @[Cat.scala 29:58] + node _T_476 = cat(_T_383, _T_387) @[Cat.scala 29:58] + node _T_477 = cat(_T_476, _T_475) @[Cat.scala 29:58] + node _T_478 = cat(_T_378, _T_382) @[Cat.scala 29:58] + node _T_479 = cat(_T_373, _T_377) @[Cat.scala 29:58] + node _T_480 = cat(_T_479, _T_478) @[Cat.scala 29:58] + node _T_481 = cat(_T_480, _T_477) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_474) @[Cat.scala 29:58] + node mrac_in = cat(_T_482, _T_467) @[Cat.scala 29:58] + node _T_483 = bits(wr_mrac_r, 0, 0) @[el2_dec_tlu_ctl.scala 1884:39] + inst rvclkhdr_10 of rvclkhdr_18 @[el2_lib.scala 485:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_10.io.en <= _T_483 @[el2_lib.scala 488:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mrac <= mrac_in @[el2_lib.scala 491:16] + io.dec_tlu_mrac_ff <= mrac @[el2_dec_tlu_ctl.scala 1886:22] + node _T_484 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1894:63] + node _T_485 = eq(_T_484, UInt<12>("h0bc0")) @[el2_dec_tlu_ctl.scala 1894:70] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_485) @[el2_dec_tlu_ctl.scala 1894:41] + node _T_486 = not(wr_mdeau_r) @[el2_dec_tlu_ctl.scala 1904:60] + node _T_487 = and(io.mdseac_locked_f, _T_486) @[el2_dec_tlu_ctl.scala 1904:58] + node _T_488 = or(mdseac_en, _T_487) @[el2_dec_tlu_ctl.scala 1904:36] + io.mdseac_locked_ns <= _T_488 @[el2_dec_tlu_ctl.scala 1904:23] + node _T_489 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 1906:50] + node _T_490 = not(io.nmi_int_detected_f) @[el2_dec_tlu_ctl.scala 1906:87] + node _T_491 = and(_T_489, _T_490) @[el2_dec_tlu_ctl.scala 1906:85] + node _T_492 = not(io.mdseac_locked_f) @[el2_dec_tlu_ctl.scala 1906:112] + node _T_493 = and(_T_491, _T_492) @[el2_dec_tlu_ctl.scala 1906:110] + mdseac_en <= _T_493 @[el2_dec_tlu_ctl.scala 1906:13] + node _T_494 = bits(mdseac_en, 0, 0) @[el2_dec_tlu_ctl.scala 1908:65] + inst rvclkhdr_11 of rvclkhdr_19 @[el2_lib.scala 485:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_11.io.en <= _T_494 @[el2_lib.scala 488:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + mdseac <= io.lsu_imprecise_error_addr_any @[el2_lib.scala 491:16] + node _T_495 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1917:62] + node _T_496 = eq(_T_495, UInt<12>("h07c6")) @[el2_dec_tlu_ctl.scala 1917:69] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_496) @[el2_dec_tlu_ctl.scala 1917:40] + node _T_497 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 1921:52] + node _T_498 = and(wr_mpmc_r, _T_497) @[el2_dec_tlu_ctl.scala 1921:31] + node _T_499 = not(io.internal_dbg_halt_mode_f2) @[el2_dec_tlu_ctl.scala 1921:58] + node _T_500 = and(_T_498, _T_499) @[el2_dec_tlu_ctl.scala 1921:56] + node _T_501 = not(io.ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 1921:90] + node _T_502 = and(_T_500, _T_501) @[el2_dec_tlu_ctl.scala 1921:88] + io.fw_halt_req <= _T_502 @[el2_dec_tlu_ctl.scala 1921:18] + node _T_503 = or(io.fw_halt_req, fw_halted) @[el2_dec_tlu_ctl.scala 1923:38] + node _T_504 = not(set_mie_pmu_fw_halt) @[el2_dec_tlu_ctl.scala 1923:53] + node fw_halted_ns = and(_T_503, _T_504) @[el2_dec_tlu_ctl.scala 1923:51] + node _T_505 = bits(wr_mpmc_r, 0, 0) @[el2_dec_tlu_ctl.scala 1924:30] + node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 1924:58] + node _T_507 = not(_T_506) @[el2_dec_tlu_ctl.scala 1924:38] + node _T_508 = not(mpmc) @[el2_dec_tlu_ctl.scala 1924:63] + node _T_509 = mux(_T_505, _T_507, _T_508) @[el2_dec_tlu_ctl.scala 1924:19] + mpmc_b_ns <= _T_509 @[el2_dec_tlu_ctl.scala 1924:13] + reg _T_510 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1926:45] + _T_510 <= mpmc_b_ns @[el2_dec_tlu_ctl.scala 1926:45] + mpmc_b <= _T_510 @[el2_dec_tlu_ctl.scala 1926:10] + reg _T_511 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1927:46] + _T_511 <= fw_halted_ns @[el2_dec_tlu_ctl.scala 1927:46] + fw_halted <= _T_511 @[el2_dec_tlu_ctl.scala 1927:13] + node _T_512 = not(mpmc_b) @[el2_dec_tlu_ctl.scala 1929:11] + mpmc <= _T_512 @[el2_dec_tlu_ctl.scala 1929:8] + node _T_513 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:41] + node _T_514 = gt(_T_513, UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 1938:49] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[el2_dec_tlu_ctl.scala 1938:93] + node csr_sat = mux(_T_514, UInt<5>("h01a"), _T_515) @[el2_dec_tlu_ctl.scala 1938:20] + node _T_516 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1940:64] + node _T_517 = eq(_T_516, UInt<12>("h07f0")) @[el2_dec_tlu_ctl.scala 1940:71] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_517) @[el2_dec_tlu_ctl.scala 1940:42] + node _T_518 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_519 = add(micect, _T_518) @[el2_dec_tlu_ctl.scala 1941:24] + node _T_520 = tail(_T_519, 1) @[el2_dec_tlu_ctl.scala 1941:24] + micect_inc <= _T_520 @[el2_dec_tlu_ctl.scala 1941:14] + node _T_521 = bits(wr_micect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1942:36] + node _T_522 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1942:76] + node _T_523 = cat(csr_sat, _T_522) @[Cat.scala 29:58] + node _T_524 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1942:96] + node _T_525 = cat(_T_524, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_521, _T_523, _T_525) @[el2_dec_tlu_ctl.scala 1942:23] + node _T_526 = or(wr_micect_r, io.ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 1944:43] + node _T_527 = bits(_T_526, 0, 0) @[el2_dec_tlu_ctl.scala 1944:62] + inst rvclkhdr_12 of rvclkhdr_20 @[el2_lib.scala 485:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_12.io.en <= _T_527 @[el2_lib.scala 488:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_528 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_528 <= micect_ns @[el2_lib.scala 491:16] + micect <= _T_528 @[el2_dec_tlu_ctl.scala 1944:10] + node _T_529 = bits(micect, 31, 27) @[el2_dec_tlu_ctl.scala 1946:48] + node _T_530 = dshl(UInt<32>("h0ffffffff"), _T_529) @[el2_dec_tlu_ctl.scala 1946:39] + node _T_531 = orr(_T_530) @[el2_dec_tlu_ctl.scala 1946:57] + node _T_532 = bits(micect, 26, 0) @[el2_dec_tlu_ctl.scala 1946:83] + node _T_533 = cat(UInt<5>("h00"), _T_532) @[Cat.scala 29:58] + node _T_534 = and(_T_531, _T_533) @[el2_dec_tlu_ctl.scala 1946:61] + mice_ce_req <= _T_534 @[el2_dec_tlu_ctl.scala 1946:15] + node _T_535 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1955:70] + node _T_536 = eq(_T_535, UInt<12>("h07f1")) @[el2_dec_tlu_ctl.scala 1955:77] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_536) @[el2_dec_tlu_ctl.scala 1955:48] + node _T_537 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1956:27] + node _T_538 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1956:71] + node _T_539 = cat(UInt<26>("h00"), _T_538) @[Cat.scala 29:58] + node _T_540 = add(_T_537, _T_539) @[el2_dec_tlu_ctl.scala 1956:34] + node _T_541 = tail(_T_540, 1) @[el2_dec_tlu_ctl.scala 1956:34] + miccmect_inc <= _T_541 @[el2_dec_tlu_ctl.scala 1956:16] + node _T_542 = bits(wr_miccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1957:46] + node _T_543 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1957:86] + node _T_544 = cat(csr_sat, _T_543) @[Cat.scala 29:58] + node _T_545 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1957:108] + node _T_546 = cat(_T_545, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_542, _T_544, _T_546) @[el2_dec_tlu_ctl.scala 1957:31] + node _T_547 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 1959:49] + node _T_548 = or(_T_547, io.iccm_dma_sb_error) @[el2_dec_tlu_ctl.scala 1959:70] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 1959:94] + inst rvclkhdr_13 of rvclkhdr_21 @[el2_lib.scala 485:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_13.io.en <= _T_549 @[el2_lib.scala 488:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_550 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_550 <= miccmect_ns @[el2_lib.scala 491:16] + miccmect <= _T_550 @[el2_dec_tlu_ctl.scala 1959:12] + node _T_551 = bits(miccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1960:53] + node _T_552 = dshl(UInt<32>("h0ffffffff"), _T_551) @[el2_dec_tlu_ctl.scala 1960:42] + node _T_553 = bits(miccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1960:86] + node _T_554 = cat(UInt<5>("h00"), _T_553) @[Cat.scala 29:58] + node _T_555 = and(_T_552, _T_554) @[el2_dec_tlu_ctl.scala 1960:62] + node _T_556 = orr(_T_555) @[el2_dec_tlu_ctl.scala 1960:95] + miccme_ce_req <= _T_556 @[el2_dec_tlu_ctl.scala 1960:17] + node _T_557 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1969:70] + node _T_558 = eq(_T_557, UInt<12>("h07f2")) @[el2_dec_tlu_ctl.scala 1969:77] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_558) @[el2_dec_tlu_ctl.scala 1969:48] + node _T_559 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1970:27] + node _T_560 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_561 = add(_T_559, _T_560) @[el2_dec_tlu_ctl.scala 1970:34] + node _T_562 = tail(_T_561, 1) @[el2_dec_tlu_ctl.scala 1970:34] + mdccmect_inc <= _T_562 @[el2_dec_tlu_ctl.scala 1970:16] + node _T_563 = bits(wr_mdccmect_r, 0, 0) @[el2_dec_tlu_ctl.scala 1971:46] + node _T_564 = bits(io.dec_csr_wrdata_r, 26, 0) @[el2_dec_tlu_ctl.scala 1971:86] + node _T_565 = cat(csr_sat, _T_564) @[Cat.scala 29:58] + node _T_566 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1971:108] + node _T_567 = cat(_T_566, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_563, _T_565, _T_567) @[el2_dec_tlu_ctl.scala 1971:31] + node _T_568 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[el2_dec_tlu_ctl.scala 1973:50] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 1973:82] + inst rvclkhdr_14 of rvclkhdr_22 @[el2_lib.scala 485:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_14.io.en <= _T_569 @[el2_lib.scala 488:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_570 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_570 <= mdccmect_ns @[el2_lib.scala 491:16] + mdccmect <= _T_570 @[el2_dec_tlu_ctl.scala 1973:12] + node _T_571 = bits(mdccmect, 31, 27) @[el2_dec_tlu_ctl.scala 1975:53] + node _T_572 = dshl(UInt<32>("h0ffffffff"), _T_571) @[el2_dec_tlu_ctl.scala 1975:42] + node _T_573 = bits(mdccmect, 26, 0) @[el2_dec_tlu_ctl.scala 1975:86] + node _T_574 = cat(UInt<5>("h00"), _T_573) @[Cat.scala 29:58] + node _T_575 = and(_T_572, _T_574) @[el2_dec_tlu_ctl.scala 1975:62] + node _T_576 = orr(_T_575) @[el2_dec_tlu_ctl.scala 1975:95] + mdccme_ce_req <= _T_576 @[el2_dec_tlu_ctl.scala 1975:17] + node _T_577 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1985:63] + node _T_578 = eq(_T_577, UInt<12>("h07ce")) @[el2_dec_tlu_ctl.scala 1985:70] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_578) @[el2_dec_tlu_ctl.scala 1985:41] + node _T_579 = bits(wr_mfdht_r, 0, 0) @[el2_dec_tlu_ctl.scala 1987:33] + node _T_580 = bits(io.dec_csr_wrdata_r, 5, 0) @[el2_dec_tlu_ctl.scala 1987:60] + node mfdht_ns = mux(_T_579, _T_580, mfdht) @[el2_dec_tlu_ctl.scala 1987:21] + reg _T_581 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 1989:44] + _T_581 <= mfdht_ns @[el2_dec_tlu_ctl.scala 1989:44] + mfdht <= _T_581 @[el2_dec_tlu_ctl.scala 1989:9] + node _T_582 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 1998:63] + node _T_583 = eq(_T_582, UInt<12>("h07cf")) @[el2_dec_tlu_ctl.scala 1998:70] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_583) @[el2_dec_tlu_ctl.scala 1998:41] + node _T_584 = bits(wr_mfdhs_r, 0, 0) @[el2_dec_tlu_ctl.scala 2000:33] + node _T_585 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2000:61] + node _T_586 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2001:30] + node _T_587 = and(io.dbg_tlu_halted, _T_586) @[el2_dec_tlu_ctl.scala 2001:28] + node _T_588 = bits(_T_587, 0, 0) @[el2_dec_tlu_ctl.scala 2001:52] + node _T_589 = not(io.lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 2001:65] + node _T_590 = not(io.ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 2001:85] + node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] + node _T_592 = mux(_T_588, _T_591, mfdhs) @[el2_dec_tlu_ctl.scala 2001:8] + node mfdhs_ns = mux(_T_584, _T_585, _T_592) @[el2_dec_tlu_ctl.scala 2000:21] + node _T_593 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2003:72] + node _T_594 = bits(_T_593, 0, 0) @[el2_dec_tlu_ctl.scala 2003:93] + reg _T_595 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_594 : @[Reg.scala 28:19] + _T_595 <= mfdhs_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdhs <= _T_595 @[el2_dec_tlu_ctl.scala 2003:9] + node _T_596 = bits(io.debug_halt_req_f, 0, 0) @[el2_dec_tlu_ctl.scala 2005:48] + node _T_597 = add(force_halt_ctr_f, UInt<32>("h01")) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_598 = tail(_T_597, 1) @[el2_dec_tlu_ctl.scala 2005:75] + node _T_599 = bits(io.dbg_tlu_halted_f, 0, 0) @[el2_dec_tlu_ctl.scala 2006:29] + node _T_600 = mux(_T_599, UInt<32>("h00"), force_halt_ctr_f) @[el2_dec_tlu_ctl.scala 2006:8] + node force_halt_ctr = mux(_T_596, _T_598, _T_600) @[el2_dec_tlu_ctl.scala 2005:27] + node _T_601 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2008:82] + reg _T_602 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_601 : @[Reg.scala 28:19] + _T_602 <= force_halt_ctr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + force_halt_ctr_f <= _T_602 @[el2_dec_tlu_ctl.scala 2008:20] + node _T_603 = bits(mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2010:25] + node _T_604 = bits(mfdht, 5, 1) @[el2_dec_tlu_ctl.scala 2010:80] + node _T_605 = dshl(UInt<32>("h0ffffffff"), _T_604) @[el2_dec_tlu_ctl.scala 2010:72] + node _T_606 = and(force_halt_ctr_f, _T_605) @[el2_dec_tlu_ctl.scala 2010:49] + node _T_607 = orr(_T_606) @[el2_dec_tlu_ctl.scala 2010:88] + node _T_608 = and(_T_603, _T_607) @[el2_dec_tlu_ctl.scala 2010:29] + io.force_halt <= _T_608 @[el2_dec_tlu_ctl.scala 2010:17] + node _T_609 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2018:63] + node _T_610 = eq(_T_609, UInt<12>("h0bc8")) @[el2_dec_tlu_ctl.scala 2018:70] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_610) @[el2_dec_tlu_ctl.scala 2018:41] + node _T_611 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2020:41] + node _T_612 = bits(wr_meivt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2020:60] + inst rvclkhdr_15 of rvclkhdr_23 @[el2_lib.scala 485:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_15.io.en <= _T_612 @[el2_lib.scala 488:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + meivt <= _T_611 @[el2_lib.scala 491:16] + node _T_613 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2032:50] + inst rvclkhdr_16 of rvclkhdr_24 @[el2_lib.scala 485:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_16.io.en <= _T_613 @[el2_lib.scala 488:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + meihap <= io.pic_claimid @[el2_lib.scala 491:16] + node _T_614 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, UInt<2>("h00")) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_615 @[el2_dec_tlu_ctl.scala 2033:21] + node _T_616 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2042:66] + node _T_617 = eq(_T_616, UInt<12>("h0bcc")) @[el2_dec_tlu_ctl.scala 2042:73] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_617) @[el2_dec_tlu_ctl.scala 2042:44] + node _T_618 = bits(wr_meicurpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2043:39] + node _T_619 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2043:66] + node meicurpl_ns = mux(_T_618, _T_619, meicurpl) @[el2_dec_tlu_ctl.scala 2043:24] + reg _T_620 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2045:47] + _T_620 <= meicurpl_ns @[el2_dec_tlu_ctl.scala 2045:47] + meicurpl <= _T_620 @[el2_dec_tlu_ctl.scala 2045:12] + io.dec_tlu_meicurpl <= meicurpl @[el2_dec_tlu_ctl.scala 2047:23] + node _T_621 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2057:67] + node _T_622 = eq(_T_621, UInt<12>("h0bcb")) @[el2_dec_tlu_ctl.scala 2057:74] + node _T_623 = and(io.dec_csr_wen_r_mod, _T_622) @[el2_dec_tlu_ctl.scala 2057:45] + node wr_meicidpl_r = or(_T_623, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2057:89] + node _T_624 = bits(wr_meicpct_r, 0, 0) @[el2_dec_tlu_ctl.scala 2059:38] + node _T_625 = bits(wr_meicidpl_r, 0, 0) @[el2_dec_tlu_ctl.scala 2060:23] + node _T_626 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2060:50] + node _T_627 = mux(_T_625, _T_626, meicidpl) @[el2_dec_tlu_ctl.scala 2060:8] + node meicidpl_ns = mux(_T_624, io.pic_pl, _T_627) @[el2_dec_tlu_ctl.scala 2059:24] + reg _T_628 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2062:45] + _T_628 <= meicidpl_ns @[el2_dec_tlu_ctl.scala 2062:45] + meicidpl <= _T_628 @[el2_dec_tlu_ctl.scala 2062:12] + node _T_629 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2069:63] + node _T_630 = eq(_T_629, UInt<12>("h0bca")) @[el2_dec_tlu_ctl.scala 2069:70] + node _T_631 = and(io.dec_csr_wen_r_mod, _T_630) @[el2_dec_tlu_ctl.scala 2069:41] + node _T_632 = or(_T_631, io.take_ext_int_start) @[el2_dec_tlu_ctl.scala 2069:84] + wr_meicpct_r <= _T_632 @[el2_dec_tlu_ctl.scala 2069:16] + node _T_633 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2078:63] + node _T_634 = eq(_T_633, UInt<12>("h0bc9")) @[el2_dec_tlu_ctl.scala 2078:70] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_634) @[el2_dec_tlu_ctl.scala 2078:41] + node _T_635 = bits(wr_meipt_r, 0, 0) @[el2_dec_tlu_ctl.scala 2079:33] + node _T_636 = bits(io.dec_csr_wrdata_r, 3, 0) @[el2_dec_tlu_ctl.scala 2079:60] + node meipt_ns = mux(_T_635, _T_636, meipt) @[el2_dec_tlu_ctl.scala 2079:21] + reg _T_637 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2081:44] + _T_637 <= meipt_ns @[el2_dec_tlu_ctl.scala 2081:44] + meipt <= _T_637 @[el2_dec_tlu_ctl.scala 2081:9] + io.dec_tlu_meipt <= meipt @[el2_dec_tlu_ctl.scala 2083:20] + node _T_638 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 2109:90] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_638) @[el2_dec_tlu_ctl.scala 2109:67] + node _T_639 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2112:35] + node _T_640 = and(io.dcsr_single_step_done_f, _T_639) @[el2_dec_tlu_ctl.scala 2112:33] + node _T_641 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2112:67] + node _T_642 = and(_T_640, _T_641) @[el2_dec_tlu_ctl.scala 2112:65] + node _T_643 = not(io.debug_halt_req) @[el2_dec_tlu_ctl.scala 2112:102] + node _T_644 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2112:100] + node _T_645 = bits(_T_644, 0, 0) @[el2_dec_tlu_ctl.scala 2112:122] + node _T_646 = not(io.ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 2113:26] + node _T_647 = and(io.debug_halt_req, _T_646) @[el2_dec_tlu_ctl.scala 2113:24] + node _T_648 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2113:58] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 2113:56] + node _T_650 = bits(_T_649, 0, 0) @[el2_dec_tlu_ctl.scala 2113:92] + node _T_651 = not(trigger_hit_for_dscr_cause_r_d1) @[el2_dec_tlu_ctl.scala 2114:37] + node _T_652 = and(io.ebreak_to_debug_mode_r_d1, _T_651) @[el2_dec_tlu_ctl.scala 2114:35] + node _T_653 = bits(_T_652, 0, 0) @[el2_dec_tlu_ctl.scala 2114:71] + node _T_654 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[el2_dec_tlu_ctl.scala 2115:39] + node _T_655 = mux(_T_645, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_656 = mux(_T_650, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_653, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = or(_T_655, _T_656) @[Mux.scala 27:72] + node _T_660 = or(_T_659, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + wire dcsr_cause : UInt<3> @[Mux.scala 27:72] + dcsr_cause <= _T_661 @[Mux.scala 27:72] + node _T_662 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2117:47] + node _T_663 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2117:92] + node _T_664 = eq(_T_663, UInt<12>("h07b0")) @[el2_dec_tlu_ctl.scala 2117:99] + node wr_dcsr_r = and(_T_662, _T_664) @[el2_dec_tlu_ctl.scala 2117:70] + node _T_665 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2123:70] + node _T_666 = eq(_T_665, UInt<3>("h03")) @[el2_dec_tlu_ctl.scala 2123:76] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_666) @[el2_dec_tlu_ctl.scala 2123:60] + node _T_667 = not(io.dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 2124:60] + node _T_668 = or(_T_667, dcsr_cause_upgradeable) @[el2_dec_tlu_ctl.scala 2124:79] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_668) @[el2_dec_tlu_ctl.scala 2124:57] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[el2_dec_tlu_ctl.scala 2126:49] + node _T_669 = bits(enter_debug_halt_req_le, 0, 0) @[el2_dec_tlu_ctl.scala 2127:45] + node _T_670 = bits(io.dcsr, 15, 9) @[el2_dec_tlu_ctl.scala 2127:65] + node _T_671 = bits(io.dcsr, 5, 2) @[el2_dec_tlu_ctl.scala 2127:92] + node _T_672 = cat(_T_671, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_673 = cat(_T_670, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_672) @[Cat.scala 29:58] + node _T_675 = bits(wr_dcsr_r, 0, 0) @[el2_dec_tlu_ctl.scala 2128:19] + node _T_676 = bits(io.dec_csr_wrdata_r, 15, 15) @[el2_dec_tlu_ctl.scala 2128:50] + node _T_677 = bits(io.dec_csr_wrdata_r, 11, 10) @[el2_dec_tlu_ctl.scala 2128:85] + node _T_678 = bits(io.dcsr, 8, 6) @[el2_dec_tlu_ctl.scala 2128:111] + node _T_679 = bits(io.dcsr, 3, 3) @[el2_dec_tlu_ctl.scala 2128:155] + node _T_680 = or(nmi_in_debug_mode, _T_679) @[el2_dec_tlu_ctl.scala 2128:146] + node _T_681 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2128:179] + node _T_682 = cat(_T_681, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_683 = cat(UInt<2>("h00"), _T_680) @[Cat.scala 29:58] + node _T_684 = cat(_T_683, _T_682) @[Cat.scala 29:58] + node _T_685 = cat(UInt<1>("h00"), _T_678) @[Cat.scala 29:58] + node _T_686 = cat(_T_676, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_677) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_685) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_684) @[Cat.scala 29:58] + node _T_690 = bits(io.dcsr, 15, 4) @[el2_dec_tlu_ctl.scala 2128:212] + node _T_691 = bits(io.dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 2128:246] + node _T_692 = cat(_T_691, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_693 = cat(_T_690, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58] + node _T_695 = mux(_T_675, _T_689, _T_694) @[el2_dec_tlu_ctl.scala 2128:8] + node dcsr_ns = mux(_T_669, _T_674, _T_695) @[el2_dec_tlu_ctl.scala 2127:20] + node _T_696 = or(enter_debug_halt_req_le, wr_dcsr_r) @[el2_dec_tlu_ctl.scala 2130:55] + node _T_697 = or(_T_696, io.internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 2130:67] + node _T_698 = or(_T_697, io.take_nmi) @[el2_dec_tlu_ctl.scala 2130:95] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_tlu_ctl.scala 2130:110] + inst rvclkhdr_17 of rvclkhdr_25 @[el2_lib.scala 485:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_17.io.en <= _T_699 @[el2_lib.scala 488:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_700 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_700 <= dcsr_ns @[el2_lib.scala 491:16] + io.dcsr <= _T_700 @[el2_dec_tlu_ctl.scala 2130:11] + node _T_701 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2138:46] + node _T_702 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2138:91] + node _T_703 = eq(_T_702, UInt<12>("h07b1")) @[el2_dec_tlu_ctl.scala 2138:98] + node wr_dpc_r = and(_T_701, _T_703) @[el2_dec_tlu_ctl.scala 2138:69] + node _T_704 = not(io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2139:45] + node _T_705 = and(io.dbg_tlu_halted, _T_704) @[el2_dec_tlu_ctl.scala 2139:43] + node _T_706 = not(io.request_debug_mode_done) @[el2_dec_tlu_ctl.scala 2139:68] + node dpc_capture_npc = and(_T_705, _T_706) @[el2_dec_tlu_ctl.scala 2139:66] + node _T_707 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2143:6] + node _T_708 = not(dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2143:24] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 2143:22] + node _T_710 = and(_T_709, wr_dpc_r) @[el2_dec_tlu_ctl.scala 2143:41] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_tlu_ctl.scala 2143:53] + node _T_712 = bits(io.dec_csr_wrdata_r, 31, 1) @[el2_dec_tlu_ctl.scala 2143:82] + node _T_713 = bits(io.request_debug_mode_r, 0, 0) @[el2_dec_tlu_ctl.scala 2144:22] + node _T_714 = not(io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2145:6] + node _T_715 = and(_T_714, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2145:22] + node _T_716 = bits(_T_715, 0, 0) @[el2_dec_tlu_ctl.scala 2145:41] + node _T_717 = mux(_T_711, _T_712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_718 = mux(_T_713, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_716, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = or(_T_717, _T_718) @[Mux.scala 27:72] + node _T_721 = or(_T_720, _T_719) @[Mux.scala 27:72] + wire dpc_ns : UInt<31> @[Mux.scala 27:72] + dpc_ns <= _T_721 @[Mux.scala 27:72] + node _T_722 = or(wr_dpc_r, io.request_debug_mode_r) @[el2_dec_tlu_ctl.scala 2147:37] + node _T_723 = or(_T_722, dpc_capture_npc) @[el2_dec_tlu_ctl.scala 2147:54] + node _T_724 = bits(_T_723, 0, 0) @[el2_dec_tlu_ctl.scala 2147:73] + inst rvclkhdr_18 of rvclkhdr_26 @[el2_lib.scala 485:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_18.io.en <= _T_724 @[el2_lib.scala 488:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_725 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_725 <= dpc_ns @[el2_lib.scala 491:16] + io.dpc <= _T_725 @[el2_dec_tlu_ctl.scala 2147:10] + node _T_726 = bits(io.dec_csr_wrdata_r, 24, 24) @[el2_dec_tlu_ctl.scala 2161:44] + node _T_727 = bits(io.dec_csr_wrdata_r, 21, 20) @[el2_dec_tlu_ctl.scala 2161:69] + node _T_728 = bits(io.dec_csr_wrdata_r, 16, 3) @[el2_dec_tlu_ctl.scala 2161:97] + node _T_729 = cat(_T_726, _T_727) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_729, _T_728) @[Cat.scala 29:58] + node _T_730 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2162:51] + node _T_731 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2162:96] + node _T_732 = eq(_T_731, UInt<12>("h07c8")) @[el2_dec_tlu_ctl.scala 2162:103] + node wr_dicawics_r = and(_T_730, _T_732) @[el2_dec_tlu_ctl.scala 2162:74] + node _T_733 = bits(wr_dicawics_r, 0, 0) @[el2_dec_tlu_ctl.scala 2164:51] + inst rvclkhdr_19 of rvclkhdr_27 @[el2_lib.scala 485:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_19.io.en <= _T_733 @[el2_lib.scala 488:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicawics <= dicawics_ns @[el2_lib.scala 491:16] + node _T_734 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2180:49] + node _T_735 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2180:94] + node _T_736 = eq(_T_735, UInt<12>("h07c9")) @[el2_dec_tlu_ctl.scala 2180:101] + node wr_dicad0_r = and(_T_734, _T_736) @[el2_dec_tlu_ctl.scala 2180:72] + node _T_737 = bits(wr_dicad0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2181:35] + node dicad0_ns = mux(_T_737, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[el2_dec_tlu_ctl.scala 2181:22] + node _T_738 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2183:47] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_tlu_ctl.scala 2183:80] + inst rvclkhdr_20 of rvclkhdr_28 @[el2_lib.scala 485:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_20.io.en <= _T_739 @[el2_lib.scala 488:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicad0 <= dicad0_ns @[el2_lib.scala 491:16] + node _T_740 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2193:50] + node _T_741 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2193:95] + node _T_742 = eq(_T_741, UInt<12>("h07cc")) @[el2_dec_tlu_ctl.scala 2193:102] + node wr_dicad0h_r = and(_T_740, _T_742) @[el2_dec_tlu_ctl.scala 2193:73] + node _T_743 = bits(wr_dicad0h_r, 0, 0) @[el2_dec_tlu_ctl.scala 2195:37] + node _T_744 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[el2_dec_tlu_ctl.scala 2195:89] + node dicad0h_ns = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[el2_dec_tlu_ctl.scala 2195:23] + node _T_745 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2197:49] + node _T_746 = bits(_T_745, 0, 0) @[el2_dec_tlu_ctl.scala 2197:82] + inst rvclkhdr_21 of rvclkhdr_29 @[el2_lib.scala 485:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_21.io.en <= _T_746 @[el2_lib.scala 488:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + dicad0h <= dicad0h_ns @[el2_lib.scala 491:16] + wire _T_747 : UInt<7> + _T_747 <= UInt<1>("h00") + node _T_748 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2205:51] + node _T_749 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2205:96] + node _T_750 = eq(_T_749, UInt<12>("h07ca")) @[el2_dec_tlu_ctl.scala 2205:103] + node _T_751 = and(_T_748, _T_750) @[el2_dec_tlu_ctl.scala 2205:74] + node _T_752 = bits(_T_751, 0, 0) @[el2_dec_tlu_ctl.scala 2207:37] + node _T_753 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[el2_dec_tlu_ctl.scala 2207:89] + node _T_754 = mux(_T_752, io.dec_csr_wrdata_r, _T_753) @[el2_dec_tlu_ctl.scala 2207:24] + node _T_755 = or(_T_751, io.ifu_ic_debug_rd_data_valid) @[el2_dec_tlu_ctl.scala 2209:81] + node _T_756 = bits(_T_755, 0, 0) @[el2_dec_tlu_ctl.scala 2209:114] + reg _T_757 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_756 : @[Reg.scala 28:19] + _T_757 <= _T_754 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_747 <= _T_757 @[el2_dec_tlu_ctl.scala 2209:16] + node _T_758 = cat(UInt<25>("h00"), _T_747) @[Cat.scala 29:58] + dicad1 <= _T_758 @[el2_dec_tlu_ctl.scala 2210:12] + node _T_759 = bits(dicad1, 6, 0) @[el2_dec_tlu_ctl.scala 2232:78] + node _T_760 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2232:92] + node _T_761 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2232:106] + node _T_762 = cat(_T_759, _T_760) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_761) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_763 @[el2_dec_tlu_ctl.scala 2232:65] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[el2_dec_tlu_ctl.scala 2235:42] + node _T_764 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 2237:53] + node _T_765 = and(_T_764, io.dec_i0_decode_d) @[el2_dec_tlu_ctl.scala 2237:76] + node _T_766 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 2237:99] + node _T_767 = and(_T_765, _T_766) @[el2_dec_tlu_ctl.scala 2237:97] + node _T_768 = bits(io.dec_csr_rdaddr_d, 11, 0) @[el2_dec_tlu_ctl.scala 2237:143] + node _T_769 = eq(_T_768, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2237:150] + node icache_rd_valid = and(_T_767, _T_769) @[el2_dec_tlu_ctl.scala 2237:121] + node _T_770 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[el2_dec_tlu_ctl.scala 2238:53] + node _T_771 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2238:98] + node _T_772 = eq(_T_771, UInt<12>("h07cb")) @[el2_dec_tlu_ctl.scala 2238:105] + node icache_wr_valid = and(_T_770, _T_772) @[el2_dec_tlu_ctl.scala 2238:76] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2240:59] + icache_rd_valid_f <= icache_rd_valid @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2241:59] + icache_wr_valid_f <= icache_wr_valid @[el2_dec_tlu_ctl.scala 2241:59] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[el2_dec_tlu_ctl.scala 2243:42] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[el2_dec_tlu_ctl.scala 2244:42] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2252:63] + node _T_774 = eq(_T_773, UInt<12>("h07a0")) @[el2_dec_tlu_ctl.scala 2252:70] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_774) @[el2_dec_tlu_ctl.scala 2252:41] + node _T_775 = bits(wr_mtsel_r, 0, 0) @[el2_dec_tlu_ctl.scala 2253:33] + node _T_776 = bits(io.dec_csr_wrdata_r, 1, 0) @[el2_dec_tlu_ctl.scala 2253:60] + node mtsel_ns = mux(_T_775, _T_776, mtsel) @[el2_dec_tlu_ctl.scala 2253:21] + reg _T_777 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2255:44] + _T_777 <= mtsel_ns @[el2_dec_tlu_ctl.scala 2255:44] + mtsel <= _T_777 @[el2_dec_tlu_ctl.scala 2255:9] + node _T_778 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2290:39] + node _T_779 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2290:65] + node _T_780 = not(_T_779) @[el2_dec_tlu_ctl.scala 2290:45] + node tdata_load = and(_T_778, _T_780) @[el2_dec_tlu_ctl.scala 2290:43] + node _T_781 = bits(io.dec_csr_wrdata_r, 2, 2) @[el2_dec_tlu_ctl.scala 2292:41] + node _T_782 = bits(io.dec_csr_wrdata_r, 19, 19) @[el2_dec_tlu_ctl.scala 2292:67] + node _T_783 = not(_T_782) @[el2_dec_tlu_ctl.scala 2292:47] + node tdata_opcode = and(_T_781, _T_783) @[el2_dec_tlu_ctl.scala 2292:45] + node _T_784 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2294:42] + node _T_785 = and(_T_784, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2294:47] + node _T_786 = bits(io.dec_csr_wrdata_r, 12, 12) @[el2_dec_tlu_ctl.scala 2294:91] + node tdata_action = and(_T_785, _T_786) @[el2_dec_tlu_ctl.scala 2294:70] + node _T_787 = bits(io.dec_csr_wrdata_r, 27, 27) @[el2_dec_tlu_ctl.scala 2296:48] + node _T_788 = and(_T_787, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2296:53] + node _T_789 = bits(io.dec_csr_wrdata_r, 20, 19) @[el2_dec_tlu_ctl.scala 2296:95] + node _T_790 = bits(io.dec_csr_wrdata_r, 11, 11) @[el2_dec_tlu_ctl.scala 2296:137] + node _T_791 = bits(io.dec_csr_wrdata_r, 7, 6) @[el2_dec_tlu_ctl.scala 2297:24] + node _T_792 = bits(io.dec_csr_wrdata_r, 1, 1) @[el2_dec_tlu_ctl.scala 2297:64] + node _T_793 = cat(_T_792, tdata_load) @[Cat.scala 29:58] + node _T_794 = cat(_T_791, tdata_opcode) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, _T_793) @[Cat.scala 29:58] + node _T_796 = cat(tdata_action, _T_790) @[Cat.scala 29:58] + node _T_797 = cat(_T_788, _T_789) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, _T_796) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_798, _T_795) @[Cat.scala 29:58] + node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_802 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_803 = and(_T_801, _T_802) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_804 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_805 = not(_T_804) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_807 = and(_T_803, _T_806) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_811 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_813 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_814 = not(_T_813) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_816 = and(_T_812, _T_815) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_820 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_821 = and(_T_819, _T_820) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_822 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_823 = not(_T_822) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_825 = and(_T_821, _T_824) @[el2_dec_tlu_ctl.scala 2300:136] + node _T_826 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2300:93] + node _T_827 = eq(_T_826, UInt<12>("h07a1")) @[el2_dec_tlu_ctl.scala 2300:100] + node _T_828 = and(io.dec_csr_wen_r_mod, _T_827) @[el2_dec_tlu_ctl.scala 2300:71] + node _T_829 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2300:122] + node _T_830 = and(_T_828, _T_829) @[el2_dec_tlu_ctl.scala 2300:113] + node _T_831 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2300:155] + node _T_832 = not(_T_831) @[el2_dec_tlu_ctl.scala 2300:139] + node _T_833 = or(_T_832, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2300:171] + node _T_834 = and(_T_830, _T_833) @[el2_dec_tlu_ctl.scala 2300:136] + wire wr_mtdata1_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[0] <= _T_807 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[1] <= _T_816 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[2] <= _T_825 @[el2_dec_tlu_ctl.scala 2300:43] + wr_mtdata1_t_r[3] <= _T_834 @[el2_dec_tlu_ctl.scala 2300:43] + node _T_835 = bits(wr_mtdata1_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_836 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_837 = bits(io.update_hit_bit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_838 = bits(io.mtdata1_t[0], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_839 = or(_T_837, _T_838) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_840 = bits(io.mtdata1_t[0], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] + node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] + node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_844 = bits(wr_mtdata1_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_845 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_846 = bits(io.update_hit_bit_r, 1, 1) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_847 = bits(io.mtdata1_t[1], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_848 = or(_T_846, _T_847) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_849 = bits(io.mtdata1_t[1], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] + node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] + node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_853 = bits(wr_mtdata1_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_854 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_855 = bits(io.update_hit_bit_r, 2, 2) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_856 = bits(io.mtdata1_t[2], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_857 = or(_T_855, _T_856) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_858 = bits(io.mtdata1_t[2], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] + node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] + node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[el2_dec_tlu_ctl.scala 2301:50] + node _T_862 = bits(wr_mtdata1_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2301:69] + node _T_863 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2301:112] + node _T_864 = bits(io.update_hit_bit_r, 3, 3) @[el2_dec_tlu_ctl.scala 2301:136] + node _T_865 = bits(io.mtdata1_t[3], 8, 8) @[el2_dec_tlu_ctl.scala 2301:157] + node _T_866 = or(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 2301:140] + node _T_867 = bits(io.mtdata1_t[3], 7, 0) @[el2_dec_tlu_ctl.scala 2301:177] + node _T_868 = cat(_T_863, _T_866) @[Cat.scala 29:58] + node _T_869 = cat(_T_868, _T_867) @[Cat.scala 29:58] + node _T_870 = mux(_T_862, tdata_wrdata_r, _T_869) @[el2_dec_tlu_ctl.scala 2301:50] + wire mtdata1_t_ns : UInt<10>[4] @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[0] <= _T_843 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[1] <= _T_852 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[2] <= _T_861 @[el2_dec_tlu_ctl.scala 2301:41] + mtdata1_t_ns[3] <= _T_870 @[el2_dec_tlu_ctl.scala 2301:41] + reg _T_871 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_871 <= mtdata1_t_ns[0] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[0] <= _T_871 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_872 <= mtdata1_t_ns[1] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[1] <= _T_872 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_873 <= mtdata1_t_ns[2] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[2] <= _T_873 @[el2_dec_tlu_ctl.scala 2303:41] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2303:76] + _T_874 <= mtdata1_t_ns[3] @[el2_dec_tlu_ctl.scala 2303:76] + io.mtdata1_t[3] <= _T_874 @[el2_dec_tlu_ctl.scala 2303:41] + node _T_875 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_876 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_877 = bits(io.mtdata1_t[0], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_878 = bits(io.mtdata1_t[0], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_879 = bits(io.mtdata1_t[0], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_880 = bits(io.mtdata1_t[0], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_881 = cat(UInt<3>("h00"), _T_880) @[Cat.scala 29:58] + node _T_882 = cat(_T_878, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_883 = cat(_T_882, _T_879) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_881) @[Cat.scala 29:58] + node _T_885 = cat(_T_877, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_886 = cat(UInt<4>("h02"), _T_876) @[Cat.scala 29:58] + node _T_887 = cat(_T_886, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, _T_885) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_884) @[Cat.scala 29:58] + node _T_890 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_891 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_892 = bits(io.mtdata1_t[1], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_893 = bits(io.mtdata1_t[1], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_894 = bits(io.mtdata1_t[1], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_895 = bits(io.mtdata1_t[1], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_896 = cat(UInt<3>("h00"), _T_895) @[Cat.scala 29:58] + node _T_897 = cat(_T_893, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, _T_894) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_896) @[Cat.scala 29:58] + node _T_900 = cat(_T_892, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_901 = cat(UInt<4>("h02"), _T_891) @[Cat.scala 29:58] + node _T_902 = cat(_T_901, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, _T_900) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_899) @[Cat.scala 29:58] + node _T_905 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_906 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_907 = bits(io.mtdata1_t[2], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_908 = bits(io.mtdata1_t[2], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_909 = bits(io.mtdata1_t[2], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_910 = bits(io.mtdata1_t[2], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_911 = cat(UInt<3>("h00"), _T_910) @[Cat.scala 29:58] + node _T_912 = cat(_T_908, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_913 = cat(_T_912, _T_909) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_911) @[Cat.scala 29:58] + node _T_915 = cat(_T_907, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_916 = cat(UInt<4>("h02"), _T_906) @[Cat.scala 29:58] + node _T_917 = cat(_T_916, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, _T_915) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_914) @[Cat.scala 29:58] + node _T_920 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2306:60] + node _T_921 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2306:106] + node _T_922 = bits(io.mtdata1_t[3], 8, 7) @[el2_dec_tlu_ctl.scala 2306:144] + node _T_923 = bits(io.mtdata1_t[3], 6, 5) @[el2_dec_tlu_ctl.scala 2306:176] + node _T_924 = bits(io.mtdata1_t[3], 4, 3) @[el2_dec_tlu_ctl.scala 2306:208] + node _T_925 = bits(io.mtdata1_t[3], 2, 0) @[el2_dec_tlu_ctl.scala 2306:240] + node _T_926 = cat(UInt<3>("h00"), _T_925) @[Cat.scala 29:58] + node _T_927 = cat(_T_923, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_928 = cat(_T_927, _T_924) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_926) @[Cat.scala 29:58] + node _T_930 = cat(_T_922, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_931 = cat(UInt<4>("h02"), _T_921) @[Cat.scala 29:58] + node _T_932 = cat(_T_931, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_930) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_929) @[Cat.scala 29:58] + node _T_935 = mux(_T_875, _T_889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_936 = mux(_T_890, _T_904, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_905, _T_919, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_920, _T_934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = or(_T_935, _T_936) @[Mux.scala 27:72] + node _T_940 = or(_T_939, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] + node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[0].match_ <= _T_943 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[0].load <= _T_945 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_946 = bits(io.mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[0].execute <= _T_946 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_947 = bits(io.mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[1].match_ <= _T_949 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[1].load <= _T_951 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_952 = bits(io.mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[1].execute <= _T_952 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_953 = bits(io.mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[2].match_ <= _T_955 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[2].load <= _T_957 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_958 = bits(io.mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[2].execute <= _T_958 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_959 = bits(io.mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] + io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] + io.trigger_pkt_any[3].match_ <= _T_961 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] + io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] + node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] + io.trigger_pkt_any[3].load <= _T_963 @[el2_dec_tlu_ctl.scala 2311:36] + node _T_964 = bits(io.mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 2312:54] + io.trigger_pkt_any[3].execute <= _T_964 @[el2_dec_tlu_ctl.scala 2312:36] + node _T_965 = bits(io.mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 2313:54] + io.trigger_pkt_any[3].m <= _T_965 @[el2_dec_tlu_ctl.scala 2313:36] + node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_969 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_970 = and(_T_968, _T_969) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_971 = bits(io.mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_972 = not(_T_971) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_974 = and(_T_970, _T_973) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_978 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_979 = and(_T_977, _T_978) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_980 = bits(io.mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_981 = not(_T_980) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_983 = and(_T_979, _T_982) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_987 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_988 = and(_T_986, _T_987) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_989 = bits(io.mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_990 = not(_T_989) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_992 = and(_T_988, _T_991) @[el2_dec_tlu_ctl.scala 2320:135] + node _T_993 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2320:92] + node _T_994 = eq(_T_993, UInt<12>("h07a2")) @[el2_dec_tlu_ctl.scala 2320:99] + node _T_995 = and(io.dec_csr_wen_r_mod, _T_994) @[el2_dec_tlu_ctl.scala 2320:70] + node _T_996 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2320:121] + node _T_997 = and(_T_995, _T_996) @[el2_dec_tlu_ctl.scala 2320:112] + node _T_998 = bits(io.mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 2320:154] + node _T_999 = not(_T_998) @[el2_dec_tlu_ctl.scala 2320:138] + node _T_1000 = or(_T_999, io.dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 2320:170] + node _T_1001 = and(_T_997, _T_1000) @[el2_dec_tlu_ctl.scala 2320:135] + wire wr_mtdata2_t_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[0] <= _T_974 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[1] <= _T_983 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[2] <= _T_992 @[el2_dec_tlu_ctl.scala 2320:43] + wr_mtdata2_t_r[3] <= _T_1001 @[el2_dec_tlu_ctl.scala 2320:43] + node _T_1002 = bits(wr_mtdata2_t_r[0], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_22 of rvclkhdr_30 @[el2_lib.scala 485:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_22.io.en <= _T_1002 @[el2_lib.scala 488:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1003 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1003 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[0] <= _T_1003 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1004 = bits(wr_mtdata2_t_r[1], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_23 of rvclkhdr_31 @[el2_lib.scala 485:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_23.io.en <= _T_1004 @[el2_lib.scala 488:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1005 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1005 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[1] <= _T_1005 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1006 = bits(wr_mtdata2_t_r[2], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_24 of rvclkhdr_32 @[el2_lib.scala 485:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_24.io.en <= _T_1006 @[el2_lib.scala 488:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1007 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1007 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[2] <= _T_1007 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1008 = bits(wr_mtdata2_t_r[3], 0, 0) @[el2_dec_tlu_ctl.scala 2321:86] + inst rvclkhdr_25 of rvclkhdr_33 @[el2_lib.scala 485:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_25.io.en <= _T_1008 @[el2_lib.scala 488:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_1009 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_1009 <= io.dec_csr_wrdata_r @[el2_lib.scala 491:16] + mtdata2_t[3] <= _T_1009 @[el2_dec_tlu_ctl.scala 2321:38] + node _T_1010 = eq(mtsel, UInt<2>("h00")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1011 = eq(mtsel, UInt<2>("h01")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1012 = eq(mtsel, UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1013 = eq(mtsel, UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2325:59] + node _T_1014 = mux(_T_1010, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1015 = mux(_T_1011, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = or(_T_1014, _T_1015) @[Mux.scala 27:72] + node _T_1019 = or(_T_1018, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1020 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[el2_dec_tlu_ctl.scala 2326:53] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[el2_dec_tlu_ctl.scala 2326:53] + mhpme_vec[0] <= mhpme3 @[el2_dec_tlu_ctl.scala 2336:16] + mhpme_vec[1] <= mhpme4 @[el2_dec_tlu_ctl.scala 2337:16] + mhpme_vec[2] <= mhpme5 @[el2_dec_tlu_ctl.scala 2338:16] + mhpme_vec[3] <= mhpme6 @[el2_dec_tlu_ctl.scala 2339:16] + node _T_1021 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1022 = mux(_T_1021, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1022) @[el2_dec_tlu_ctl.scala 2345:60] + wire mhpmc_inc_r : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2346:25] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[el2_dec_tlu_ctl.scala 2347:28] + node _T_1023 = bits(mcountinhibit, 3, 3) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1024 = not(_T_1023) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1025 = eq(mhpme_vec[0], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1026 = bits(_T_1025, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1027 = eq(mhpme_vec[0], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1028 = bits(_T_1027, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1030 = bits(_T_1029, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1031 = eq(mhpme_vec[0], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1032 = bits(_T_1031, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1033 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1034 = and(io.tlu_i0_commit_cmt, _T_1033) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1035 = eq(mhpme_vec[0], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1036 = bits(_T_1035, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1037 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1038 = and(io.tlu_i0_commit_cmt, _T_1037) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1039 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1040 = and(_T_1038, _T_1039) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1041 = eq(mhpme_vec[0], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1042 = bits(_T_1041, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1043 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1044 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1045 = and(_T_1043, _T_1044) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1046 = eq(mhpme_vec[0], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1047 = bits(_T_1046, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1048 = eq(mhpme_vec[0], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1049 = bits(_T_1048, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1050 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1051 = bits(_T_1050, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1052 = eq(mhpme_vec[0], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1053 = bits(_T_1052, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1056 = bits(_T_1055, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1057 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1058 = eq(mhpme_vec[0], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1059 = bits(_T_1058, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1060 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1062 = bits(_T_1061, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1065 = bits(_T_1064, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1067 = eq(mhpme_vec[0], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1068 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1067) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1069 = bits(_T_1068, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1070 = and(_T_1066, _T_1069) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1072 = and(_T_1070, _T_1071) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1074 = and(_T_1072, _T_1073) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1076 = bits(_T_1075, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1079 = bits(_T_1078, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1082 = bits(_T_1081, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1085 = bits(_T_1084, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1088 = bits(_T_1087, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1091 = bits(_T_1090, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1094 = bits(_T_1093, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1097 = bits(_T_1096, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1100 = bits(_T_1099, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1103 = bits(_T_1102, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1106 = or(_T_1104, _T_1105) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1108 = bits(_T_1107, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1111 = bits(_T_1110, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1114 = bits(_T_1113, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1117 = bits(_T_1116, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1119 = bits(_T_1118, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1121 = bits(_T_1120, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1123 = bits(_T_1122, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1125 = bits(_T_1124, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1127 = bits(_T_1126, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1129 = bits(_T_1128, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1131 = bits(_T_1130, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1135 = bits(_T_1134, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1139 = bits(_T_1138, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1141 = bits(_T_1140, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1143 = bits(_T_1142, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1147 = bits(_T_1146, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1149 = bits(_T_1148, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1151 = bits(_T_1150, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1153 = bits(_T_1152, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1155 = bits(_T_1154, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1157 = bits(_T_1156, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1159 = bits(_T_1158, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1161 = bits(_T_1160, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1163 = bits(_T_1162, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1164 = not(_T_1163) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1166 = bits(_T_1165, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1168 = bits(_T_1167, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1169 = not(_T_1168) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1170 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1171 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1172 = and(_T_1170, _T_1171) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1173 = and(_T_1169, _T_1172) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1175 = bits(_T_1174, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1178 = bits(_T_1177, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1181 = bits(_T_1180, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1184 = bits(_T_1183, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1186 = bits(_T_1185, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1188 = bits(_T_1187, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1190 = bits(_T_1189, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1192 = bits(_T_1191, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1193 = mux(_T_1026, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1028, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, _T_1034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1036, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1042, _T_1045, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1047, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, _T_1054, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1056, _T_1057, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1059, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1062, _T_1063, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1065, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1166, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1195) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1196) @[Mux.scala 27:72] + node _T_1252 = or(_T_1251, _T_1197) @[Mux.scala 27:72] + node _T_1253 = or(_T_1252, _T_1198) @[Mux.scala 27:72] + node _T_1254 = or(_T_1253, _T_1199) @[Mux.scala 27:72] + node _T_1255 = or(_T_1254, _T_1200) @[Mux.scala 27:72] + node _T_1256 = or(_T_1255, _T_1201) @[Mux.scala 27:72] + node _T_1257 = or(_T_1256, _T_1202) @[Mux.scala 27:72] + node _T_1258 = or(_T_1257, _T_1203) @[Mux.scala 27:72] + node _T_1259 = or(_T_1258, _T_1204) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1205) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1206) @[Mux.scala 27:72] + node _T_1262 = or(_T_1261, _T_1207) @[Mux.scala 27:72] + node _T_1263 = or(_T_1262, _T_1208) @[Mux.scala 27:72] + node _T_1264 = or(_T_1263, _T_1209) @[Mux.scala 27:72] + node _T_1265 = or(_T_1264, _T_1210) @[Mux.scala 27:72] + node _T_1266 = or(_T_1265, _T_1211) @[Mux.scala 27:72] + node _T_1267 = or(_T_1266, _T_1212) @[Mux.scala 27:72] + node _T_1268 = or(_T_1267, _T_1213) @[Mux.scala 27:72] + node _T_1269 = or(_T_1268, _T_1214) @[Mux.scala 27:72] + node _T_1270 = or(_T_1269, _T_1215) @[Mux.scala 27:72] + node _T_1271 = or(_T_1270, _T_1216) @[Mux.scala 27:72] + node _T_1272 = or(_T_1271, _T_1217) @[Mux.scala 27:72] + node _T_1273 = or(_T_1272, _T_1218) @[Mux.scala 27:72] + node _T_1274 = or(_T_1273, _T_1219) @[Mux.scala 27:72] + node _T_1275 = or(_T_1274, _T_1220) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1221) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1222) @[Mux.scala 27:72] + node _T_1278 = or(_T_1277, _T_1223) @[Mux.scala 27:72] + node _T_1279 = or(_T_1278, _T_1224) @[Mux.scala 27:72] + node _T_1280 = or(_T_1279, _T_1225) @[Mux.scala 27:72] + node _T_1281 = or(_T_1280, _T_1226) @[Mux.scala 27:72] + node _T_1282 = or(_T_1281, _T_1227) @[Mux.scala 27:72] + node _T_1283 = or(_T_1282, _T_1228) @[Mux.scala 27:72] + node _T_1284 = or(_T_1283, _T_1229) @[Mux.scala 27:72] + node _T_1285 = or(_T_1284, _T_1230) @[Mux.scala 27:72] + node _T_1286 = or(_T_1285, _T_1231) @[Mux.scala 27:72] + node _T_1287 = or(_T_1286, _T_1232) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1233) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1234) @[Mux.scala 27:72] + node _T_1290 = or(_T_1289, _T_1235) @[Mux.scala 27:72] + node _T_1291 = or(_T_1290, _T_1236) @[Mux.scala 27:72] + node _T_1292 = or(_T_1291, _T_1237) @[Mux.scala 27:72] + node _T_1293 = or(_T_1292, _T_1238) @[Mux.scala 27:72] + node _T_1294 = or(_T_1293, _T_1239) @[Mux.scala 27:72] + node _T_1295 = or(_T_1294, _T_1240) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1241) @[Mux.scala 27:72] + node _T_1297 = or(_T_1296, _T_1242) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1243) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1244) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1245) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1246) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1247) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1248) @[Mux.scala 27:72] + wire _T_1304 : UInt<6> @[Mux.scala 27:72] + _T_1304 <= _T_1303 @[Mux.scala 27:72] + node _T_1305 = and(_T_1024, _T_1304) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[0] <= _T_1305 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1306 = bits(mcountinhibit, 4, 4) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1307 = not(_T_1306) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1308 = eq(mhpme_vec[1], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1309 = bits(_T_1308, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1310 = eq(mhpme_vec[1], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1311 = bits(_T_1310, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1313 = bits(_T_1312, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1314 = eq(mhpme_vec[1], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1315 = bits(_T_1314, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1316 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1317 = and(io.tlu_i0_commit_cmt, _T_1316) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1318 = eq(mhpme_vec[1], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1319 = bits(_T_1318, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1320 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1321 = and(io.tlu_i0_commit_cmt, _T_1320) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1322 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1323 = and(_T_1321, _T_1322) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1324 = eq(mhpme_vec[1], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1325 = bits(_T_1324, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1326 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1327 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1328 = and(_T_1326, _T_1327) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1329 = eq(mhpme_vec[1], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1330 = bits(_T_1329, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1331 = eq(mhpme_vec[1], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1332 = bits(_T_1331, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1333 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1334 = bits(_T_1333, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1335 = eq(mhpme_vec[1], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1336 = bits(_T_1335, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1339 = bits(_T_1338, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1340 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1342 = bits(_T_1341, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1345 = bits(_T_1344, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1348 = bits(_T_1347, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1351 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1350) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1352 = bits(_T_1351, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1353 = and(_T_1349, _T_1352) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1354 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1355 = and(_T_1353, _T_1354) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1357 = and(_T_1355, _T_1356) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1359 = bits(_T_1358, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1362 = bits(_T_1361, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1365 = bits(_T_1364, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1368 = bits(_T_1367, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1371 = bits(_T_1370, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1377 = bits(_T_1376, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1380 = bits(_T_1379, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1383 = bits(_T_1382, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1386 = bits(_T_1385, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1389 = or(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1391 = bits(_T_1390, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1394 = bits(_T_1393, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1397 = bits(_T_1396, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1400 = bits(_T_1399, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1402 = bits(_T_1401, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1404 = bits(_T_1403, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1406 = bits(_T_1405, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1408 = bits(_T_1407, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1410 = bits(_T_1409, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1412 = bits(_T_1411, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1414 = bits(_T_1413, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1418 = bits(_T_1417, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1422 = bits(_T_1421, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1424 = bits(_T_1423, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1426 = bits(_T_1425, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1430 = bits(_T_1429, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1432 = bits(_T_1431, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1434 = bits(_T_1433, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1436 = bits(_T_1435, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1438 = bits(_T_1437, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1440 = bits(_T_1439, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1442 = bits(_T_1441, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1444 = bits(_T_1443, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1446 = bits(_T_1445, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1447 = not(_T_1446) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1449 = bits(_T_1448, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1451 = bits(_T_1450, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1452 = not(_T_1451) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1453 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1454 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1455 = and(_T_1453, _T_1454) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1456 = and(_T_1452, _T_1455) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1457 = eq(mhpme_vec[1], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1458 = bits(_T_1457, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1459 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1460 = eq(mhpme_vec[1], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1461 = bits(_T_1460, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1462 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1463 = eq(mhpme_vec[1], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1465 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1466 = eq(mhpme_vec[1], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1467 = bits(_T_1466, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1469 = bits(_T_1468, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1471 = bits(_T_1470, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1473 = bits(_T_1472, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1475 = bits(_T_1474, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1476 = mux(_T_1309, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1311, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1319, _T_1323, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1325, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1330, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1348, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1449, _T_1456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1458, _T_1459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1461, _T_1462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1464, _T_1465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1467, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1469, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1471, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1473, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1475, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = or(_T_1476, _T_1477) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1478) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1479) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1480) @[Mux.scala 27:72] + node _T_1536 = or(_T_1535, _T_1481) @[Mux.scala 27:72] + node _T_1537 = or(_T_1536, _T_1482) @[Mux.scala 27:72] + node _T_1538 = or(_T_1537, _T_1483) @[Mux.scala 27:72] + node _T_1539 = or(_T_1538, _T_1484) @[Mux.scala 27:72] + node _T_1540 = or(_T_1539, _T_1485) @[Mux.scala 27:72] + node _T_1541 = or(_T_1540, _T_1486) @[Mux.scala 27:72] + node _T_1542 = or(_T_1541, _T_1487) @[Mux.scala 27:72] + node _T_1543 = or(_T_1542, _T_1488) @[Mux.scala 27:72] + node _T_1544 = or(_T_1543, _T_1489) @[Mux.scala 27:72] + node _T_1545 = or(_T_1544, _T_1490) @[Mux.scala 27:72] + node _T_1546 = or(_T_1545, _T_1491) @[Mux.scala 27:72] + node _T_1547 = or(_T_1546, _T_1492) @[Mux.scala 27:72] + node _T_1548 = or(_T_1547, _T_1493) @[Mux.scala 27:72] + node _T_1549 = or(_T_1548, _T_1494) @[Mux.scala 27:72] + node _T_1550 = or(_T_1549, _T_1495) @[Mux.scala 27:72] + node _T_1551 = or(_T_1550, _T_1496) @[Mux.scala 27:72] + node _T_1552 = or(_T_1551, _T_1497) @[Mux.scala 27:72] + node _T_1553 = or(_T_1552, _T_1498) @[Mux.scala 27:72] + node _T_1554 = or(_T_1553, _T_1499) @[Mux.scala 27:72] + node _T_1555 = or(_T_1554, _T_1500) @[Mux.scala 27:72] + node _T_1556 = or(_T_1555, _T_1501) @[Mux.scala 27:72] + node _T_1557 = or(_T_1556, _T_1502) @[Mux.scala 27:72] + node _T_1558 = or(_T_1557, _T_1503) @[Mux.scala 27:72] + node _T_1559 = or(_T_1558, _T_1504) @[Mux.scala 27:72] + node _T_1560 = or(_T_1559, _T_1505) @[Mux.scala 27:72] + node _T_1561 = or(_T_1560, _T_1506) @[Mux.scala 27:72] + node _T_1562 = or(_T_1561, _T_1507) @[Mux.scala 27:72] + node _T_1563 = or(_T_1562, _T_1508) @[Mux.scala 27:72] + node _T_1564 = or(_T_1563, _T_1509) @[Mux.scala 27:72] + node _T_1565 = or(_T_1564, _T_1510) @[Mux.scala 27:72] + node _T_1566 = or(_T_1565, _T_1511) @[Mux.scala 27:72] + node _T_1567 = or(_T_1566, _T_1512) @[Mux.scala 27:72] + node _T_1568 = or(_T_1567, _T_1513) @[Mux.scala 27:72] + node _T_1569 = or(_T_1568, _T_1514) @[Mux.scala 27:72] + node _T_1570 = or(_T_1569, _T_1515) @[Mux.scala 27:72] + node _T_1571 = or(_T_1570, _T_1516) @[Mux.scala 27:72] + node _T_1572 = or(_T_1571, _T_1517) @[Mux.scala 27:72] + node _T_1573 = or(_T_1572, _T_1518) @[Mux.scala 27:72] + node _T_1574 = or(_T_1573, _T_1519) @[Mux.scala 27:72] + node _T_1575 = or(_T_1574, _T_1520) @[Mux.scala 27:72] + node _T_1576 = or(_T_1575, _T_1521) @[Mux.scala 27:72] + node _T_1577 = or(_T_1576, _T_1522) @[Mux.scala 27:72] + node _T_1578 = or(_T_1577, _T_1523) @[Mux.scala 27:72] + node _T_1579 = or(_T_1578, _T_1524) @[Mux.scala 27:72] + node _T_1580 = or(_T_1579, _T_1525) @[Mux.scala 27:72] + node _T_1581 = or(_T_1580, _T_1526) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1527) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1528) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1529) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1530) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1531) @[Mux.scala 27:72] + wire _T_1587 : UInt<6> @[Mux.scala 27:72] + _T_1587 <= _T_1586 @[Mux.scala 27:72] + node _T_1588 = and(_T_1307, _T_1587) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[1] <= _T_1588 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1589 = bits(mcountinhibit, 5, 5) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1590 = not(_T_1589) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1591 = eq(mhpme_vec[2], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1592 = bits(_T_1591, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1593 = eq(mhpme_vec[2], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1594 = bits(_T_1593, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1595 = eq(mhpme_vec[2], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1596 = bits(_T_1595, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1597 = eq(mhpme_vec[2], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1598 = bits(_T_1597, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1599 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1600 = and(io.tlu_i0_commit_cmt, _T_1599) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1602 = bits(_T_1601, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1603 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1605 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1606 = and(_T_1604, _T_1605) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1607 = eq(mhpme_vec[2], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1608 = bits(_T_1607, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1609 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1610 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1611 = and(_T_1609, _T_1610) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1612 = eq(mhpme_vec[2], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1613 = bits(_T_1612, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1614 = eq(mhpme_vec[2], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1615 = bits(_T_1614, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1616 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1617 = bits(_T_1616, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1619 = bits(_T_1618, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1620 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1622 = bits(_T_1621, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1623 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1625 = bits(_T_1624, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1626 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1628 = bits(_T_1627, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1631 = bits(_T_1630, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1634 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1633) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1635 = bits(_T_1634, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1636 = and(_T_1632, _T_1635) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1638 = and(_T_1636, _T_1637) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1639 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1640 = and(_T_1638, _T_1639) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1641 = eq(mhpme_vec[2], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1642 = bits(_T_1641, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1644 = eq(mhpme_vec[2], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1645 = bits(_T_1644, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1647 = eq(mhpme_vec[2], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1648 = bits(_T_1647, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1650 = eq(mhpme_vec[2], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1651 = bits(_T_1650, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1653 = eq(mhpme_vec[2], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1654 = bits(_T_1653, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1656 = eq(mhpme_vec[2], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1657 = bits(_T_1656, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1659 = eq(mhpme_vec[2], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1660 = bits(_T_1659, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1662 = eq(mhpme_vec[2], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1663 = bits(_T_1662, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1665 = eq(mhpme_vec[2], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1666 = bits(_T_1665, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1667 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1668 = eq(mhpme_vec[2], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1669 = bits(_T_1668, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1670 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1672 = or(_T_1670, _T_1671) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1673 = eq(mhpme_vec[2], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1674 = bits(_T_1673, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1675 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1676 = eq(mhpme_vec[2], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1677 = bits(_T_1676, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1678 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1680 = bits(_T_1679, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1681 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1682 = eq(mhpme_vec[2], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1683 = bits(_T_1682, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1685 = bits(_T_1684, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1687 = bits(_T_1686, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1688 = eq(mhpme_vec[2], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1689 = bits(_T_1688, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1691 = bits(_T_1690, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1693 = bits(_T_1692, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1695 = bits(_T_1694, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1697 = bits(_T_1696, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1698 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1699 = or(_T_1698, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1700 = eq(mhpme_vec[2], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1701 = bits(_T_1700, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1702 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1703 = or(_T_1702, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1704 = eq(mhpme_vec[2], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1705 = bits(_T_1704, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1707 = bits(_T_1706, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1709 = bits(_T_1708, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1710 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1711 = and(_T_1710, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1712 = eq(mhpme_vec[2], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1713 = bits(_T_1712, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1715 = bits(_T_1714, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_1717 = bits(_T_1716, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_1719 = bits(_T_1718, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_1721 = bits(_T_1720, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_1723 = bits(_T_1722, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_1725 = bits(_T_1724, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_1727 = bits(_T_1726, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_1728 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1729 = bits(_T_1728, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_1730 = not(_T_1729) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_1731 = eq(mhpme_vec[2], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_1732 = bits(_T_1731, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_1733 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1734 = bits(_T_1733, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_1735 = not(_T_1734) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_1736 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_1737 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_1738 = and(_T_1736, _T_1737) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_1739 = and(_T_1735, _T_1738) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_1740 = eq(mhpme_vec[2], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_1741 = bits(_T_1740, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_1742 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_1744 = bits(_T_1743, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_1745 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_1747 = bits(_T_1746, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_1750 = bits(_T_1749, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_1752 = bits(_T_1751, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_1754 = bits(_T_1753, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_1756 = bits(_T_1755, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_1758 = bits(_T_1757, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_1759 = mux(_T_1592, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1594, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1596, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1598, _T_1600, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1602, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1608, _T_1611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1613, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1615, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1617, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1631, _T_1640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1642, _T_1643, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1645, _T_1646, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1648, _T_1649, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1651, _T_1652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1654, _T_1655, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1660, _T_1661, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1669, _T_1672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1674, _T_1675, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1680, _T_1681, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1683, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1685, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1687, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1689, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1691, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1693, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1695, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1697, _T_1699, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1701, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1705, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1707, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1709, _T_1711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1713, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1715, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1717, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1719, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1721, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1723, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1725, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1727, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1732, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1750, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1752, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1754, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1756, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1758, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = or(_T_1759, _T_1760) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1761) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1762) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1763) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1764) @[Mux.scala 27:72] + node _T_1820 = or(_T_1819, _T_1765) @[Mux.scala 27:72] + node _T_1821 = or(_T_1820, _T_1766) @[Mux.scala 27:72] + node _T_1822 = or(_T_1821, _T_1767) @[Mux.scala 27:72] + node _T_1823 = or(_T_1822, _T_1768) @[Mux.scala 27:72] + node _T_1824 = or(_T_1823, _T_1769) @[Mux.scala 27:72] + node _T_1825 = or(_T_1824, _T_1770) @[Mux.scala 27:72] + node _T_1826 = or(_T_1825, _T_1771) @[Mux.scala 27:72] + node _T_1827 = or(_T_1826, _T_1772) @[Mux.scala 27:72] + node _T_1828 = or(_T_1827, _T_1773) @[Mux.scala 27:72] + node _T_1829 = or(_T_1828, _T_1774) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1775) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1776) @[Mux.scala 27:72] + node _T_1832 = or(_T_1831, _T_1777) @[Mux.scala 27:72] + node _T_1833 = or(_T_1832, _T_1778) @[Mux.scala 27:72] + node _T_1834 = or(_T_1833, _T_1779) @[Mux.scala 27:72] + node _T_1835 = or(_T_1834, _T_1780) @[Mux.scala 27:72] + node _T_1836 = or(_T_1835, _T_1781) @[Mux.scala 27:72] + node _T_1837 = or(_T_1836, _T_1782) @[Mux.scala 27:72] + node _T_1838 = or(_T_1837, _T_1783) @[Mux.scala 27:72] + node _T_1839 = or(_T_1838, _T_1784) @[Mux.scala 27:72] + node _T_1840 = or(_T_1839, _T_1785) @[Mux.scala 27:72] + node _T_1841 = or(_T_1840, _T_1786) @[Mux.scala 27:72] + node _T_1842 = or(_T_1841, _T_1787) @[Mux.scala 27:72] + node _T_1843 = or(_T_1842, _T_1788) @[Mux.scala 27:72] + node _T_1844 = or(_T_1843, _T_1789) @[Mux.scala 27:72] + node _T_1845 = or(_T_1844, _T_1790) @[Mux.scala 27:72] + node _T_1846 = or(_T_1845, _T_1791) @[Mux.scala 27:72] + node _T_1847 = or(_T_1846, _T_1792) @[Mux.scala 27:72] + node _T_1848 = or(_T_1847, _T_1793) @[Mux.scala 27:72] + node _T_1849 = or(_T_1848, _T_1794) @[Mux.scala 27:72] + node _T_1850 = or(_T_1849, _T_1795) @[Mux.scala 27:72] + node _T_1851 = or(_T_1850, _T_1796) @[Mux.scala 27:72] + node _T_1852 = or(_T_1851, _T_1797) @[Mux.scala 27:72] + node _T_1853 = or(_T_1852, _T_1798) @[Mux.scala 27:72] + node _T_1854 = or(_T_1853, _T_1799) @[Mux.scala 27:72] + node _T_1855 = or(_T_1854, _T_1800) @[Mux.scala 27:72] + node _T_1856 = or(_T_1855, _T_1801) @[Mux.scala 27:72] + node _T_1857 = or(_T_1856, _T_1802) @[Mux.scala 27:72] + node _T_1858 = or(_T_1857, _T_1803) @[Mux.scala 27:72] + node _T_1859 = or(_T_1858, _T_1804) @[Mux.scala 27:72] + node _T_1860 = or(_T_1859, _T_1805) @[Mux.scala 27:72] + node _T_1861 = or(_T_1860, _T_1806) @[Mux.scala 27:72] + node _T_1862 = or(_T_1861, _T_1807) @[Mux.scala 27:72] + node _T_1863 = or(_T_1862, _T_1808) @[Mux.scala 27:72] + node _T_1864 = or(_T_1863, _T_1809) @[Mux.scala 27:72] + node _T_1865 = or(_T_1864, _T_1810) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1811) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1812) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1813) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1814) @[Mux.scala 27:72] + wire _T_1870 : UInt<6> @[Mux.scala 27:72] + _T_1870 <= _T_1869 @[Mux.scala 27:72] + node _T_1871 = and(_T_1590, _T_1870) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[2] <= _T_1871 @[el2_dec_tlu_ctl.scala 2351:20] + node _T_1872 = bits(mcountinhibit, 6, 6) @[el2_dec_tlu_ctl.scala 2351:39] + node _T_1873 = not(_T_1872) @[el2_dec_tlu_ctl.scala 2351:25] + node _T_1874 = eq(mhpme_vec[3], UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 2352:21] + node _T_1875 = bits(_T_1874, 0, 0) @[el2_dec_tlu_ctl.scala 2352:49] + node _T_1876 = eq(mhpme_vec[3], UInt<2>("h02")) @[el2_dec_tlu_ctl.scala 2353:21] + node _T_1877 = bits(_T_1876, 0, 0) @[el2_dec_tlu_ctl.scala 2353:49] + node _T_1878 = eq(mhpme_vec[3], UInt<2>("h03")) @[el2_dec_tlu_ctl.scala 2354:21] + node _T_1879 = bits(_T_1878, 0, 0) @[el2_dec_tlu_ctl.scala 2354:49] + node _T_1880 = eq(mhpme_vec[3], UInt<3>("h04")) @[el2_dec_tlu_ctl.scala 2355:21] + node _T_1881 = bits(_T_1880, 0, 0) @[el2_dec_tlu_ctl.scala 2355:49] + node _T_1882 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2355:83] + node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[el2_dec_tlu_ctl.scala 2355:81] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h05")) @[el2_dec_tlu_ctl.scala 2356:21] + node _T_1885 = bits(_T_1884, 0, 0) @[el2_dec_tlu_ctl.scala 2356:49] + node _T_1886 = not(io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2356:83] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[el2_dec_tlu_ctl.scala 2356:81] + node _T_1888 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2356:104] + node _T_1889 = and(_T_1887, _T_1888) @[el2_dec_tlu_ctl.scala 2356:102] + node _T_1890 = eq(mhpme_vec[3], UInt<3>("h06")) @[el2_dec_tlu_ctl.scala 2357:21] + node _T_1891 = bits(_T_1890, 0, 0) @[el2_dec_tlu_ctl.scala 2357:49] + node _T_1892 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[el2_dec_tlu_ctl.scala 2357:81] + node _T_1893 = not(io.illegal_r) @[el2_dec_tlu_ctl.scala 2357:104] + node _T_1894 = and(_T_1892, _T_1893) @[el2_dec_tlu_ctl.scala 2357:102] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h07")) @[el2_dec_tlu_ctl.scala 2358:21] + node _T_1896 = bits(_T_1895, 0, 0) @[el2_dec_tlu_ctl.scala 2358:49] + node _T_1897 = eq(mhpme_vec[3], UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2359:21] + node _T_1898 = bits(_T_1897, 0, 0) @[el2_dec_tlu_ctl.scala 2359:49] + node _T_1899 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2360:21] + node _T_1900 = bits(_T_1899, 0, 0) @[el2_dec_tlu_ctl.scala 2360:49] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2361:21] + node _T_1902 = bits(_T_1901, 0, 0) @[el2_dec_tlu_ctl.scala 2361:49] + node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[el2_dec_tlu_ctl.scala 2361:78] + node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2362:21] + node _T_1905 = bits(_T_1904, 0, 0) @[el2_dec_tlu_ctl.scala 2362:49] + node _T_1906 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2362:92] + node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2363:21] + node _T_1908 = bits(_T_1907, 0, 0) @[el2_dec_tlu_ctl.scala 2363:49] + node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2363:78] + node _T_1910 = eq(mhpme_vec[3], UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2364:21] + node _T_1911 = bits(_T_1910, 0, 0) @[el2_dec_tlu_ctl.scala 2364:49] + node _T_1912 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2364:78] + node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2365:21] + node _T_1914 = bits(_T_1913, 0, 0) @[el2_dec_tlu_ctl.scala 2365:49] + node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[el2_dec_tlu_ctl.scala 2365:79] + node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2366:21] + node _T_1917 = dshr(io.dec_tlu_packet_r.pmu_lsu_misaligned, _T_1916) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1918 = bits(_T_1917, 0, 0) @[el2_dec_tlu_ctl.scala 2366:7] + node _T_1919 = and(_T_1915, _T_1918) @[el2_dec_tlu_ctl.scala 2365:89] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[el2_dec_tlu_ctl.scala 2366:66] + node _T_1921 = and(_T_1919, _T_1920) @[el2_dec_tlu_ctl.scala 2366:45] + node _T_1922 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[el2_dec_tlu_ctl.scala 2367:48] + node _T_1923 = and(_T_1921, _T_1922) @[el2_dec_tlu_ctl.scala 2366:77] + node _T_1924 = eq(mhpme_vec[3], UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2368:21] + node _T_1925 = bits(_T_1924, 0, 0) @[el2_dec_tlu_ctl.scala 2368:41] + node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[el2_dec_tlu_ctl.scala 2368:76] + node _T_1927 = eq(mhpme_vec[3], UInt<5>("h010")) @[el2_dec_tlu_ctl.scala 2369:21] + node _T_1928 = bits(_T_1927, 0, 0) @[el2_dec_tlu_ctl.scala 2369:46] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[el2_dec_tlu_ctl.scala 2369:76] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h012")) @[el2_dec_tlu_ctl.scala 2370:21] + node _T_1931 = bits(_T_1930, 0, 0) @[el2_dec_tlu_ctl.scala 2370:46] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[el2_dec_tlu_ctl.scala 2370:76] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h011")) @[el2_dec_tlu_ctl.scala 2371:21] + node _T_1934 = bits(_T_1933, 0, 0) @[el2_dec_tlu_ctl.scala 2371:46] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[el2_dec_tlu_ctl.scala 2371:76] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h013")) @[el2_dec_tlu_ctl.scala 2372:21] + node _T_1937 = bits(_T_1936, 0, 0) @[el2_dec_tlu_ctl.scala 2372:46] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 2372:76] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h014")) @[el2_dec_tlu_ctl.scala 2373:21] + node _T_1940 = bits(_T_1939, 0, 0) @[el2_dec_tlu_ctl.scala 2373:46] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 2373:76] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h015")) @[el2_dec_tlu_ctl.scala 2374:21] + node _T_1943 = bits(_T_1942, 0, 0) @[el2_dec_tlu_ctl.scala 2374:46] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[el2_dec_tlu_ctl.scala 2374:76] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h016")) @[el2_dec_tlu_ctl.scala 2375:21] + node _T_1946 = bits(_T_1945, 0, 0) @[el2_dec_tlu_ctl.scala 2375:46] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[el2_dec_tlu_ctl.scala 2375:76] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h017")) @[el2_dec_tlu_ctl.scala 2376:21] + node _T_1949 = bits(_T_1948, 0, 0) @[el2_dec_tlu_ctl.scala 2376:46] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 2376:76] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h018")) @[el2_dec_tlu_ctl.scala 2377:21] + node _T_1952 = bits(_T_1951, 0, 0) @[el2_dec_tlu_ctl.scala 2377:46] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[el2_dec_tlu_ctl.scala 2377:76] + node _T_1954 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[el2_dec_tlu_ctl.scala 2377:109] + node _T_1955 = or(_T_1953, _T_1954) @[el2_dec_tlu_ctl.scala 2377:88] + node _T_1956 = eq(mhpme_vec[3], UInt<5>("h019")) @[el2_dec_tlu_ctl.scala 2378:21] + node _T_1957 = bits(_T_1956, 0, 0) @[el2_dec_tlu_ctl.scala 2378:49] + node _T_1958 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2378:82] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01a")) @[el2_dec_tlu_ctl.scala 2379:21] + node _T_1960 = bits(_T_1959, 0, 0) @[el2_dec_tlu_ctl.scala 2379:49] + node _T_1961 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2379:84] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01b")) @[el2_dec_tlu_ctl.scala 2380:21] + node _T_1963 = bits(_T_1962, 0, 0) @[el2_dec_tlu_ctl.scala 2380:49] + node _T_1964 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[el2_dec_tlu_ctl.scala 2380:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01c")) @[el2_dec_tlu_ctl.scala 2381:21] + node _T_1966 = bits(_T_1965, 0, 0) @[el2_dec_tlu_ctl.scala 2381:49] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01e")) @[el2_dec_tlu_ctl.scala 2382:21] + node _T_1968 = bits(_T_1967, 0, 0) @[el2_dec_tlu_ctl.scala 2382:49] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01f")) @[el2_dec_tlu_ctl.scala 2383:21] + node _T_1970 = bits(_T_1969, 0, 0) @[el2_dec_tlu_ctl.scala 2383:49] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h020")) @[el2_dec_tlu_ctl.scala 2384:21] + node _T_1972 = bits(_T_1971, 0, 0) @[el2_dec_tlu_ctl.scala 2384:49] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h022")) @[el2_dec_tlu_ctl.scala 2385:21] + node _T_1974 = bits(_T_1973, 0, 0) @[el2_dec_tlu_ctl.scala 2385:49] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h023")) @[el2_dec_tlu_ctl.scala 2386:21] + node _T_1976 = bits(_T_1975, 0, 0) @[el2_dec_tlu_ctl.scala 2386:49] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h024")) @[el2_dec_tlu_ctl.scala 2387:21] + node _T_1978 = bits(_T_1977, 0, 0) @[el2_dec_tlu_ctl.scala 2387:49] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h025")) @[el2_dec_tlu_ctl.scala 2388:21] + node _T_1980 = bits(_T_1979, 0, 0) @[el2_dec_tlu_ctl.scala 2388:49] + node _T_1981 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 2388:85] + node _T_1982 = or(_T_1981, io.lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 2388:107] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h026")) @[el2_dec_tlu_ctl.scala 2389:21] + node _T_1984 = bits(_T_1983, 0, 0) @[el2_dec_tlu_ctl.scala 2389:49] + node _T_1985 = or(io.take_timer_int, io.take_int_timer0_int) @[el2_dec_tlu_ctl.scala 2389:79] + node _T_1986 = or(_T_1985, io.take_int_timer1_int) @[el2_dec_tlu_ctl.scala 2389:104] + node _T_1987 = eq(mhpme_vec[3], UInt<6>("h027")) @[el2_dec_tlu_ctl.scala 2390:21] + node _T_1988 = bits(_T_1987, 0, 0) @[el2_dec_tlu_ctl.scala 2390:49] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h028")) @[el2_dec_tlu_ctl.scala 2391:21] + node _T_1990 = bits(_T_1989, 0, 0) @[el2_dec_tlu_ctl.scala 2391:49] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h029")) @[el2_dec_tlu_ctl.scala 2392:21] + node _T_1992 = bits(_T_1991, 0, 0) @[el2_dec_tlu_ctl.scala 2392:49] + node _T_1993 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[el2_dec_tlu_ctl.scala 2392:84] + node _T_1994 = and(_T_1993, io.rfpc_i0_r) @[el2_dec_tlu_ctl.scala 2392:116] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02a")) @[el2_dec_tlu_ctl.scala 2393:21] + node _T_1996 = bits(_T_1995, 0, 0) @[el2_dec_tlu_ctl.scala 2393:49] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02b")) @[el2_dec_tlu_ctl.scala 2394:21] + node _T_1998 = bits(_T_1997, 0, 0) @[el2_dec_tlu_ctl.scala 2394:49] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02c")) @[el2_dec_tlu_ctl.scala 2395:21] + node _T_2000 = bits(_T_1999, 0, 0) @[el2_dec_tlu_ctl.scala 2395:49] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02d")) @[el2_dec_tlu_ctl.scala 2396:21] + node _T_2002 = bits(_T_2001, 0, 0) @[el2_dec_tlu_ctl.scala 2396:49] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02e")) @[el2_dec_tlu_ctl.scala 2397:21] + node _T_2004 = bits(_T_2003, 0, 0) @[el2_dec_tlu_ctl.scala 2397:49] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02f")) @[el2_dec_tlu_ctl.scala 2398:21] + node _T_2006 = bits(_T_2005, 0, 0) @[el2_dec_tlu_ctl.scala 2398:49] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h030")) @[el2_dec_tlu_ctl.scala 2399:21] + node _T_2008 = bits(_T_2007, 0, 0) @[el2_dec_tlu_ctl.scala 2399:49] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h031")) @[el2_dec_tlu_ctl.scala 2400:21] + node _T_2010 = bits(_T_2009, 0, 0) @[el2_dec_tlu_ctl.scala 2400:49] + node _T_2011 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2012 = bits(_T_2011, 0, 0) @[el2_dec_tlu_ctl.scala 2400:71] + node _T_2013 = not(_T_2012) @[el2_dec_tlu_ctl.scala 2400:60] + node _T_2014 = eq(mhpme_vec[3], UInt<6>("h032")) @[el2_dec_tlu_ctl.scala 2401:21] + node _T_2015 = bits(_T_2014, 0, 0) @[el2_dec_tlu_ctl.scala 2401:49] + node _T_2016 = dshr(io.mstatus, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2017 = bits(_T_2016, 0, 0) @[el2_dec_tlu_ctl.scala 2401:71] + node _T_2018 = not(_T_2017) @[el2_dec_tlu_ctl.scala 2401:60] + node _T_2019 = bits(io.mip, 5, 0) @[el2_dec_tlu_ctl.scala 2401:94] + node _T_2020 = bits(mie, 5, 0) @[el2_dec_tlu_ctl.scala 2401:105] + node _T_2021 = and(_T_2019, _T_2020) @[el2_dec_tlu_ctl.scala 2401:100] + node _T_2022 = and(_T_2018, _T_2021) @[el2_dec_tlu_ctl.scala 2401:85] + node _T_2023 = eq(mhpme_vec[3], UInt<6>("h036")) @[el2_dec_tlu_ctl.scala 2402:21] + node _T_2024 = bits(_T_2023, 0, 0) @[el2_dec_tlu_ctl.scala 2402:49] + node _T_2025 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[el2_dec_tlu_ctl.scala 2402:78] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h037")) @[el2_dec_tlu_ctl.scala 2403:21] + node _T_2027 = bits(_T_2026, 0, 0) @[el2_dec_tlu_ctl.scala 2403:49] + node _T_2028 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[el2_dec_tlu_ctl.scala 2403:81] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h038")) @[el2_dec_tlu_ctl.scala 2404:21] + node _T_2030 = bits(_T_2029, 0, 0) @[el2_dec_tlu_ctl.scala 2404:49] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[el2_dec_tlu_ctl.scala 2404:81] + node _T_2032 = eq(mhpme_vec[3], UInt<10>("h0200")) @[el2_dec_tlu_ctl.scala 2406:21] + node _T_2033 = bits(_T_2032, 0, 0) @[el2_dec_tlu_ctl.scala 2406:49] + node _T_2034 = eq(mhpme_vec[3], UInt<10>("h0201")) @[el2_dec_tlu_ctl.scala 2407:21] + node _T_2035 = bits(_T_2034, 0, 0) @[el2_dec_tlu_ctl.scala 2407:49] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0202")) @[el2_dec_tlu_ctl.scala 2408:21] + node _T_2037 = bits(_T_2036, 0, 0) @[el2_dec_tlu_ctl.scala 2408:49] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0203")) @[el2_dec_tlu_ctl.scala 2409:21] + node _T_2039 = bits(_T_2038, 0, 0) @[el2_dec_tlu_ctl.scala 2409:49] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2410:21] + node _T_2041 = bits(_T_2040, 0, 0) @[el2_dec_tlu_ctl.scala 2410:49] + node _T_2042 = mux(_T_1875, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1877, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1879, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1881, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1885, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1891, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1896, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1898, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1900, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1902, _T_1903, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1914, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1952, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1966, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1968, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1970, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1972, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1974, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1976, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1978, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1980, _T_1982, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1984, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1988, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1990, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1992, _T_1994, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1996, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1998, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2000, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2002, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2004, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2006, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2008, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2010, _T_2013, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2015, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2033, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2035, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2037, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2039, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2041, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = or(_T_2042, _T_2043) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2044) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2045) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2046) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2047) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2048) @[Mux.scala 27:72] + node _T_2104 = or(_T_2103, _T_2049) @[Mux.scala 27:72] + node _T_2105 = or(_T_2104, _T_2050) @[Mux.scala 27:72] + node _T_2106 = or(_T_2105, _T_2051) @[Mux.scala 27:72] + node _T_2107 = or(_T_2106, _T_2052) @[Mux.scala 27:72] + node _T_2108 = or(_T_2107, _T_2053) @[Mux.scala 27:72] + node _T_2109 = or(_T_2108, _T_2054) @[Mux.scala 27:72] + node _T_2110 = or(_T_2109, _T_2055) @[Mux.scala 27:72] + node _T_2111 = or(_T_2110, _T_2056) @[Mux.scala 27:72] + node _T_2112 = or(_T_2111, _T_2057) @[Mux.scala 27:72] + node _T_2113 = or(_T_2112, _T_2058) @[Mux.scala 27:72] + node _T_2114 = or(_T_2113, _T_2059) @[Mux.scala 27:72] + node _T_2115 = or(_T_2114, _T_2060) @[Mux.scala 27:72] + node _T_2116 = or(_T_2115, _T_2061) @[Mux.scala 27:72] + node _T_2117 = or(_T_2116, _T_2062) @[Mux.scala 27:72] + node _T_2118 = or(_T_2117, _T_2063) @[Mux.scala 27:72] + node _T_2119 = or(_T_2118, _T_2064) @[Mux.scala 27:72] + node _T_2120 = or(_T_2119, _T_2065) @[Mux.scala 27:72] + node _T_2121 = or(_T_2120, _T_2066) @[Mux.scala 27:72] + node _T_2122 = or(_T_2121, _T_2067) @[Mux.scala 27:72] + node _T_2123 = or(_T_2122, _T_2068) @[Mux.scala 27:72] + node _T_2124 = or(_T_2123, _T_2069) @[Mux.scala 27:72] + node _T_2125 = or(_T_2124, _T_2070) @[Mux.scala 27:72] + node _T_2126 = or(_T_2125, _T_2071) @[Mux.scala 27:72] + node _T_2127 = or(_T_2126, _T_2072) @[Mux.scala 27:72] + node _T_2128 = or(_T_2127, _T_2073) @[Mux.scala 27:72] + node _T_2129 = or(_T_2128, _T_2074) @[Mux.scala 27:72] + node _T_2130 = or(_T_2129, _T_2075) @[Mux.scala 27:72] + node _T_2131 = or(_T_2130, _T_2076) @[Mux.scala 27:72] + node _T_2132 = or(_T_2131, _T_2077) @[Mux.scala 27:72] + node _T_2133 = or(_T_2132, _T_2078) @[Mux.scala 27:72] + node _T_2134 = or(_T_2133, _T_2079) @[Mux.scala 27:72] + node _T_2135 = or(_T_2134, _T_2080) @[Mux.scala 27:72] + node _T_2136 = or(_T_2135, _T_2081) @[Mux.scala 27:72] + node _T_2137 = or(_T_2136, _T_2082) @[Mux.scala 27:72] + node _T_2138 = or(_T_2137, _T_2083) @[Mux.scala 27:72] + node _T_2139 = or(_T_2138, _T_2084) @[Mux.scala 27:72] + node _T_2140 = or(_T_2139, _T_2085) @[Mux.scala 27:72] + node _T_2141 = or(_T_2140, _T_2086) @[Mux.scala 27:72] + node _T_2142 = or(_T_2141, _T_2087) @[Mux.scala 27:72] + node _T_2143 = or(_T_2142, _T_2088) @[Mux.scala 27:72] + node _T_2144 = or(_T_2143, _T_2089) @[Mux.scala 27:72] + node _T_2145 = or(_T_2144, _T_2090) @[Mux.scala 27:72] + node _T_2146 = or(_T_2145, _T_2091) @[Mux.scala 27:72] + node _T_2147 = or(_T_2146, _T_2092) @[Mux.scala 27:72] + node _T_2148 = or(_T_2147, _T_2093) @[Mux.scala 27:72] + node _T_2149 = or(_T_2148, _T_2094) @[Mux.scala 27:72] + node _T_2150 = or(_T_2149, _T_2095) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2096) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2097) @[Mux.scala 27:72] + wire _T_2153 : UInt<6> @[Mux.scala 27:72] + _T_2153 <= _T_2152 @[Mux.scala 27:72] + node _T_2154 = and(_T_1873, _T_2153) @[el2_dec_tlu_ctl.scala 2351:45] + mhpmc_inc_r[3] <= _T_2154 @[el2_dec_tlu_ctl.scala 2351:20] + reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2413:54] + _T_2155 <= mhpmc_inc_r[0] @[el2_dec_tlu_ctl.scala 2413:54] + mhpmc_inc_r_d1[0] <= _T_2155 @[el2_dec_tlu_ctl.scala 2413:21] + reg _T_2156 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2414:54] + _T_2156 <= mhpmc_inc_r[1] @[el2_dec_tlu_ctl.scala 2414:54] + mhpmc_inc_r_d1[1] <= _T_2156 @[el2_dec_tlu_ctl.scala 2414:21] + reg _T_2157 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2415:54] + _T_2157 <= mhpmc_inc_r[2] @[el2_dec_tlu_ctl.scala 2415:54] + mhpmc_inc_r_d1[2] <= _T_2157 @[el2_dec_tlu_ctl.scala 2415:21] + reg _T_2158 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2416:54] + _T_2158 <= mhpmc_inc_r[3] @[el2_dec_tlu_ctl.scala 2416:54] + mhpmc_inc_r_d1[3] <= _T_2158 @[el2_dec_tlu_ctl.scala 2416:21] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2417:57] + perfcnt_halted_d1 <= perfcnt_halted @[el2_dec_tlu_ctl.scala 2417:57] + node _T_2159 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2420:54] + node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[el2_dec_tlu_ctl.scala 2420:45] + node _T_2161 = or(_T_2160, io.dec_tlu_pmu_fw_halted) @[el2_dec_tlu_ctl.scala 2420:68] + perfcnt_halted <= _T_2161 @[el2_dec_tlu_ctl.scala 2420:18] + node _T_2162 = bits(io.dcsr, 10, 10) @[el2_dec_tlu_ctl.scala 2421:71] + node _T_2163 = and(io.dec_tlu_dbg_halted, _T_2162) @[el2_dec_tlu_ctl.scala 2421:62] + node _T_2164 = not(_T_2163) @[el2_dec_tlu_ctl.scala 2421:38] + node _T_2165 = bits(_T_2164, 0, 0) @[Bitwise.scala 72:15] + node _T_2166 = mux(_T_2165, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2167 = bits(mhpme_vec[3], 9, 9) @[el2_dec_tlu_ctl.scala 2421:105] + node _T_2168 = bits(mhpme_vec[2], 9, 9) @[el2_dec_tlu_ctl.scala 2421:121] + node _T_2169 = bits(mhpme_vec[1], 9, 9) @[el2_dec_tlu_ctl.scala 2421:137] + node _T_2170 = bits(mhpme_vec[0], 9, 9) @[el2_dec_tlu_ctl.scala 2421:153] + node _T_2171 = cat(_T_2169, _T_2170) @[Cat.scala 29:58] + node _T_2172 = cat(_T_2167, _T_2168) @[Cat.scala 29:58] + node _T_2173 = cat(_T_2172, _T_2171) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2166, _T_2173) @[el2_dec_tlu_ctl.scala 2421:87] + node _T_2174 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2423:89] + node _T_2175 = not(_T_2174) @[el2_dec_tlu_ctl.scala 2423:68] + node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[el2_dec_tlu_ctl.scala 2423:66] + node _T_2177 = not(_T_2176) @[el2_dec_tlu_ctl.scala 2423:46] + node _T_2178 = and(mhpmc_inc_r_d1[0], _T_2177) @[el2_dec_tlu_ctl.scala 2423:44] + io.dec_tlu_perfcnt0 <= _T_2178 @[el2_dec_tlu_ctl.scala 2423:23] + node _T_2179 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2424:89] + node _T_2180 = not(_T_2179) @[el2_dec_tlu_ctl.scala 2424:68] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[el2_dec_tlu_ctl.scala 2424:66] + node _T_2182 = not(_T_2181) @[el2_dec_tlu_ctl.scala 2424:46] + node _T_2183 = and(mhpmc_inc_r_d1[1], _T_2182) @[el2_dec_tlu_ctl.scala 2424:44] + io.dec_tlu_perfcnt1 <= _T_2183 @[el2_dec_tlu_ctl.scala 2424:23] + node _T_2184 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2425:89] + node _T_2185 = not(_T_2184) @[el2_dec_tlu_ctl.scala 2425:68] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[el2_dec_tlu_ctl.scala 2425:66] + node _T_2187 = not(_T_2186) @[el2_dec_tlu_ctl.scala 2425:46] + node _T_2188 = and(mhpmc_inc_r_d1[2], _T_2187) @[el2_dec_tlu_ctl.scala 2425:44] + io.dec_tlu_perfcnt2 <= _T_2188 @[el2_dec_tlu_ctl.scala 2425:23] + node _T_2189 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2426:89] + node _T_2190 = not(_T_2189) @[el2_dec_tlu_ctl.scala 2426:68] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[el2_dec_tlu_ctl.scala 2426:66] + node _T_2192 = not(_T_2191) @[el2_dec_tlu_ctl.scala 2426:46] + node _T_2193 = and(mhpmc_inc_r_d1[3], _T_2192) @[el2_dec_tlu_ctl.scala 2426:44] + io.dec_tlu_perfcnt3 <= _T_2193 @[el2_dec_tlu_ctl.scala 2426:23] + node _T_2194 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2432:66] + node _T_2195 = eq(_T_2194, UInt<12>("h0b03")) @[el2_dec_tlu_ctl.scala 2432:73] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2195) @[el2_dec_tlu_ctl.scala 2432:44] + node _T_2196 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2433:24] + node _T_2197 = bits(perfcnt_during_sleep, 0, 0) @[el2_dec_tlu_ctl.scala 2433:62] + node _T_2198 = or(_T_2196, _T_2197) @[el2_dec_tlu_ctl.scala 2433:40] + node _T_2199 = orr(mhpmc_inc_r[0]) @[el2_dec_tlu_ctl.scala 2433:87] + node mhpmc3_wr_en1 = and(_T_2198, _T_2199) @[el2_dec_tlu_ctl.scala 2433:67] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2434:37] + node _T_2200 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2437:29] + node _T_2201 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2437:42] + node _T_2202 = cat(_T_2200, _T_2201) @[Cat.scala 29:58] + node _T_2203 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2204 = add(_T_2202, _T_2203) @[el2_dec_tlu_ctl.scala 2437:50] + node _T_2205 = tail(_T_2204, 1) @[el2_dec_tlu_ctl.scala 2437:50] + mhpmc3_incr <= _T_2205 @[el2_dec_tlu_ctl.scala 2437:15] + node _T_2206 = bits(mhpmc3_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2438:37] + node _T_2207 = bits(mhpmc3_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2438:77] + node mhpmc3_ns = mux(_T_2206, io.dec_csr_wrdata_r, _T_2207) @[el2_dec_tlu_ctl.scala 2438:22] + node _T_2208 = bits(mhpmc3_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2440:43] + inst rvclkhdr_26 of rvclkhdr_34 @[el2_lib.scala 485:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_26.io.en <= _T_2208 @[el2_lib.scala 488:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2209 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2209 <= mhpmc3_ns @[el2_lib.scala 491:16] + mhpmc3 <= _T_2209 @[el2_dec_tlu_ctl.scala 2440:10] + node _T_2210 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2442:67] + node _T_2211 = eq(_T_2210, UInt<12>("h0b83")) @[el2_dec_tlu_ctl.scala 2442:74] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2211) @[el2_dec_tlu_ctl.scala 2442:45] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[el2_dec_tlu_ctl.scala 2443:39] + node _T_2212 = bits(mhpmc3h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2444:39] + node _T_2213 = bits(mhpmc3_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2444:79] + node mhpmc3h_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[el2_dec_tlu_ctl.scala 2444:23] + node _T_2214 = bits(mhpmc3h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2446:47] + inst rvclkhdr_27 of rvclkhdr_35 @[el2_lib.scala 485:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_27.io.en <= _T_2214 @[el2_lib.scala 488:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2215 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2215 <= mhpmc3h_ns @[el2_lib.scala 491:16] + mhpmc3h <= _T_2215 @[el2_dec_tlu_ctl.scala 2446:11] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2451:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b04")) @[el2_dec_tlu_ctl.scala 2451:73] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[el2_dec_tlu_ctl.scala 2451:44] + node _T_2218 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2452:24] + node _T_2219 = bits(perfcnt_during_sleep, 1, 1) @[el2_dec_tlu_ctl.scala 2452:62] + node _T_2220 = or(_T_2218, _T_2219) @[el2_dec_tlu_ctl.scala 2452:40] + node _T_2221 = orr(mhpmc_inc_r[1]) @[el2_dec_tlu_ctl.scala 2452:87] + node mhpmc4_wr_en1 = and(_T_2220, _T_2221) @[el2_dec_tlu_ctl.scala 2452:67] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2453:37] + node _T_2222 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2457:29] + node _T_2223 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2457:42] + node _T_2224 = cat(_T_2222, _T_2223) @[Cat.scala 29:58] + node _T_2225 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2226 = add(_T_2224, _T_2225) @[el2_dec_tlu_ctl.scala 2457:50] + node _T_2227 = tail(_T_2226, 1) @[el2_dec_tlu_ctl.scala 2457:50] + mhpmc4_incr <= _T_2227 @[el2_dec_tlu_ctl.scala 2457:15] + node _T_2228 = bits(mhpmc4_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2458:37] + node _T_2229 = bits(io.dec_csr_wrdata_r, 31, 0) @[el2_dec_tlu_ctl.scala 2458:64] + node _T_2230 = bits(mhpmc4_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2458:83] + node mhpmc4_ns = mux(_T_2228, _T_2229, _T_2230) @[el2_dec_tlu_ctl.scala 2458:22] + node _T_2231 = bits(mhpmc4_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2459:44] + inst rvclkhdr_28 of rvclkhdr_36 @[el2_lib.scala 485:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_28.io.en <= _T_2231 @[el2_lib.scala 488:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2232 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2232 <= mhpmc4_ns @[el2_lib.scala 491:16] + mhpmc4 <= _T_2232 @[el2_dec_tlu_ctl.scala 2459:10] + node _T_2233 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2461:67] + node _T_2234 = eq(_T_2233, UInt<12>("h0b84")) @[el2_dec_tlu_ctl.scala 2461:74] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2234) @[el2_dec_tlu_ctl.scala 2461:45] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[el2_dec_tlu_ctl.scala 2462:39] + node _T_2235 = bits(mhpmc4h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2463:39] + node _T_2236 = bits(mhpmc4_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2463:79] + node mhpmc4h_ns = mux(_T_2235, io.dec_csr_wrdata_r, _T_2236) @[el2_dec_tlu_ctl.scala 2463:23] + node _T_2237 = bits(mhpmc4h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2464:47] + inst rvclkhdr_29 of rvclkhdr_37 @[el2_lib.scala 485:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_29.io.en <= _T_2237 @[el2_lib.scala 488:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2238 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2238 <= mhpmc4h_ns @[el2_lib.scala 491:16] + mhpmc4h <= _T_2238 @[el2_dec_tlu_ctl.scala 2464:11] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2470:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b05")) @[el2_dec_tlu_ctl.scala 2470:73] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[el2_dec_tlu_ctl.scala 2470:44] + node _T_2241 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2471:24] + node _T_2242 = bits(perfcnt_during_sleep, 2, 2) @[el2_dec_tlu_ctl.scala 2471:62] + node _T_2243 = or(_T_2241, _T_2242) @[el2_dec_tlu_ctl.scala 2471:40] + node _T_2244 = orr(mhpmc_inc_r[2]) @[el2_dec_tlu_ctl.scala 2471:87] + node mhpmc5_wr_en1 = and(_T_2243, _T_2244) @[el2_dec_tlu_ctl.scala 2471:67] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2472:37] + node _T_2245 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2474:29] + node _T_2246 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2474:42] + node _T_2247 = cat(_T_2245, _T_2246) @[Cat.scala 29:58] + node _T_2248 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2249 = add(_T_2247, _T_2248) @[el2_dec_tlu_ctl.scala 2474:50] + node _T_2250 = tail(_T_2249, 1) @[el2_dec_tlu_ctl.scala 2474:50] + mhpmc5_incr <= _T_2250 @[el2_dec_tlu_ctl.scala 2474:15] + node _T_2251 = bits(mhpmc5_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2475:37] + node _T_2252 = bits(mhpmc5_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2475:77] + node mhpmc5_ns = mux(_T_2251, io.dec_csr_wrdata_r, _T_2252) @[el2_dec_tlu_ctl.scala 2475:22] + node _T_2253 = bits(mhpmc5_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2477:44] + inst rvclkhdr_30 of rvclkhdr_38 @[el2_lib.scala 485:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_30.io.en <= _T_2253 @[el2_lib.scala 488:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2254 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2254 <= mhpmc5_ns @[el2_lib.scala 491:16] + mhpmc5 <= _T_2254 @[el2_dec_tlu_ctl.scala 2477:10] + node _T_2255 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2479:67] + node _T_2256 = eq(_T_2255, UInt<12>("h0b85")) @[el2_dec_tlu_ctl.scala 2479:74] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2256) @[el2_dec_tlu_ctl.scala 2479:45] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[el2_dec_tlu_ctl.scala 2480:39] + node _T_2257 = bits(mhpmc5h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2481:39] + node _T_2258 = bits(mhpmc5_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2481:79] + node mhpmc5h_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[el2_dec_tlu_ctl.scala 2481:23] + node _T_2259 = bits(mhpmc5h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2483:47] + inst rvclkhdr_31 of rvclkhdr_39 @[el2_lib.scala 485:23] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_31.io.en <= _T_2259 @[el2_lib.scala 488:17] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2260 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2260 <= mhpmc5h_ns @[el2_lib.scala 491:16] + mhpmc5h <= _T_2260 @[el2_dec_tlu_ctl.scala 2483:11] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2488:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b06")) @[el2_dec_tlu_ctl.scala 2488:73] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[el2_dec_tlu_ctl.scala 2488:44] + node _T_2263 = not(perfcnt_halted) @[el2_dec_tlu_ctl.scala 2489:24] + node _T_2264 = bits(perfcnt_during_sleep, 3, 3) @[el2_dec_tlu_ctl.scala 2489:62] + node _T_2265 = or(_T_2263, _T_2264) @[el2_dec_tlu_ctl.scala 2489:40] + node _T_2266 = orr(mhpmc_inc_r[3]) @[el2_dec_tlu_ctl.scala 2489:87] + node mhpmc6_wr_en1 = and(_T_2265, _T_2266) @[el2_dec_tlu_ctl.scala 2489:67] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2490:37] + node _T_2267 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2492:29] + node _T_2268 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2492:42] + node _T_2269 = cat(_T_2267, _T_2268) @[Cat.scala 29:58] + node _T_2270 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2271 = add(_T_2269, _T_2270) @[el2_dec_tlu_ctl.scala 2492:50] + node _T_2272 = tail(_T_2271, 1) @[el2_dec_tlu_ctl.scala 2492:50] + mhpmc6_incr <= _T_2272 @[el2_dec_tlu_ctl.scala 2492:15] + node _T_2273 = bits(mhpmc6_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2493:37] + node _T_2274 = bits(mhpmc6_incr, 31, 0) @[el2_dec_tlu_ctl.scala 2493:77] + node mhpmc6_ns = mux(_T_2273, io.dec_csr_wrdata_r, _T_2274) @[el2_dec_tlu_ctl.scala 2493:22] + node _T_2275 = bits(mhpmc6_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2495:44] + inst rvclkhdr_32 of rvclkhdr_40 @[el2_lib.scala 485:23] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_32.io.en <= _T_2275 @[el2_lib.scala 488:17] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2276 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2276 <= mhpmc6_ns @[el2_lib.scala 491:16] + mhpmc6 <= _T_2276 @[el2_dec_tlu_ctl.scala 2495:10] + node _T_2277 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2497:67] + node _T_2278 = eq(_T_2277, UInt<12>("h0b86")) @[el2_dec_tlu_ctl.scala 2497:74] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2278) @[el2_dec_tlu_ctl.scala 2497:45] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[el2_dec_tlu_ctl.scala 2498:39] + node _T_2279 = bits(mhpmc6h_wr_en0, 0, 0) @[el2_dec_tlu_ctl.scala 2499:39] + node _T_2280 = bits(mhpmc6_incr, 63, 32) @[el2_dec_tlu_ctl.scala 2499:79] + node mhpmc6h_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[el2_dec_tlu_ctl.scala 2499:23] + node _T_2281 = bits(mhpmc6h_wr_en, 0, 0) @[el2_dec_tlu_ctl.scala 2501:47] + inst rvclkhdr_33 of rvclkhdr_41 @[el2_lib.scala 485:23] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[el2_lib.scala 487:18] + rvclkhdr_33.io.en <= _T_2281 @[el2_lib.scala 488:17] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24] + reg _T_2282 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16] + _T_2282 <= mhpmc6h_ns @[el2_lib.scala 491:16] + mhpmc6h <= _T_2282 @[el2_dec_tlu_ctl.scala 2501:11] + node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:51] + node _T_2284 = gt(_T_2283, UInt<10>("h0204")) @[el2_dec_tlu_ctl.scala 2508:57] + node _T_2285 = bits(io.dec_csr_wrdata_r, 31, 10) @[el2_dec_tlu_ctl.scala 2508:94] + node _T_2286 = orr(_T_2285) @[el2_dec_tlu_ctl.scala 2508:103] + node _T_2287 = or(_T_2284, _T_2286) @[el2_dec_tlu_ctl.scala 2508:72] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[el2_dec_tlu_ctl.scala 2508:142] + node event_saturate_r = mux(_T_2287, UInt<10>("h0204"), _T_2288) @[el2_dec_tlu_ctl.scala 2508:29] + node _T_2289 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2510:64] + node _T_2290 = eq(_T_2289, UInt<12>("h0323")) @[el2_dec_tlu_ctl.scala 2510:71] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2290) @[el2_dec_tlu_ctl.scala 2510:42] + node _T_2291 = bits(wr_mhpme3_r, 0, 0) @[el2_dec_tlu_ctl.scala 2512:81] + reg _T_2292 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2291 : @[Reg.scala 28:19] + _T_2292 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme3 <= _T_2292 @[el2_dec_tlu_ctl.scala 2512:10] + node _T_2293 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2517:64] + node _T_2294 = eq(_T_2293, UInt<12>("h0324")) @[el2_dec_tlu_ctl.scala 2517:71] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2294) @[el2_dec_tlu_ctl.scala 2517:42] + node _T_2295 = bits(wr_mhpme4_r, 0, 0) @[el2_dec_tlu_ctl.scala 2518:81] + reg _T_2296 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2295 : @[Reg.scala 28:19] + _T_2296 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme4 <= _T_2296 @[el2_dec_tlu_ctl.scala 2518:10] + node _T_2297 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2524:64] + node _T_2298 = eq(_T_2297, UInt<12>("h0325")) @[el2_dec_tlu_ctl.scala 2524:71] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2298) @[el2_dec_tlu_ctl.scala 2524:42] + node _T_2299 = bits(wr_mhpme5_r, 0, 0) @[el2_dec_tlu_ctl.scala 2525:81] + reg _T_2300 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2299 : @[Reg.scala 28:19] + _T_2300 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme5 <= _T_2300 @[el2_dec_tlu_ctl.scala 2525:10] + node _T_2301 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2531:64] + node _T_2302 = eq(_T_2301, UInt<12>("h0326")) @[el2_dec_tlu_ctl.scala 2531:71] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2302) @[el2_dec_tlu_ctl.scala 2531:42] + node _T_2303 = bits(wr_mhpme6_r, 0, 0) @[el2_dec_tlu_ctl.scala 2532:81] + reg _T_2304 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2303 : @[Reg.scala 28:19] + _T_2304 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme6 <= _T_2304 @[el2_dec_tlu_ctl.scala 2532:10] + node _T_2305 = bits(io.dec_csr_wraddr_r, 11, 0) @[el2_dec_tlu_ctl.scala 2548:71] + node _T_2306 = eq(_T_2305, UInt<12>("h0320")) @[el2_dec_tlu_ctl.scala 2548:78] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2306) @[el2_dec_tlu_ctl.scala 2548:49] + node _T_2307 = bits(mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2550:55] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_2307 + node _T_2308 = bits(mcountinhibit, 1, 1) @[el2_dec_tlu_ctl.scala 2551:55] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_2308 + node _T_2309 = bits(mcountinhibit, 6, 2) @[el2_dec_tlu_ctl.scala 2552:56] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_2309 + node _T_2310 = bits(io.dec_csr_wrdata_r, 6, 2) @[el2_dec_tlu_ctl.scala 2553:75] + node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2553:104] + reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2311 : @[Reg.scala 28:19] + _T_2312 <= _T_2310 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount6_2 <= _T_2312 @[el2_dec_tlu_ctl.scala 2553:18] + node _T_2313 = bits(io.dec_csr_wrdata_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:73] + node _T_2314 = bits(wr_mcountinhibit_r, 0, 0) @[el2_dec_tlu_ctl.scala 2555:100] + reg _T_2315 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2314 : @[Reg.scala 28:19] + _T_2315 <= _T_2313 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_2315 @[el2_dec_tlu_ctl.scala 2555:16] + node _T_2316 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2317 = cat(_T_2316, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2317 @[el2_dec_tlu_ctl.scala 2556:17] + node _T_2318 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:52] + node _T_2319 = or(_T_2318, io.interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 2563:79] + node _T_2320 = or(_T_2319, io.dec_tlu_i0_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:105] + node _T_2321 = or(_T_2320, io.dec_tlu_i0_exc_valid_wb1) @[el2_dec_tlu_ctl.scala 2563:131] + node _T_2322 = or(_T_2321, io.dec_tlu_int_valid_wb1) @[el2_dec_tlu_ctl.scala 2564:33] + node _T_2323 = or(_T_2322, io.clk_override) @[el2_dec_tlu_ctl.scala 2564:60] + node _T_2324 = bits(_T_2323, 0, 0) @[el2_dec_tlu_ctl.scala 2564:79] + inst rvclkhdr_34 of rvclkhdr_42 @[el2_lib.scala 474:22] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_34.io.en <= _T_2324 @[el2_lib.scala 476:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2566:63] + _T_2325 <= io.i0_valid_wb @[el2_dec_tlu_ctl.scala 2566:63] + io.dec_tlu_i0_valid_wb1 <= _T_2325 @[el2_dec_tlu_ctl.scala 2566:31] + node _T_2326 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[el2_dec_tlu_ctl.scala 2567:92] + node _T_2327 = not(io.trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 2567:138] + node _T_2328 = and(io.trigger_hit_r_d1, _T_2327) @[el2_dec_tlu_ctl.scala 2567:136] + node _T_2329 = or(_T_2326, _T_2328) @[el2_dec_tlu_ctl.scala 2567:113] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2567:63] + _T_2330 <= _T_2329 @[el2_dec_tlu_ctl.scala 2567:63] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2330 @[el2_dec_tlu_ctl.scala 2567:31] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2568:63] + _T_2331 <= io.exc_cause_wb @[el2_dec_tlu_ctl.scala 2568:63] + io.dec_tlu_exc_cause_wb1 <= _T_2331 @[el2_dec_tlu_ctl.scala 2568:31] + reg _T_2332 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 2569:63] + _T_2332 <= io.interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 2569:63] + io.dec_tlu_int_valid_wb1 <= _T_2332 @[el2_dec_tlu_ctl.scala 2569:31] + io.dec_tlu_mtval_wb1 <= mtval @[el2_dec_tlu_ctl.scala 2571:25] + node _T_2333 = bits(io.csr_pkt.csr_misa, 0, 0) @[el2_dec_tlu_ctl.scala 2577:25] + node _T_2334 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[el2_dec_tlu_ctl.scala 2578:30] + node _T_2335 = bits(io.csr_pkt.csr_marchid, 0, 0) @[el2_dec_tlu_ctl.scala 2579:28] + node _T_2336 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[el2_dec_tlu_ctl.scala 2580:27] + node _T_2337 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[el2_dec_tlu_ctl.scala 2581:28] + node _T_2338 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2339 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:28] + node _T_2340 = bits(io.mstatus, 1, 1) @[el2_dec_tlu_ctl.scala 2582:91] + node _T_2341 = bits(io.mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 2582:116] + node _T_2342 = cat(UInt<3>("h00"), _T_2341) @[Cat.scala 29:58] + node _T_2343 = cat(_T_2342, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2344 = cat(UInt<3>("h00"), _T_2340) @[Cat.scala 29:58] + node _T_2345 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2346 = cat(_T_2345, _T_2344) @[Cat.scala 29:58] + node _T_2347 = cat(_T_2346, _T_2343) @[Cat.scala 29:58] + node _T_2348 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:26] + node _T_2349 = bits(io.mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 2583:58] + node _T_2350 = bits(io.mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 2583:84] + node _T_2351 = cat(_T_2349, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:24] + node _T_2354 = bits(io.mip, 5, 3) @[el2_dec_tlu_ctl.scala 2584:66] + node _T_2355 = bits(io.mip, 2, 2) @[el2_dec_tlu_ctl.scala 2584:90] + node _T_2356 = bits(io.mip, 1, 1) @[el2_dec_tlu_ctl.scala 2584:111] + node _T_2357 = bits(io.mip, 0, 0) @[el2_dec_tlu_ctl.scala 2584:132] + node _T_2358 = cat(_T_2357, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2359 = cat(_T_2356, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, _T_2358) @[Cat.scala 29:58] + node _T_2361 = cat(_T_2355, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2362 = cat(UInt<1>("h00"), _T_2354) @[Cat.scala 29:58] + node _T_2363 = cat(_T_2362, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2363, _T_2361) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2360) @[Cat.scala 29:58] + node _T_2366 = bits(io.csr_pkt.csr_mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:24] + node _T_2367 = bits(mie, 5, 3) @[el2_dec_tlu_ctl.scala 2585:63] + node _T_2368 = bits(mie, 2, 2) @[el2_dec_tlu_ctl.scala 2585:84] + node _T_2369 = bits(mie, 1, 1) @[el2_dec_tlu_ctl.scala 2585:102] + node _T_2370 = bits(mie, 0, 0) @[el2_dec_tlu_ctl.scala 2585:120] + node _T_2371 = cat(_T_2370, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2372 = cat(_T_2369, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, _T_2371) @[Cat.scala 29:58] + node _T_2374 = cat(_T_2368, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2375 = cat(UInt<1>("h00"), _T_2367) @[Cat.scala 29:58] + node _T_2376 = cat(_T_2375, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2376, _T_2374) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2373) @[Cat.scala 29:58] + node _T_2379 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[el2_dec_tlu_ctl.scala 2586:28] + node _T_2380 = bits(mcyclel, 31, 0) @[el2_dec_tlu_ctl.scala 2586:53] + node _T_2381 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[el2_dec_tlu_ctl.scala 2587:28] + node _T_2382 = bits(mcycleh_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2587:57] + node _T_2383 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[el2_dec_tlu_ctl.scala 2588:30] + node _T_2384 = bits(minstretl, 31, 0) @[el2_dec_tlu_ctl.scala 2588:60] + node _T_2385 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[el2_dec_tlu_ctl.scala 2589:30] + node _T_2386 = bits(minstreth_inc, 31, 0) @[el2_dec_tlu_ctl.scala 2589:60] + node _T_2387 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[el2_dec_tlu_ctl.scala 2590:29] + node _T_2388 = bits(mscratch, 31, 0) @[el2_dec_tlu_ctl.scala 2590:54] + node _T_2389 = bits(io.csr_pkt.csr_mepc, 0, 0) @[el2_dec_tlu_ctl.scala 2591:25] + node _T_2390 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2391 = bits(io.csr_pkt.csr_mcause, 0, 0) @[el2_dec_tlu_ctl.scala 2592:27] + node _T_2392 = bits(mcause, 31, 0) @[el2_dec_tlu_ctl.scala 2592:52] + node _T_2393 = bits(io.csr_pkt.csr_mscause, 0, 0) @[el2_dec_tlu_ctl.scala 2593:28] + node _T_2394 = bits(mscause, 3, 0) @[el2_dec_tlu_ctl.scala 2593:68] + node _T_2395 = cat(UInt<28>("h00"), _T_2394) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mtval, 0, 0) @[el2_dec_tlu_ctl.scala 2594:26] + node _T_2397 = bits(mtval, 31, 0) @[el2_dec_tlu_ctl.scala 2594:51] + node _T_2398 = bits(io.csr_pkt.csr_mrac, 0, 0) @[el2_dec_tlu_ctl.scala 2595:25] + node _T_2399 = bits(mrac, 31, 0) @[el2_dec_tlu_ctl.scala 2595:50] + node _T_2400 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[el2_dec_tlu_ctl.scala 2596:27] + node _T_2401 = bits(mdseac, 31, 0) @[el2_dec_tlu_ctl.scala 2596:52] + node _T_2402 = bits(io.csr_pkt.csr_meivt, 0, 0) @[el2_dec_tlu_ctl.scala 2597:26] + node _T_2403 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2404 = bits(io.csr_pkt.csr_meihap, 0, 0) @[el2_dec_tlu_ctl.scala 2598:27] + node _T_2405 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2406 = cat(_T_2405, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2407 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[el2_dec_tlu_ctl.scala 2599:29] + node _T_2408 = bits(meicurpl, 3, 0) @[el2_dec_tlu_ctl.scala 2599:69] + node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[el2_dec_tlu_ctl.scala 2600:29] + node _T_2411 = bits(meicidpl, 3, 0) @[el2_dec_tlu_ctl.scala 2600:69] + node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meipt, 0, 0) @[el2_dec_tlu_ctl.scala 2601:26] + node _T_2414 = bits(meipt, 3, 0) @[el2_dec_tlu_ctl.scala 2601:66] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[el2_dec_tlu_ctl.scala 2602:25] + node _T_2417 = bits(mcgc, 8, 0) @[el2_dec_tlu_ctl.scala 2602:65] + node _T_2418 = cat(UInt<23>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[el2_dec_tlu_ctl.scala 2603:25] + node _T_2420 = bits(mfdc, 18, 0) @[el2_dec_tlu_ctl.scala 2603:65] + node _T_2421 = cat(UInt<13>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[el2_dec_tlu_ctl.scala 2604:25] + node _T_2423 = bits(io.dcsr, 15, 2) @[el2_dec_tlu_ctl.scala 2604:73] + node _T_2424 = cat(UInt<16>("h04000"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = cat(_T_2424, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2426 = bits(io.csr_pkt.csr_dpc, 0, 0) @[el2_dec_tlu_ctl.scala 2605:24] + node _T_2427 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[el2_dec_tlu_ctl.scala 2606:27] + node _T_2429 = bits(dicad0, 31, 0) @[el2_dec_tlu_ctl.scala 2606:52] + node _T_2430 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[el2_dec_tlu_ctl.scala 2607:28] + node _T_2431 = bits(dicad0h, 31, 0) @[el2_dec_tlu_ctl.scala 2607:53] + node _T_2432 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[el2_dec_tlu_ctl.scala 2608:27] + node _T_2433 = bits(dicad1, 31, 0) @[el2_dec_tlu_ctl.scala 2608:52] + node _T_2434 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[el2_dec_tlu_ctl.scala 2609:29] + node _T_2435 = bits(dicawics, 16, 16) @[el2_dec_tlu_ctl.scala 2609:68] + node _T_2436 = bits(dicawics, 15, 14) @[el2_dec_tlu_ctl.scala 2609:92] + node _T_2437 = bits(dicawics, 13, 0) @[el2_dec_tlu_ctl.scala 2609:119] + node _T_2438 = cat(UInt<3>("h00"), _T_2437) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2440 = cat(UInt<2>("h00"), _T_2436) @[Cat.scala 29:58] + node _T_2441 = cat(UInt<7>("h00"), _T_2435) @[Cat.scala 29:58] + node _T_2442 = cat(_T_2441, _T_2440) @[Cat.scala 29:58] + node _T_2443 = cat(_T_2442, _T_2439) @[Cat.scala 29:58] + node _T_2444 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[el2_dec_tlu_ctl.scala 2610:26] + node _T_2445 = bits(mtsel, 1, 0) @[el2_dec_tlu_ctl.scala 2610:66] + node _T_2446 = cat(UInt<30>("h00"), _T_2445) @[Cat.scala 29:58] + node _T_2447 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[el2_dec_tlu_ctl.scala 2611:28] + node _T_2448 = bits(mtdata1_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2611:62] + node _T_2449 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[el2_dec_tlu_ctl.scala 2612:28] + node _T_2450 = bits(mtdata2_tsel_out, 31, 0) @[el2_dec_tlu_ctl.scala 2612:62] + node _T_2451 = bits(io.csr_pkt.csr_micect, 0, 0) @[el2_dec_tlu_ctl.scala 2613:27] + node _T_2452 = bits(micect, 31, 0) @[el2_dec_tlu_ctl.scala 2613:52] + node _T_2453 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2614:29] + node _T_2454 = bits(miccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2614:54] + node _T_2455 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[el2_dec_tlu_ctl.scala 2615:29] + node _T_2456 = bits(mdccmect, 31, 0) @[el2_dec_tlu_ctl.scala 2615:54] + node _T_2457 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[el2_dec_tlu_ctl.scala 2616:27] + node _T_2458 = bits(mhpmc3, 31, 0) @[el2_dec_tlu_ctl.scala 2616:52] + node _T_2459 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[el2_dec_tlu_ctl.scala 2617:27] + node _T_2460 = bits(mhpmc4, 31, 0) @[el2_dec_tlu_ctl.scala 2617:52] + node _T_2461 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[el2_dec_tlu_ctl.scala 2618:27] + node _T_2462 = bits(mhpmc5, 31, 0) @[el2_dec_tlu_ctl.scala 2618:52] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[el2_dec_tlu_ctl.scala 2619:27] + node _T_2464 = bits(mhpmc6, 31, 0) @[el2_dec_tlu_ctl.scala 2619:52] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[el2_dec_tlu_ctl.scala 2620:28] + node _T_2466 = bits(mhpmc3h, 31, 0) @[el2_dec_tlu_ctl.scala 2620:53] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[el2_dec_tlu_ctl.scala 2621:28] + node _T_2468 = bits(mhpmc4h, 31, 0) @[el2_dec_tlu_ctl.scala 2621:53] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[el2_dec_tlu_ctl.scala 2622:28] + node _T_2470 = bits(mhpmc5h, 31, 0) @[el2_dec_tlu_ctl.scala 2622:53] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[el2_dec_tlu_ctl.scala 2623:28] + node _T_2472 = bits(mhpmc6h, 31, 0) @[el2_dec_tlu_ctl.scala 2623:53] + node _T_2473 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[el2_dec_tlu_ctl.scala 2624:26] + node _T_2474 = bits(mfdht, 5, 0) @[el2_dec_tlu_ctl.scala 2624:66] + node _T_2475 = cat(UInt<26>("h00"), _T_2474) @[Cat.scala 29:58] + node _T_2476 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[el2_dec_tlu_ctl.scala 2625:26] + node _T_2477 = bits(mfdhs, 1, 0) @[el2_dec_tlu_ctl.scala 2625:66] + node _T_2478 = cat(UInt<30>("h00"), _T_2477) @[Cat.scala 29:58] + node _T_2479 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[el2_dec_tlu_ctl.scala 2626:27] + node _T_2480 = bits(mhpme3, 9, 0) @[el2_dec_tlu_ctl.scala 2626:67] + node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[el2_dec_tlu_ctl.scala 2627:27] + node _T_2483 = bits(mhpme4, 9, 0) @[el2_dec_tlu_ctl.scala 2627:67] + node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[el2_dec_tlu_ctl.scala 2628:27] + node _T_2486 = bits(mhpme5, 9, 0) @[el2_dec_tlu_ctl.scala 2628:66] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[el2_dec_tlu_ctl.scala 2629:27] + node _T_2489 = bits(mhpme6, 9, 0) @[el2_dec_tlu_ctl.scala 2629:66] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[el2_dec_tlu_ctl.scala 2630:34] + node _T_2492 = bits(mcountinhibit, 6, 0) @[el2_dec_tlu_ctl.scala 2630:74] + node _T_2493 = cat(UInt<25>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[el2_dec_tlu_ctl.scala 2631:25] + node _T_2495 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2496 = cat(_T_2495, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2497 = bits(io.dec_timer_read_d, 0, 0) @[el2_dec_tlu_ctl.scala 2632:25] + node _T_2498 = bits(io.dec_timer_rddata_d, 31, 0) @[el2_dec_tlu_ctl.scala 2632:64] + node _T_2499 = mux(_T_2333, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2334, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2335, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2336, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2337, _T_2338, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2339, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2348, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2353, _T_2365, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2366, _T_2378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2379, _T_2380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2381, _T_2382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2383, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2393, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2398, _T_2399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2400, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2422, _T_2425, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2426, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2428, _T_2429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2430, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2434, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2444, _T_2446, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2447, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2449, _T_2450, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2451, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2497, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = or(_T_2499, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] + node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] + node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] + node _T_2565 = or(_T_2564, _T_2510) @[Mux.scala 27:72] + node _T_2566 = or(_T_2565, _T_2511) @[Mux.scala 27:72] + node _T_2567 = or(_T_2566, _T_2512) @[Mux.scala 27:72] + node _T_2568 = or(_T_2567, _T_2513) @[Mux.scala 27:72] + node _T_2569 = or(_T_2568, _T_2514) @[Mux.scala 27:72] + node _T_2570 = or(_T_2569, _T_2515) @[Mux.scala 27:72] + node _T_2571 = or(_T_2570, _T_2516) @[Mux.scala 27:72] + node _T_2572 = or(_T_2571, _T_2517) @[Mux.scala 27:72] + node _T_2573 = or(_T_2572, _T_2518) @[Mux.scala 27:72] + node _T_2574 = or(_T_2573, _T_2519) @[Mux.scala 27:72] + node _T_2575 = or(_T_2574, _T_2520) @[Mux.scala 27:72] + node _T_2576 = or(_T_2575, _T_2521) @[Mux.scala 27:72] + node _T_2577 = or(_T_2576, _T_2522) @[Mux.scala 27:72] + node _T_2578 = or(_T_2577, _T_2523) @[Mux.scala 27:72] + node _T_2579 = or(_T_2578, _T_2524) @[Mux.scala 27:72] + node _T_2580 = or(_T_2579, _T_2525) @[Mux.scala 27:72] + node _T_2581 = or(_T_2580, _T_2526) @[Mux.scala 27:72] + node _T_2582 = or(_T_2581, _T_2527) @[Mux.scala 27:72] + node _T_2583 = or(_T_2582, _T_2528) @[Mux.scala 27:72] + node _T_2584 = or(_T_2583, _T_2529) @[Mux.scala 27:72] + node _T_2585 = or(_T_2584, _T_2530) @[Mux.scala 27:72] + node _T_2586 = or(_T_2585, _T_2531) @[Mux.scala 27:72] + node _T_2587 = or(_T_2586, _T_2532) @[Mux.scala 27:72] + node _T_2588 = or(_T_2587, _T_2533) @[Mux.scala 27:72] + node _T_2589 = or(_T_2588, _T_2534) @[Mux.scala 27:72] + node _T_2590 = or(_T_2589, _T_2535) @[Mux.scala 27:72] + node _T_2591 = or(_T_2590, _T_2536) @[Mux.scala 27:72] + node _T_2592 = or(_T_2591, _T_2537) @[Mux.scala 27:72] + node _T_2593 = or(_T_2592, _T_2538) @[Mux.scala 27:72] + node _T_2594 = or(_T_2593, _T_2539) @[Mux.scala 27:72] + node _T_2595 = or(_T_2594, _T_2540) @[Mux.scala 27:72] + node _T_2596 = or(_T_2595, _T_2541) @[Mux.scala 27:72] + node _T_2597 = or(_T_2596, _T_2542) @[Mux.scala 27:72] + node _T_2598 = or(_T_2597, _T_2543) @[Mux.scala 27:72] + node _T_2599 = or(_T_2598, _T_2544) @[Mux.scala 27:72] + node _T_2600 = or(_T_2599, _T_2545) @[Mux.scala 27:72] + node _T_2601 = or(_T_2600, _T_2546) @[Mux.scala 27:72] + node _T_2602 = or(_T_2601, _T_2547) @[Mux.scala 27:72] + node _T_2603 = or(_T_2602, _T_2548) @[Mux.scala 27:72] + node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] + node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] + node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + wire _T_2610 : UInt @[Mux.scala 27:72] + _T_2610 <= _T_2609 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2610 @[el2_dec_tlu_ctl.scala 2576:22] + + module el2_dec_decode_csr_read : + input clock : Clock + input reset : Reset + output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1 = eq(_T, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_9 = and(_T_1, _T_3) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_10 = and(_T_9, _T_5) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_11 = and(_T_10, _T_7) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_12 = and(_T_11, _T_8) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_misa <= _T_12 @[el2_dec_tlu_ctl.scala 2650:49] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_19 = and(_T_13, _T_15) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_20 = and(_T_19, _T_17) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_21 = and(_T_20, _T_18) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mvendorid <= _T_21 @[el2_dec_tlu_ctl.scala 2651:49] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_28 = and(_T_22, _T_24) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_29 = and(_T_28, _T_25) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_30 = and(_T_29, _T_27) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_marchid <= _T_30 @[el2_dec_tlu_ctl.scala 2652:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_36 = and(_T_31, _T_33) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_37 = and(_T_36, _T_34) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_38 = and(_T_37, _T_35) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mimpid <= _T_38 @[el2_dec_tlu_ctl.scala 2653:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_43 = and(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_44 = and(_T_43, _T_42) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhartid <= _T_44 @[el2_dec_tlu_ctl.scala 2654:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_55 = and(_T_46, _T_48) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_56 = and(_T_55, _T_50) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_57 = and(_T_56, _T_52) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_58 = and(_T_57, _T_54) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mstatus <= _T_58 @[el2_dec_tlu_ctl.scala 2655:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_67 = and(_T_60, _T_62) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_68 = and(_T_67, _T_64) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_69 = and(_T_68, _T_65) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_70 = and(_T_69, _T_66) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtvec <= _T_70 @[el2_dec_tlu_ctl.scala 2656:49] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_75 = and(_T_72, _T_73) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_76 = and(_T_75, _T_74) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mip <= _T_76 @[el2_dec_tlu_ctl.scala 2657:57] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_86 = and(_T_78, _T_80) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_87 = and(_T_86, _T_82) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_88 = and(_T_87, _T_83) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_89 = and(_T_88, _T_85) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mie <= _T_89 @[el2_dec_tlu_ctl.scala 2658:57] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_101 = and(_T_90, _T_92) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_102 = and(_T_101, _T_94) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_103 = and(_T_102, _T_96) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_104 = and(_T_103, _T_98) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_105 = and(_T_104, _T_100) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcyclel <= _T_105 @[el2_dec_tlu_ctl.scala 2659:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_119 = and(_T_106, _T_108) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_120 = and(_T_119, _T_110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_121 = and(_T_120, _T_112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_122 = and(_T_121, _T_114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_123 = and(_T_122, _T_116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_124 = and(_T_123, _T_118) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcycleh <= _T_124 @[el2_dec_tlu_ctl.scala 2660:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_138 = and(_T_126, _T_128) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_139 = and(_T_138, _T_130) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_140 = and(_T_139, _T_132) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_141 = and(_T_140, _T_134) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_142 = and(_T_141, _T_135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_143 = and(_T_142, _T_137) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstretl <= _T_143 @[el2_dec_tlu_ctl.scala 2661:49] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_156 = and(_T_145, _T_146) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_157 = and(_T_156, _T_148) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_158 = and(_T_157, _T_150) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_159 = and(_T_158, _T_152) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_160 = and(_T_159, _T_153) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_161 = and(_T_160, _T_155) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_minstreth <= _T_161 @[el2_dec_tlu_ctl.scala 2662:49] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_171 = and(_T_163, _T_164) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_172 = and(_T_171, _T_166) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_173 = and(_T_172, _T_168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_174 = and(_T_173, _T_170) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscratch <= _T_174 @[el2_dec_tlu_ctl.scala 2663:49] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_181 = and(_T_176, _T_177) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_182 = and(_T_181, _T_179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_183 = and(_T_182, _T_180) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mepc <= _T_183 @[el2_dec_tlu_ctl.scala 2664:49] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_190 = and(_T_185, _T_186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_191 = and(_T_190, _T_187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_192 = and(_T_191, _T_189) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcause <= _T_192 @[el2_dec_tlu_ctl.scala 2665:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_196 = and(_T_193, _T_194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_197 = and(_T_196, _T_195) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mscause <= _T_197 @[el2_dec_tlu_ctl.scala 2666:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_203 = and(_T_199, _T_200) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_204 = and(_T_203, _T_201) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_205 = and(_T_204, _T_202) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtval <= _T_205 @[el2_dec_tlu_ctl.scala 2667:49] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_217 = and(_T_207, _T_208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_218 = and(_T_217, _T_210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_219 = and(_T_218, _T_212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_220 = and(_T_219, _T_214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_221 = and(_T_220, _T_216) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mrac <= _T_221 @[el2_dec_tlu_ctl.scala 2668:49] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_230 = and(_T_222, _T_224) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_231 = and(_T_230, _T_226) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_232 = and(_T_231, _T_227) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_233 = and(_T_232, _T_229) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dmst <= _T_233 @[el2_dec_tlu_ctl.scala 2669:49] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_240 = and(_T_234, _T_235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_241 = and(_T_240, _T_237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_242 = and(_T_241, _T_239) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdseac <= _T_242 @[el2_dec_tlu_ctl.scala 2670:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_246 = and(_T_243, _T_244) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_247 = and(_T_246, _T_245) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meihap <= _T_247 @[el2_dec_tlu_ctl.scala 2671:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_258 = and(_T_249, _T_250) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_259 = and(_T_258, _T_251) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_260 = and(_T_259, _T_253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_261 = and(_T_260, _T_255) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_262 = and(_T_261, _T_257) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meivt <= _T_262 @[el2_dec_tlu_ctl.scala 2672:49] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_268 = and(_T_263, _T_264) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_269 = and(_T_268, _T_266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_270 = and(_T_269, _T_267) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meipt <= _T_270 @[el2_dec_tlu_ctl.scala 2673:49] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_274 = and(_T_271, _T_272) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_275 = and(_T_274, _T_273) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicurpl <= _T_275 @[el2_dec_tlu_ctl.scala 2674:49] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_280 = and(_T_276, _T_277) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_281 = and(_T_280, _T_278) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_282 = and(_T_281, _T_279) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicidpl <= _T_282 @[el2_dec_tlu_ctl.scala 2675:49] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_290 = and(_T_283, _T_285) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_291 = and(_T_290, _T_286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_292 = and(_T_291, _T_287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_293 = and(_T_292, _T_289) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dcsr <= _T_293 @[el2_dec_tlu_ctl.scala 2676:49] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_299 = and(_T_294, _T_295) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_300 = and(_T_299, _T_296) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_301 = and(_T_300, _T_298) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcgc <= _T_301 @[el2_dec_tlu_ctl.scala 2677:49] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_308 = and(_T_302, _T_303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_309 = and(_T_308, _T_304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_310 = and(_T_309, _T_306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_311 = and(_T_310, _T_307) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdc <= _T_311 @[el2_dec_tlu_ctl.scala 2678:49] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_318 = and(_T_312, _T_314) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_319 = and(_T_318, _T_315) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_320 = and(_T_319, _T_316) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_321 = and(_T_320, _T_317) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dpc <= _T_321 @[el2_dec_tlu_ctl.scala 2679:57] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_330 = and(_T_322, _T_323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_331 = and(_T_330, _T_325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_332 = and(_T_331, _T_327) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_333 = and(_T_332, _T_329) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtsel <= _T_333 @[el2_dec_tlu_ctl.scala 2680:49] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_340 = and(_T_334, _T_336) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_341 = and(_T_340, _T_338) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_342 = and(_T_341, _T_339) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata1 <= _T_342 @[el2_dec_tlu_ctl.scala 2681:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_348 = and(_T_343, _T_344) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_349 = and(_T_348, _T_346) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_350 = and(_T_349, _T_347) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mtdata2 <= _T_350 @[el2_dec_tlu_ctl.scala 2682:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_361 = and(_T_351, _T_353) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_362 = and(_T_361, _T_355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_363 = and(_T_362, _T_357) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_364 = and(_T_363, _T_359) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_365 = and(_T_364, _T_360) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[el2_dec_tlu_ctl.scala 2683:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_378 = and(_T_366, _T_368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_379 = and(_T_378, _T_370) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_380 = and(_T_379, _T_372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_381 = and(_T_380, _T_373) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_382 = and(_T_381, _T_375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_383 = and(_T_382, _T_377) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[el2_dec_tlu_ctl.scala 2684:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_394 = and(_T_384, _T_386) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_395 = and(_T_394, _T_388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_396 = and(_T_395, _T_390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_397 = and(_T_396, _T_392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_398 = and(_T_397, _T_393) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[el2_dec_tlu_ctl.scala 2685:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_411 = and(_T_400, _T_402) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_412 = and(_T_411, _T_404) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_413 = and(_T_412, _T_406) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_414 = and(_T_413, _T_407) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_415 = and(_T_414, _T_408) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_416 = and(_T_415, _T_410) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[el2_dec_tlu_ctl.scala 2686:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_426 = and(_T_417, _T_419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_427 = and(_T_426, _T_421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_428 = and(_T_427, _T_423) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_429 = and(_T_428, _T_424) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_430 = and(_T_429, _T_425) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[el2_dec_tlu_ctl.scala 2687:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_443 = and(_T_431, _T_433) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_444 = and(_T_443, _T_435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_445 = and(_T_444, _T_437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_446 = and(_T_445, _T_438) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_447 = and(_T_446, _T_440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_448 = and(_T_447, _T_442) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[el2_dec_tlu_ctl.scala 2688:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_458 = and(_T_449, _T_451) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_459 = and(_T_458, _T_453) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_460 = and(_T_459, _T_454) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_461 = and(_T_460, _T_456) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_462 = and(_T_461, _T_457) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[el2_dec_tlu_ctl.scala 2689:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_474 = and(_T_463, _T_465) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_475 = and(_T_474, _T_467) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_476 = and(_T_475, _T_469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_477 = and(_T_476, _T_470) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_478 = and(_T_477, _T_471) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_479 = and(_T_478, _T_473) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[el2_dec_tlu_ctl.scala 2690:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_490 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_491 = and(_T_490, _T_484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_492 = and(_T_491, _T_486) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_493 = and(_T_492, _T_488) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_494 = and(_T_493, _T_489) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme3 <= _T_494 @[el2_dec_tlu_ctl.scala 2691:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_505 = and(_T_495, _T_497) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_506 = and(_T_505, _T_499) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_507 = and(_T_506, _T_500) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_508 = and(_T_507, _T_502) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_509 = and(_T_508, _T_504) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme4 <= _T_509 @[el2_dec_tlu_ctl.scala 2692:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_519 = and(_T_510, _T_512) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_520 = and(_T_519, _T_514) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_521 = and(_T_520, _T_515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_522 = and(_T_521, _T_517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_523 = and(_T_522, _T_518) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme5 <= _T_523 @[el2_dec_tlu_ctl.scala 2693:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_533 = and(_T_524, _T_526) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_534 = and(_T_533, _T_528) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_535 = and(_T_534, _T_529) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_536 = and(_T_535, _T_530) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_537 = and(_T_536, _T_532) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mhpme6 <= _T_537 @[el2_dec_tlu_ctl.scala 2694:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_549 = and(_T_539, _T_540) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_550 = and(_T_549, _T_542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_551 = and(_T_550, _T_544) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_552 = and(_T_551, _T_546) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_553 = and(_T_552, _T_548) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[el2_dec_tlu_ctl.scala 2695:41] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_562 = and(_T_554, _T_556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_563 = and(_T_562, _T_557) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_564 = and(_T_563, _T_559) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_565 = and(_T_564, _T_561) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl0 <= _T_565 @[el2_dec_tlu_ctl.scala 2696:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_572 = and(_T_566, _T_568) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_573 = and(_T_572, _T_569) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_574 = and(_T_573, _T_570) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_575 = and(_T_574, _T_571) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitctl1 <= _T_575 @[el2_dec_tlu_ctl.scala 2697:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_583 = and(_T_576, _T_578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_584 = and(_T_583, _T_579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_585 = and(_T_584, _T_581) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_586 = and(_T_585, _T_582) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb0 <= _T_586 @[el2_dec_tlu_ctl.scala 2698:49] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_593 = and(_T_587, _T_588) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_594 = and(_T_593, _T_589) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_595 = and(_T_594, _T_590) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_596 = and(_T_595, _T_592) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitb1 <= _T_596 @[el2_dec_tlu_ctl.scala 2699:49] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_605 = and(_T_597, _T_599) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_606 = and(_T_605, _T_600) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_607 = and(_T_606, _T_602) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_608 = and(_T_607, _T_604) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[el2_dec_tlu_ctl.scala 2700:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_614 = and(_T_609, _T_610) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_615 = and(_T_614, _T_612) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_616 = and(_T_615, _T_613) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[el2_dec_tlu_ctl.scala 2701:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_624 = and(_T_617, _T_619) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_625 = and(_T_624, _T_621) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_626 = and(_T_625, _T_622) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_627 = and(_T_626, _T_623) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mpmc <= _T_627 @[el2_dec_tlu_ctl.scala 2702:49] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_637 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_638 = and(_T_637, _T_631) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_639 = and(_T_638, _T_633) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_640 = and(_T_639, _T_635) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_641 = and(_T_640, _T_636) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mcpc <= _T_641 @[el2_dec_tlu_ctl.scala 2703:49] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_647 = and(_T_642, _T_643) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_648 = and(_T_647, _T_644) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_649 = and(_T_648, _T_646) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_meicpct <= _T_649 @[el2_dec_tlu_ctl.scala 2704:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_656 = and(_T_651, _T_652) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_657 = and(_T_656, _T_653) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_658 = and(_T_657, _T_655) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdeau <= _T_658 @[el2_dec_tlu_ctl.scala 2705:49] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_667 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_668 = and(_T_667, _T_662) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_669 = and(_T_668, _T_664) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_670 = and(_T_669, _T_666) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_micect <= _T_670 @[el2_dec_tlu_ctl.scala 2706:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_676 = and(_T_671, _T_672) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_677 = and(_T_676, _T_674) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_678 = and(_T_677, _T_675) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_miccmect <= _T_678 @[el2_dec_tlu_ctl.scala 2707:49] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_684 = and(_T_679, _T_680) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_685 = and(_T_684, _T_681) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_686 = and(_T_685, _T_683) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mdccmect <= _T_686 @[el2_dec_tlu_ctl.scala 2708:49] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_693 = and(_T_687, _T_688) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_694 = and(_T_693, _T_689) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_695 = and(_T_694, _T_690) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_696 = and(_T_695, _T_692) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdht <= _T_696 @[el2_dec_tlu_ctl.scala 2709:49] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_702 = and(_T_697, _T_699) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_703 = and(_T_702, _T_700) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_704 = and(_T_703, _T_701) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_mfdhs <= _T_704 @[el2_dec_tlu_ctl.scala 2710:49] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_716 = and(_T_706, _T_708) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_717 = and(_T_716, _T_709) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_718 = and(_T_717, _T_711) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_719 = and(_T_718, _T_713) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_720 = and(_T_719, _T_715) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicawics <= _T_720 @[el2_dec_tlu_ctl.scala 2711:49] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_726 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_727 = and(_T_726, _T_723) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_728 = and(_T_727, _T_725) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0h <= _T_728 @[el2_dec_tlu_ctl.scala 2712:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_736 = and(_T_729, _T_731) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_737 = and(_T_736, _T_732) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_738 = and(_T_737, _T_734) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_739 = and(_T_738, _T_735) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad0 <= _T_739 @[el2_dec_tlu_ctl.scala 2713:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_747 = and(_T_740, _T_741) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_748 = and(_T_747, _T_743) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_749 = and(_T_748, _T_744) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_750 = and(_T_749, _T_746) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicad1 <= _T_750 @[el2_dec_tlu_ctl.scala 2714:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_757 = and(_T_751, _T_752) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_758 = and(_T_757, _T_754) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_759 = and(_T_758, _T_755) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_760 = and(_T_759, _T_756) @[el2_dec_tlu_ctl.scala 2648:192] + io.csr_pkt.csr_dicago <= _T_760 @[el2_dec_tlu_ctl.scala 2715:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_767 = and(_T_761, _T_762) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_768 = and(_T_767, _T_763) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_769 = and(_T_768, _T_765) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_770 = and(_T_769, _T_766) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_782 = and(_T_772, _T_773) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_783 = and(_T_782, _T_775) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_784 = and(_T_783, _T_777) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_785 = and(_T_784, _T_779) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_786 = and(_T_785, _T_781) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_787 = or(_T_770, _T_786) @[el2_dec_tlu_ctl.scala 2716:73] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_799 = and(_T_789, _T_791) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_800 = and(_T_799, _T_793) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_801 = and(_T_800, _T_795) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_802 = and(_T_801, _T_797) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_803 = and(_T_802, _T_798) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_804 = or(_T_787, _T_803) @[el2_dec_tlu_ctl.scala 2716:113] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_813 = and(_T_805, _T_807) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_814 = and(_T_813, _T_809) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_815 = and(_T_814, _T_810) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_816 = and(_T_815, _T_812) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_817 = or(_T_804, _T_816) @[el2_dec_tlu_ctl.scala 2716:147] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_826 = and(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_827 = and(_T_826, _T_822) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_828 = and(_T_827, _T_823) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_829 = and(_T_828, _T_825) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_830 = or(_T_817, _T_829) @[el2_dec_tlu_ctl.scala 2717:41] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_841 = and(_T_831, _T_833) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_842 = and(_T_841, _T_835) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_843 = and(_T_842, _T_837) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_844 = and(_T_843, _T_839) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_845 = and(_T_844, _T_840) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_846 = or(_T_830, _T_845) @[el2_dec_tlu_ctl.scala 2717:81] + io.csr_pkt.presync <= _T_846 @[el2_dec_tlu_ctl.scala 2716:26] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_853 = and(_T_847, _T_848) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_854 = and(_T_853, _T_849) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_855 = and(_T_854, _T_851) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_856 = and(_T_855, _T_852) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_865 = and(_T_858, _T_860) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_866 = and(_T_865, _T_862) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_867 = and(_T_866, _T_863) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_868 = and(_T_867, _T_864) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_869 = or(_T_856, _T_868) @[el2_dec_tlu_ctl.scala 2718:73] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_876 = and(_T_871, _T_872) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_877 = and(_T_876, _T_874) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_878 = and(_T_877, _T_875) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_879 = or(_T_869, _T_878) @[el2_dec_tlu_ctl.scala 2718:113] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_886 = and(_T_880, _T_882) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_887 = and(_T_886, _T_884) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_888 = and(_T_887, _T_885) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_889 = or(_T_879, _T_888) @[el2_dec_tlu_ctl.scala 2718:154] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_904 = and(_T_891, _T_893) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_905 = and(_T_904, _T_895) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_906 = and(_T_905, _T_897) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_907 = and(_T_906, _T_899) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_908 = and(_T_907, _T_901) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_909 = and(_T_908, _T_903) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_910 = or(_T_889, _T_909) @[el2_dec_tlu_ctl.scala 2719:41] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_921 = and(_T_912, _T_913) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_922 = and(_T_921, _T_914) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_923 = and(_T_922, _T_916) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_924 = and(_T_923, _T_918) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_925 = and(_T_924, _T_920) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_926 = or(_T_910, _T_925) @[el2_dec_tlu_ctl.scala 2719:81] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_935 = and(_T_927, _T_929) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_936 = and(_T_935, _T_931) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_937 = and(_T_936, _T_933) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_938 = and(_T_937, _T_934) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_939 = or(_T_926, _T_938) @[el2_dec_tlu_ctl.scala 2719:114] + io.csr_pkt.postsync <= _T_939 @[el2_dec_tlu_ctl.scala 2718:24] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_955 = and(_T_941, _T_942) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_956 = and(_T_955, _T_943) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_957 = and(_T_956, _T_944) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_958 = and(_T_957, _T_945) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_959 = and(_T_958, _T_946) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_960 = and(_T_959, _T_947) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_961 = and(_T_960, _T_949) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_962 = and(_T_961, _T_951) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_963 = and(_T_962, _T_952) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_964 = and(_T_963, _T_954) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_983 = and(_T_966, _T_968) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_984 = and(_T_983, _T_969) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_985 = and(_T_984, _T_970) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_986 = and(_T_985, _T_972) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_987 = and(_T_986, _T_974) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_988 = and(_T_987, _T_976) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_989 = and(_T_988, _T_978) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_990 = and(_T_989, _T_980) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_991 = and(_T_990, _T_982) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_992 = or(_T_964, _T_991) @[el2_dec_tlu_ctl.scala 2721:73] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1008 = and(_T_994, _T_996) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1009 = and(_T_1008, _T_997) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1010 = and(_T_1009, _T_998) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1011 = and(_T_1010, _T_1000) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1012 = and(_T_1011, _T_1002) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1013 = and(_T_1012, _T_1003) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1014 = and(_T_1013, _T_1005) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1015 = and(_T_1014, _T_1007) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1016 = or(_T_992, _T_1015) @[el2_dec_tlu_ctl.scala 2721:121] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1032 = and(_T_1017, _T_1018) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1033 = and(_T_1032, _T_1019) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1034 = and(_T_1033, _T_1020) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1035 = and(_T_1034, _T_1021) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1036 = and(_T_1035, _T_1023) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1037 = and(_T_1036, _T_1025) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1038 = and(_T_1037, _T_1027) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1039 = and(_T_1038, _T_1029) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1040 = and(_T_1039, _T_1031) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1041 = or(_T_1016, _T_1040) @[el2_dec_tlu_ctl.scala 2722:57] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1053 = and(_T_1042, _T_1044) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1054 = and(_T_1053, _T_1045) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1055 = and(_T_1054, _T_1046) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1056 = and(_T_1055, _T_1048) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1057 = and(_T_1056, _T_1050) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1058 = and(_T_1057, _T_1052) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1059 = or(_T_1041, _T_1058) @[el2_dec_tlu_ctl.scala 2722:105] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1073 = and(_T_1061, _T_1062) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1074 = and(_T_1073, _T_1063) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1075 = and(_T_1074, _T_1064) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1076 = and(_T_1075, _T_1065) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1077 = and(_T_1076, _T_1066) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1078 = and(_T_1077, _T_1067) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1079 = and(_T_1078, _T_1068) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1080 = and(_T_1079, _T_1069) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1081 = and(_T_1080, _T_1070) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1082 = and(_T_1081, _T_1071) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1083 = and(_T_1082, _T_1072) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1084 = or(_T_1059, _T_1083) @[el2_dec_tlu_ctl.scala 2723:65] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1098 = and(_T_1086, _T_1087) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1099 = and(_T_1098, _T_1088) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1100 = and(_T_1099, _T_1089) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1101 = and(_T_1100, _T_1090) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1102 = and(_T_1101, _T_1091) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1103 = and(_T_1102, _T_1092) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1104 = and(_T_1103, _T_1093) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1105 = and(_T_1104, _T_1095) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1106 = and(_T_1105, _T_1097) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1107 = or(_T_1084, _T_1106) @[el2_dec_tlu_ctl.scala 2723:113] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1123 = and(_T_1108, _T_1109) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1124 = and(_T_1123, _T_1110) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1125 = and(_T_1124, _T_1112) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1126 = and(_T_1125, _T_1114) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1127 = and(_T_1126, _T_1116) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1128 = and(_T_1127, _T_1117) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1129 = and(_T_1128, _T_1119) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1130 = and(_T_1129, _T_1121) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1131 = and(_T_1130, _T_1122) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1132 = or(_T_1107, _T_1131) @[el2_dec_tlu_ctl.scala 2724:57] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1148 = and(_T_1134, _T_1135) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1149 = and(_T_1148, _T_1136) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1150 = and(_T_1149, _T_1137) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1151 = and(_T_1150, _T_1138) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1152 = and(_T_1151, _T_1140) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1153 = and(_T_1152, _T_1141) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1154 = and(_T_1153, _T_1143) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1155 = and(_T_1154, _T_1145) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1156 = and(_T_1155, _T_1147) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1157 = or(_T_1132, _T_1156) @[el2_dec_tlu_ctl.scala 2724:113] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1170 = and(_T_1159, _T_1161) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1171 = and(_T_1170, _T_1162) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1172 = and(_T_1171, _T_1163) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1173 = and(_T_1172, _T_1165) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1174 = and(_T_1173, _T_1167) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1175 = and(_T_1174, _T_1168) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1176 = and(_T_1175, _T_1169) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1177 = or(_T_1157, _T_1176) @[el2_dec_tlu_ctl.scala 2725:57] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1195 = and(_T_1178, _T_1179) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1196 = and(_T_1195, _T_1180) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1197 = and(_T_1196, _T_1182) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1198 = and(_T_1197, _T_1184) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1199 = and(_T_1198, _T_1186) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1200 = and(_T_1199, _T_1187) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1201 = and(_T_1200, _T_1189) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1202 = and(_T_1201, _T_1190) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1203 = and(_T_1202, _T_1192) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1204 = and(_T_1203, _T_1194) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1205 = or(_T_1177, _T_1204) @[el2_dec_tlu_ctl.scala 2725:113] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1219 = and(_T_1207, _T_1208) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1220 = and(_T_1219, _T_1209) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1221 = and(_T_1220, _T_1210) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1222 = and(_T_1221, _T_1211) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1223 = and(_T_1222, _T_1212) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1224 = and(_T_1223, _T_1214) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1225 = and(_T_1224, _T_1216) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1226 = and(_T_1225, _T_1217) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1227 = and(_T_1226, _T_1218) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1228 = or(_T_1205, _T_1227) @[el2_dec_tlu_ctl.scala 2726:57] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1242 = and(_T_1230, _T_1231) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1243 = and(_T_1242, _T_1232) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1244 = and(_T_1243, _T_1233) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1245 = and(_T_1244, _T_1234) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1246 = and(_T_1245, _T_1235) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1247 = and(_T_1246, _T_1237) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1248 = and(_T_1247, _T_1238) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1249 = and(_T_1248, _T_1240) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1250 = and(_T_1249, _T_1241) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1251 = or(_T_1228, _T_1250) @[el2_dec_tlu_ctl.scala 2726:113] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1267 = and(_T_1252, _T_1253) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1268 = and(_T_1267, _T_1254) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1269 = and(_T_1268, _T_1256) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1270 = and(_T_1269, _T_1258) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1271 = and(_T_1270, _T_1260) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1272 = and(_T_1271, _T_1261) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1273 = and(_T_1272, _T_1263) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1274 = and(_T_1273, _T_1265) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1275 = and(_T_1274, _T_1266) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1276 = or(_T_1251, _T_1275) @[el2_dec_tlu_ctl.scala 2727:57] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1290 = and(_T_1278, _T_1280) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1291 = and(_T_1290, _T_1281) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1292 = and(_T_1291, _T_1282) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1293 = and(_T_1292, _T_1284) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1294 = and(_T_1293, _T_1286) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1295 = and(_T_1294, _T_1287) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1296 = and(_T_1295, _T_1288) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1297 = and(_T_1296, _T_1289) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1298 = or(_T_1276, _T_1297) @[el2_dec_tlu_ctl.scala 2727:113] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1312 = and(_T_1299, _T_1301) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1313 = and(_T_1312, _T_1302) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1314 = and(_T_1313, _T_1303) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1315 = and(_T_1314, _T_1304) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1316 = and(_T_1315, _T_1306) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1317 = and(_T_1316, _T_1308) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1318 = and(_T_1317, _T_1309) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1319 = and(_T_1318, _T_1311) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1320 = or(_T_1298, _T_1319) @[el2_dec_tlu_ctl.scala 2728:65] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1336 = and(_T_1321, _T_1323) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1337 = and(_T_1336, _T_1324) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1338 = and(_T_1337, _T_1325) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1339 = and(_T_1338, _T_1326) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1340 = and(_T_1339, _T_1328) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1341 = and(_T_1340, _T_1330) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1342 = and(_T_1341, _T_1331) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1343 = and(_T_1342, _T_1333) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1344 = and(_T_1343, _T_1335) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1345 = or(_T_1320, _T_1344) @[el2_dec_tlu_ctl.scala 2728:121] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1356 = and(_T_1346, _T_1348) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1357 = and(_T_1356, _T_1349) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1358 = and(_T_1357, _T_1350) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1359 = and(_T_1358, _T_1352) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1360 = and(_T_1359, _T_1354) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1361 = and(_T_1360, _T_1355) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1362 = or(_T_1345, _T_1361) @[el2_dec_tlu_ctl.scala 2729:57] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1376 = and(_T_1364, _T_1365) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1377 = and(_T_1376, _T_1366) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1378 = and(_T_1377, _T_1367) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1379 = and(_T_1378, _T_1368) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1380 = and(_T_1379, _T_1369) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1381 = and(_T_1380, _T_1371) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1382 = and(_T_1381, _T_1372) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1383 = and(_T_1382, _T_1374) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1384 = and(_T_1383, _T_1375) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1385 = or(_T_1362, _T_1384) @[el2_dec_tlu_ctl.scala 2729:113] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1399 = and(_T_1387, _T_1388) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1400 = and(_T_1399, _T_1389) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1401 = and(_T_1400, _T_1390) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1402 = and(_T_1401, _T_1391) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1403 = and(_T_1402, _T_1392) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1404 = and(_T_1403, _T_1394) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1405 = and(_T_1404, _T_1396) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1406 = and(_T_1405, _T_1398) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1407 = or(_T_1385, _T_1406) @[el2_dec_tlu_ctl.scala 2730:57] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1422 = and(_T_1409, _T_1410) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1423 = and(_T_1422, _T_1411) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1424 = and(_T_1423, _T_1412) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1425 = and(_T_1424, _T_1413) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1426 = and(_T_1425, _T_1414) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1427 = and(_T_1426, _T_1416) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1428 = and(_T_1427, _T_1418) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1429 = and(_T_1428, _T_1419) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1430 = and(_T_1429, _T_1421) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1431 = or(_T_1407, _T_1430) @[el2_dec_tlu_ctl.scala 2730:113] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1449 = and(_T_1433, _T_1434) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1450 = and(_T_1449, _T_1435) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1451 = and(_T_1450, _T_1436) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1452 = and(_T_1451, _T_1437) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1453 = and(_T_1452, _T_1439) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1454 = and(_T_1453, _T_1440) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1455 = and(_T_1454, _T_1442) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1456 = and(_T_1455, _T_1444) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1457 = and(_T_1456, _T_1446) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1458 = and(_T_1457, _T_1448) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1459 = or(_T_1431, _T_1458) @[el2_dec_tlu_ctl.scala 2731:57] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1470 = and(_T_1460, _T_1462) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1471 = and(_T_1470, _T_1463) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1472 = and(_T_1471, _T_1464) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1473 = and(_T_1472, _T_1466) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1474 = and(_T_1473, _T_1468) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1475 = and(_T_1474, _T_1469) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1476 = or(_T_1459, _T_1475) @[el2_dec_tlu_ctl.scala 2731:105] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1494 = and(_T_1478, _T_1480) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1495 = and(_T_1494, _T_1481) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1496 = and(_T_1495, _T_1482) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1497 = and(_T_1496, _T_1484) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1498 = and(_T_1497, _T_1485) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1499 = and(_T_1498, _T_1487) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1500 = and(_T_1499, _T_1489) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1501 = and(_T_1500, _T_1491) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1502 = and(_T_1501, _T_1493) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1503 = or(_T_1476, _T_1502) @[el2_dec_tlu_ctl.scala 2732:65] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[el2_dec_tlu_ctl.scala 2648:179] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:159] + node _T_1522 = and(_T_1505, _T_1507) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1523 = and(_T_1522, _T_1508) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1524 = and(_T_1523, _T_1509) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1525 = and(_T_1524, _T_1511) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1526 = and(_T_1525, _T_1513) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1527 = and(_T_1526, _T_1515) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1528 = and(_T_1527, _T_1517) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1529 = and(_T_1528, _T_1519) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1530 = and(_T_1529, _T_1521) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1531 = or(_T_1503, _T_1530) @[el2_dec_tlu_ctl.scala 2732:113] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1544 = and(_T_1533, _T_1535) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1545 = and(_T_1544, _T_1536) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1546 = and(_T_1545, _T_1537) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1547 = and(_T_1546, _T_1539) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1548 = and(_T_1547, _T_1541) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1549 = and(_T_1548, _T_1542) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1550 = and(_T_1549, _T_1543) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1551 = or(_T_1531, _T_1550) @[el2_dec_tlu_ctl.scala 2733:57] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1562 = and(_T_1552, _T_1554) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1563 = and(_T_1562, _T_1555) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1564 = and(_T_1563, _T_1556) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1565 = and(_T_1564, _T_1558) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1566 = and(_T_1565, _T_1560) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1567 = and(_T_1566, _T_1561) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1568 = or(_T_1551, _T_1567) @[el2_dec_tlu_ctl.scala 2733:113] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1581 = and(_T_1570, _T_1572) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1582 = and(_T_1581, _T_1573) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1583 = and(_T_1582, _T_1574) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1584 = and(_T_1583, _T_1576) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1585 = and(_T_1584, _T_1578) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1586 = and(_T_1585, _T_1579) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1587 = and(_T_1586, _T_1580) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1588 = or(_T_1568, _T_1587) @[el2_dec_tlu_ctl.scala 2734:65] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[el2_dec_tlu_ctl.scala 2648:143] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 2648:123] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[el2_dec_tlu_ctl.scala 2648:100] + node _T_1599 = and(_T_1589, _T_1591) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1600 = and(_T_1599, _T_1592) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1601 = and(_T_1600, _T_1593) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1602 = and(_T_1601, _T_1595) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1603 = and(_T_1602, _T_1597) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1604 = and(_T_1603, _T_1598) @[el2_dec_tlu_ctl.scala 2648:192] + node _T_1605 = or(_T_1588, _T_1604) @[el2_dec_tlu_ctl.scala 2734:121] + io.csr_pkt.legal <= _T_1605 @[el2_dec_tlu_ctl.scala 2721:20] + + module el2_dec_tlu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + + wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] + wire pause_expired_wb : UInt<1> @[el2_dec_tlu_ctl.scala 237:54] + wire take_nmi_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 238:62] + wire exc_or_int_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 239:54] + wire interrupt_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 240:54] + wire tlu_flush_lower_r : UInt<1> @[el2_dec_tlu_ctl.scala 241:54] + wire synchronous_flush_r : UInt<1> @[el2_dec_tlu_ctl.scala 242:62] + wire interrupt_valid_r : UInt<1> @[el2_dec_tlu_ctl.scala 243:54] + wire take_nmi : UInt<1> @[el2_dec_tlu_ctl.scala 244:62] + wire take_reset : UInt<1> @[el2_dec_tlu_ctl.scala 245:70] + wire take_int_timer1_int : UInt<1> @[el2_dec_tlu_ctl.scala 246:62] + wire take_int_timer0_int : UInt<1> @[el2_dec_tlu_ctl.scala 247:62] + wire take_timer_int : UInt<1> @[el2_dec_tlu_ctl.scala 248:62] + wire take_soft_int : UInt<1> @[el2_dec_tlu_ctl.scala 249:62] + wire take_ce_int : UInt<1> @[el2_dec_tlu_ctl.scala 250:70] + wire take_ext_int_start : UInt<1> @[el2_dec_tlu_ctl.scala 251:62] + wire ext_int_freeze : UInt<1> @[el2_dec_tlu_ctl.scala 252:62] + wire ext_int_freeze_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 253:62] + wire take_ext_int_start_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 254:54] + wire take_ext_int_start_d2 : UInt<1> @[el2_dec_tlu_ctl.scala 255:54] + wire take_ext_int_start_d3 : UInt<1> @[el2_dec_tlu_ctl.scala 256:54] + wire fast_int_meicpct : UInt<1> @[el2_dec_tlu_ctl.scala 257:54] + wire ignore_ext_int_due_to_lsu_stall : UInt<1> @[el2_dec_tlu_ctl.scala 258:44] + wire take_ext_int : UInt<1> @[el2_dec_tlu_ctl.scala 259:62] + wire internal_dbg_halt_timers : UInt<1> @[el2_dec_tlu_ctl.scala 260:46] + wire int_timer1_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 261:62] + wire int_timer0_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 262:62] + wire mhwakeup_ready : UInt<1> @[el2_dec_tlu_ctl.scala 263:62] + wire ext_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 264:54] + wire ce_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 265:54] + wire soft_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 266:54] + wire timer_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 267:54] + wire ebreak_to_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 268:54] + wire ebreak_to_debug_mode_r : UInt<1> @[el2_dec_tlu_ctl.scala 269:54] + wire inst_acc_r : UInt<1> @[el2_dec_tlu_ctl.scala 270:70] + wire inst_acc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 271:62] + wire iccm_sbecc_r : UInt<1> @[el2_dec_tlu_ctl.scala 272:62] + wire ic_perr_r : UInt<1> @[el2_dec_tlu_ctl.scala 273:62] + wire fence_i_r : UInt<1> @[el2_dec_tlu_ctl.scala 274:62] + wire ebreak_r : UInt<1> @[el2_dec_tlu_ctl.scala 275:62] + wire ecall_r : UInt<1> @[el2_dec_tlu_ctl.scala 276:62] + wire illegal_r : UInt<1> @[el2_dec_tlu_ctl.scala 277:62] + wire mret_r : UInt<1> @[el2_dec_tlu_ctl.scala 278:62] + wire iccm_repair_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 279:54] + wire rfpc_i0_r : UInt<1> @[el2_dec_tlu_ctl.scala 280:70] + wire tlu_i0_kill_writeb_r : UInt<1> @[el2_dec_tlu_ctl.scala 281:54] + wire lsu_exc_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 282:62] + wire lsu_i0_exc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 283:54] + wire mdseac_locked_f : UInt<1> @[el2_dec_tlu_ctl.scala 284:62] + wire i_cpu_run_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 285:54] + wire cpu_run_ack : UInt<1> @[el2_dec_tlu_ctl.scala 286:70] + wire cpu_halt_status : UInt<1> @[el2_dec_tlu_ctl.scala 287:62] + wire cpu_halt_ack : UInt<1> @[el2_dec_tlu_ctl.scala 288:62] + wire pmu_fw_tlu_halted : UInt<1> @[el2_dec_tlu_ctl.scala 289:54] + wire internal_pmu_fw_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 290:46] + wire pmu_fw_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 291:62] + wire pmu_fw_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 292:62] + wire pmu_fw_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 293:54] + wire int_timer0_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 294:54] + wire int_timer1_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 295:54] + wire trigger_hit_dmode_r : UInt<1> @[el2_dec_tlu_ctl.scala 296:54] + wire i0_trigger_hit_r : UInt<1> @[el2_dec_tlu_ctl.scala 297:54] + wire pause_expired_r : UInt<1> @[el2_dec_tlu_ctl.scala 298:62] + wire dec_tlu_pmu_fw_halted : UInt<1> @[el2_dec_tlu_ctl.scala 299:54] + wire dec_tlu_flush_noredir_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 300:54] + wire halt_taken_f : UInt<1> @[el2_dec_tlu_ctl.scala 301:62] + wire lsu_idle_any_f : UInt<1> @[el2_dec_tlu_ctl.scala 302:62] + wire ifu_miss_state_idle_f : UInt<1> @[el2_dec_tlu_ctl.scala 303:54] + wire dbg_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 304:54] + wire debug_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 305:54] + wire debug_resume_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 306:62] + wire trigger_hit_dmode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 307:54] + wire dcsr_single_step_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 308:54] + wire debug_halt_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 309:54] + wire request_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 310:54] + wire request_debug_mode_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 311:46] + wire dcsr_single_step_running_f : UInt<1> @[el2_dec_tlu_ctl.scala 312:54] + wire dec_tlu_flush_pause_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 313:46] + wire dbg_halt_req_held : UInt<1> @[el2_dec_tlu_ctl.scala 314:54] + wire debug_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 315:62] + wire internal_dbg_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 316:54] + wire core_empty : UInt<1> @[el2_dec_tlu_ctl.scala 317:70] + wire dbg_halt_req_final : UInt<1> @[el2_dec_tlu_ctl.scala 318:62] + wire debug_brkpt_status_ns : UInt<1> @[el2_dec_tlu_ctl.scala 319:54] + wire mpc_debug_halt_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 320:54] + wire mpc_debug_run_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 321:54] + wire mpc_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 322:62] + wire mpc_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 323:54] + wire dbg_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 324:62] + wire dbg_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 325:54] + wire dbg_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 326:54] + wire mpc_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 327:54] + wire nmi_int_detected : UInt<1> @[el2_dec_tlu_ctl.scala 328:54] + wire nmi_lsu_load_type : UInt<1> @[el2_dec_tlu_ctl.scala 329:62] + wire nmi_lsu_store_type : UInt<1> @[el2_dec_tlu_ctl.scala 330:62] + wire reset_delayed : UInt<1> @[el2_dec_tlu_ctl.scala 331:62] + wire debug_mode_status : UInt<1> @[el2_dec_tlu_ctl.scala 332:46] + wire e5_valid : UInt<1> @[el2_dec_tlu_ctl.scala 333:62] + wire ic_perr_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 334:62] + wire iccm_sbecc_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 335:62] + wire npc_r : UInt<31> @[el2_dec_tlu_ctl.scala 337:41] + wire npc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 338:41] + wire mie_ns : UInt<6> @[el2_dec_tlu_ctl.scala 339:41] + wire mepc : UInt<31> @[el2_dec_tlu_ctl.scala 340:41] + wire mdseac_locked_ns : UInt<1> @[el2_dec_tlu_ctl.scala 341:41] + wire force_halt : UInt<1> @[el2_dec_tlu_ctl.scala 342:57] + wire dpc : UInt<31> @[el2_dec_tlu_ctl.scala 343:41] + wire mstatus_mie_ns : UInt<1> @[el2_dec_tlu_ctl.scala 344:41] + wire dec_csr_wen_r_mod : UInt<1> @[el2_dec_tlu_ctl.scala 345:41] + wire fw_halt_req : UInt<1> @[el2_dec_tlu_ctl.scala 346:41] + wire mstatus : UInt<2> @[el2_dec_tlu_ctl.scala 347:41] + wire dcsr : UInt<16> @[el2_dec_tlu_ctl.scala 348:41] + wire mtvec : UInt<31> @[el2_dec_tlu_ctl.scala 349:41] + wire mip : UInt<6> @[el2_dec_tlu_ctl.scala 350:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> @[el2_dec_tlu_ctl.scala 352:41] + node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] + node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] + dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] + inst int_timers of el2_dec_timer_ctl @[el2_dec_tlu_ctl.scala 355:24] + int_timers.clock <= clock + int_timers.reset <= reset + int_timers.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 356:57] + int_timers.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 357:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 358:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 359:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 360:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 361:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 362:49] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 363:49] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 364:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 365:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 366:49] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 367:49] + int_timers.io.dec_pause_state <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 368:41] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 369:41] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[el2_dec_tlu_ctl.scala 370:41] + node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] + node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] + node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 174:81] + _T_8 <= _T_7 @[el2_lib.scala 174:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 174:58] + syncro_ff <= _T_8 @[el2_lib.scala 174:58] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[el2_dec_tlu_ctl.scala 382:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[el2_dec_tlu_ctl.scala 383:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[el2_dec_tlu_ctl.scala 384:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[el2_dec_tlu_ctl.scala 385:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[el2_dec_tlu_ctl.scala 386:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[el2_dec_tlu_ctl.scala 387:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[el2_dec_tlu_ctl.scala 388:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 391:52] + node _T_10 = bits(_T_9, 0, 0) @[el2_dec_tlu_ctl.scala 391:68] + inst rvclkhdr of rvclkhdr_4 @[el2_lib.scala 474:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr.io.en <= _T_10 @[el2_lib.scala 476:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node _T_11 = or(io.lsu_error_pkt_r.exc_valid, lsu_exc_valid_r_d1) @[el2_dec_tlu_ctl.scala 392:65] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 392:86] + node _T_13 = bits(_T_12, 0, 0) @[el2_dec_tlu_ctl.scala 392:102] + inst rvclkhdr_1 of rvclkhdr_5 @[el2_lib.scala 474:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 476:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[el2_dec_tlu_ctl.scala 395:29] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 396:49] + node _T_15 = or(_T_14, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 396:68] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 396:88] + node _T_17 = or(_T_16, reset_delayed) @[el2_dec_tlu_ctl.scala 396:111] + node _T_18 = or(_T_17, pause_expired_r) @[el2_dec_tlu_ctl.scala 396:127] + node _T_19 = or(_T_18, pause_expired_wb) @[el2_dec_tlu_ctl.scala 396:145] + node _T_20 = or(_T_19, ic_perr_r) @[el2_dec_tlu_ctl.scala 396:164] + node _T_21 = or(_T_20, ic_perr_r_d1) @[el2_dec_tlu_ctl.scala 396:176] + node _T_22 = or(_T_21, iccm_sbecc_r) @[el2_dec_tlu_ctl.scala 396:191] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 396:206] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 396:224] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[el2_dec_tlu_ctl.scala 398:43] + node _T_25 = bits(_T_24, 0, 0) @[el2_dec_tlu_ctl.scala 398:59] + inst rvclkhdr_2 of rvclkhdr_6 @[el2_lib.scala 474:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 476:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[el2_dec_tlu_ctl.scala 399:47] + node _T_27 = bits(_T_26, 0, 0) @[el2_dec_tlu_ctl.scala 399:65] + inst rvclkhdr_3 of rvclkhdr_7 @[el2_lib.scala 474:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 475:17] + rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 476:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 477:23] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 401:72] + iccm_repair_state_d1 <= iccm_repair_state_ns @[el2_dec_tlu_ctl.scala 401:72] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 402:81] + _T_28 <= ic_perr_r @[el2_dec_tlu_ctl.scala 402:81] + ic_perr_r_d1 <= _T_28 @[el2_dec_tlu_ctl.scala 402:49] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 403:89] + _T_29 <= iccm_sbecc_r @[el2_dec_tlu_ctl.scala 403:89] + iccm_sbecc_r_d1 <= _T_29 @[el2_dec_tlu_ctl.scala 403:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 404:89] + _T_30 <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 404:89] + e5_valid <= _T_30 @[el2_dec_tlu_ctl.scala 404:57] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 405:73] + _T_31 <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 405:73] + debug_mode_status <= _T_31 @[el2_dec_tlu_ctl.scala 405:41] + reg lsu_pmu_load_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 406:72] + lsu_pmu_load_external_r <= io.lsu_pmu_load_external_m @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 407:64] + lsu_pmu_store_external_r <= io.lsu_pmu_store_external_m @[el2_dec_tlu_ctl.scala 407:64] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 408:72] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 408:72] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 409:65] + _T_32 <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 409:65] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[el2_dec_tlu_ctl.scala 409:33] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 410:64] + internal_dbg_halt_mode_f2 <= debug_mode_status @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 411:73] + _T_33 <= force_halt @[el2_dec_tlu_ctl.scala 411:73] + io.dec_tlu_force_halt <= _T_33 @[el2_dec_tlu_ctl.scala 411:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[el2_dec_tlu_ctl.scala 415:33] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 416:80] + reset_detect <= UInt<1>("h01") @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 417:80] + reset_detected <= reset_detect @[el2_dec_tlu_ctl.scala 417:80] + node _T_34 = xor(reset_detect, reset_detected) @[el2_dec_tlu_ctl.scala 418:64] + reset_delayed <= _T_34 @[el2_dec_tlu_ctl.scala 418:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 420:64] + nmi_int_delayed <= nmi_int_sync @[el2_dec_tlu_ctl.scala 420:64] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 421:72] + nmi_int_detected_f <= nmi_int_detected @[el2_dec_tlu_ctl.scala 421:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 422:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 423:64] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 423:64] + node _T_35 = not(mdseac_locked_f) @[el2_dec_tlu_ctl.scala 427:26] + node _T_36 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 427:78] + node nmi_lsu_detected = and(_T_35, _T_36) @[el2_dec_tlu_ctl.scala 427:43] + node _T_37 = not(nmi_int_delayed) @[el2_dec_tlu_ctl.scala 429:39] + node _T_38 = and(nmi_int_sync, _T_37) @[el2_dec_tlu_ctl.scala 429:37] + node _T_39 = or(_T_38, nmi_lsu_detected) @[el2_dec_tlu_ctl.scala 429:57] + node _T_40 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 429:100] + node _T_41 = and(nmi_int_detected_f, _T_40) @[el2_dec_tlu_ctl.scala 429:98] + node _T_42 = or(_T_39, _T_41) @[el2_dec_tlu_ctl.scala 429:76] + node _T_43 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 429:159] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[el2_dec_tlu_ctl.scala 429:140] + node _T_45 = or(_T_42, _T_44) @[el2_dec_tlu_ctl.scala 429:116] + nmi_int_detected <= _T_45 @[el2_dec_tlu_ctl.scala 429:20] + node _T_46 = and(nmi_lsu_detected, io.lsu_imprecise_error_load_any) @[el2_dec_tlu_ctl.scala 431:42] + node _T_47 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:101] + node _T_48 = and(nmi_int_detected_f, _T_47) @[el2_dec_tlu_ctl.scala 431:99] + node _T_49 = not(_T_48) @[el2_dec_tlu_ctl.scala 431:78] + node _T_50 = and(_T_46, _T_49) @[el2_dec_tlu_ctl.scala 431:76] + node _T_51 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 431:143] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[el2_dec_tlu_ctl.scala 431:141] + node _T_53 = or(_T_50, _T_52) @[el2_dec_tlu_ctl.scala 431:118] + nmi_lsu_load_type <= _T_53 @[el2_dec_tlu_ctl.scala 431:21] + node _T_54 = and(nmi_lsu_detected, io.lsu_imprecise_error_store_any) @[el2_dec_tlu_ctl.scala 432:43] + node _T_55 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:103] + node _T_56 = and(nmi_int_detected_f, _T_55) @[el2_dec_tlu_ctl.scala 432:101] + node _T_57 = not(_T_56) @[el2_dec_tlu_ctl.scala 432:80] + node _T_58 = and(_T_54, _T_57) @[el2_dec_tlu_ctl.scala 432:78] + node _T_59 = not(take_nmi_r_d1) @[el2_dec_tlu_ctl.scala 432:146] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[el2_dec_tlu_ctl.scala 432:144] + node _T_61 = or(_T_58, _T_60) @[el2_dec_tlu_ctl.scala 432:120] + nmi_lsu_store_type <= _T_61 @[el2_dec_tlu_ctl.scala 432:22] + node _T_62 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 439:63] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[el2_dec_tlu_ctl.scala 439:61] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 440:64] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 441:64] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[el2_dec_tlu_ctl.scala 441:64] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 442:81] + _T_63 <= mpc_halt_state_ns @[el2_dec_tlu_ctl.scala 442:81] + mpc_halt_state_f <= _T_63 @[el2_dec_tlu_ctl.scala 442:49] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 443:80] + mpc_run_state_f <= mpc_run_state_ns @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 444:72] + debug_brkpt_status_f <= debug_brkpt_status_ns @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 445:72] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 446:80] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[el2_dec_tlu_ctl.scala 446:80] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 447:81] + _T_64 <= dbg_halt_state_ns @[el2_dec_tlu_ctl.scala 447:81] + dbg_halt_state_f <= _T_64 @[el2_dec_tlu_ctl.scala 447:49] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 448:80] + dbg_run_state_f <= dbg_run_state_ns @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 449:73] + _T_65 <= dec_tlu_mpc_halted_only_ns @[el2_dec_tlu_ctl.scala 449:73] + io.dec_tlu_mpc_halted_only <= _T_65 @[el2_dec_tlu_ctl.scala 449:41] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[el2_dec_tlu_ctl.scala 453:65] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[el2_dec_tlu_ctl.scala 453:63] + node _T_67 = not(mpc_debug_run_req_sync_f) @[el2_dec_tlu_ctl.scala 454:64] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[el2_dec_tlu_ctl.scala 454:62] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[el2_dec_tlu_ctl.scala 456:42] + node _T_69 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 456:93] + node _T_70 = and(reset_delayed, _T_69) @[el2_dec_tlu_ctl.scala 456:91] + node _T_71 = or(_T_68, _T_70) @[el2_dec_tlu_ctl.scala 456:74] + node _T_72 = not(mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 456:119] + node _T_73 = and(_T_71, _T_72) @[el2_dec_tlu_ctl.scala 456:117] + mpc_halt_state_ns <= _T_73 @[el2_dec_tlu_ctl.scala 456:21] + node _T_74 = not(mpc_debug_run_ack_f) @[el2_dec_tlu_ctl.scala 457:74] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[el2_dec_tlu_ctl.scala 457:72] + node _T_76 = or(mpc_run_state_f, _T_75) @[el2_dec_tlu_ctl.scala 457:40] + node _T_77 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 457:127] + node _T_78 = and(debug_mode_status, _T_77) @[el2_dec_tlu_ctl.scala 457:125] + node _T_79 = and(_T_76, _T_78) @[el2_dec_tlu_ctl.scala 457:97] + mpc_run_state_ns <= _T_79 @[el2_dec_tlu_ctl.scala 457:20] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 459:64] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 459:90] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 459:115] + node _T_83 = or(dbg_halt_state_f, _T_82) @[el2_dec_tlu_ctl.scala 459:42] + node _T_84 = not(io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 459:147] + node _T_85 = and(_T_83, _T_84) @[el2_dec_tlu_ctl.scala 459:145] + dbg_halt_state_ns <= _T_85 @[el2_dec_tlu_ctl.scala 459:21] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[el2_dec_tlu_ctl.scala 460:40] + node _T_87 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 460:91] + node _T_88 = and(debug_mode_status, _T_87) @[el2_dec_tlu_ctl.scala 460:89] + node _T_89 = and(_T_86, _T_88) @[el2_dec_tlu_ctl.scala 460:61] + dbg_run_state_ns <= _T_89 @[el2_dec_tlu_ctl.scala 460:20] + node _T_90 = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 463:33] + node _T_91 = and(_T_90, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 463:51] + dec_tlu_mpc_halted_only_ns <= _T_91 @[el2_dec_tlu_ctl.scala 463:30] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 466:53] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[el2_dec_tlu_ctl.scala 467:47] + node _T_93 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 467:99] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[el2_dec_tlu_ctl.scala 467:97] + node _T_95 = and(_T_92, _T_94) @[el2_dec_tlu_ctl.scala 467:71] + debug_brkpt_status_ns <= _T_95 @[el2_dec_tlu_ctl.scala 467:25] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[el2_dec_tlu_ctl.scala 470:45] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 470:72] + node _T_98 = and(_T_97, core_empty) @[el2_dec_tlu_ctl.scala 470:98] + mpc_debug_halt_ack_ns <= _T_98 @[el2_dec_tlu_ctl.scala 470:25] + node _T_99 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 471:53] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[el2_dec_tlu_ctl.scala 471:51] + node _T_101 = not(mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 471:74] + node _T_102 = and(_T_100, _T_101) @[el2_dec_tlu_ctl.scala 471:72] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[el2_dec_tlu_ctl.scala 471:123] + node _T_104 = or(_T_102, _T_103) @[el2_dec_tlu_ctl.scala 471:100] + mpc_debug_run_ack_ns <= _T_104 @[el2_dec_tlu_ctl.scala 471:24] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[el2_dec_tlu_ctl.scala 474:25] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[el2_dec_tlu_ctl.scala 475:25] + io.debug_brkpt_status <= debug_brkpt_status_f @[el2_dec_tlu_ctl.scala 476:25] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 479:47] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 479:68] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[el2_dec_tlu_ctl.scala 480:42] + node _T_107 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 480:65] + node _T_108 = and(_T_106, _T_107) @[el2_dec_tlu_ctl.scala 480:63] + dbg_halt_req_final <= _T_108 @[el2_dec_tlu_ctl.scala 480:22] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[el2_dec_tlu_ctl.scala 483:44] + node _T_110 = not(io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 483:89] + node _T_111 = and(reset_delayed, _T_110) @[el2_dec_tlu_ctl.scala 483:87] + node _T_112 = or(_T_109, _T_111) @[el2_dec_tlu_ctl.scala 483:70] + node _T_113 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 483:115] + node _T_114 = and(_T_112, _T_113) @[el2_dec_tlu_ctl.scala 483:113] + node _T_115 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 483:143] + node debug_halt_req = and(_T_114, _T_115) @[el2_dec_tlu_ctl.scala 483:141] + node _T_116 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 485:26] + node _T_117 = not(dbg_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:69] + node _T_118 = and(mpc_run_state_ns, _T_117) @[el2_dec_tlu_ctl.scala 485:67] + node _T_119 = not(mpc_halt_state_ns) @[el2_dec_tlu_ctl.scala 485:111] + node _T_120 = and(dbg_run_state_ns, _T_119) @[el2_dec_tlu_ctl.scala 485:109] + node _T_121 = or(_T_118, _T_120) @[el2_dec_tlu_ctl.scala 485:89] + node debug_resume_req = and(_T_116, _T_121) @[el2_dec_tlu_ctl.scala 485:46] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 490:37] + node _T_123 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 490:60] + node _T_124 = and(_T_122, _T_123) @[el2_dec_tlu_ctl.scala 490:58] + node _T_125 = not(mret_r) @[el2_dec_tlu_ctl.scala 490:83] + node _T_126 = and(_T_124, _T_125) @[el2_dec_tlu_ctl.scala 490:81] + node _T_127 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 490:93] + node _T_128 = and(_T_126, _T_127) @[el2_dec_tlu_ctl.scala 490:91] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[el2_dec_tlu_ctl.scala 490:109] + node _T_130 = and(_T_128, _T_129) @[el2_dec_tlu_ctl.scala 490:107] + node _T_131 = not(take_reset) @[el2_dec_tlu_ctl.scala 490:139] + node take_halt = and(_T_130, _T_131) @[el2_dec_tlu_ctl.scala 490:137] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[el2_dec_tlu_ctl.scala 493:50] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[el2_dec_tlu_ctl.scala 493:48] + node _T_134 = not(take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 493:78] + node _T_135 = and(_T_133, _T_134) @[el2_dec_tlu_ctl.scala 493:76] + node _T_136 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:120] + node _T_137 = and(halt_taken_f, _T_136) @[el2_dec_tlu_ctl.scala 493:118] + node _T_138 = not(pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 493:140] + node _T_139 = and(_T_137, _T_138) @[el2_dec_tlu_ctl.scala 493:138] + node _T_140 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 493:163] + node _T_141 = and(_T_139, _T_140) @[el2_dec_tlu_ctl.scala 493:161] + node halt_taken = or(_T_135, _T_141) @[el2_dec_tlu_ctl.scala 493:102] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[el2_dec_tlu_ctl.scala 497:47] + node _T_143 = and(_T_142, io.ifu_miss_state_idle) @[el2_dec_tlu_ctl.scala 497:64] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[el2_dec_tlu_ctl.scala 497:89] + node _T_145 = not(debug_halt_req) @[el2_dec_tlu_ctl.scala 497:115] + node _T_146 = and(_T_144, _T_145) @[el2_dec_tlu_ctl.scala 497:113] + node _T_147 = not(debug_halt_req_d1) @[el2_dec_tlu_ctl.scala 497:133] + node _T_148 = and(_T_146, _T_147) @[el2_dec_tlu_ctl.scala 497:131] + node _T_149 = not(io.dec_div_active) @[el2_dec_tlu_ctl.scala 497:154] + node _T_150 = and(_T_148, _T_149) @[el2_dec_tlu_ctl.scala 497:152] + node _T_151 = or(force_halt, _T_150) @[el2_dec_tlu_ctl.scala 497:28] + core_empty <= _T_151 @[el2_dec_tlu_ctl.scala 497:14] + node _T_152 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 503:31] + node _T_153 = and(_T_152, debug_halt_req) @[el2_dec_tlu_ctl.scala 503:57] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 503:75] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[el2_dec_tlu_ctl.scala 503:101] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 503:126] + node _T_156 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 506:105] + node _T_157 = not(_T_156) @[el2_dec_tlu_ctl.scala 506:100] + node _T_158 = and(debug_resume_req_f, _T_157) @[el2_dec_tlu_ctl.scala 506:98] + node _T_159 = not(_T_158) @[el2_dec_tlu_ctl.scala 506:77] + node _T_160 = and(debug_mode_status, _T_159) @[el2_dec_tlu_ctl.scala 506:75] + node _T_161 = or(debug_halt_req_ns, _T_160) @[el2_dec_tlu_ctl.scala 506:47] + internal_dbg_halt_mode <= _T_161 @[el2_dec_tlu_ctl.scala 506:26] + node _T_162 = not(dcsr_single_step_running_f) @[el2_dec_tlu_ctl.scala 508:61] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[el2_dec_tlu_ctl.scala 508:59] + node _T_163 = and(debug_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 513:42] + node _T_164 = and(_T_163, halt_taken) @[el2_dec_tlu_ctl.scala 513:55] + node _T_165 = not(debug_resume_req_f) @[el2_dec_tlu_ctl.scala 513:91] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[el2_dec_tlu_ctl.scala 513:89] + node dbg_tlu_halted = or(_T_164, _T_166) @[el2_dec_tlu_ctl.scala 513:69] + node _T_167 = not(dbg_tlu_halted) @[el2_dec_tlu_ctl.scala 514:67] + node _T_168 = and(debug_halt_req_f, _T_167) @[el2_dec_tlu_ctl.scala 514:65] + node _T_169 = or(enter_debug_halt_req, _T_168) @[el2_dec_tlu_ctl.scala 514:45] + debug_halt_req_ns <= _T_169 @[el2_dec_tlu_ctl.scala 514:21] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 515:43] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[el2_dec_tlu_ctl.scala 515:62] + node _T_171 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 517:55] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[el2_dec_tlu_ctl.scala 517:53] + node _T_173 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 517:84] + node _T_174 = and(_T_172, _T_173) @[el2_dec_tlu_ctl.scala 517:78] + node _T_175 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 517:98] + node dcsr_single_step_done = and(_T_174, _T_175) @[el2_dec_tlu_ctl.scala 517:96] + node _T_176 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 519:60] + node _T_177 = and(debug_resume_req_f, _T_176) @[el2_dec_tlu_ctl.scala 519:54] + node _T_178 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 519:105] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[el2_dec_tlu_ctl.scala 519:103] + node dcsr_single_step_running = or(_T_177, _T_179) @[el2_dec_tlu_ctl.scala 519:73] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 521:47] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 524:51] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 524:106] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[el2_dec_tlu_ctl.scala 524:104] + node request_debug_mode_r = or(_T_180, _T_182) @[el2_dec_tlu_ctl.scala 524:77] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[el2_dec_tlu_ctl.scala 526:58] + node _T_184 = not(dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 526:89] + node request_debug_mode_done = and(_T_183, _T_184) @[el2_dec_tlu_ctl.scala 526:87] + reg _T_185 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 529:73] + _T_185 <= io.dec_tlu_flush_noredir_r @[el2_dec_tlu_ctl.scala 529:73] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[el2_dec_tlu_ctl.scala 529:41] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 530:81] + _T_186 <= halt_taken @[el2_dec_tlu_ctl.scala 530:81] + halt_taken_f <= _T_186 @[el2_dec_tlu_ctl.scala 530:49] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 531:89] + _T_187 <= io.lsu_idle_any @[el2_dec_tlu_ctl.scala 531:89] + lsu_idle_any_f <= _T_187 @[el2_dec_tlu_ctl.scala 531:57] + reg _T_188 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 532:73] + _T_188 <= io.ifu_miss_state_idle @[el2_dec_tlu_ctl.scala 532:73] + ifu_miss_state_idle_f <= _T_188 @[el2_dec_tlu_ctl.scala 532:41] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 533:81] + _T_189 <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 533:81] + dbg_tlu_halted_f <= _T_189 @[el2_dec_tlu_ctl.scala 533:49] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 534:73] + _T_190 <= resume_ack_ns @[el2_dec_tlu_ctl.scala 534:73] + io.dec_tlu_resume_ack <= _T_190 @[el2_dec_tlu_ctl.scala 534:41] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 535:81] + _T_191 <= debug_halt_req_ns @[el2_dec_tlu_ctl.scala 535:81] + debug_halt_req_f <= _T_191 @[el2_dec_tlu_ctl.scala 535:49] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 536:81] + _T_192 <= debug_resume_req @[el2_dec_tlu_ctl.scala 536:81] + debug_resume_req_f <= _T_192 @[el2_dec_tlu_ctl.scala 536:49] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 537:81] + _T_193 <= trigger_hit_dmode_r @[el2_dec_tlu_ctl.scala 537:81] + trigger_hit_dmode_r_d1 <= _T_193 @[el2_dec_tlu_ctl.scala 537:49] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 538:81] + _T_194 <= dcsr_single_step_done @[el2_dec_tlu_ctl.scala 538:81] + dcsr_single_step_done_f <= _T_194 @[el2_dec_tlu_ctl.scala 538:49] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 539:81] + _T_195 <= debug_halt_req @[el2_dec_tlu_ctl.scala 539:81] + debug_halt_req_d1 <= _T_195 @[el2_dec_tlu_ctl.scala 539:49] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 540:73] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 540:73] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 541:73] + dec_pause_state_f <= io.dec_pause_state @[el2_dec_tlu_ctl.scala 541:73] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 542:81] + _T_196 <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 542:81] + request_debug_mode_r_d1 <= _T_196 @[el2_dec_tlu_ctl.scala 542:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 543:73] + _T_197 <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 543:73] + request_debug_mode_done_f <= _T_197 @[el2_dec_tlu_ctl.scala 543:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 544:73] + _T_198 <= dcsr_single_step_running @[el2_dec_tlu_ctl.scala 544:73] + dcsr_single_step_running_f <= _T_198 @[el2_dec_tlu_ctl.scala 544:41] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 545:73] + _T_199 <= io.dec_tlu_flush_pause_r @[el2_dec_tlu_ctl.scala 545:73] + dec_tlu_flush_pause_r_d1 <= _T_199 @[el2_dec_tlu_ctl.scala 545:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 546:81] + _T_200 <= dbg_halt_req_held_ns @[el2_dec_tlu_ctl.scala 546:81] + dbg_halt_req_held <= _T_200 @[el2_dec_tlu_ctl.scala 546:49] + io.dec_tlu_debug_stall <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 549:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 550:41] + io.dec_tlu_debug_mode <= debug_mode_status @[el2_dec_tlu_ctl.scala 551:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[el2_dec_tlu_ctl.scala 552:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 555:56] + node _T_202 = or(take_halt, _T_201) @[el2_dec_tlu_ctl.scala 555:43] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[el2_dec_tlu_ctl.scala 555:82] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 555:129] + node _T_205 = or(_T_203, _T_204) @[el2_dec_tlu_ctl.scala 555:109] + node _T_206 = or(_T_205, take_ext_int_start) @[el2_dec_tlu_ctl.scala 555:152] + io.dec_tlu_flush_noredir_r <= _T_206 @[el2_dec_tlu_ctl.scala 555:30] + io.dec_tlu_flush_extint <= take_ext_int_start @[el2_dec_tlu_ctl.scala 557:27] + node _T_207 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 560:55] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[el2_dec_tlu_ctl.scala 560:53] + node _T_209 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 560:76] + node _T_210 = and(_T_208, _T_209) @[el2_dec_tlu_ctl.scala 560:74] + io.dec_tlu_flush_pause_r <= _T_210 @[el2_dec_tlu_ctl.scala 560:28] + node _T_211 = not(io.dec_pause_state) @[el2_dec_tlu_ctl.scala 562:22] + node _T_212 = and(_T_211, dec_pause_state_f) @[el2_dec_tlu_ctl.scala 562:42] + node _T_213 = or(ext_int_ready, ce_int_ready) @[el2_dec_tlu_ctl.scala 562:80] + node _T_214 = or(_T_213, timer_int_ready) @[el2_dec_tlu_ctl.scala 562:95] + node _T_215 = or(_T_214, soft_int_ready) @[el2_dec_tlu_ctl.scala 562:113] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 562:130] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 562:154] + node _T_218 = or(_T_217, nmi_int_detected) @[el2_dec_tlu_ctl.scala 562:178] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 562:197] + node _T_220 = not(_T_219) @[el2_dec_tlu_ctl.scala 562:64] + node _T_221 = and(_T_212, _T_220) @[el2_dec_tlu_ctl.scala 562:62] + node _T_222 = not(interrupt_valid_r_d1) @[el2_dec_tlu_ctl.scala 562:220] + node _T_223 = and(_T_221, _T_222) @[el2_dec_tlu_ctl.scala 562:218] + node _T_224 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 562:244] + node _T_225 = and(_T_223, _T_224) @[el2_dec_tlu_ctl.scala 562:242] + node _T_226 = not(pmu_fw_halt_req_f) @[el2_dec_tlu_ctl.scala 562:264] + node _T_227 = and(_T_225, _T_226) @[el2_dec_tlu_ctl.scala 562:262] + node _T_228 = not(halt_taken_f) @[el2_dec_tlu_ctl.scala 562:285] + node _T_229 = and(_T_227, _T_228) @[el2_dec_tlu_ctl.scala 562:283] + pause_expired_r <= _T_229 @[el2_dec_tlu_ctl.scala 562:19] + node _T_230 = bits(dcsr, 2, 2) @[el2_dec_tlu_ctl.scala 564:66] + node _T_231 = and(io.dec_tlu_flush_lower_r, _T_230) @[el2_dec_tlu_ctl.scala 564:60] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 564:103] + node _T_233 = and(_T_231, _T_232) @[el2_dec_tlu_ctl.scala 564:78] + node _T_234 = not(io.dec_tlu_flush_noredir_r) @[el2_dec_tlu_ctl.scala 564:133] + node _T_235 = and(_T_233, _T_234) @[el2_dec_tlu_ctl.scala 564:131] + io.dec_tlu_flush_leak_one_r <= _T_235 @[el2_dec_tlu_ctl.scala 564:31] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 565:70] + node _T_237 = and(io.dec_tlu_flush_lower_r, _T_236) @[el2_dec_tlu_ctl.scala 565:54] + io.dec_tlu_flush_err_r <= _T_237 @[el2_dec_tlu_ctl.scala 565:26] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[el2_dec_tlu_ctl.scala 568:23] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[el2_dec_tlu_ctl.scala 569:36] + io.dec_dbg_cmd_fail <= _T_238 @[el2_dec_tlu_ctl.scala 569:23] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[el2_dec_tlu_ctl.scala 582:42] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[el2_dec_tlu_ctl.scala 582:69] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[el2_dec_tlu_ctl.scala 582:96] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[el2_dec_tlu_ctl.scala 582:123] + node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] + node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] + node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 583:44] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 583:71] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 583:98] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 583:125] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] + node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 584:44] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 584:71] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 584:98] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 584:125] + node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] + node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] + node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 587:45] + node _T_258 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:71] + node _T_259 = or(_T_257, _T_258) @[el2_dec_tlu_ctl.scala 587:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[el2_dec_tlu_ctl.scala 587:100] + node _T_261 = and(_T_259, _T_260) @[el2_dec_tlu_ctl.scala 587:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 587:133] + node _T_263 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:159] + node _T_264 = or(_T_262, _T_263) @[el2_dec_tlu_ctl.scala 587:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[el2_dec_tlu_ctl.scala 587:188] + node _T_266 = and(_T_264, _T_265) @[el2_dec_tlu_ctl.scala 587:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 587:222] + node _T_268 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:248] + node _T_269 = or(_T_267, _T_268) @[el2_dec_tlu_ctl.scala 587:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[el2_dec_tlu_ctl.scala 587:277] + node _T_271 = and(_T_269, _T_270) @[el2_dec_tlu_ctl.scala 587:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 587:311] + node _T_273 = bits(mstatus, 0, 0) @[el2_dec_tlu_ctl.scala 587:337] + node _T_274 = or(_T_272, _T_273) @[el2_dec_tlu_ctl.scala 587:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[el2_dec_tlu_ctl.scala 587:366] + node _T_276 = and(_T_274, _T_275) @[el2_dec_tlu_ctl.scala 587:352] + node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] + node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] + node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] + node _T_279 = and(trigger_execute, trigger_data) @[el2_dec_tlu_ctl.scala 590:56] + node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_282 = and(_T_279, _T_281) @[el2_dec_tlu_ctl.scala 590:71] + node _T_283 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 590:128] + node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] + node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_286 = or(_T_282, _T_285) @[el2_dec_tlu_ctl.scala 590:97] + node i0_iside_trigger_has_pri_r = not(_T_286) @[el2_dec_tlu_ctl.scala 590:37] + node _T_287 = and(trigger_store, trigger_data) @[el2_dec_tlu_ctl.scala 593:50] + node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_287, _T_289) @[el2_dec_tlu_ctl.scala 593:65] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[el2_dec_tlu_ctl.scala 593:34] + node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] + node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[el2_dec_tlu_ctl.scala 598:83] + node _T_294 = and(_T_292, _T_293) @[el2_dec_tlu_ctl.scala 598:52] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:89] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[el2_dec_tlu_ctl.scala 598:118] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[el2_dec_tlu_ctl.scala 598:145] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 600:57] + node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_300 = not(_T_299) @[el2_dec_tlu_ctl.scala 600:22] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[el2_dec_tlu_ctl.scala 600:83] + node _T_301 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:52] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:72] + node _T_303 = not(_T_302) @[el2_dec_tlu_ctl.scala 603:59] + node _T_304 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:102] + node _T_305 = or(_T_303, _T_304) @[el2_dec_tlu_ctl.scala 603:88] + node _T_306 = and(_T_301, _T_305) @[el2_dec_tlu_ctl.scala 603:56] + node _T_307 = bits(i0_trigger_r, 2, 2) @[el2_dec_tlu_ctl.scala 603:120] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[el2_dec_tlu_ctl.scala 603:140] + node _T_309 = not(_T_308) @[el2_dec_tlu_ctl.scala 603:127] + node _T_310 = bits(i0_trigger_r, 3, 3) @[el2_dec_tlu_ctl.scala 603:170] + node _T_311 = or(_T_309, _T_310) @[el2_dec_tlu_ctl.scala 603:156] + node _T_312 = and(_T_307, _T_311) @[el2_dec_tlu_ctl.scala 603:124] + node _T_313 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:188] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:208] + node _T_315 = not(_T_314) @[el2_dec_tlu_ctl.scala 603:195] + node _T_316 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:238] + node _T_317 = or(_T_315, _T_316) @[el2_dec_tlu_ctl.scala 603:224] + node _T_318 = and(_T_313, _T_317) @[el2_dec_tlu_ctl.scala 603:192] + node _T_319 = bits(i0_trigger_r, 0, 0) @[el2_dec_tlu_ctl.scala 603:256] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[el2_dec_tlu_ctl.scala 603:276] + node _T_321 = not(_T_320) @[el2_dec_tlu_ctl.scala 603:263] + node _T_322 = bits(i0_trigger_r, 1, 1) @[el2_dec_tlu_ctl.scala 603:306] + node _T_323 = or(_T_321, _T_322) @[el2_dec_tlu_ctl.scala 603:292] + node _T_324 = and(_T_319, _T_323) @[el2_dec_tlu_ctl.scala 603:260] + node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] + node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] + node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 606:56] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[el2_dec_tlu_ctl.scala 608:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[el2_dec_tlu_ctl.scala 612:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[el2_dec_tlu_ctl.scala 612:75] + node _T_329 = and(_T_327, _T_328) @[el2_dec_tlu_ctl.scala 612:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[el2_dec_tlu_ctl.scala 612:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[el2_dec_tlu_ctl.scala 612:135] + node _T_332 = and(_T_330, _T_331) @[el2_dec_tlu_ctl.scala 612:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[el2_dec_tlu_ctl.scala 612:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[el2_dec_tlu_ctl.scala 612:195] + node _T_335 = and(_T_333, _T_334) @[el2_dec_tlu_ctl.scala 612:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[el2_dec_tlu_ctl.scala 612:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[el2_dec_tlu_ctl.scala 612:255] + node _T_338 = and(_T_336, _T_337) @[el2_dec_tlu_ctl.scala 612:241] + node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] + node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] + node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] + node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] + node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[el2_dec_tlu_ctl.scala 615:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[el2_dec_tlu_ctl.scala 618:56] + node i0_trigger_action_r = orr(_T_343) @[el2_dec_tlu_ctl.scala 618:74] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[el2_dec_tlu_ctl.scala 620:44] + trigger_hit_dmode_r <= _T_344 @[el2_dec_tlu_ctl.scala 620:23] + node _T_345 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 622:54] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[el2_dec_tlu_ctl.scala 622:52] + node _T_346 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 649:56] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[el2_dec_tlu_ctl.scala 649:54] + node _T_348 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 649:81] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[el2_dec_tlu_ctl.scala 649:79] + node _T_349 = not(io.dec_tlu_debug_mode) @[el2_dec_tlu_ctl.scala 650:54] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[el2_dec_tlu_ctl.scala 650:52] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 650:77] + node _T_352 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 650:101] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[el2_dec_tlu_ctl.scala 650:99] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 652:80] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[el2_dec_tlu_ctl.scala 652:80] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 653:72] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[el2_dec_tlu_ctl.scala 653:72] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 654:73] + _T_353 <= cpu_halt_status @[el2_dec_tlu_ctl.scala 654:73] + io.o_cpu_halt_status <= _T_353 @[el2_dec_tlu_ctl.scala 654:41] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 655:81] + _T_354 <= cpu_halt_ack @[el2_dec_tlu_ctl.scala 655:81] + io.o_cpu_halt_ack <= _T_354 @[el2_dec_tlu_ctl.scala 655:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 656:81] + _T_355 <= cpu_run_ack @[el2_dec_tlu_ctl.scala 656:81] + io.o_cpu_run_ack <= _T_355 @[el2_dec_tlu_ctl.scala 656:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 657:66] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[el2_dec_tlu_ctl.scala 657:66] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 658:73] + _T_356 <= pmu_fw_halt_req_ns @[el2_dec_tlu_ctl.scala 658:73] + pmu_fw_halt_req_f <= _T_356 @[el2_dec_tlu_ctl.scala 658:41] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 659:73] + _T_357 <= pmu_fw_tlu_halted @[el2_dec_tlu_ctl.scala 659:73] + pmu_fw_tlu_halted_f <= _T_357 @[el2_dec_tlu_ctl.scala 659:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 660:65] + _T_358 <= int_timer0_int_hold @[el2_dec_tlu_ctl.scala 660:65] + int_timer0_int_hold_f <= _T_358 @[el2_dec_tlu_ctl.scala 660:33] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 661:65] + _T_359 <= int_timer1_int_hold @[el2_dec_tlu_ctl.scala 661:65] + int_timer1_int_hold_f <= _T_359 @[el2_dec_tlu_ctl.scala 661:33] + node _T_360 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 665:51] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[el2_dec_tlu_ctl.scala 665:49] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[el2_dec_tlu_ctl.scala 666:47] + node _T_361 = not(pmu_fw_tlu_halted) @[el2_dec_tlu_ctl.scala 667:71] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[el2_dec_tlu_ctl.scala 667:69] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[el2_dec_tlu_ctl.scala 667:48] + node _T_364 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 667:94] + node _T_365 = and(_T_363, _T_364) @[el2_dec_tlu_ctl.scala 667:92] + pmu_fw_halt_req_ns <= _T_365 @[el2_dec_tlu_ctl.scala 667:22] + node _T_366 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 668:84] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[el2_dec_tlu_ctl.scala 668:82] + node _T_368 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 668:104] + node _T_369 = and(_T_367, _T_368) @[el2_dec_tlu_ctl.scala 668:102] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[el2_dec_tlu_ctl.scala 668:51] + internal_pmu_fw_halt_mode <= _T_370 @[el2_dec_tlu_ctl.scala 668:29] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[el2_dec_tlu_ctl.scala 671:44] + node _T_372 = and(_T_371, halt_taken) @[el2_dec_tlu_ctl.scala 671:57] + node _T_373 = not(enter_debug_halt_req) @[el2_dec_tlu_ctl.scala 671:72] + node _T_374 = and(_T_372, _T_373) @[el2_dec_tlu_ctl.scala 671:70] + node _T_375 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 671:120] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[el2_dec_tlu_ctl.scala 671:118] + node _T_377 = or(_T_374, _T_376) @[el2_dec_tlu_ctl.scala 671:95] + node _T_378 = not(debug_halt_req_f) @[el2_dec_tlu_ctl.scala 671:142] + node _T_379 = and(_T_377, _T_378) @[el2_dec_tlu_ctl.scala 671:140] + pmu_fw_tlu_halted <= _T_379 @[el2_dec_tlu_ctl.scala 671:21] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 673:37] + cpu_halt_ack <= _T_380 @[el2_dec_tlu_ctl.scala 673:16] + node _T_381 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:45] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[el2_dec_tlu_ctl.scala 674:43] + node _T_383 = not(i_cpu_run_req_d1) @[el2_dec_tlu_ctl.scala 674:90] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[el2_dec_tlu_ctl.scala 674:88] + node _T_385 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 674:110] + node _T_386 = and(_T_384, _T_385) @[el2_dec_tlu_ctl.scala 674:108] + node _T_387 = or(_T_382, _T_386) @[el2_dec_tlu_ctl.scala 674:64] + cpu_halt_status <= _T_387 @[el2_dec_tlu_ctl.scala 674:19] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:40] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[el2_dec_tlu_ctl.scala 675:87] + node _T_390 = or(_T_388, _T_389) @[el2_dec_tlu_ctl.scala 675:67] + cpu_run_ack <= _T_390 @[el2_dec_tlu_ctl.scala 675:15] + io.o_debug_mode_status <= debug_mode_status @[el2_dec_tlu_ctl.scala 677:26] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[el2_dec_tlu_ctl.scala 680:65] + node _T_392 = or(_T_391, soft_int_ready) @[el2_dec_tlu_ctl.scala 680:83] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 680:100] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 680:124] + node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[el2_dec_tlu_ctl.scala 680:163] + node _T_396 = or(_T_394, _T_395) @[el2_dec_tlu_ctl.scala 680:148] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[el2_dec_tlu_ctl.scala 680:182] + node _T_398 = not(i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 680:207] + node _T_399 = and(_T_397, _T_398) @[el2_dec_tlu_ctl.scala 680:205] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[el2_dec_tlu_ctl.scala 680:44] + i_cpu_run_req_d1 <= _T_400 @[el2_dec_tlu_ctl.scala 680:20] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 686:89] + _T_401 <= mdseac_locked_ns @[el2_dec_tlu_ctl.scala 686:89] + mdseac_locked_f <= _T_401 @[el2_dec_tlu_ctl.scala 686:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 687:64] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[el2_dec_tlu_ctl.scala 687:64] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[el2_dec_tlu_ctl.scala 689:60] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.exc_valid, _T_402) @[el2_dec_tlu_ctl.scala 689:58] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 690:20] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[el2_dec_tlu_ctl.scala 691:39] + node _T_404 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 691:63] + node _T_405 = and(_T_403, _T_404) @[el2_dec_tlu_ctl.scala 691:61] + node _T_406 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 691:83] + node lsu_exc_valid_r = and(_T_405, _T_406) @[el2_dec_tlu_ctl.scala 691:81] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 693:74] + _T_407 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 693:74] + lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] + node _T_408 = not(io.lsu_error_pkt_r.exc_type) @[el2_dec_tlu_ctl.scala 695:39] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.exc_type) @[el2_dec_tlu_ctl.scala 696:37] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.inst_type) @[el2_dec_tlu_ctl.scala 697:37] + node _T_409 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 701:48] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[el2_dec_tlu_ctl.scala 701:46] + node _T_411 = not(io.lsu_error_pkt_r.inst_type) @[el2_dec_tlu_ctl.scala 701:69] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.single_ecc_error) @[el2_dec_tlu_ctl.scala 701:99] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[el2_dec_tlu_ctl.scala 701:66] + node _T_413 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 704:51] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[el2_dec_tlu_ctl.scala 704:49] + node _T_415 = not(lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 704:64] + node _T_416 = and(_T_414, _T_415) @[el2_dec_tlu_ctl.scala 704:62] + node _T_417 = not(inst_acc_r) @[el2_dec_tlu_ctl.scala 704:81] + node _T_418 = and(_T_416, _T_417) @[el2_dec_tlu_ctl.scala 704:78] + node _T_419 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 704:95] + node _T_420 = and(_T_418, _T_419) @[el2_dec_tlu_ctl.scala 704:93] + node _T_421 = not(request_debug_mode_r_d1) @[el2_dec_tlu_ctl.scala 704:120] + node _T_422 = and(_T_420, _T_421) @[el2_dec_tlu_ctl.scala 704:118] + node _T_423 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 704:147] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[el2_dec_tlu_ctl.scala 704:145] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 707:37] + node _T_425 = or(_T_424, inst_acc_r) @[el2_dec_tlu_ctl.scala 707:52] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 707:78] + node _T_427 = or(_T_425, _T_426) @[el2_dec_tlu_ctl.scala 707:65] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 707:103] + tlu_i0_kill_writeb_r <= _T_428 @[el2_dec_tlu_ctl.scala 707:24] + io.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 708:28] + node _T_429 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 713:43] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[el2_dec_tlu_ctl.scala 713:41] + node _T_431 = or(io.exu_i0_br_error_r, io.exu_i0_br_start_error_r) @[el2_dec_tlu_ctl.scala 713:89] + node _T_432 = and(_T_430, _T_431) @[el2_dec_tlu_ctl.scala 713:65] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[el2_dec_tlu_ctl.scala 713:137] + node _T_434 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 713:158] + node _T_435 = and(_T_433, _T_434) @[el2_dec_tlu_ctl.scala 713:156] + node _T_436 = or(_T_432, _T_435) @[el2_dec_tlu_ctl.scala 713:120] + node _T_437 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 713:182] + node _T_438 = and(_T_436, _T_437) @[el2_dec_tlu_ctl.scala 713:179] + node _T_439 = not(lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 713:203] + node _T_440 = and(_T_438, _T_439) @[el2_dec_tlu_ctl.scala 713:200] + rfpc_i0_r <= _T_440 @[el2_dec_tlu_ctl.scala 713:13] + node _T_441 = not(io.dec_tlu_flush_lower_r) @[el2_dec_tlu_ctl.scala 716:69] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[el2_dec_tlu_ctl.scala 716:67] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[el2_dec_tlu_ctl.scala 716:43] + iccm_repair_state_ns <= _T_443 @[el2_dec_tlu_ctl.scala 716:24] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[el2_dec_tlu_ctl.scala 722:51] + node _T_445 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 722:87] + node _T_446 = or(_T_445, mret_r) @[el2_dec_tlu_ctl.scala 722:97] + node _T_447 = or(_T_446, take_reset) @[el2_dec_tlu_ctl.scala 722:106] + node _T_448 = or(_T_447, illegal_r) @[el2_dec_tlu_ctl.scala 722:119] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[el2_dec_tlu_ctl.scala 722:175] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[el2_dec_tlu_ctl.scala 722:152] + node _T_451 = or(_T_448, _T_450) @[el2_dec_tlu_ctl.scala 722:131] + node _T_452 = not(_T_451) @[el2_dec_tlu_ctl.scala 722:76] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[el2_dec_tlu_ctl.scala 722:74] + node _T_453 = and(io.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 725:50] + node _T_454 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 725:76] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[el2_dec_tlu_ctl.scala 725:74] + node _T_455 = and(io.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 726:62] + node _T_456 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 726:88] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[el2_dec_tlu_ctl.scala 726:86] + node _T_457 = and(io.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 727:46] + node _T_458 = not(tlu_flush_lower_r_d1) @[el2_dec_tlu_ctl.scala 727:72] + node _T_459 = and(_T_457, _T_458) @[el2_dec_tlu_ctl.scala 727:70] + node _T_460 = not(io.exu_i0_br_mp_r) @[el2_dec_tlu_ctl.scala 727:97] + node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] + node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] + io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49] + io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41] + io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] + io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49] + io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] + node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] + node _T_466 = and(_T_464, _T_465) @[el2_dec_tlu_ctl.scala 738:88] + node _T_467 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 738:115] + node _T_468 = not(_T_467) @[el2_dec_tlu_ctl.scala 738:110] + node _T_469 = and(_T_466, _T_468) @[el2_dec_tlu_ctl.scala 738:108] + node _T_470 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 738:132] + node _T_471 = and(_T_469, _T_470) @[el2_dec_tlu_ctl.scala 738:130] + ebreak_r <= _T_471 @[el2_dec_tlu_ctl.scala 738:13] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[el2_dec_tlu_ctl.scala 739:51] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 739:64] + node _T_474 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 739:90] + node _T_475 = and(_T_473, _T_474) @[el2_dec_tlu_ctl.scala 739:88] + node _T_476 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 739:110] + node _T_477 = and(_T_475, _T_476) @[el2_dec_tlu_ctl.scala 739:108] + ecall_r <= _T_477 @[el2_dec_tlu_ctl.scala 739:13] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[el2_dec_tlu_ctl.scala 740:17] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 740:46] + node _T_480 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 740:72] + node _T_481 = and(_T_479, _T_480) @[el2_dec_tlu_ctl.scala 740:70] + node _T_482 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 740:92] + node _T_483 = and(_T_481, _T_482) @[el2_dec_tlu_ctl.scala 740:90] + illegal_r <= _T_483 @[el2_dec_tlu_ctl.scala 740:13] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[el2_dec_tlu_ctl.scala 741:51] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 741:64] + node _T_486 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 741:90] + node _T_487 = and(_T_485, _T_486) @[el2_dec_tlu_ctl.scala 741:88] + node _T_488 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 741:110] + node _T_489 = and(_T_487, _T_488) @[el2_dec_tlu_ctl.scala 741:108] + mret_r <= _T_489 @[el2_dec_tlu_ctl.scala 741:13] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 743:49] + node _T_491 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 743:75] + node _T_492 = and(_T_490, _T_491) @[el2_dec_tlu_ctl.scala 743:73] + node _T_493 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 743:96] + node _T_494 = and(_T_492, _T_493) @[el2_dec_tlu_ctl.scala 743:94] + fence_i_r <= _T_494 @[el2_dec_tlu_ctl.scala 743:16] + node _T_495 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 744:44] + node _T_496 = and(io.ifu_ic_error_start, _T_495) @[el2_dec_tlu_ctl.scala 744:42] + node _T_497 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 744:66] + node _T_498 = or(_T_497, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 744:92] + node _T_499 = and(_T_496, _T_498) @[el2_dec_tlu_ctl.scala 744:63] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 744:122] + node _T_501 = and(_T_499, _T_500) @[el2_dec_tlu_ctl.scala 744:120] + ic_perr_r <= _T_501 @[el2_dec_tlu_ctl.scala 744:16] + node _T_502 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 745:52] + node _T_503 = and(io.ifu_iccm_rd_ecc_single_err, _T_502) @[el2_dec_tlu_ctl.scala 745:50] + node _T_504 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 745:74] + node _T_505 = or(_T_504, dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 745:100] + node _T_506 = and(_T_503, _T_505) @[el2_dec_tlu_ctl.scala 745:71] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[el2_dec_tlu_ctl.scala 745:130] + node _T_508 = and(_T_506, _T_507) @[el2_dec_tlu_ctl.scala 745:128] + iccm_sbecc_r <= _T_508 @[el2_dec_tlu_ctl.scala 745:16] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 746:48] + inst_acc_r_raw <= _T_509 @[el2_dec_tlu_ctl.scala 746:19] + node _T_510 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 747:34] + node _T_511 = and(inst_acc_r_raw, _T_510) @[el2_dec_tlu_ctl.scala 747:32] + node _T_512 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 747:47] + node _T_513 = and(_T_511, _T_512) @[el2_dec_tlu_ctl.scala 747:45] + inst_acc_r <= _T_513 @[el2_dec_tlu_ctl.scala 747:14] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 750:63] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 750:76] + node _T_516 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 750:102] + node _T_517 = and(_T_515, _T_516) @[el2_dec_tlu_ctl.scala 750:100] + node _T_518 = bits(dcsr, 15, 15) @[el2_dec_tlu_ctl.scala 750:126] + node _T_519 = and(_T_517, _T_518) @[el2_dec_tlu_ctl.scala 750:120] + node _T_520 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 750:143] + node _T_521 = and(_T_519, _T_520) @[el2_dec_tlu_ctl.scala 750:141] + ebreak_to_debug_mode_r <= _T_521 @[el2_dec_tlu_ctl.scala 750:26] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 752:58] + _T_522 <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 752:58] + ebreak_to_debug_mode_r_d1 <= _T_522 @[el2_dec_tlu_ctl.scala 752:28] + io.dec_tlu_fence_i_r <= fence_i_r @[el2_dec_tlu_ctl.scala 753:24] + node _T_523 = or(ebreak_r, ecall_r) @[el2_dec_tlu_ctl.scala 766:40] + node _T_524 = or(_T_523, illegal_r) @[el2_dec_tlu_ctl.scala 766:50] + node _T_525 = or(_T_524, inst_acc_r) @[el2_dec_tlu_ctl.scala 766:62] + node _T_526 = not(rfpc_i0_r) @[el2_dec_tlu_ctl.scala 766:78] + node _T_527 = and(_T_525, _T_526) @[el2_dec_tlu_ctl.scala 766:76] + node _T_528 = not(io.dec_tlu_dbg_halted) @[el2_dec_tlu_ctl.scala 766:91] + node i0_exception_valid_r = and(_T_527, _T_528) @[el2_dec_tlu_ctl.scala 766:89] + node _T_529 = not(take_nmi) @[el2_dec_tlu_ctl.scala 775:21] + node _T_530 = and(take_ext_int, _T_529) @[el2_dec_tlu_ctl.scala 775:19] + node _T_531 = bits(_T_530, 0, 0) @[el2_dec_tlu_ctl.scala 775:32] + node _T_532 = not(take_nmi) @[el2_dec_tlu_ctl.scala 776:23] + node _T_533 = and(take_timer_int, _T_532) @[el2_dec_tlu_ctl.scala 776:21] + node _T_534 = bits(_T_533, 0, 0) @[el2_dec_tlu_ctl.scala 776:34] + node _T_535 = not(take_nmi) @[el2_dec_tlu_ctl.scala 777:22] + node _T_536 = and(take_soft_int, _T_535) @[el2_dec_tlu_ctl.scala 777:20] + node _T_537 = bits(_T_536, 0, 0) @[el2_dec_tlu_ctl.scala 777:33] + node _T_538 = not(take_nmi) @[el2_dec_tlu_ctl.scala 778:28] + node _T_539 = and(take_int_timer0_int, _T_538) @[el2_dec_tlu_ctl.scala 778:26] + node _T_540 = bits(_T_539, 0, 0) @[el2_dec_tlu_ctl.scala 778:39] + node _T_541 = not(take_nmi) @[el2_dec_tlu_ctl.scala 779:28] + node _T_542 = and(take_int_timer1_int, _T_541) @[el2_dec_tlu_ctl.scala 779:26] + node _T_543 = bits(_T_542, 0, 0) @[el2_dec_tlu_ctl.scala 779:39] + node _T_544 = not(take_nmi) @[el2_dec_tlu_ctl.scala 780:20] + node _T_545 = and(take_ce_int, _T_544) @[el2_dec_tlu_ctl.scala 780:18] + node _T_546 = bits(_T_545, 0, 0) @[el2_dec_tlu_ctl.scala 780:31] + node _T_547 = not(take_nmi) @[el2_dec_tlu_ctl.scala 781:18] + node _T_548 = and(illegal_r, _T_547) @[el2_dec_tlu_ctl.scala 781:16] + node _T_549 = bits(_T_548, 0, 0) @[el2_dec_tlu_ctl.scala 781:29] + node _T_550 = not(take_nmi) @[el2_dec_tlu_ctl.scala 782:17] + node _T_551 = and(ecall_r, _T_550) @[el2_dec_tlu_ctl.scala 782:15] + node _T_552 = bits(_T_551, 0, 0) @[el2_dec_tlu_ctl.scala 782:28] + node _T_553 = not(take_nmi) @[el2_dec_tlu_ctl.scala 783:20] + node _T_554 = and(inst_acc_r, _T_553) @[el2_dec_tlu_ctl.scala 783:18] + node _T_555 = bits(_T_554, 0, 0) @[el2_dec_tlu_ctl.scala 783:31] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 784:16] + node _T_557 = not(take_nmi) @[el2_dec_tlu_ctl.scala 784:38] + node _T_558 = and(_T_556, _T_557) @[el2_dec_tlu_ctl.scala 784:36] + node _T_559 = bits(_T_558, 0, 0) @[el2_dec_tlu_ctl.scala 784:49] + node _T_560 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 785:21] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[el2_dec_tlu_ctl.scala 785:19] + node _T_562 = not(take_nmi) @[el2_dec_tlu_ctl.scala 785:37] + node _T_563 = and(_T_561, _T_562) @[el2_dec_tlu_ctl.scala 785:35] + node _T_564 = bits(_T_563, 0, 0) @[el2_dec_tlu_ctl.scala 785:48] + node _T_565 = not(lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 786:22] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[el2_dec_tlu_ctl.scala 786:20] + node _T_567 = not(take_nmi) @[el2_dec_tlu_ctl.scala 786:38] + node _T_568 = and(_T_566, _T_567) @[el2_dec_tlu_ctl.scala 786:36] + node _T_569 = bits(_T_568, 0, 0) @[el2_dec_tlu_ctl.scala 786:49] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 787:19] + node _T_571 = not(take_nmi) @[el2_dec_tlu_ctl.scala 787:36] + node _T_572 = and(_T_570, _T_571) @[el2_dec_tlu_ctl.scala 787:34] + node _T_573 = bits(_T_572, 0, 0) @[el2_dec_tlu_ctl.scala 787:47] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[el2_dec_tlu_ctl.scala 788:20] + node _T_575 = not(take_nmi) @[el2_dec_tlu_ctl.scala 788:37] + node _T_576 = and(_T_574, _T_575) @[el2_dec_tlu_ctl.scala 788:35] + node _T_577 = bits(_T_576, 0, 0) @[el2_dec_tlu_ctl.scala 788:48] + node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_581 = mux(_T_540, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_582 = mux(_T_543, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_583 = mux(_T_546, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_584 = mux(_T_549, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_585 = mux(_T_552, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_586 = mux(_T_555, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_587 = mux(_T_559, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_588 = mux(_T_564, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_589 = mux(_T_569, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_590 = mux(_T_573, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_591 = mux(_T_577, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_592 = or(_T_578, _T_579) @[Mux.scala 27:72] + node _T_593 = or(_T_592, _T_580) @[Mux.scala 27:72] + node _T_594 = or(_T_593, _T_581) @[Mux.scala 27:72] + node _T_595 = or(_T_594, _T_582) @[Mux.scala 27:72] + node _T_596 = or(_T_595, _T_583) @[Mux.scala 27:72] + node _T_597 = or(_T_596, _T_584) @[Mux.scala 27:72] + node _T_598 = or(_T_597, _T_585) @[Mux.scala 27:72] + node _T_599 = or(_T_598, _T_586) @[Mux.scala 27:72] + node _T_600 = or(_T_599, _T_587) @[Mux.scala 27:72] + node _T_601 = or(_T_600, _T_588) @[Mux.scala 27:72] + node _T_602 = or(_T_601, _T_589) @[Mux.scala 27:72] + node _T_603 = or(_T_602, _T_590) @[Mux.scala 27:72] + node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] + wire exc_cause_r : UInt<5> @[Mux.scala 27:72] + exc_cause_r <= _T_604 @[Mux.scala 27:72] + node _T_605 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 799:23] + node _T_606 = and(_T_605, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 799:48] + node _T_607 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 799:70] + node _T_608 = and(_T_606, _T_607) @[el2_dec_tlu_ctl.scala 799:65] + node _T_609 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 799:91] + node _T_610 = and(_T_608, _T_609) @[el2_dec_tlu_ctl.scala 799:83] + mhwakeup_ready <= _T_610 @[el2_dec_tlu_ctl.scala 799:19] + node _T_611 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 800:22] + node _T_612 = and(_T_611, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 800:47] + node _T_613 = bits(mip, 2, 2) @[el2_dec_tlu_ctl.scala 800:69] + node _T_614 = and(_T_612, _T_613) @[el2_dec_tlu_ctl.scala 800:64] + node _T_615 = bits(mie_ns, 2, 2) @[el2_dec_tlu_ctl.scala 800:90] + node _T_616 = and(_T_614, _T_615) @[el2_dec_tlu_ctl.scala 800:82] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[el2_dec_tlu_ctl.scala 800:103] + node _T_618 = and(_T_616, _T_617) @[el2_dec_tlu_ctl.scala 800:101] + ext_int_ready <= _T_618 @[el2_dec_tlu_ctl.scala 800:19] + node _T_619 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 801:22] + node _T_620 = and(_T_619, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 801:47] + node _T_621 = bits(mip, 5, 5) @[el2_dec_tlu_ctl.scala 801:69] + node _T_622 = and(_T_620, _T_621) @[el2_dec_tlu_ctl.scala 801:64] + node _T_623 = bits(mie_ns, 5, 5) @[el2_dec_tlu_ctl.scala 801:90] + node _T_624 = and(_T_622, _T_623) @[el2_dec_tlu_ctl.scala 801:82] + ce_int_ready <= _T_624 @[el2_dec_tlu_ctl.scala 801:19] + node _T_625 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 802:22] + node _T_626 = and(_T_625, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 802:47] + node _T_627 = bits(mip, 0, 0) @[el2_dec_tlu_ctl.scala 802:69] + node _T_628 = and(_T_626, _T_627) @[el2_dec_tlu_ctl.scala 802:64] + node _T_629 = bits(mie_ns, 0, 0) @[el2_dec_tlu_ctl.scala 802:90] + node _T_630 = and(_T_628, _T_629) @[el2_dec_tlu_ctl.scala 802:82] + soft_int_ready <= _T_630 @[el2_dec_tlu_ctl.scala 802:19] + node _T_631 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 803:22] + node _T_632 = and(_T_631, mstatus_mie_ns) @[el2_dec_tlu_ctl.scala 803:47] + node _T_633 = bits(mip, 1, 1) @[el2_dec_tlu_ctl.scala 803:69] + node _T_634 = and(_T_632, _T_633) @[el2_dec_tlu_ctl.scala 803:64] + node _T_635 = bits(mie_ns, 1, 1) @[el2_dec_tlu_ctl.scala 803:90] + node _T_636 = and(_T_634, _T_635) @[el2_dec_tlu_ctl.scala 803:82] + timer_int_ready <= _T_636 @[el2_dec_tlu_ctl.scala 803:19] + node _T_637 = bits(mie_ns, 4, 4) @[el2_dec_tlu_ctl.scala 806:56] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[el2_dec_tlu_ctl.scala 806:48] + node _T_638 = bits(mip, 4, 4) @[el2_dec_tlu_ctl.scala 807:33] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 807:46] + node _T_639 = bits(mie_ns, 3, 3) @[el2_dec_tlu_ctl.scala 808:56] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[el2_dec_tlu_ctl.scala 808:48] + node _T_640 = bits(mip, 3, 3) @[el2_dec_tlu_ctl.scala 809:33] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 809:46] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 813:51] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 813:73] + node int_timer_stalled = or(_T_642, mret_r) @[el2_dec_tlu_ctl.scala 813:97] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 815:71] + node _T_644 = and(int_timer0_int_ready, _T_643) @[el2_dec_tlu_ctl.scala 815:48] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 815:120] + node _T_646 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 815:146] + node _T_647 = and(_T_645, _T_646) @[el2_dec_tlu_ctl.scala 815:144] + node _T_648 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 815:167] + node _T_649 = and(_T_647, _T_648) @[el2_dec_tlu_ctl.scala 815:165] + node _T_650 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 815:189] + node _T_651 = and(_T_649, _T_650) @[el2_dec_tlu_ctl.scala 815:187] + node _T_652 = or(_T_644, _T_651) @[el2_dec_tlu_ctl.scala 815:93] + int_timer0_int_hold <= _T_652 @[el2_dec_tlu_ctl.scala 815:23] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[el2_dec_tlu_ctl.scala 816:71] + node _T_654 = and(int_timer1_int_ready, _T_653) @[el2_dec_tlu_ctl.scala 816:48] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 816:120] + node _T_656 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 816:146] + node _T_657 = and(_T_655, _T_656) @[el2_dec_tlu_ctl.scala 816:144] + node _T_658 = not(take_ext_int_start) @[el2_dec_tlu_ctl.scala 816:167] + node _T_659 = and(_T_657, _T_658) @[el2_dec_tlu_ctl.scala 816:165] + node _T_660 = not(debug_mode_status) @[el2_dec_tlu_ctl.scala 816:189] + node _T_661 = and(_T_659, _T_660) @[el2_dec_tlu_ctl.scala 816:187] + node _T_662 = or(_T_654, _T_661) @[el2_dec_tlu_ctl.scala 816:93] + int_timer1_int_hold <= _T_662 @[el2_dec_tlu_ctl.scala 816:23] + node _T_663 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 818:58] + node _T_664 = and(debug_mode_status, _T_663) @[el2_dec_tlu_ctl.scala 818:56] + internal_dbg_halt_timers <= _T_664 @[el2_dec_tlu_ctl.scala 818:28] + node _T_665 = not(dcsr_single_step_running) @[el2_dec_tlu_ctl.scala 820:54] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 820:80] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[el2_dec_tlu_ctl.scala 820:51] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 820:106] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[el2_dec_tlu_ctl.scala 820:134] + node _T_670 = or(_T_669, take_nmi) @[el2_dec_tlu_ctl.scala 820:154] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 820:165] + node _T_672 = or(_T_671, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 820:190] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[el2_dec_tlu_ctl.scala 820:213] + node _T_674 = or(_T_673, mret_r) @[el2_dec_tlu_ctl.scala 820:237] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 820:246] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 824:58] + _T_675 <= take_ext_int_start @[el2_dec_tlu_ctl.scala 824:58] + take_ext_int_start_d1 <= _T_675 @[el2_dec_tlu_ctl.scala 824:26] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 825:58] + _T_676 <= take_ext_int_start_d1 @[el2_dec_tlu_ctl.scala 825:58] + take_ext_int_start_d2 <= _T_676 @[el2_dec_tlu_ctl.scala 825:26] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 826:58] + _T_677 <= take_ext_int_start_d2 @[el2_dec_tlu_ctl.scala 826:58] + take_ext_int_start_d3 <= _T_677 @[el2_dec_tlu_ctl.scala 826:26] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 827:58] + _T_678 <= ext_int_freeze @[el2_dec_tlu_ctl.scala 827:58] + ext_int_freeze_d1 <= _T_678 @[el2_dec_tlu_ctl.scala 827:26] + node _T_679 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 828:43] + node _T_680 = and(ext_int_ready, _T_679) @[el2_dec_tlu_ctl.scala 828:41] + take_ext_int_start <= _T_680 @[el2_dec_tlu_ctl.scala 828:24] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[el2_dec_tlu_ctl.scala 830:42] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[el2_dec_tlu_ctl.scala 830:66] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[el2_dec_tlu_ctl.scala 830:90] + ext_int_freeze <= _T_683 @[el2_dec_tlu_ctl.scala 830:20] + node _T_684 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 831:63] + node _T_685 = not(_T_684) @[el2_dec_tlu_ctl.scala 831:45] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[el2_dec_tlu_ctl.scala 831:43] + take_ext_int <= _T_686 @[el2_dec_tlu_ctl.scala 831:18] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 832:45] + fast_int_meicpct <= _T_687 @[el2_dec_tlu_ctl.scala 832:22] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[el2_dec_tlu_ctl.scala 833:37] + node _T_688 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 846:34] + node _T_689 = and(ce_int_ready, _T_688) @[el2_dec_tlu_ctl.scala 846:32] + node _T_690 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 846:51] + node _T_691 = and(_T_689, _T_690) @[el2_dec_tlu_ctl.scala 846:49] + take_ce_int <= _T_691 @[el2_dec_tlu_ctl.scala 846:16] + node _T_692 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 847:37] + node _T_693 = and(soft_int_ready, _T_692) @[el2_dec_tlu_ctl.scala 847:35] + node _T_694 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 847:54] + node _T_695 = and(_T_693, _T_694) @[el2_dec_tlu_ctl.scala 847:52] + node _T_696 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 847:70] + node _T_697 = and(_T_695, _T_696) @[el2_dec_tlu_ctl.scala 847:68] + take_soft_int <= _T_697 @[el2_dec_tlu_ctl.scala 847:17] + node _T_698 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 848:39] + node _T_699 = and(timer_int_ready, _T_698) @[el2_dec_tlu_ctl.scala 848:37] + node _T_700 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 848:57] + node _T_701 = and(_T_699, _T_700) @[el2_dec_tlu_ctl.scala 848:55] + node _T_702 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 848:74] + node _T_703 = and(_T_701, _T_702) @[el2_dec_tlu_ctl.scala 848:72] + node _T_704 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 848:90] + node _T_705 = and(_T_703, _T_704) @[el2_dec_tlu_ctl.scala 848:88] + take_timer_int <= _T_705 @[el2_dec_tlu_ctl.scala 848:18] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 849:48] + node _T_707 = and(_T_706, int_timer0_int_possible) @[el2_dec_tlu_ctl.scala 849:73] + node _T_708 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 849:101] + node _T_709 = and(_T_707, _T_708) @[el2_dec_tlu_ctl.scala 849:99] + node _T_710 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 849:128] + node _T_711 = and(_T_709, _T_710) @[el2_dec_tlu_ctl.scala 849:126] + node _T_712 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 849:147] + node _T_713 = and(_T_711, _T_712) @[el2_dec_tlu_ctl.scala 849:145] + node _T_714 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 849:165] + node _T_715 = and(_T_713, _T_714) @[el2_dec_tlu_ctl.scala 849:163] + node _T_716 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 849:182] + node _T_717 = and(_T_715, _T_716) @[el2_dec_tlu_ctl.scala 849:180] + node _T_718 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 849:198] + node _T_719 = and(_T_717, _T_718) @[el2_dec_tlu_ctl.scala 849:196] + take_int_timer0_int <= _T_719 @[el2_dec_tlu_ctl.scala 849:23] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[el2_dec_tlu_ctl.scala 850:48] + node _T_721 = and(_T_720, int_timer1_int_possible) @[el2_dec_tlu_ctl.scala 850:73] + node _T_722 = not(io.dec_csr_stall_int_ff) @[el2_dec_tlu_ctl.scala 850:101] + node _T_723 = and(_T_721, _T_722) @[el2_dec_tlu_ctl.scala 850:99] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[el2_dec_tlu_ctl.scala 850:151] + node _T_725 = not(_T_724) @[el2_dec_tlu_ctl.scala 850:128] + node _T_726 = and(_T_723, _T_725) @[el2_dec_tlu_ctl.scala 850:126] + node _T_727 = not(timer_int_ready) @[el2_dec_tlu_ctl.scala 850:178] + node _T_728 = and(_T_726, _T_727) @[el2_dec_tlu_ctl.scala 850:176] + node _T_729 = not(soft_int_ready) @[el2_dec_tlu_ctl.scala 850:197] + node _T_730 = and(_T_728, _T_729) @[el2_dec_tlu_ctl.scala 850:195] + node _T_731 = not(ext_int_ready) @[el2_dec_tlu_ctl.scala 850:215] + node _T_732 = and(_T_730, _T_731) @[el2_dec_tlu_ctl.scala 850:213] + node _T_733 = not(ce_int_ready) @[el2_dec_tlu_ctl.scala 850:232] + node _T_734 = and(_T_732, _T_733) @[el2_dec_tlu_ctl.scala 850:230] + node _T_735 = not(block_interrupts) @[el2_dec_tlu_ctl.scala 850:248] + node _T_736 = and(_T_734, _T_735) @[el2_dec_tlu_ctl.scala 850:246] + take_int_timer1_int <= _T_736 @[el2_dec_tlu_ctl.scala 850:23] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[el2_dec_tlu_ctl.scala 851:31] + take_reset <= _T_737 @[el2_dec_tlu_ctl.scala 851:14] + node _T_738 = not(internal_pmu_fw_halt_mode) @[el2_dec_tlu_ctl.scala 852:34] + node _T_739 = and(nmi_int_detected, _T_738) @[el2_dec_tlu_ctl.scala 852:32] + node _T_740 = not(internal_dbg_halt_mode) @[el2_dec_tlu_ctl.scala 852:64] + node _T_741 = bits(dcsr, 11, 11) @[el2_dec_tlu_ctl.scala 852:124] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[el2_dec_tlu_ctl.scala 852:118] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 852:140] + node _T_744 = and(_T_742, _T_743) @[el2_dec_tlu_ctl.scala 852:138] + node _T_745 = not(dcsr_single_step_done_f) @[el2_dec_tlu_ctl.scala 852:165] + node _T_746 = and(_T_744, _T_745) @[el2_dec_tlu_ctl.scala 852:163] + node _T_747 = or(_T_740, _T_746) @[el2_dec_tlu_ctl.scala 852:88] + node _T_748 = and(_T_739, _T_747) @[el2_dec_tlu_ctl.scala 852:61] + node _T_749 = not(synchronous_flush_r) @[el2_dec_tlu_ctl.scala 852:194] + node _T_750 = and(_T_748, _T_749) @[el2_dec_tlu_ctl.scala 852:192] + node _T_751 = not(mret_r) @[el2_dec_tlu_ctl.scala 852:217] + node _T_752 = and(_T_750, _T_751) @[el2_dec_tlu_ctl.scala 852:215] + node _T_753 = not(take_reset) @[el2_dec_tlu_ctl.scala 852:227] + node _T_754 = and(_T_752, _T_753) @[el2_dec_tlu_ctl.scala 852:225] + node _T_755 = not(ebreak_to_debug_mode_r) @[el2_dec_tlu_ctl.scala 852:241] + node _T_756 = and(_T_754, _T_755) @[el2_dec_tlu_ctl.scala 852:239] + node _T_757 = not(ext_int_freeze_d1) @[el2_dec_tlu_ctl.scala 852:268] + node _T_758 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 852:331] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[el2_dec_tlu_ctl.scala 852:312] + node _T_760 = or(_T_757, _T_759) @[el2_dec_tlu_ctl.scala 852:287] + node _T_761 = and(_T_756, _T_760) @[el2_dec_tlu_ctl.scala 852:265] + take_nmi <= _T_761 @[el2_dec_tlu_ctl.scala 852:12] + node _T_762 = or(take_ext_int, take_timer_int) @[el2_dec_tlu_ctl.scala 855:37] + node _T_763 = or(_T_762, take_soft_int) @[el2_dec_tlu_ctl.scala 855:54] + node _T_764 = or(_T_763, take_nmi) @[el2_dec_tlu_ctl.scala 855:70] + node _T_765 = or(_T_764, take_ce_int) @[el2_dec_tlu_ctl.scala 855:81] + node _T_766 = or(_T_765, take_int_timer0_int) @[el2_dec_tlu_ctl.scala 855:95] + node _T_767 = or(_T_766, take_int_timer1_int) @[el2_dec_tlu_ctl.scala 855:117] + interrupt_valid_r <= _T_767 @[el2_dec_tlu_ctl.scala 855:21] + node _T_768 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 860:33] + node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_772 = add(_T_769, _T_771) @[el2_dec_tlu_ctl.scala 860:50] + node vectored_path = tail(_T_772, 1) @[el2_dec_tlu_ctl.scala 860:50] + node _T_773 = bits(take_nmi, 0, 0) @[el2_dec_tlu_ctl.scala 861:37] + node _T_774 = bits(mtvec, 0, 0) @[el2_dec_tlu_ctl.scala 861:66] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 861:70] + node _T_776 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 861:103] + node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[el2_dec_tlu_ctl.scala 861:60] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[el2_dec_tlu_ctl.scala 861:27] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[el2_dec_tlu_ctl.scala 862:35] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 862:47] + node _T_781 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 862:95] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[el2_dec_tlu_ctl.scala 862:93] + node _T_783 = or(_T_780, _T_782) @[el2_dec_tlu_ctl.scala 862:73] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 862:130] + node _T_785 = and(rfpc_i0_r, _T_784) @[el2_dec_tlu_ctl.scala 862:128] + node sel_npc_r = or(_T_783, _T_785) @[el2_dec_tlu_ctl.scala 862:115] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[el2_dec_tlu_ctl.scala 863:42] + node sel_npc_resume = or(_T_786, pause_expired_r) @[el2_dec_tlu_ctl.scala 863:65] + node _T_787 = orr(io.lsu_fir_error) @[el2_dec_tlu_ctl.scala 864:64] + node _T_788 = not(_T_787) @[el2_dec_tlu_ctl.scala 864:46] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[el2_dec_tlu_ctl.scala 864:44] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[el2_dec_tlu_ctl.scala 865:48] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 865:60] + node _T_791 = or(_T_790, fence_i_r) @[el2_dec_tlu_ctl.scala 865:78] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[el2_dec_tlu_ctl.scala 865:90] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[el2_dec_tlu_ctl.scala 865:107] + node _T_794 = or(_T_793, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 865:134] + node _T_795 = or(_T_794, sel_npc_resume) @[el2_dec_tlu_ctl.scala 865:156] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[el2_dec_tlu_ctl.scala 865:174] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 865:200] + synchronous_flush_r <= _T_797 @[el2_dec_tlu_ctl.scala 865:24] + node _T_798 = or(interrupt_valid_r, mret_r) @[el2_dec_tlu_ctl.scala 866:42] + node _T_799 = or(_T_798, synchronous_flush_r) @[el2_dec_tlu_ctl.scala 866:51] + node _T_800 = or(_T_799, take_halt) @[el2_dec_tlu_ctl.scala 866:73] + node _T_801 = or(_T_800, take_reset) @[el2_dec_tlu_ctl.scala 866:85] + node _T_802 = or(_T_801, take_ext_int_start) @[el2_dec_tlu_ctl.scala 866:98] + tlu_flush_lower_r <= _T_802 @[el2_dec_tlu_ctl.scala 866:21] + node _T_803 = bits(take_reset, 0, 0) @[el2_dec_tlu_ctl.scala 868:41] + node _T_804 = bits(sel_fir_addr, 0, 0) @[el2_dec_tlu_ctl.scala 869:20] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 870:14] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 870:32] + node _T_807 = and(_T_805, _T_806) @[el2_dec_tlu_ctl.scala 870:21] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:14] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:32] + node _T_810 = and(_T_808, _T_809) @[el2_dec_tlu_ctl.scala 871:21] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 871:62] + node _T_812 = and(_T_810, _T_811) @[el2_dec_tlu_ctl.scala 871:39] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 871:80] + node _T_814 = and(_T_812, _T_813) @[el2_dec_tlu_ctl.scala 871:69] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 872:23] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 872:44] + node _T_817 = and(_T_815, _T_816) @[el2_dec_tlu_ctl.scala 872:30] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[el2_dec_tlu_ctl.scala 873:28] + node _T_819 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 873:68] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[el2_dec_tlu_ctl.scala 873:66] + node _T_821 = or(_T_818, _T_820) @[el2_dec_tlu_ctl.scala 873:46] + node _T_822 = not(interrupt_valid_r) @[el2_dec_tlu_ctl.scala 873:93] + node _T_823 = and(_T_821, _T_822) @[el2_dec_tlu_ctl.scala 873:91] + node _T_824 = not(sel_fir_addr) @[el2_dec_tlu_ctl.scala 873:114] + node _T_825 = and(_T_823, _T_824) @[el2_dec_tlu_ctl.scala 873:112] + node _T_826 = bits(_T_825, 0, 0) @[el2_dec_tlu_ctl.scala 873:129] + node _T_827 = bits(mtvec, 30, 1) @[el2_dec_tlu_ctl.scala 873:149] + node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_829 = not(take_nmi) @[el2_dec_tlu_ctl.scala 874:6] + node _T_830 = and(_T_829, mret_r) @[el2_dec_tlu_ctl.scala 874:16] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_tlu_ctl.scala 874:26] + node _T_832 = not(take_nmi) @[el2_dec_tlu_ctl.scala 875:6] + node _T_833 = and(_T_832, debug_resume_req_f) @[el2_dec_tlu_ctl.scala 875:16] + node _T_834 = bits(_T_833, 0, 0) @[el2_dec_tlu_ctl.scala 875:38] + node _T_835 = not(take_nmi) @[el2_dec_tlu_ctl.scala 876:6] + node _T_836 = and(_T_835, sel_npc_resume) @[el2_dec_tlu_ctl.scala 876:16] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_tlu_ctl.scala 876:34] + node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_841 = mux(_T_817, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_842 = mux(_T_826, _T_828, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_843 = mux(_T_831, mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_844 = mux(_T_834, dpc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_845 = mux(_T_837, npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = or(_T_838, _T_839) @[Mux.scala 27:72] + node _T_847 = or(_T_846, _T_840) @[Mux.scala 27:72] + node _T_848 = or(_T_847, _T_841) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_842) @[Mux.scala 27:72] + node _T_850 = or(_T_849, _T_843) @[Mux.scala 27:72] + node _T_851 = or(_T_850, _T_844) @[Mux.scala 27:72] + node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] + wire _T_853 : UInt<31> @[Mux.scala 27:72] + _T_853 <= _T_852 @[Mux.scala 27:72] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[el2_dec_tlu_ctl.scala 868:29] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 879:58] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 879:58] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 881:33] + io.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 882:33] + io.dec_tlu_flush_path_r <= tlu_flush_path_r @[el2_dec_tlu_ctl.scala 883:33] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[el2_dec_tlu_ctl.scala 886:44] + node _T_855 = or(_T_854, interrupt_valid_r) @[el2_dec_tlu_ctl.scala 886:67] + node _T_856 = not(trigger_hit_dmode_r) @[el2_dec_tlu_ctl.scala 886:109] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[el2_dec_tlu_ctl.scala 886:107] + node exc_or_int_valid_r = or(_T_855, _T_857) @[el2_dec_tlu_ctl.scala 886:87] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 888:82] + _T_858 <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 888:82] + interrupt_valid_r_d1 <= _T_858 @[el2_dec_tlu_ctl.scala 888:49] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 889:81] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 889:81] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 890:82] + _T_859 <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 890:82] + exc_or_int_valid_r_d1 <= _T_859 @[el2_dec_tlu_ctl.scala 890:49] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 891:89] + exc_cause_wb <= exc_cause_r @[el2_dec_tlu_ctl.scala 891:89] + node _T_860 = not(illegal_r) @[el2_dec_tlu_ctl.scala 892:119] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[el2_dec_tlu_ctl.scala 892:117] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 892:97] + i0_valid_wb <= _T_861 @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 893:81] + trigger_hit_r_d1 <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 893:81] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 894:90] + _T_862 <= take_nmi @[el2_dec_tlu_ctl.scala 894:90] + take_nmi_r_d1 <= _T_862 @[el2_dec_tlu_ctl.scala 894:57] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 895:90] + _T_863 <= pause_expired_r @[el2_dec_tlu_ctl.scala 895:90] + pause_expired_wb <= _T_863 @[el2_dec_tlu_ctl.scala 895:57] + inst csr of csr_tlu @[el2_dec_tlu_ctl.scala 897:17] + csr.clock <= clock + csr.reset <= reset + csr.io.free_clk <= io.free_clk @[el2_dec_tlu_ctl.scala 898:44] + csr.io.active_clk <= io.active_clk @[el2_dec_tlu_ctl.scala 899:44] + csr.io.scan_mode <= io.scan_mode @[el2_dec_tlu_ctl.scala 900:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[el2_dec_tlu_ctl.scala 901:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[el2_dec_tlu_ctl.scala 902:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 903:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[el2_dec_tlu_ctl.scala 904:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[el2_dec_tlu_ctl.scala 905:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec_tlu_ctl.scala 906:44] + csr.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 907:44] + csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec_tlu_ctl.scala 908:44] + csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec_tlu_ctl.scala 909:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec_tlu_ctl.scala 910:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[el2_dec_tlu_ctl.scala 911:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[el2_dec_tlu_ctl.scala 912:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[el2_dec_tlu_ctl.scala 913:44] + csr.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec_tlu_ctl.scala 914:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[el2_dec_tlu_ctl.scala 915:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[el2_dec_tlu_ctl.scala 915:44] + csr.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec_tlu_ctl.scala 916:44] + csr.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec_tlu_ctl.scala 917:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[el2_dec_tlu_ctl.scala 918:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec_tlu_ctl.scala 919:44] + csr.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec_tlu_ctl.scala 920:44] + csr.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec_tlu_ctl.scala 921:44] + csr.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec_tlu_ctl.scala 922:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[el2_dec_tlu_ctl.scala 923:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[el2_dec_tlu_ctl.scala 924:44] + csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec_tlu_ctl.scala 925:44] + csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec_tlu_ctl.scala 926:44] + csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec_tlu_ctl.scala 927:44] + csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec_tlu_ctl.scala 928:44] + csr.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 929:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[el2_dec_tlu_ctl.scala 930:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[el2_dec_tlu_ctl.scala 931:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[el2_dec_tlu_ctl.scala 932:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[el2_dec_tlu_ctl.scala 933:44] + csr.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec_tlu_ctl.scala 934:44] + csr.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec_tlu_ctl.scala 935:44] + csr.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec_tlu_ctl.scala 936:44] + csr.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec_tlu_ctl.scala 937:44] + csr.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec_tlu_ctl.scala 938:44] + csr.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec_tlu_ctl.scala 939:44] + csr.io.pic_pl <= io.pic_pl @[el2_dec_tlu_ctl.scala 940:44] + csr.io.pic_claimid <= io.pic_claimid @[el2_dec_tlu_ctl.scala 941:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec_tlu_ctl.scala 942:44] + csr.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec_tlu_ctl.scala 943:44] + csr.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec_tlu_ctl.scala 944:44] + csr.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec_tlu_ctl.scala 945:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 946:44] + csr.io.lsu_error_pkt_r.addr <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.mscause <= io.lsu_error_pkt_r.mscause @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.exc_type <= io.lsu_error_pkt_r.exc_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.inst_type <= io.lsu_error_pkt_r.inst_type @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.single_ecc_error <= io.lsu_error_pkt_r.single_ecc_error @[el2_dec_tlu_ctl.scala 947:44] + csr.io.lsu_error_pkt_r.exc_valid <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 947:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 948:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 949:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 950:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 951:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 952:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 953:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 954:44] + io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[el2_dec_tlu_ctl.scala 955:44] + io.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[el2_dec_tlu_ctl.scala 956:44] + io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[el2_dec_tlu_ctl.scala 957:44] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[el2_dec_tlu_ctl.scala 958:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec_tlu_ctl.scala 959:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[el2_dec_tlu_ctl.scala 960:44] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec_tlu_ctl.scala 961:44] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec_tlu_ctl.scala 961:44] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_ <= csr.io.trigger_pkt_any[0].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_ <= csr.io.trigger_pkt_any[1].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_ <= csr.io.trigger_pkt_any[2].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_ <= csr.io.trigger_pkt_any[3].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[el2_dec_tlu_ctl.scala 965:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[el2_dec_tlu_ctl.scala 966:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[el2_dec_tlu_ctl.scala 967:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[el2_dec_tlu_ctl.scala 968:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[el2_dec_tlu_ctl.scala 969:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 970:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[el2_dec_tlu_ctl.scala 971:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[el2_dec_tlu_ctl.scala 972:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[el2_dec_tlu_ctl.scala 973:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[el2_dec_tlu_ctl.scala 974:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[el2_dec_tlu_ctl.scala 975:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[el2_dec_tlu_ctl.scala 976:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[el2_dec_tlu_ctl.scala 977:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[el2_dec_tlu_ctl.scala 978:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[el2_dec_tlu_ctl.scala 979:40] + io.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[el2_dec_tlu_ctl.scala 980:40] + io.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[el2_dec_tlu_ctl.scala 981:40] + io.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[el2_dec_tlu_ctl.scala 982:40] + io.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[el2_dec_tlu_ctl.scala 983:40] + io.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[el2_dec_tlu_ctl.scala 984:40] + io.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[el2_dec_tlu_ctl.scala 985:40] + io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[el2_dec_tlu_ctl.scala 986:40] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[el2_dec_tlu_ctl.scala 987:44] + csr.io.lsu_error_pkt_r.addr <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.mscause <= io.lsu_error_pkt_r.mscause @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.exc_type <= io.lsu_error_pkt_r.exc_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.inst_type <= io.lsu_error_pkt_r.inst_type @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.single_ecc_error <= io.lsu_error_pkt_r.single_ecc_error @[el2_dec_tlu_ctl.scala 988:44] + csr.io.lsu_error_pkt_r.exc_valid <= io.lsu_error_pkt_r.exc_valid @[el2_dec_tlu_ctl.scala 988:44] + csr.io.mexintpend <= io.mexintpend @[el2_dec_tlu_ctl.scala 989:44] + csr.io.exu_npc_r <= io.exu_npc_r @[el2_dec_tlu_ctl.scala 990:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec_tlu_ctl.scala 991:44] + csr.io.rst_vec <= io.rst_vec @[el2_dec_tlu_ctl.scala 992:44] + csr.io.core_id <= io.core_id @[el2_dec_tlu_ctl.scala 993:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[el2_dec_tlu_ctl.scala 994:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[el2_dec_tlu_ctl.scala 995:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[el2_dec_tlu_ctl.scala 998:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[el2_dec_tlu_ctl.scala 999:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[el2_dec_tlu_ctl.scala 1000:39] + csr.io.mret_r <= mret_r @[el2_dec_tlu_ctl.scala 1001:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[el2_dec_tlu_ctl.scala 1002:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[el2_dec_tlu_ctl.scala 1003:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[el2_dec_tlu_ctl.scala 1004:39] + csr.io.timer_int_sync <= timer_int_sync @[el2_dec_tlu_ctl.scala 1005:39] + csr.io.soft_int_sync <= soft_int_sync @[el2_dec_tlu_ctl.scala 1006:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[el2_dec_tlu_ctl.scala 1007:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[el2_dec_tlu_ctl.scala 1008:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[el2_dec_tlu_ctl.scala 1009:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec_tlu_ctl.scala 1010:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[el2_dec_tlu_ctl.scala 1011:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[el2_dec_tlu_ctl.scala 1012:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[el2_dec_tlu_ctl.scala 1013:39] + csr.io.reset_delayed <= reset_delayed @[el2_dec_tlu_ctl.scala 1014:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[el2_dec_tlu_ctl.scala 1015:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[el2_dec_tlu_ctl.scala 1016:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1017:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[el2_dec_tlu_ctl.scala 1018:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[el2_dec_tlu_ctl.scala 1019:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 1020:39] + csr.io.inst_acc_r <= inst_acc_r @[el2_dec_tlu_ctl.scala 1021:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[el2_dec_tlu_ctl.scala 1022:39] + csr.io.take_nmi <= take_nmi @[el2_dec_tlu_ctl.scala 1023:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.addr @[el2_dec_tlu_ctl.scala 1024:39] + csr.io.exc_cause_r <= exc_cause_r @[el2_dec_tlu_ctl.scala 1025:39] + csr.io.i0_valid_wb <= i0_valid_wb @[el2_dec_tlu_ctl.scala 1026:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[el2_dec_tlu_ctl.scala 1027:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[el2_dec_tlu_ctl.scala 1028:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[el2_dec_tlu_ctl.scala 1029:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[el2_dec_tlu_ctl.scala 1030:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[el2_dec_tlu_ctl.scala 1031:39] + csr.io.exc_cause_wb <= exc_cause_wb @[el2_dec_tlu_ctl.scala 1032:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[el2_dec_tlu_ctl.scala 1033:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[el2_dec_tlu_ctl.scala 1034:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[el2_dec_tlu_ctl.scala 1035:39] + csr.io.ebreak_r <= ebreak_r @[el2_dec_tlu_ctl.scala 1036:39] + csr.io.ecall_r <= ecall_r @[el2_dec_tlu_ctl.scala 1037:39] + csr.io.illegal_r <= illegal_r @[el2_dec_tlu_ctl.scala 1038:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[el2_dec_tlu_ctl.scala 1039:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[el2_dec_tlu_ctl.scala 1040:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[el2_dec_tlu_ctl.scala 1041:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[el2_dec_tlu_ctl.scala 1042:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[el2_dec_tlu_ctl.scala 1043:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[el2_dec_tlu_ctl.scala 1044:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[el2_dec_tlu_ctl.scala 1045:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[el2_dec_tlu_ctl.scala 1046:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[el2_dec_tlu_ctl.scala 1047:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[el2_dec_tlu_ctl.scala 1048:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[el2_dec_tlu_ctl.scala 1049:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[el2_dec_tlu_ctl.scala 1050:51] + csr.io.take_ext_int_start <= take_ext_int_start @[el2_dec_tlu_ctl.scala 1051:47] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[el2_dec_tlu_ctl.scala 1052:43] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[el2_dec_tlu_ctl.scala 1053:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[el2_dec_tlu_ctl.scala 1054:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[el2_dec_tlu_ctl.scala 1055:39] + csr.io.debug_halt_req <= debug_halt_req @[el2_dec_tlu_ctl.scala 1056:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[el2_dec_tlu_ctl.scala 1057:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[el2_dec_tlu_ctl.scala 1058:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[el2_dec_tlu_ctl.scala 1059:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[el2_dec_tlu_ctl.scala 1060:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[el2_dec_tlu_ctl.scala 1061:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[el2_dec_tlu_ctl.scala 1062:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[el2_dec_tlu_ctl.scala 1063:39] + csr.io.take_timer_int <= take_timer_int @[el2_dec_tlu_ctl.scala 1064:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[el2_dec_tlu_ctl.scala 1065:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[el2_dec_tlu_ctl.scala 1066:39] + csr.io.take_ext_int <= take_ext_int @[el2_dec_tlu_ctl.scala 1067:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[el2_dec_tlu_ctl.scala 1068:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 1069:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 1070:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[el2_dec_tlu_ctl.scala 1071:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[el2_dec_tlu_ctl.scala 1072:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1073:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1073:39] + npc_r <= csr.io.npc_r @[el2_dec_tlu_ctl.scala 1075:31] + npc_r_d1 <= csr.io.npc_r_d1 @[el2_dec_tlu_ctl.scala 1076:31] + mie_ns <= csr.io.mie_ns @[el2_dec_tlu_ctl.scala 1077:31] + mepc <= csr.io.mepc @[el2_dec_tlu_ctl.scala 1078:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[el2_dec_tlu_ctl.scala 1079:31] + force_halt <= csr.io.force_halt @[el2_dec_tlu_ctl.scala 1080:31] + dpc <= csr.io.dpc @[el2_dec_tlu_ctl.scala 1081:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[el2_dec_tlu_ctl.scala 1082:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[el2_dec_tlu_ctl.scala 1083:31] + fw_halt_req <= csr.io.fw_halt_req @[el2_dec_tlu_ctl.scala 1084:31] + mstatus <= csr.io.mstatus @[el2_dec_tlu_ctl.scala 1085:31] + dcsr <= csr.io.dcsr @[el2_dec_tlu_ctl.scala 1086:31] + mtvec <= csr.io.mtvec @[el2_dec_tlu_ctl.scala 1087:31] + mip <= csr.io.mip @[el2_dec_tlu_ctl.scala 1088:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[el2_dec_tlu_ctl.scala 1089:33] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[el2_dec_tlu_ctl.scala 1089:33] + inst csr_read of el2_dec_decode_csr_read @[el2_dec_tlu_ctl.scala 1090:22] + csr_read.clock <= clock + csr_read.reset <= reset + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[el2_dec_tlu_ctl.scala 1091:31] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[el2_dec_tlu_ctl.scala 1092:10] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[el2_dec_tlu_ctl.scala 1092:10] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1094:44] + node _T_865 = not(io.dec_csr_wen_unq_d) @[el2_dec_tlu_ctl.scala 1094:69] + node _T_866 = and(_T_864, _T_865) @[el2_dec_tlu_ctl.scala 1094:67] + io.dec_tlu_presync_d <= _T_866 @[el2_dec_tlu_ctl.scala 1094:25] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[el2_dec_tlu_ctl.scala 1095:45] + io.dec_tlu_postsync_d <= _T_867 @[el2_dec_tlu_ctl.scala 1095:25] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[el2_dec_tlu_ctl.scala 1098:52] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[el2_dec_tlu_ctl.scala 1098:74] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[el2_dec_tlu_ctl.scala 1098:94] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[el2_dec_tlu_ctl.scala 1098:114] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[el2_dec_tlu_ctl.scala 1098:136] + node _T_873 = not(UInt<1>("h01")) @[el2_dec_tlu_ctl.scala 1098:161] + node conditionally_illegal = and(_T_872, _T_873) @[el2_dec_tlu_ctl.scala 1098:159] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[el2_dec_tlu_ctl.scala 1099:57] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[el2_dec_tlu_ctl.scala 1099:75] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[el2_dec_tlu_ctl.scala 1099:94] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[el2_dec_tlu_ctl.scala 1099:117] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[el2_dec_tlu_ctl.scala 1099:138] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[el2_dec_tlu_ctl.scala 1099:160] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[el2_dec_tlu_ctl.scala 1099:181] + node _T_881 = not(_T_880) @[el2_dec_tlu_ctl.scala 1099:38] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[el2_dec_tlu_ctl.scala 1099:203] + node _T_883 = and(csr_pkt.legal, _T_882) @[el2_dec_tlu_ctl.scala 1099:35] + node _T_884 = not(fast_int_meicpct) @[el2_dec_tlu_ctl.scala 1099:225] + node _T_885 = and(_T_883, _T_884) @[el2_dec_tlu_ctl.scala 1099:223] + node _T_886 = not(conditionally_illegal) @[el2_dec_tlu_ctl.scala 1099:245] + node valid_csr = and(_T_885, _T_886) @[el2_dec_tlu_ctl.scala 1099:243] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[el2_dec_tlu_ctl.scala 1101:48] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[el2_dec_tlu_ctl.scala 1101:109] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[el2_dec_tlu_ctl.scala 1101:131] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[el2_dec_tlu_ctl.scala 1101:152] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[el2_dec_tlu_ctl.scala 1101:174] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[el2_dec_tlu_ctl.scala 1101:195] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[el2_dec_tlu_ctl.scala 1101:84] + node _T_894 = not(_T_893) @[el2_dec_tlu_ctl.scala 1101:61] + node _T_895 = and(_T_887, _T_894) @[el2_dec_tlu_ctl.scala 1101:59] + io.dec_csr_legal_d <= _T_895 @[el2_dec_tlu_ctl.scala 1101:22] + diff --git a/el2_dec_tlu_ctl.v b/el2_dec_tlu_ctl.v new file mode 100644 index 00000000..cc7ab018 --- /dev/null +++ b/el2_dec_tlu_ctl.v @@ -0,0 +1,7181 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 465:26] + wire clkhdr_CK; // @[el2_lib.scala 465:26] + wire clkhdr_EN; // @[el2_lib.scala 465:26] + wire clkhdr_SE; // @[el2_lib.scala 465:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18] +endmodule +module el2_dec_timer_ctl( + input clock, + input reset, + input io_free_clk, + input io_scan_mode, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_csr_mitctl0, + input io_csr_mitctl1, + input io_csr_mitb0, + input io_csr_mitb1, + input io_csr_mitcnt0, + input io_csr_mitcnt1, + input io_dec_pause_state, + input io_dec_tlu_pmu_fw_halted, + input io_internal_dbg_halt_timers, + output [31:0] io_dec_timer_rddata_d, + output io_dec_timer_read_d, + output io_dec_timer_t0_pulse, + output io_dec_timer_t1_pulse +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + reg [31:0] mitcnt0; // @[el2_lib.scala 491:16] + reg [31:0] mitb0_b; // @[el2_lib.scala 491:16] + wire [31:0] mitb0 = ~mitb0_b; // @[el2_dec_tlu_ctl.scala 2791:14] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2752:30] + reg [31:0] mitcnt1; // @[el2_lib.scala 491:16] + reg [31:0] mitb1_b; // @[el2_lib.scala 491:16] + wire [31:0] mitb1 = ~mitb1_b; // @[el2_dec_tlu_ctl.scala 2800:12] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2753:30] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[el2_dec_tlu_ctl.scala 2763:66] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[el2_dec_tlu_ctl.scala 2763:43] + reg [1:0] _T_57; // @[el2_dec_tlu_ctl.scala 2816:67] + reg mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2815:54] + wire _T_58 = ~mitctl0_0_b; // @[el2_dec_tlu_ctl.scala 2816:90] + wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] + wire _T_2 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 2765:50] + wire _T_4 = _T_2 | mitctl0[2]; // @[el2_dec_tlu_ctl.scala 2765:70] + wire _T_5 = mitctl0[0] & _T_4; // @[el2_dec_tlu_ctl.scala 2765:47] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2765:106] + wire _T_8 = _T_6 | mitctl0[1]; // @[el2_dec_tlu_ctl.scala 2765:132] + wire _T_9 = _T_5 & _T_8; // @[el2_dec_tlu_ctl.scala 2765:103] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:60] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] + reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] + reg mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2829:49] + wire _T_67 = ~mitctl1_0_b; // @[el2_dec_tlu_ctl.scala 2830:69] + wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] + wire _T_23 = _T_2 | mitctl1[2]; // @[el2_dec_tlu_ctl.scala 2777:70] + wire _T_24 = mitctl1[0] & _T_23; // @[el2_dec_tlu_ctl.scala 2777:47] + wire _T_27 = _T_6 | mitctl1[1]; // @[el2_dec_tlu_ctl.scala 2777:132] + wire _T_28 = _T_24 & _T_27; // @[el2_dec_tlu_ctl.scala 2777:103] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[el2_dec_tlu_ctl.scala 2777:165] + wire _T_32 = ~mitctl1[3]; // @[el2_dec_tlu_ctl.scala 2780:54] + wire _T_33 = _T_32 | mit0_match_ns; // @[el2_dec_tlu_ctl.scala 2780:66] + wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[el2_dec_tlu_ctl.scala 2780:29] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[el2_dec_tlu_ctl.scala 2782:52] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[el2_dec_tlu_ctl.scala 2789:64] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[el2_dec_tlu_ctl.scala 2798:63] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[el2_dec_tlu_ctl.scala 2811:66] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[el2_dec_tlu_ctl.scala 2811:43] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[el2_dec_tlu_ctl.scala 2812:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[el2_dec_tlu_ctl.scala 2826:65] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[el2_dec_tlu_ctl.scala 2826:43] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[el2_dec_tlu_ctl.scala 2827:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 2832:43] + wire _T_70 = _T_69 | io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 2832:60] + wire _T_71 = _T_70 | io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 2832:75] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 2832:90] + wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] + wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] + wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_86 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_87 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_88 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_89 = io_csr_mitctl0 ? _T_81 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_90 = io_csr_mitctl1 ? _T_84 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_91 = _T_85 | _T_86; // @[Mux.scala 27:72] + wire [31:0] _T_92 = _T_91 | _T_87; // @[Mux.scala 27:72] + wire [31:0] _T_93 = _T_92 | _T_88; // @[Mux.scala 27:72] + wire [31:0] _T_94 = _T_93 | _T_89; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[el2_dec_tlu_ctl.scala 2833:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 2832:25] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[el2_dec_tlu_ctl.scala 2755:25] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[el2_dec_tlu_ctl.scala 2756:25] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mitcnt0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + mitb0_b = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + mitcnt1 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + mitb1_b = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + _T_57 = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + mitctl0_0_b = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[2:0]; + _RAND_7 = {1{`RANDOM}}; + mitctl1_0_b = _RAND_7[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mitcnt0 = 32'h0; + end + if (reset) begin + mitb0_b = 32'h0; + end + if (reset) begin + mitcnt1 = 32'h0; + end + if (reset) begin + mitb1_b = 32'h0; + end + if (reset) begin + _T_57 = 2'h0; + end + if (reset) begin + mitctl0_0_b = 1'h0; + end + if (reset) begin + _T_66 = 3'h0; + end + if (reset) begin + mitctl1_0_b = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt0 <= 32'h0; + end else if (mit0_match_ns) begin + mitcnt0 <= 32'h0; + end else if (wr_mitcnt0_r) begin + mitcnt0 <= io_dec_csr_wrdata_r; + end else begin + mitcnt0 <= mitcnt0_inc; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mitb0_b <= 32'h0; + end else begin + mitb0_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + mitcnt1 <= 32'h0; + end else if (mit1_match_ns) begin + mitcnt1 <= 32'h0; + end else if (wr_mitcnt1_r) begin + mitcnt1 <= io_dec_csr_wrdata_r; + end else begin + mitcnt1 <= mitcnt1_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + mitb1_b <= 32'h0; + end else begin + mitb1_b <= ~io_dec_csr_wrdata_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_57 <= 2'h0; + end else begin + _T_57 <= mitctl0_ns[2:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl0_0_b <= 1'h0; + end else begin + mitctl0_0_b <= ~mitctl0_ns[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 3'h0; + end else begin + _T_66 <= mitctl1_ns[3:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mitctl1_0_b <= 1'h0; + end else begin + mitctl1_0_b <= ~mitctl1_ns[0]; + end + end +endmodule +module csr_tlu( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_scan_mode, + input [31:0] io_dec_csr_wrdata_r, + input [11:0] io_dec_csr_wraddr_r, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_unq_d, + input io_dec_i0_decode_d, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_ifu_ic_debug_rd_data_valid, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_pmu_bus_trxn, + input io_dma_iccm_stall_any, + input io_dma_dccm_stall_any, + input io_lsu_store_stall_any, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_decode_stall, + input io_ifu_pmu_fetch_stall, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_instr_decoded, + input io_ifu_pmu_instr_aligned, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + output io_dec_tlu_int_valid_wb1, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + input io_dec_csr_wen_r, + output [31:0] io_dec_tlu_mtval_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + input io_dec_tlu_dbg_halted, + input io_dma_pmu_dccm_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_any_write, + input io_dma_pmu_any_read, + input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_i0_valid_r, + input io_dec_csr_any_unq_d, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output [31:0] io_dec_csr_rddata_d, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_wr_pause_r, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_trxn, + input [70:0] io_ifu_ic_debug_rd_data, + output [3:0] io_dec_tlu_meipt, + input [3:0] io_pic_pl, + output [3:0] io_dec_tlu_meicurpl, + output [29:0] io_dec_tlu_meihap, + input [7:0] io_pic_claimid, + input io_iccm_dma_sb_error, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_external_ldfwd_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + input [31:0] io_dec_illegal_inst, + input io_lsu_error_pkt_r_mscause, + input io_mexintpend, + input [30:0] io_exu_npc_r, + input io_mpc_reset_run_req, + input [30:0] io_rst_vec, + input [27:0] io_core_id, + input [31:0] io_dec_timer_rddata_d, + input io_dec_timer_read_d, + output io_dec_csr_wen_r_mod, + input io_rfpc_i0_r, + input io_i0_trigger_hit_r, + output io_fw_halt_req, + output [1:0] io_mstatus, + input io_exc_or_int_valid_r, + input io_mret_r, + output io_mstatus_mie_ns, + input io_dcsr_single_step_running_f, + output [15:0] io_dcsr, + output [30:0] io_mtvec, + output [5:0] io_mip, + input io_dec_timer_t0_pulse, + input io_dec_timer_t1_pulse, + input io_timer_int_sync, + input io_soft_int_sync, + output [5:0] io_mie_ns, + input io_csr_wr_clk, + input io_ebreak_to_debug_mode_r, + input io_dec_tlu_pmu_fw_halted, + input [1:0] io_lsu_fir_error, + output [30:0] io_npc_r, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_flush_noredir_r_d1, + input [30:0] io_tlu_flush_path_r_d1, + output [30:0] io_npc_r_d1, + input io_reset_delayed, + output [30:0] io_mepc, + input io_interrupt_valid_r, + input io_i0_exception_valid_r, + input io_lsu_exc_valid_r, + input io_mepc_trigger_hit_sel_pc_r, + input io_e4e5_int_clk, + input io_lsu_i0_exc_r, + input io_inst_acc_r, + input io_inst_acc_second_r, + input io_take_nmi, + input [31:0] io_lsu_error_pkt_addr_r, + input [4:0] io_exc_cause_r, + input io_i0_valid_wb, + input io_exc_or_int_valid_r_d1, + input io_interrupt_valid_r_d1, + input io_clk_override, + input io_i0_exception_valid_r_d1, + input io_lsu_i0_exc_r_d1, + input [4:0] io_exc_cause_wb, + input io_nmi_lsu_store_type, + input io_nmi_lsu_load_type, + input io_tlu_i0_commit_cmt, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + output io_mdseac_locked_ns, + input io_mdseac_locked_f, + input io_nmi_int_detected_f, + input io_internal_dbg_halt_mode_f2, + input io_ext_int_freeze_d1, + input io_ic_perr_r_d1, + input io_iccm_sbecc_r_d1, + input io_lsu_single_ecc_error_r_d1, + input io_ifu_miss_state_idle_f, + input io_lsu_idle_any_f, + input io_dbg_tlu_halted_f, + input io_dbg_tlu_halted, + input io_debug_halt_req_f, + output io_force_halt, + input io_take_ext_int_start, + input io_trigger_hit_dmode_r_d1, + input io_trigger_hit_r_d1, + input io_dcsr_single_step_done_f, + input io_ebreak_to_debug_mode_r_d1, + input io_debug_halt_req, + input io_allow_dbg_halt_csr_write, + input io_internal_dbg_halt_mode_f, + input io_enter_debug_halt_req, + input io_internal_dbg_halt_mode, + input io_request_debug_mode_done, + input io_request_debug_mode_r, + output [30:0] io_dpc, + input [3:0] io_update_hit_bit_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_dec_tlu_br0_start_error_r, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + input io_csr_pkt_csr_misa, + input io_csr_pkt_csr_mvendorid, + input io_csr_pkt_csr_marchid, + input io_csr_pkt_csr_mimpid, + input io_csr_pkt_csr_mhartid, + input io_csr_pkt_csr_mstatus, + input io_csr_pkt_csr_mtvec, + input io_csr_pkt_csr_mip, + input io_csr_pkt_csr_mie, + input io_csr_pkt_csr_mcyclel, + input io_csr_pkt_csr_mcycleh, + input io_csr_pkt_csr_minstretl, + input io_csr_pkt_csr_minstreth, + input io_csr_pkt_csr_mscratch, + input io_csr_pkt_csr_mepc, + input io_csr_pkt_csr_mcause, + input io_csr_pkt_csr_mscause, + input io_csr_pkt_csr_mtval, + input io_csr_pkt_csr_mrac, + input io_csr_pkt_csr_mdseac, + input io_csr_pkt_csr_meihap, + input io_csr_pkt_csr_meivt, + input io_csr_pkt_csr_meipt, + input io_csr_pkt_csr_meicurpl, + input io_csr_pkt_csr_meicidpl, + input io_csr_pkt_csr_dcsr, + input io_csr_pkt_csr_mcgc, + input io_csr_pkt_csr_mfdc, + input io_csr_pkt_csr_dpc, + input io_csr_pkt_csr_mtsel, + input io_csr_pkt_csr_mtdata1, + input io_csr_pkt_csr_mtdata2, + input io_csr_pkt_csr_mhpmc3, + input io_csr_pkt_csr_mhpmc4, + input io_csr_pkt_csr_mhpmc5, + input io_csr_pkt_csr_mhpmc6, + input io_csr_pkt_csr_mhpmc3h, + input io_csr_pkt_csr_mhpmc4h, + input io_csr_pkt_csr_mhpmc5h, + input io_csr_pkt_csr_mhpmc6h, + input io_csr_pkt_csr_mhpme3, + input io_csr_pkt_csr_mhpme4, + input io_csr_pkt_csr_mhpme5, + input io_csr_pkt_csr_mhpme6, + input io_csr_pkt_csr_mcountinhibit, + input io_csr_pkt_csr_mpmc, + input io_csr_pkt_csr_micect, + input io_csr_pkt_csr_miccmect, + input io_csr_pkt_csr_mdccmect, + input io_csr_pkt_csr_mfdht, + input io_csr_pkt_csr_mfdhs, + input io_csr_pkt_csr_dicawics, + input io_csr_pkt_csr_dicad0h, + input io_csr_pkt_csr_dicad0, + input io_csr_pkt_csr_dicad1, + output [9:0] io_mtdata1_t_0, + output [9:0] io_mtdata1_t_1, + output [9:0] io_mtdata1_t_2, + output [9:0] io_mtdata1_t_3 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [63:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [63:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [95:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_clk; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_en; // @[el2_lib.scala 485:23] + wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 485:23] + wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 474:22] + wire _T = ~io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 1530:46] + wire _T_1 = io_dec_csr_wen_r & _T; // @[el2_dec_tlu_ctl.scala 1530:44] + wire _T_2 = ~io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 1530:69] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[el2_dec_tlu_ctl.scala 1531:72] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[el2_dec_tlu_ctl.scala 1531:43] + wire _T_496 = io_dec_csr_wraddr_r == 12'h7c6; // @[el2_dec_tlu_ctl.scala 1917:69] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_496; // @[el2_dec_tlu_ctl.scala 1917:40] + wire _T_507 = ~io_dec_csr_wrdata_r[1]; // @[el2_dec_tlu_ctl.scala 1924:38] + reg mpmc_b; // @[el2_dec_tlu_ctl.scala 1926:45] + wire mpmc = ~mpmc_b; // @[el2_dec_tlu_ctl.scala 1929:11] + wire _T_508 = ~mpmc; // @[el2_dec_tlu_ctl.scala 1924:63] + wire mpmc_b_ns = wr_mpmc_r ? _T_507 : _T_508; // @[el2_dec_tlu_ctl.scala 1924:19] + wire _T_6 = ~mpmc_b_ns; // @[el2_dec_tlu_ctl.scala 1534:29] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1534:40] + wire _T_7 = ~wr_mstatus_r; // @[el2_dec_tlu_ctl.scala 1537:6] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1537:20] + wire _T_12 = wr_mstatus_r & io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1538:19] + wire _T_15 = ~io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 1539:18] + wire _T_16 = io_mret_r & _T_15; // @[el2_dec_tlu_ctl.scala 1539:16] + wire [1:0] _T_19 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_22 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] + wire _T_24 = wr_mstatus_r & _T_15; // @[el2_dec_tlu_ctl.scala 1541:19] + wire [1:0] _T_28 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + wire _T_31 = _T_7 & _T_15; // @[el2_dec_tlu_ctl.scala 1542:20] + wire _T_32 = ~io_mret_r; // @[el2_dec_tlu_ctl.scala 1542:47] + wire _T_33 = _T_31 & _T_32; // @[el2_dec_tlu_ctl.scala 1542:45] + wire _T_34 = ~set_mie_pmu_fw_halt; // @[el2_dec_tlu_ctl.scala 1542:60] + wire _T_35 = _T_33 & _T_34; // @[el2_dec_tlu_ctl.scala 1542:58] + wire _T_37 = _T_8 & io_mstatus[0]; // @[Mux.scala 27:72] + wire _T_38 = _T_12 & io_dec_csr_wrdata_r[3]; // @[Mux.scala 27:72] + wire [1:0] _T_39 = _T_16 ? _T_19 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_40 = set_mie_pmu_fw_halt ? _T_22 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_41 = _T_24 ? _T_28 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_42 = _T_35 ? io_mstatus : 2'h0; // @[Mux.scala 27:72] + wire _T_43 = _T_37 | _T_38; // @[Mux.scala 27:72] + wire [1:0] _GEN_9 = {{1'd0}, _T_43}; // @[Mux.scala 27:72] + wire [1:0] _T_44 = _GEN_9 | _T_39; // @[Mux.scala 27:72] + wire [1:0] _T_45 = _T_44 | _T_40; // @[Mux.scala 27:72] + wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] + wire _T_50 = ~io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1545:51] + wire _T_52 = _T_50 | io_dcsr[11]; // @[el2_dec_tlu_ctl.scala 1545:82] + reg [1:0] _T_54; // @[el2_dec_tlu_ctl.scala 1547:12] + wire _T_56 = io_dec_csr_wraddr_r == 12'h305; // @[el2_dec_tlu_ctl.scala 1556:70] + reg [30:0] _T_60; // @[el2_lib.scala 491:16] + reg [31:0] mdccmect; // @[el2_lib.scala 491:16] + wire [62:0] _T_572 = 63'hffffffff << mdccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1975:42] + wire [31:0] _T_574 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_574}; // @[el2_dec_tlu_ctl.scala 1975:62] + wire [62:0] _T_575 = _T_572 & _GEN_10; // @[el2_dec_tlu_ctl.scala 1975:62] + wire mdccme_ce_req = |_T_575; // @[el2_dec_tlu_ctl.scala 1975:95] + reg [31:0] miccmect; // @[el2_lib.scala 491:16] + wire [62:0] _T_552 = 63'hffffffff << miccmect[31:27]; // @[el2_dec_tlu_ctl.scala 1960:42] + wire [31:0] _T_554 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_554}; // @[el2_dec_tlu_ctl.scala 1960:62] + wire [62:0] _T_555 = _T_552 & _GEN_11; // @[el2_dec_tlu_ctl.scala 1960:62] + wire miccme_ce_req = |_T_555; // @[el2_dec_tlu_ctl.scala 1960:95] + wire _T_61 = mdccme_ce_req | miccme_ce_req; // @[el2_dec_tlu_ctl.scala 1570:31] + reg [31:0] micect; // @[el2_lib.scala 491:16] + wire [62:0] _T_530 = 63'hffffffff << micect[31:27]; // @[el2_dec_tlu_ctl.scala 1946:39] + wire _T_531 = |_T_530; // @[el2_dec_tlu_ctl.scala 1946:57] + wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] + wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1455:41 el2_dec_tlu_ctl.scala 1946:15] + wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] + wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] + wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] + reg [5:0] _T_66; // @[el2_dec_tlu_ctl.scala 1574:12] + wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[el2_dec_tlu_ctl.scala 1586:68] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[el2_dec_tlu_ctl.scala 1586:39] + wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + reg [5:0] mie; // @[el2_dec_tlu_ctl.scala 1589:12] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1596:55] + wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[el2_dec_tlu_ctl.scala 1598:72] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[el2_dec_tlu_ctl.scala 1598:43] + wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[el2_dec_tlu_ctl.scala 1600:72] + wire _T_84 = kill_ebreak_count_r | _T_83; // @[el2_dec_tlu_ctl.scala 1600:47] + wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 1600:95] + reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] + reg temp_ncount0; // @[Reg.scala 27:20] + wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire _T_87 = _T_85 | mcountinhibit[0]; // @[el2_dec_tlu_ctl.scala 1600:122] + wire mcyclel_cout_in = ~_T_87; // @[el2_dec_tlu_ctl.scala 1600:25] + wire [31:0] _T_88 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] + reg [32:0] _T_95; // @[el2_lib.scala 491:16] + wire [31:0] mcyclel = _T_95[31:0]; // @[el2_dec_tlu_ctl.scala 1607:11] + wire [31:0] _T_90 = mcyclel + _T_88; // @[el2_dec_tlu_ctl.scala 1604:26] + wire [32:0] mcyclel_inc = {{1'd0}, _T_90}; // @[el2_dec_tlu_ctl.scala 1604:15] + wire mcyclel_cout = mcyclel_inc[32]; // @[el2_dec_tlu_ctl.scala 1606:33] + wire _T_99 = io_dec_csr_wraddr_r == 12'hb80; // @[el2_dec_tlu_ctl.scala 1614:69] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_99; // @[el2_dec_tlu_ctl.scala 1614:40] + wire _T_96 = ~wr_mcycleh_r; // @[el2_dec_tlu_ctl.scala 1608:72] + reg mcyclel_cout_f; // @[el2_dec_tlu_ctl.scala 1608:55] + wire [31:0] _T_101 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] + reg [31:0] mcycleh; // @[el2_lib.scala 491:16] + wire [31:0] mcycleh_inc = mcycleh + _T_101; // @[el2_dec_tlu_ctl.scala 1616:29] + wire _T_107 = io_ebreak_r | io_ecall_r; // @[el2_dec_tlu_ctl.scala 1633:73] + wire _T_108 = _T_107 | io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 1633:86] + wire _T_109 = _T_108 | io_illegal_r; // @[el2_dec_tlu_ctl.scala 1633:114] + wire _T_111 = _T_109 | mcountinhibit[2]; // @[el2_dec_tlu_ctl.scala 1633:129] + wire _T_113 = ~_T_111; // @[el2_dec_tlu_ctl.scala 1633:59] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_113; // @[el2_dec_tlu_ctl.scala 1633:57] + wire _T_115 = io_dec_csr_wraddr_r == 12'hb02; // @[el2_dec_tlu_ctl.scala 1635:74] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_115; // @[el2_dec_tlu_ctl.scala 1635:45] + wire [31:0] _T_116 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] + reg [32:0] _T_122; // @[el2_lib.scala 491:16] + wire [31:0] minstretl = _T_122[31:0]; // @[el2_dec_tlu_ctl.scala 1642:13] + wire [31:0] _T_118 = minstretl + _T_116; // @[el2_dec_tlu_ctl.scala 1637:30] + wire [32:0] minstretl_inc = {{1'd0}, _T_118}; // @[el2_dec_tlu_ctl.scala 1637:17] + wire minstretl_cout = minstretl_inc[32]; // @[el2_dec_tlu_ctl.scala 1638:37] + reg minstret_enable_f; // @[el2_dec_tlu_ctl.scala 1643:57] + wire _T_126 = io_dec_csr_wraddr_r == 12'hb82; // @[el2_dec_tlu_ctl.scala 1652:72] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_126; // @[el2_dec_tlu_ctl.scala 1652:43] + wire _T_123 = ~wr_minstreth_r; // @[el2_dec_tlu_ctl.scala 1644:76] + reg minstretl_cout_f; // @[el2_dec_tlu_ctl.scala 1644:57] + wire [31:0] _T_129 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] + reg [31:0] minstreth; // @[el2_lib.scala 491:16] + wire [31:0] minstreth_inc = minstreth + _T_129; // @[el2_dec_tlu_ctl.scala 1655:30] + wire _T_137 = io_dec_csr_wraddr_r == 12'h340; // @[el2_dec_tlu_ctl.scala 1666:73] + reg [31:0] mscratch; // @[el2_lib.scala 491:16] + wire _T_140 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 1677:23] + wire _T_141 = ~io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1677:48] + wire _T_142 = _T_140 & _T_141; // @[el2_dec_tlu_ctl.scala 1677:46] + wire sel_exu_npc_r = _T_142 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1677:73] + wire _T_144 = _T_140 & io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1678:48] + wire _T_145 = ~io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1678:76] + wire sel_flush_npc_r = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 1678:74] + wire _T_146 = ~sel_exu_npc_r; // @[el2_dec_tlu_ctl.scala 1679:24] + wire _T_147 = ~sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1679:41] + wire sel_hold_npc_r = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 1679:39] + wire _T_149 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 1683:6] + wire _T_150 = _T_149 & io_reset_delayed; // @[el2_dec_tlu_ctl.scala 1683:28] + wire [30:0] _T_154 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_155 = _T_150 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_156 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_157 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_158 = _T_154 | _T_155; // @[Mux.scala 27:72] + wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72] + wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49] + reg [30:0] _T_165; // @[el2_lib.scala 491:16] + wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45] + wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5] + wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[el2_lib.scala 491:16] + wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72] + wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40] + wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30] + wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51] + wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16] + wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6] + wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17] + wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72] + wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72] + reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48] + wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42] + wire _T_197 = io_exc_or_int_valid_r & io_take_nmi; // @[el2_dec_tlu_ctl.scala 1714:52] + wire mcause_sel_nmi_store = _T_197 & io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 1714:66] + wire mcause_sel_nmi_load = _T_197 & io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 1715:65] + wire _T_200 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1716:83] + wire mcause_sel_nmi_ext = _T_197 & _T_200; // @[el2_dec_tlu_ctl.scala 1716:64] + wire _T_201 = &io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1722:52] + wire _T_204 = ~io_lsu_fir_error[0]; // @[el2_dec_tlu_ctl.scala 1722:81] + wire _T_205 = io_lsu_fir_error[1] & _T_204; // @[el2_dec_tlu_ctl.scala 1722:79] + wire [31:0] _T_210 = {30'h3c000400,_T_201,_T_205}; // @[Cat.scala 29:58] + wire _T_211 = ~io_take_nmi; // @[el2_dec_tlu_ctl.scala 1728:30] + wire _T_212 = io_exc_or_int_valid_r & _T_211; // @[el2_dec_tlu_ctl.scala 1728:28] + wire [31:0] _T_215 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] + wire _T_217 = wr_mcause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1729:18] + wire _T_219 = ~wr_mcause_r; // @[el2_dec_tlu_ctl.scala 1730:6] + wire _T_221 = _T_219 & _T_15; // @[el2_dec_tlu_ctl.scala 1730:19] + wire [31:0] _T_223 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_224 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_225 = mcause_sel_nmi_ext ? _T_210 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_226 = _T_212 ? _T_215 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_227 = _T_217 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mcause; // @[el2_dec_tlu_ctl.scala 1732:47] + wire [31:0] _T_228 = _T_221 ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_229 = _T_223 | _T_224; // @[Mux.scala 27:72] + wire [31:0] _T_230 = _T_229 | _T_225; // @[Mux.scala 27:72] + wire [31:0] _T_231 = _T_230 | _T_226; // @[Mux.scala 27:72] + wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] + wire _T_236 = io_dec_csr_wraddr_r == 12'h7ff; // @[el2_dec_tlu_ctl.scala 1739:72] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_236; // @[el2_dec_tlu_ctl.scala 1739:43] + wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] + wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] + wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] + wire _T_243 = io_lsu_i0_exc_r & io_lsu_error_pkt_r_mscause; // @[Mux.scala 27:72] + wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] + wire _T_247 = _T_243 | io_i0_trigger_hit_r; // @[Mux.scala 27:72] + wire [1:0] _GEN_13 = {{1'd0}, _T_247}; // @[Mux.scala 27:72] + wire [1:0] _T_248 = _GEN_13 | _T_245; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_248}; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _GEN_14 | _T_246; // @[Mux.scala 27:72] + wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] + wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] + wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] + wire [3:0] _T_259 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_260 = _T_252 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] + reg [3:0] mscause; // @[el2_dec_tlu_ctl.scala 1755:48] + wire [3:0] _T_261 = _T_257 ? mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72] + wire _T_266 = io_dec_csr_wraddr_r == 12'h343; // @[el2_dec_tlu_ctl.scala 1762:70] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_266; // @[el2_dec_tlu_ctl.scala 1762:41] + wire _T_267 = ~io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1763:84] + wire _T_268 = io_inst_acc_r & _T_267; // @[el2_dec_tlu_ctl.scala 1763:82] + wire _T_269 = io_ebreak_r | _T_268; // @[el2_dec_tlu_ctl.scala 1763:65] + wire _T_270 = _T_269 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1763:107] + wire _T_271 = io_exc_or_int_valid_r & _T_270; // @[el2_dec_tlu_ctl.scala 1763:50] + wire mtval_capture_pc_r = _T_271 & _T_211; // @[el2_dec_tlu_ctl.scala 1763:139] + wire _T_273 = io_inst_acc_r & io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 1764:73] + wire _T_274 = io_exc_or_int_valid_r & _T_273; // @[el2_dec_tlu_ctl.scala 1764:56] + wire mtval_capture_pc_plus2_r = _T_274 & _T_211; // @[el2_dec_tlu_ctl.scala 1764:97] + wire _T_276 = io_exc_or_int_valid_r & io_illegal_r; // @[el2_dec_tlu_ctl.scala 1765:52] + wire mtval_capture_inst_r = _T_276 & _T_211; // @[el2_dec_tlu_ctl.scala 1765:67] + wire _T_278 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1766:51] + wire mtval_capture_lsu_r = _T_278 & _T_211; // @[el2_dec_tlu_ctl.scala 1766:72] + wire _T_280 = ~mtval_capture_pc_r; // @[el2_dec_tlu_ctl.scala 1767:47] + wire _T_281 = io_exc_or_int_valid_r & _T_280; // @[el2_dec_tlu_ctl.scala 1767:45] + wire _T_282 = ~mtval_capture_inst_r; // @[el2_dec_tlu_ctl.scala 1767:69] + wire _T_283 = _T_281 & _T_282; // @[el2_dec_tlu_ctl.scala 1767:67] + wire _T_284 = ~mtval_capture_lsu_r; // @[el2_dec_tlu_ctl.scala 1767:93] + wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91] + wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116] + wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114] + wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84] + wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58] + wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19] + wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17] + wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21] + wire _T_300 = _T_211 & _T_299; // @[el2_dec_tlu_ctl.scala 1776:19] + wire _T_302 = _T_300 & _T_280; // @[el2_dec_tlu_ctl.scala 1776:33] + wire _T_304 = _T_302 & _T_282; // @[el2_dec_tlu_ctl.scala 1776:55] + wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81] + wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79] + wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96] + wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47] + wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72] + wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72] + wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72] + wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] + wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69] + reg [8:0] mcgc; // @[el2_lib.scala 491:16] + wire _T_335 = io_dec_csr_wraddr_r == 12'h7f9; // @[el2_dec_tlu_ctl.scala 1823:69] + reg [14:0] mfdc_int; // @[el2_lib.scala 491:16] + wire [2:0] _T_339 = ~io_dec_csr_wrdata_r[18:16]; // @[el2_dec_tlu_ctl.scala 1832:20] + wire _T_342 = ~io_dec_csr_wrdata_r[6]; // @[el2_dec_tlu_ctl.scala 1832:75] + wire [6:0] _T_344 = {_T_342,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_345 = {_T_339,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_348 = ~mfdc_int[14:12]; // @[el2_dec_tlu_ctl.scala 1833:20] + wire _T_351 = ~mfdc_int[6]; // @[el2_dec_tlu_ctl.scala 1833:63] + wire [18:0] mfdc = {_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_365 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 1856:78] + wire _T_366 = io_dec_csr_wen_r_mod & _T_365; // @[el2_dec_tlu_ctl.scala 1856:49] + wire _T_368 = _T_366 & _T_295; // @[el2_dec_tlu_ctl.scala 1856:88] + wire _T_369 = ~io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1856:114] + wire _T_372 = io_dec_csr_wraddr_r == 12'h7c0; // @[el2_dec_tlu_ctl.scala 1863:69] + wire _T_376 = ~io_dec_csr_wrdata_r[31]; // @[el2_dec_tlu_ctl.scala 1866:72] + wire _T_377 = io_dec_csr_wrdata_r[30] & _T_376; // @[el2_dec_tlu_ctl.scala 1866:70] + wire _T_381 = ~io_dec_csr_wrdata_r[29]; // @[el2_dec_tlu_ctl.scala 1867:56] + wire _T_382 = io_dec_csr_wrdata_r[28] & _T_381; // @[el2_dec_tlu_ctl.scala 1867:54] + wire _T_386 = ~io_dec_csr_wrdata_r[27]; // @[el2_dec_tlu_ctl.scala 1868:56] + wire _T_387 = io_dec_csr_wrdata_r[26] & _T_386; // @[el2_dec_tlu_ctl.scala 1868:54] + wire _T_391 = ~io_dec_csr_wrdata_r[25]; // @[el2_dec_tlu_ctl.scala 1869:56] + wire _T_392 = io_dec_csr_wrdata_r[24] & _T_391; // @[el2_dec_tlu_ctl.scala 1869:54] + wire _T_396 = ~io_dec_csr_wrdata_r[23]; // @[el2_dec_tlu_ctl.scala 1870:56] + wire _T_397 = io_dec_csr_wrdata_r[22] & _T_396; // @[el2_dec_tlu_ctl.scala 1870:54] + wire _T_401 = ~io_dec_csr_wrdata_r[21]; // @[el2_dec_tlu_ctl.scala 1871:56] + wire _T_402 = io_dec_csr_wrdata_r[20] & _T_401; // @[el2_dec_tlu_ctl.scala 1871:54] + wire _T_406 = ~io_dec_csr_wrdata_r[19]; // @[el2_dec_tlu_ctl.scala 1872:56] + wire _T_407 = io_dec_csr_wrdata_r[18] & _T_406; // @[el2_dec_tlu_ctl.scala 1872:54] + wire _T_411 = ~io_dec_csr_wrdata_r[17]; // @[el2_dec_tlu_ctl.scala 1873:56] + wire _T_412 = io_dec_csr_wrdata_r[16] & _T_411; // @[el2_dec_tlu_ctl.scala 1873:54] + wire _T_416 = ~io_dec_csr_wrdata_r[15]; // @[el2_dec_tlu_ctl.scala 1874:56] + wire _T_417 = io_dec_csr_wrdata_r[14] & _T_416; // @[el2_dec_tlu_ctl.scala 1874:54] + wire _T_421 = ~io_dec_csr_wrdata_r[13]; // @[el2_dec_tlu_ctl.scala 1875:56] + wire _T_422 = io_dec_csr_wrdata_r[12] & _T_421; // @[el2_dec_tlu_ctl.scala 1875:54] + wire _T_426 = ~io_dec_csr_wrdata_r[11]; // @[el2_dec_tlu_ctl.scala 1876:56] + wire _T_427 = io_dec_csr_wrdata_r[10] & _T_426; // @[el2_dec_tlu_ctl.scala 1876:54] + wire _T_431 = ~io_dec_csr_wrdata_r[9]; // @[el2_dec_tlu_ctl.scala 1877:56] + wire _T_432 = io_dec_csr_wrdata_r[8] & _T_431; // @[el2_dec_tlu_ctl.scala 1877:53] + wire _T_436 = ~io_dec_csr_wrdata_r[7]; // @[el2_dec_tlu_ctl.scala 1878:56] + wire _T_437 = io_dec_csr_wrdata_r[6] & _T_436; // @[el2_dec_tlu_ctl.scala 1878:53] + wire _T_441 = ~io_dec_csr_wrdata_r[5]; // @[el2_dec_tlu_ctl.scala 1879:56] + wire _T_442 = io_dec_csr_wrdata_r[4] & _T_441; // @[el2_dec_tlu_ctl.scala 1879:53] + wire _T_446 = ~io_dec_csr_wrdata_r[3]; // @[el2_dec_tlu_ctl.scala 1880:56] + wire _T_447 = io_dec_csr_wrdata_r[2] & _T_446; // @[el2_dec_tlu_ctl.scala 1880:53] + wire _T_452 = io_dec_csr_wrdata_r[0] & _T_507; // @[el2_dec_tlu_ctl.scala 1881:53] + wire [7:0] _T_459 = {io_dec_csr_wrdata_r[7],_T_437,io_dec_csr_wrdata_r[5],_T_442,io_dec_csr_wrdata_r[3],_T_447,io_dec_csr_wrdata_r[1],_T_452}; // @[Cat.scala 29:58] + wire [15:0] _T_467 = {io_dec_csr_wrdata_r[15],_T_417,io_dec_csr_wrdata_r[13],_T_422,io_dec_csr_wrdata_r[11],_T_427,io_dec_csr_wrdata_r[9],_T_432,_T_459}; // @[Cat.scala 29:58] + wire [7:0] _T_474 = {io_dec_csr_wrdata_r[23],_T_397,io_dec_csr_wrdata_r[21],_T_402,io_dec_csr_wrdata_r[19],_T_407,io_dec_csr_wrdata_r[17],_T_412}; // @[Cat.scala 29:58] + wire [15:0] _T_482 = {io_dec_csr_wrdata_r[31],_T_377,io_dec_csr_wrdata_r[29],_T_382,io_dec_csr_wrdata_r[27],_T_387,io_dec_csr_wrdata_r[25],_T_392,_T_474}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[el2_lib.scala 491:16] + wire _T_485 = io_dec_csr_wraddr_r == 12'hbc0; // @[el2_dec_tlu_ctl.scala 1894:70] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_485; // @[el2_dec_tlu_ctl.scala 1894:41] + wire _T_486 = ~wr_mdeau_r; // @[el2_dec_tlu_ctl.scala 1904:60] + wire _T_487 = io_mdseac_locked_f & _T_486; // @[el2_dec_tlu_ctl.scala 1904:58] + wire _T_489 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 1906:50] + wire _T_490 = ~io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1906:87] + wire _T_491 = _T_489 & _T_490; // @[el2_dec_tlu_ctl.scala 1906:85] + wire _T_492 = ~io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1906:112] + wire mdseac_en = _T_491 & _T_492; // @[el2_dec_tlu_ctl.scala 1906:110] + reg [31:0] mdseac; // @[el2_lib.scala 491:16] + wire _T_498 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[el2_dec_tlu_ctl.scala 1921:31] + wire _T_499 = ~io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1921:58] + wire _T_500 = _T_498 & _T_499; // @[el2_dec_tlu_ctl.scala 1921:56] + wire _T_501 = ~io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1921:90] + wire _T_514 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[el2_dec_tlu_ctl.scala 1938:49] + wire [4:0] csr_sat = _T_514 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[el2_dec_tlu_ctl.scala 1938:20] + wire _T_517 = io_dec_csr_wraddr_r == 12'h7f0; // @[el2_dec_tlu_ctl.scala 1940:71] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_517; // @[el2_dec_tlu_ctl.scala 1940:42] + wire [26:0] _T_518 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_15 = {{5'd0}, _T_518}; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_520 = micect + _GEN_15; // @[el2_dec_tlu_ctl.scala 1941:24] + wire [31:0] _T_523 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_520[26:0]; // @[el2_dec_tlu_ctl.scala 1941:14] + wire [31:0] _T_525 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_536 = io_dec_csr_wraddr_r == 12'h7f1; // @[el2_dec_tlu_ctl.scala 1955:77] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_536; // @[el2_dec_tlu_ctl.scala 1955:48] + wire _T_538 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 1956:71] + wire [26:0] _T_539 = {26'h0,_T_538}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_539; // @[el2_dec_tlu_ctl.scala 1956:34] + wire [31:0] _T_546 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_547 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1959:49] + wire _T_558 = io_dec_csr_wraddr_r == 12'h7f2; // @[el2_dec_tlu_ctl.scala 1969:77] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_558; // @[el2_dec_tlu_ctl.scala 1969:48] + wire [26:0] _T_560 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_560; // @[el2_dec_tlu_ctl.scala 1970:34] + wire [31:0] _T_567 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_578 = io_dec_csr_wraddr_r == 12'h7ce; // @[el2_dec_tlu_ctl.scala 1985:70] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_578; // @[el2_dec_tlu_ctl.scala 1985:41] + reg [5:0] mfdht; // @[el2_dec_tlu_ctl.scala 1989:44] + wire _T_583 = io_dec_csr_wraddr_r == 12'h7cf; // @[el2_dec_tlu_ctl.scala 1998:70] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_583; // @[el2_dec_tlu_ctl.scala 1998:41] + wire _T_586 = ~io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2001:30] + wire _T_587 = io_dbg_tlu_halted & _T_586; // @[el2_dec_tlu_ctl.scala 2001:28] + wire _T_589 = ~io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 2001:65] + wire _T_590 = ~io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 2001:85] + wire [1:0] _T_591 = {_T_589,_T_590}; // @[Cat.scala 29:58] + reg [1:0] mfdhs; // @[Reg.scala 27:20] + wire _T_593 = wr_mfdhs_r | io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2003:72] + reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] + wire [31:0] _T_598 = force_halt_ctr_f + 32'h1; // @[el2_dec_tlu_ctl.scala 2005:75] + wire [62:0] _T_605 = 63'hffffffff << mfdht[5:1]; // @[el2_dec_tlu_ctl.scala 2010:72] + wire [62:0] _GEN_16 = {{31'd0}, force_halt_ctr_f}; // @[el2_dec_tlu_ctl.scala 2010:49] + wire [62:0] _T_606 = _GEN_16 & _T_605; // @[el2_dec_tlu_ctl.scala 2010:49] + wire _T_607 = |_T_606; // @[el2_dec_tlu_ctl.scala 2010:88] + wire _T_610 = io_dec_csr_wraddr_r == 12'hbc8; // @[el2_dec_tlu_ctl.scala 2018:70] + reg [21:0] meivt; // @[el2_lib.scala 491:16] + wire _T_630 = io_dec_csr_wraddr_r == 12'hbca; // @[el2_dec_tlu_ctl.scala 2069:70] + wire _T_631 = io_dec_csr_wen_r_mod & _T_630; // @[el2_dec_tlu_ctl.scala 2069:41] + wire wr_meicpct_r = _T_631 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2069:84] + reg [7:0] meihap; // @[el2_lib.scala 491:16] + wire [31:0] _T_615 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire _T_617 = io_dec_csr_wraddr_r == 12'hbcc; // @[el2_dec_tlu_ctl.scala 2042:73] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_617; // @[el2_dec_tlu_ctl.scala 2042:44] + reg [3:0] meicurpl; // @[el2_dec_tlu_ctl.scala 2045:47] + wire _T_622 = io_dec_csr_wraddr_r == 12'hbcb; // @[el2_dec_tlu_ctl.scala 2057:74] + wire _T_623 = io_dec_csr_wen_r_mod & _T_622; // @[el2_dec_tlu_ctl.scala 2057:45] + wire wr_meicidpl_r = _T_623 | io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 2057:89] + reg [3:0] meicidpl; // @[el2_dec_tlu_ctl.scala 2062:45] + wire _T_634 = io_dec_csr_wraddr_r == 12'hbc9; // @[el2_dec_tlu_ctl.scala 2078:70] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_634; // @[el2_dec_tlu_ctl.scala 2078:41] + reg [3:0] meipt; // @[el2_dec_tlu_ctl.scala 2081:44] + wire _T_638 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 2109:90] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_638; // @[el2_dec_tlu_ctl.scala 2109:67] + wire _T_639 = ~io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 2112:35] + wire _T_640 = io_dcsr_single_step_done_f & _T_639; // @[el2_dec_tlu_ctl.scala 2112:33] + wire _T_641 = ~trigger_hit_for_dscr_cause_r_d1; // @[el2_dec_tlu_ctl.scala 2112:67] + wire _T_642 = _T_640 & _T_641; // @[el2_dec_tlu_ctl.scala 2112:65] + wire _T_643 = ~io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 2112:102] + wire _T_644 = _T_642 & _T_643; // @[el2_dec_tlu_ctl.scala 2112:100] + wire _T_647 = io_debug_halt_req & _T_639; // @[el2_dec_tlu_ctl.scala 2113:24] + wire _T_649 = _T_647 & _T_641; // @[el2_dec_tlu_ctl.scala 2113:56] + wire _T_652 = io_ebreak_to_debug_mode_r_d1 & _T_641; // @[el2_dec_tlu_ctl.scala 2114:35] + wire [2:0] _T_655 = _T_644 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_656 = _T_649 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_652 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = _T_655 | _T_656; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_659 | _T_657; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_660 | _T_658; // @[Mux.scala 27:72] + wire _T_662 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 2117:47] + wire _T_664 = io_dec_csr_wraddr_r == 12'h7b0; // @[el2_dec_tlu_ctl.scala 2117:99] + wire wr_dcsr_r = _T_662 & _T_664; // @[el2_dec_tlu_ctl.scala 2117:70] + wire _T_666 = io_dcsr[8:6] == 3'h3; // @[el2_dec_tlu_ctl.scala 2123:76] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_666; // @[el2_dec_tlu_ctl.scala 2123:60] + wire _T_667 = ~io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 2124:60] + wire _T_668 = _T_667 | dcsr_cause_upgradeable; // @[el2_dec_tlu_ctl.scala 2124:79] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_668; // @[el2_dec_tlu_ctl.scala 2124:57] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 2126:49] + wire [15:0] _T_674 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_680 = nmi_in_debug_mode | io_dcsr[3]; // @[el2_dec_tlu_ctl.scala 2128:146] + wire [15:0] _T_689 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_680,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_694 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_696 = enter_debug_halt_req_le | wr_dcsr_r; // @[el2_dec_tlu_ctl.scala 2130:55] + wire _T_697 = _T_696 | io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 2130:67] + reg [15:0] _T_700; // @[el2_lib.scala 491:16] + wire _T_703 = io_dec_csr_wraddr_r == 12'h7b1; // @[el2_dec_tlu_ctl.scala 2138:98] + wire wr_dpc_r = _T_662 & _T_703; // @[el2_dec_tlu_ctl.scala 2138:69] + wire _T_706 = ~io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 2139:68] + wire dpc_capture_npc = _T_587 & _T_706; // @[el2_dec_tlu_ctl.scala 2139:66] + wire _T_707 = ~io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2143:6] + wire _T_708 = ~dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2143:24] + wire _T_709 = _T_707 & _T_708; // @[el2_dec_tlu_ctl.scala 2143:22] + wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41] + wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22] + wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72] + wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37] + reg [30:0] _T_725; // @[el2_lib.scala 491:16] + wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_732 = io_dec_csr_wraddr_r == 12'h7c8; // @[el2_dec_tlu_ctl.scala 2162:103] + reg [16:0] dicawics; // @[el2_lib.scala 491:16] + wire _T_736 = io_dec_csr_wraddr_r == 12'h7c9; // @[el2_dec_tlu_ctl.scala 2180:101] + wire wr_dicad0_r = _T_662 & _T_736; // @[el2_dec_tlu_ctl.scala 2180:72] + reg [70:0] dicad0; // @[el2_lib.scala 491:16] + wire _T_742 = io_dec_csr_wraddr_r == 12'h7cc; // @[el2_dec_tlu_ctl.scala 2193:102] + wire wr_dicad0h_r = _T_662 & _T_742; // @[el2_dec_tlu_ctl.scala 2193:73] + reg [31:0] dicad0h; // @[el2_lib.scala 491:16] + wire _T_750 = io_dec_csr_wraddr_r == 12'h7ca; // @[el2_dec_tlu_ctl.scala 2205:103] + wire _T_751 = _T_662 & _T_750; // @[el2_dec_tlu_ctl.scala 2205:74] + wire _T_755 = _T_751 | io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 2209:81] + reg [31:0] _T_757; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_757[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_762 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_764 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 2237:53] + wire _T_765 = _T_764 & io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 2237:76] + wire _T_766 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 2237:99] + wire _T_767 = _T_765 & _T_766; // @[el2_dec_tlu_ctl.scala 2237:97] + wire _T_769 = io_dec_csr_rdaddr_d == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2237:150] + wire _T_772 = io_dec_csr_wraddr_r == 12'h7cb; // @[el2_dec_tlu_ctl.scala 2238:105] + reg icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2240:59] + reg icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2241:59] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7a0; // @[el2_dec_tlu_ctl.scala 2252:70] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_774; // @[el2_dec_tlu_ctl.scala 2252:41] + reg [1:0] mtsel; // @[el2_dec_tlu_ctl.scala 2255:44] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_406; // @[el2_dec_tlu_ctl.scala 2290:43] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_406; // @[el2_dec_tlu_ctl.scala 2292:45] + wire _T_785 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2294:47] + wire tdata_action = _T_785 & io_dec_csr_wrdata_r[12]; // @[el2_dec_tlu_ctl.scala 2294:70] + wire [9:0] tdata_wrdata_r = {_T_785,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_800 = io_dec_csr_wraddr_r == 12'h7a1; // @[el2_dec_tlu_ctl.scala 2300:100] + wire _T_801 = io_dec_csr_wen_r_mod & _T_800; // @[el2_dec_tlu_ctl.scala 2300:71] + wire _T_802 = mtsel == 2'h0; // @[el2_dec_tlu_ctl.scala 2300:122] + wire _T_803 = _T_801 & _T_802; // @[el2_dec_tlu_ctl.scala 2300:113] + wire _T_805 = ~io_mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_0 = _T_803 & _T_806; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_814 = ~io_mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_1 = _T_803 & _T_815; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_823 = ~io_mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_2 = _T_803 & _T_824; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_832 = ~io_mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 2300:139] + wire _T_833 = _T_832 | io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 2300:171] + wire wr_mtdata1_t_r_3 = _T_803 & _T_833; // @[el2_dec_tlu_ctl.scala 2300:136] + wire _T_839 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_842 = {io_mtdata1_t_0[9],_T_839,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_848 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_851 = {io_mtdata1_t_1[9],_T_848,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_857 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_860 = {io_mtdata1_t_2[9],_T_857,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_866 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[el2_dec_tlu_ctl.scala 2301:140] + wire [9:0] _T_869 = {io_mtdata1_t_3[9],_T_866,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_871; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_872; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_873; // @[el2_dec_tlu_ctl.scala 2303:76] + reg [9:0] _T_874; // @[el2_dec_tlu_ctl.scala 2303:76] + wire [31:0] _T_889 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire _T_890 = mtsel == 2'h1; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_904 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire _T_905 = mtsel == 2'h2; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_919 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire _T_920 = mtsel == 2'h3; // @[el2_dec_tlu_ctl.scala 2306:60] + wire [31:0] _T_934 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = _T_802 ? _T_889 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_936 = _T_890 ? _T_904 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_905 ? _T_919 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_920 ? _T_934 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_935 | _T_936; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_939 | _T_937; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_940 | _T_938; // @[Mux.scala 27:72] + wire _T_967 = io_dec_csr_wraddr_r == 12'h7a2; // @[el2_dec_tlu_ctl.scala 2320:99] + wire _T_968 = io_dec_csr_wen_r_mod & _T_967; // @[el2_dec_tlu_ctl.scala 2320:70] + wire _T_970 = _T_968 & _T_802; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_979 = _T_968 & _T_890; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_988 = _T_968 & _T_905; // @[el2_dec_tlu_ctl.scala 2320:112] + wire _T_997 = _T_968 & _T_920; // @[el2_dec_tlu_ctl.scala 2320:112] + reg [31:0] mtdata2_t_0; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_1; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_2; // @[el2_lib.scala 491:16] + reg [31:0] mtdata2_t_3; // @[el2_lib.scala 491:16] + wire [31:0] _T_1014 = _T_802 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1015 = _T_890 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_905 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_920 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_1014 | _T_1015; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1018 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [3:0] _T_1022 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1022; // @[el2_dec_tlu_ctl.scala 2345:60] + wire _T_1024 = ~mcountinhibit[3]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme3; // @[Reg.scala 27:20] + wire _T_1025 = mhpme3 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1027 = mhpme3 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1029 = mhpme3 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1031 = mhpme3 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1033 = ~io_illegal_r; // @[el2_dec_tlu_ctl.scala 2355:83] + wire _T_1034 = io_tlu_i0_commit_cmt & _T_1033; // @[el2_dec_tlu_ctl.scala 2355:81] + wire _T_1035 = mhpme3 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1037 = ~io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2356:83] + wire _T_1038 = io_tlu_i0_commit_cmt & _T_1037; // @[el2_dec_tlu_ctl.scala 2356:81] + wire _T_1040 = _T_1038 & _T_1033; // @[el2_dec_tlu_ctl.scala 2356:102] + wire _T_1041 = mhpme3 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1043 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 2357:81] + wire _T_1045 = _T_1043 & _T_1033; // @[el2_dec_tlu_ctl.scala 2357:102] + wire _T_1046 = mhpme3 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1048 = mhpme3 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1050 = mhpme3 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1052 = mhpme3 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1054 = pmu_i0_itype_qual == 4'h1; // @[el2_dec_tlu_ctl.scala 2361:78] + wire _T_1055 = mhpme3 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1057 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2362:92] + wire _T_1058 = mhpme3 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1060 = pmu_i0_itype_qual == 4'h2; // @[el2_dec_tlu_ctl.scala 2363:78] + wire _T_1061 = mhpme3 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1063 = pmu_i0_itype_qual == 4'h3; // @[el2_dec_tlu_ctl.scala 2364:78] + wire _T_1064 = mhpme3 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1067 = mhpme3 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1068 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1067; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1070 = _T_1060 & _T_1068; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1072 = _T_1070 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1074 = _T_1072 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1075 = mhpme3 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[el2_dec_tlu_ctl.scala 2368:76] + wire _T_1078 = mhpme3 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[el2_dec_tlu_ctl.scala 2369:76] + wire _T_1081 = mhpme3 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[el2_dec_tlu_ctl.scala 2370:76] + wire _T_1084 = mhpme3 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[el2_dec_tlu_ctl.scala 2371:76] + wire _T_1087 = mhpme3 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[el2_dec_tlu_ctl.scala 2372:76] + wire _T_1090 = mhpme3 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[el2_dec_tlu_ctl.scala 2373:76] + wire _T_1093 = mhpme3 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[el2_dec_tlu_ctl.scala 2374:76] + wire _T_1096 = mhpme3 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[el2_dec_tlu_ctl.scala 2375:76] + wire _T_1099 = mhpme3 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[el2_dec_tlu_ctl.scala 2376:76] + wire _T_1102 = mhpme3 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[el2_dec_tlu_ctl.scala 2377:76] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[el2_dec_tlu_ctl.scala 2377:109] + wire _T_1106 = _T_1104 | _T_1105; // @[el2_dec_tlu_ctl.scala 2377:88] + wire _T_1107 = mhpme3 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2378:82] + wire _T_1110 = mhpme3 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2379:84] + wire _T_1113 = mhpme3 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 2380:97] + wire _T_1116 = mhpme3 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1120 = mhpme3 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1122 = mhpme3 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1124 = mhpme3 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1126 = mhpme3 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1128 = mhpme3 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1130 = mhpme3 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 2388:85] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 2388:107] + wire _T_1134 = mhpme3 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 2389:79] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 2389:104] + wire _T_1138 = mhpme3 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1140 = mhpme3 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1142 = mhpme3 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 2392:84] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 2392:116] + wire _T_1146 = mhpme3 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1148 = mhpme3 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1150 = mhpme3 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1152 = mhpme3 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1154 = mhpme3 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1156 = mhpme3 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1158 = mhpme3 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1160 = mhpme3 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1164 = ~io_mstatus[0]; // @[el2_dec_tlu_ctl.scala 2400:60] + wire _T_1165 = mhpme3 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire [5:0] _T_1172 = io_mip & mie; // @[el2_dec_tlu_ctl.scala 2401:100] + wire [5:0] _GEN_17 = {{5'd0}, _T_1164}; // @[el2_dec_tlu_ctl.scala 2401:85] + wire [5:0] _T_1173 = _GEN_17 & _T_1172; // @[el2_dec_tlu_ctl.scala 2401:85] + wire _T_1174 = mhpme3 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[el2_dec_tlu_ctl.scala 2402:78] + wire _T_1177 = mhpme3 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 2403:81] + wire _T_1180 = mhpme3 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 2404:81] + wire _T_1183 = mhpme3 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1185 = mhpme3 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1187 = mhpme3 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1189 = mhpme3 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1191 = mhpme3 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1194 = _T_1027 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & _T_1034; // @[Mux.scala 27:72] + wire _T_1197 = _T_1035 & _T_1040; // @[Mux.scala 27:72] + wire _T_1198 = _T_1041 & _T_1045; // @[Mux.scala 27:72] + wire _T_1199 = _T_1046 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & _T_1054; // @[Mux.scala 27:72] + wire _T_1203 = _T_1055 & _T_1057; // @[Mux.scala 27:72] + wire _T_1204 = _T_1058 & _T_1060; // @[Mux.scala 27:72] + wire _T_1205 = _T_1061 & _T_1063; // @[Mux.scala 27:72] + wire _T_1206 = _T_1064 & _T_1074; // @[Mux.scala 27:72] + wire _T_1207 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1208 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1209 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1210 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1211 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1212 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1213 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1214 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1215 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1216 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1217 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1218 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1219 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1220 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1222 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1225 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1228 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1229 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1230 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1231 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1232 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1233 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1235 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1236 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1238 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1240 = _T_1165 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1241 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1242 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1243 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1244 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1245 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1246 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1247 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1025 | _T_1194; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1195; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1196; // @[Mux.scala 27:72] + wire _T_1252 = _T_1251 | _T_1197; // @[Mux.scala 27:72] + wire _T_1253 = _T_1252 | _T_1198; // @[Mux.scala 27:72] + wire _T_1254 = _T_1253 | _T_1199; // @[Mux.scala 27:72] + wire _T_1255 = _T_1254 | _T_1200; // @[Mux.scala 27:72] + wire _T_1256 = _T_1255 | _T_1201; // @[Mux.scala 27:72] + wire _T_1257 = _T_1256 | _T_1202; // @[Mux.scala 27:72] + wire _T_1258 = _T_1257 | _T_1203; // @[Mux.scala 27:72] + wire _T_1259 = _T_1258 | _T_1204; // @[Mux.scala 27:72] + wire _T_1260 = _T_1259 | _T_1205; // @[Mux.scala 27:72] + wire _T_1261 = _T_1260 | _T_1206; // @[Mux.scala 27:72] + wire _T_1262 = _T_1261 | _T_1207; // @[Mux.scala 27:72] + wire _T_1263 = _T_1262 | _T_1208; // @[Mux.scala 27:72] + wire _T_1264 = _T_1263 | _T_1209; // @[Mux.scala 27:72] + wire _T_1265 = _T_1264 | _T_1210; // @[Mux.scala 27:72] + wire _T_1266 = _T_1265 | _T_1211; // @[Mux.scala 27:72] + wire _T_1267 = _T_1266 | _T_1212; // @[Mux.scala 27:72] + wire _T_1268 = _T_1267 | _T_1213; // @[Mux.scala 27:72] + wire _T_1269 = _T_1268 | _T_1214; // @[Mux.scala 27:72] + wire _T_1270 = _T_1269 | _T_1215; // @[Mux.scala 27:72] + wire _T_1271 = _T_1270 | _T_1216; // @[Mux.scala 27:72] + wire _T_1272 = _T_1271 | _T_1217; // @[Mux.scala 27:72] + wire _T_1273 = _T_1272 | _T_1218; // @[Mux.scala 27:72] + wire _T_1274 = _T_1273 | _T_1219; // @[Mux.scala 27:72] + wire _T_1275 = _T_1274 | _T_1220; // @[Mux.scala 27:72] + wire _T_1276 = _T_1275 | _T_1201; // @[Mux.scala 27:72] + wire _T_1277 = _T_1276 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1223; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1224; // @[Mux.scala 27:72] + wire _T_1280 = _T_1279 | _T_1225; // @[Mux.scala 27:72] + wire _T_1281 = _T_1280 | _T_1226; // @[Mux.scala 27:72] + wire _T_1282 = _T_1281 | _T_1227; // @[Mux.scala 27:72] + wire _T_1283 = _T_1282 | _T_1228; // @[Mux.scala 27:72] + wire _T_1284 = _T_1283 | _T_1229; // @[Mux.scala 27:72] + wire _T_1285 = _T_1284 | _T_1230; // @[Mux.scala 27:72] + wire _T_1286 = _T_1285 | _T_1231; // @[Mux.scala 27:72] + wire _T_1287 = _T_1286 | _T_1232; // @[Mux.scala 27:72] + wire _T_1288 = _T_1287 | _T_1233; // @[Mux.scala 27:72] + wire _T_1289 = _T_1288 | _T_1234; // @[Mux.scala 27:72] + wire _T_1290 = _T_1289 | _T_1235; // @[Mux.scala 27:72] + wire _T_1291 = _T_1290 | _T_1236; // @[Mux.scala 27:72] + wire _T_1292 = _T_1291 | _T_1237; // @[Mux.scala 27:72] + wire _T_1293 = _T_1292 | _T_1238; // @[Mux.scala 27:72] + wire _T_1294 = _T_1293 | _T_1239; // @[Mux.scala 27:72] + wire [5:0] _GEN_18 = {{5'd0}, _T_1294}; // @[Mux.scala 27:72] + wire [5:0] _T_1295 = _GEN_18 | _T_1240; // @[Mux.scala 27:72] + wire [5:0] _GEN_19 = {{5'd0}, _T_1241}; // @[Mux.scala 27:72] + wire [5:0] _T_1296 = _T_1295 | _GEN_19; // @[Mux.scala 27:72] + wire [5:0] _GEN_20 = {{5'd0}, _T_1242}; // @[Mux.scala 27:72] + wire [5:0] _T_1297 = _T_1296 | _GEN_20; // @[Mux.scala 27:72] + wire [5:0] _GEN_21 = {{5'd0}, _T_1243}; // @[Mux.scala 27:72] + wire [5:0] _T_1298 = _T_1297 | _GEN_21; // @[Mux.scala 27:72] + wire [5:0] _GEN_22 = {{5'd0}, _T_1244}; // @[Mux.scala 27:72] + wire [5:0] _T_1299 = _T_1298 | _GEN_22; // @[Mux.scala 27:72] + wire [5:0] _GEN_23 = {{5'd0}, _T_1245}; // @[Mux.scala 27:72] + wire [5:0] _T_1300 = _T_1299 | _GEN_23; // @[Mux.scala 27:72] + wire [5:0] _GEN_24 = {{5'd0}, _T_1246}; // @[Mux.scala 27:72] + wire [5:0] _T_1301 = _T_1300 | _GEN_24; // @[Mux.scala 27:72] + wire [5:0] _GEN_25 = {{5'd0}, _T_1247}; // @[Mux.scala 27:72] + wire [5:0] _T_1302 = _T_1301 | _GEN_25; // @[Mux.scala 27:72] + wire [5:0] _GEN_26 = {{5'd0}, _T_1248}; // @[Mux.scala 27:72] + wire [5:0] _T_1303 = _T_1302 | _GEN_26; // @[Mux.scala 27:72] + wire [5:0] _GEN_27 = {{5'd0}, _T_1024}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1305 = _GEN_27 & _T_1303; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1307 = ~mcountinhibit[4]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme4; // @[Reg.scala 27:20] + wire _T_1308 = mhpme4 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1310 = mhpme4 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1312 = mhpme4 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1314 = mhpme4 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1318 = mhpme4 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1324 = mhpme4 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1329 = mhpme4 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1331 = mhpme4 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1333 = mhpme4 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1335 = mhpme4 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1338 = mhpme4 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1341 = mhpme4 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1344 = mhpme4 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1347 = mhpme4 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1350 = mhpme4 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1351 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1350; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1353 = _T_1060 & _T_1351; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1355 = _T_1353 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1357 = _T_1355 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1358 = mhpme4 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1361 = mhpme4 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1364 = mhpme4 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1367 = mhpme4 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1370 = mhpme4 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1373 = mhpme4 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1376 = mhpme4 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1379 = mhpme4 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1382 = mhpme4 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1385 = mhpme4 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1390 = mhpme4 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1393 = mhpme4 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1396 = mhpme4 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1399 = mhpme4 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1403 = mhpme4 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1405 = mhpme4 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1407 = mhpme4 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1409 = mhpme4 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1411 = mhpme4 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1413 = mhpme4 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1417 = mhpme4 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1421 = mhpme4 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1423 = mhpme4 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1425 = mhpme4 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1429 = mhpme4 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1431 = mhpme4 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1433 = mhpme4 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1435 = mhpme4 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1437 = mhpme4 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1439 = mhpme4 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1441 = mhpme4 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1443 = mhpme4 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1448 = mhpme4 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1457 = mhpme4 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1460 = mhpme4 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1463 = mhpme4 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1466 = mhpme4 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1468 = mhpme4 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1470 = mhpme4 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1472 = mhpme4 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1474 = mhpme4 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1477 = _T_1310 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & _T_1034; // @[Mux.scala 27:72] + wire _T_1480 = _T_1318 & _T_1040; // @[Mux.scala 27:72] + wire _T_1481 = _T_1324 & _T_1045; // @[Mux.scala 27:72] + wire _T_1482 = _T_1329 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & _T_1054; // @[Mux.scala 27:72] + wire _T_1486 = _T_1338 & _T_1057; // @[Mux.scala 27:72] + wire _T_1487 = _T_1341 & _T_1060; // @[Mux.scala 27:72] + wire _T_1488 = _T_1344 & _T_1063; // @[Mux.scala 27:72] + wire _T_1489 = _T_1347 & _T_1357; // @[Mux.scala 27:72] + wire _T_1490 = _T_1358 & _T_1077; // @[Mux.scala 27:72] + wire _T_1491 = _T_1361 & _T_1080; // @[Mux.scala 27:72] + wire _T_1492 = _T_1364 & _T_1083; // @[Mux.scala 27:72] + wire _T_1493 = _T_1367 & _T_1086; // @[Mux.scala 27:72] + wire _T_1494 = _T_1370 & _T_1089; // @[Mux.scala 27:72] + wire _T_1495 = _T_1373 & _T_1092; // @[Mux.scala 27:72] + wire _T_1496 = _T_1376 & _T_1095; // @[Mux.scala 27:72] + wire _T_1497 = _T_1379 & _T_1098; // @[Mux.scala 27:72] + wire _T_1498 = _T_1382 & _T_1101; // @[Mux.scala 27:72] + wire _T_1499 = _T_1385 & _T_1106; // @[Mux.scala 27:72] + wire _T_1500 = _T_1390 & _T_1109; // @[Mux.scala 27:72] + wire _T_1501 = _T_1393 & _T_1112; // @[Mux.scala 27:72] + wire _T_1502 = _T_1396 & _T_1115; // @[Mux.scala 27:72] + wire _T_1503 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1505 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1506 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1508 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1509 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1413 & _T_1133; // @[Mux.scala 27:72] + wire _T_1511 = _T_1417 & _T_1137; // @[Mux.scala 27:72] + wire _T_1512 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1513 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1514 = _T_1425 & _T_1145; // @[Mux.scala 27:72] + wire _T_1515 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1516 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1517 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1518 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1519 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1520 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1521 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1522 = _T_1443 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1523 = _T_1448 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1524 = _T_1457 & _T_1176; // @[Mux.scala 27:72] + wire _T_1525 = _T_1460 & _T_1179; // @[Mux.scala 27:72] + wire _T_1526 = _T_1463 & _T_1182; // @[Mux.scala 27:72] + wire _T_1527 = _T_1466 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1528 = _T_1468 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1529 = _T_1470 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1530 = _T_1472 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1474 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1308 | _T_1477; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1478; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1479; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1480; // @[Mux.scala 27:72] + wire _T_1536 = _T_1535 | _T_1481; // @[Mux.scala 27:72] + wire _T_1537 = _T_1536 | _T_1482; // @[Mux.scala 27:72] + wire _T_1538 = _T_1537 | _T_1483; // @[Mux.scala 27:72] + wire _T_1539 = _T_1538 | _T_1484; // @[Mux.scala 27:72] + wire _T_1540 = _T_1539 | _T_1485; // @[Mux.scala 27:72] + wire _T_1541 = _T_1540 | _T_1486; // @[Mux.scala 27:72] + wire _T_1542 = _T_1541 | _T_1487; // @[Mux.scala 27:72] + wire _T_1543 = _T_1542 | _T_1488; // @[Mux.scala 27:72] + wire _T_1544 = _T_1543 | _T_1489; // @[Mux.scala 27:72] + wire _T_1545 = _T_1544 | _T_1490; // @[Mux.scala 27:72] + wire _T_1546 = _T_1545 | _T_1491; // @[Mux.scala 27:72] + wire _T_1547 = _T_1546 | _T_1492; // @[Mux.scala 27:72] + wire _T_1548 = _T_1547 | _T_1493; // @[Mux.scala 27:72] + wire _T_1549 = _T_1548 | _T_1494; // @[Mux.scala 27:72] + wire _T_1550 = _T_1549 | _T_1495; // @[Mux.scala 27:72] + wire _T_1551 = _T_1550 | _T_1496; // @[Mux.scala 27:72] + wire _T_1552 = _T_1551 | _T_1497; // @[Mux.scala 27:72] + wire _T_1553 = _T_1552 | _T_1498; // @[Mux.scala 27:72] + wire _T_1554 = _T_1553 | _T_1499; // @[Mux.scala 27:72] + wire _T_1555 = _T_1554 | _T_1500; // @[Mux.scala 27:72] + wire _T_1556 = _T_1555 | _T_1501; // @[Mux.scala 27:72] + wire _T_1557 = _T_1556 | _T_1502; // @[Mux.scala 27:72] + wire _T_1558 = _T_1557 | _T_1503; // @[Mux.scala 27:72] + wire _T_1559 = _T_1558 | _T_1484; // @[Mux.scala 27:72] + wire _T_1560 = _T_1559 | _T_1505; // @[Mux.scala 27:72] + wire _T_1561 = _T_1560 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1507; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1508; // @[Mux.scala 27:72] + wire _T_1564 = _T_1563 | _T_1509; // @[Mux.scala 27:72] + wire _T_1565 = _T_1564 | _T_1510; // @[Mux.scala 27:72] + wire _T_1566 = _T_1565 | _T_1511; // @[Mux.scala 27:72] + wire _T_1567 = _T_1566 | _T_1512; // @[Mux.scala 27:72] + wire _T_1568 = _T_1567 | _T_1513; // @[Mux.scala 27:72] + wire _T_1569 = _T_1568 | _T_1514; // @[Mux.scala 27:72] + wire _T_1570 = _T_1569 | _T_1515; // @[Mux.scala 27:72] + wire _T_1571 = _T_1570 | _T_1516; // @[Mux.scala 27:72] + wire _T_1572 = _T_1571 | _T_1517; // @[Mux.scala 27:72] + wire _T_1573 = _T_1572 | _T_1518; // @[Mux.scala 27:72] + wire _T_1574 = _T_1573 | _T_1519; // @[Mux.scala 27:72] + wire _T_1575 = _T_1574 | _T_1520; // @[Mux.scala 27:72] + wire _T_1576 = _T_1575 | _T_1521; // @[Mux.scala 27:72] + wire _T_1577 = _T_1576 | _T_1522; // @[Mux.scala 27:72] + wire [5:0] _GEN_29 = {{5'd0}, _T_1577}; // @[Mux.scala 27:72] + wire [5:0] _T_1578 = _GEN_29 | _T_1523; // @[Mux.scala 27:72] + wire [5:0] _GEN_30 = {{5'd0}, _T_1524}; // @[Mux.scala 27:72] + wire [5:0] _T_1579 = _T_1578 | _GEN_30; // @[Mux.scala 27:72] + wire [5:0] _GEN_31 = {{5'd0}, _T_1525}; // @[Mux.scala 27:72] + wire [5:0] _T_1580 = _T_1579 | _GEN_31; // @[Mux.scala 27:72] + wire [5:0] _GEN_32 = {{5'd0}, _T_1526}; // @[Mux.scala 27:72] + wire [5:0] _T_1581 = _T_1580 | _GEN_32; // @[Mux.scala 27:72] + wire [5:0] _GEN_33 = {{5'd0}, _T_1527}; // @[Mux.scala 27:72] + wire [5:0] _T_1582 = _T_1581 | _GEN_33; // @[Mux.scala 27:72] + wire [5:0] _GEN_34 = {{5'd0}, _T_1528}; // @[Mux.scala 27:72] + wire [5:0] _T_1583 = _T_1582 | _GEN_34; // @[Mux.scala 27:72] + wire [5:0] _GEN_35 = {{5'd0}, _T_1529}; // @[Mux.scala 27:72] + wire [5:0] _T_1584 = _T_1583 | _GEN_35; // @[Mux.scala 27:72] + wire [5:0] _GEN_36 = {{5'd0}, _T_1530}; // @[Mux.scala 27:72] + wire [5:0] _T_1585 = _T_1584 | _GEN_36; // @[Mux.scala 27:72] + wire [5:0] _GEN_37 = {{5'd0}, _T_1531}; // @[Mux.scala 27:72] + wire [5:0] _T_1586 = _T_1585 | _GEN_37; // @[Mux.scala 27:72] + wire [5:0] _GEN_38 = {{5'd0}, _T_1307}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1588 = _GEN_38 & _T_1586; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1590 = ~mcountinhibit[5]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme5; // @[Reg.scala 27:20] + wire _T_1591 = mhpme5 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1593 = mhpme5 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1595 = mhpme5 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1597 = mhpme5 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1601 = mhpme5 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1607 = mhpme5 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1612 = mhpme5 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1614 = mhpme5 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1616 = mhpme5 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1618 = mhpme5 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1621 = mhpme5 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1624 = mhpme5 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1627 = mhpme5 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1630 = mhpme5 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1633 = mhpme5 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1634 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1633; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1636 = _T_1060 & _T_1634; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1638 = _T_1636 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1640 = _T_1638 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1641 = mhpme5 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1644 = mhpme5 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1647 = mhpme5 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1650 = mhpme5 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1653 = mhpme5 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1656 = mhpme5 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1659 = mhpme5 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1662 = mhpme5 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1665 = mhpme5 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1668 = mhpme5 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1673 = mhpme5 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1676 = mhpme5 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1679 = mhpme5 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1682 = mhpme5 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1686 = mhpme5 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1688 = mhpme5 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1690 = mhpme5 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1692 = mhpme5 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1694 = mhpme5 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1696 = mhpme5 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1700 = mhpme5 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1704 = mhpme5 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1706 = mhpme5 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1708 = mhpme5 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1712 = mhpme5 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1714 = mhpme5 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1716 = mhpme5 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_1718 = mhpme5 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_1720 = mhpme5 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_1722 = mhpme5 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_1724 = mhpme5 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_1726 = mhpme5 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_1731 = mhpme5 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_1740 = mhpme5 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_1743 = mhpme5 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_1746 = mhpme5 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_1749 = mhpme5 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_1751 = mhpme5 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_1753 = mhpme5 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_1755 = mhpme5 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_1757 = mhpme5 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_1760 = _T_1593 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1761 = _T_1595 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1762 = _T_1597 & _T_1034; // @[Mux.scala 27:72] + wire _T_1763 = _T_1601 & _T_1040; // @[Mux.scala 27:72] + wire _T_1764 = _T_1607 & _T_1045; // @[Mux.scala 27:72] + wire _T_1765 = _T_1612 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1766 = _T_1614 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1767 = _T_1616 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1768 = _T_1618 & _T_1054; // @[Mux.scala 27:72] + wire _T_1769 = _T_1621 & _T_1057; // @[Mux.scala 27:72] + wire _T_1770 = _T_1624 & _T_1060; // @[Mux.scala 27:72] + wire _T_1771 = _T_1627 & _T_1063; // @[Mux.scala 27:72] + wire _T_1772 = _T_1630 & _T_1640; // @[Mux.scala 27:72] + wire _T_1773 = _T_1641 & _T_1077; // @[Mux.scala 27:72] + wire _T_1774 = _T_1644 & _T_1080; // @[Mux.scala 27:72] + wire _T_1775 = _T_1647 & _T_1083; // @[Mux.scala 27:72] + wire _T_1776 = _T_1650 & _T_1086; // @[Mux.scala 27:72] + wire _T_1777 = _T_1653 & _T_1089; // @[Mux.scala 27:72] + wire _T_1778 = _T_1656 & _T_1092; // @[Mux.scala 27:72] + wire _T_1779 = _T_1659 & _T_1095; // @[Mux.scala 27:72] + wire _T_1780 = _T_1662 & _T_1098; // @[Mux.scala 27:72] + wire _T_1781 = _T_1665 & _T_1101; // @[Mux.scala 27:72] + wire _T_1782 = _T_1668 & _T_1106; // @[Mux.scala 27:72] + wire _T_1783 = _T_1673 & _T_1109; // @[Mux.scala 27:72] + wire _T_1784 = _T_1676 & _T_1112; // @[Mux.scala 27:72] + wire _T_1785 = _T_1679 & _T_1115; // @[Mux.scala 27:72] + wire _T_1786 = _T_1682 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1788 = _T_1686 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1789 = _T_1688 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1790 = _T_1690 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1791 = _T_1692 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1792 = _T_1694 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1793 = _T_1696 & _T_1133; // @[Mux.scala 27:72] + wire _T_1794 = _T_1700 & _T_1137; // @[Mux.scala 27:72] + wire _T_1795 = _T_1704 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1796 = _T_1706 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1797 = _T_1708 & _T_1145; // @[Mux.scala 27:72] + wire _T_1798 = _T_1712 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1799 = _T_1714 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1800 = _T_1716 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1801 = _T_1718 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1802 = _T_1720 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1803 = _T_1722 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1804 = _T_1724 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1805 = _T_1726 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_1806 = _T_1731 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_1807 = _T_1740 & _T_1176; // @[Mux.scala 27:72] + wire _T_1808 = _T_1743 & _T_1179; // @[Mux.scala 27:72] + wire _T_1809 = _T_1746 & _T_1182; // @[Mux.scala 27:72] + wire _T_1810 = _T_1749 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1811 = _T_1751 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1812 = _T_1753 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1813 = _T_1755 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1814 = _T_1757 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1815 = _T_1591 | _T_1760; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1761; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1762; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1763; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1764; // @[Mux.scala 27:72] + wire _T_1820 = _T_1819 | _T_1765; // @[Mux.scala 27:72] + wire _T_1821 = _T_1820 | _T_1766; // @[Mux.scala 27:72] + wire _T_1822 = _T_1821 | _T_1767; // @[Mux.scala 27:72] + wire _T_1823 = _T_1822 | _T_1768; // @[Mux.scala 27:72] + wire _T_1824 = _T_1823 | _T_1769; // @[Mux.scala 27:72] + wire _T_1825 = _T_1824 | _T_1770; // @[Mux.scala 27:72] + wire _T_1826 = _T_1825 | _T_1771; // @[Mux.scala 27:72] + wire _T_1827 = _T_1826 | _T_1772; // @[Mux.scala 27:72] + wire _T_1828 = _T_1827 | _T_1773; // @[Mux.scala 27:72] + wire _T_1829 = _T_1828 | _T_1774; // @[Mux.scala 27:72] + wire _T_1830 = _T_1829 | _T_1775; // @[Mux.scala 27:72] + wire _T_1831 = _T_1830 | _T_1776; // @[Mux.scala 27:72] + wire _T_1832 = _T_1831 | _T_1777; // @[Mux.scala 27:72] + wire _T_1833 = _T_1832 | _T_1778; // @[Mux.scala 27:72] + wire _T_1834 = _T_1833 | _T_1779; // @[Mux.scala 27:72] + wire _T_1835 = _T_1834 | _T_1780; // @[Mux.scala 27:72] + wire _T_1836 = _T_1835 | _T_1781; // @[Mux.scala 27:72] + wire _T_1837 = _T_1836 | _T_1782; // @[Mux.scala 27:72] + wire _T_1838 = _T_1837 | _T_1783; // @[Mux.scala 27:72] + wire _T_1839 = _T_1838 | _T_1784; // @[Mux.scala 27:72] + wire _T_1840 = _T_1839 | _T_1785; // @[Mux.scala 27:72] + wire _T_1841 = _T_1840 | _T_1786; // @[Mux.scala 27:72] + wire _T_1842 = _T_1841 | _T_1767; // @[Mux.scala 27:72] + wire _T_1843 = _T_1842 | _T_1788; // @[Mux.scala 27:72] + wire _T_1844 = _T_1843 | _T_1789; // @[Mux.scala 27:72] + wire _T_1845 = _T_1844 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1791; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1792; // @[Mux.scala 27:72] + wire _T_1848 = _T_1847 | _T_1793; // @[Mux.scala 27:72] + wire _T_1849 = _T_1848 | _T_1794; // @[Mux.scala 27:72] + wire _T_1850 = _T_1849 | _T_1795; // @[Mux.scala 27:72] + wire _T_1851 = _T_1850 | _T_1796; // @[Mux.scala 27:72] + wire _T_1852 = _T_1851 | _T_1797; // @[Mux.scala 27:72] + wire _T_1853 = _T_1852 | _T_1798; // @[Mux.scala 27:72] + wire _T_1854 = _T_1853 | _T_1799; // @[Mux.scala 27:72] + wire _T_1855 = _T_1854 | _T_1800; // @[Mux.scala 27:72] + wire _T_1856 = _T_1855 | _T_1801; // @[Mux.scala 27:72] + wire _T_1857 = _T_1856 | _T_1802; // @[Mux.scala 27:72] + wire _T_1858 = _T_1857 | _T_1803; // @[Mux.scala 27:72] + wire _T_1859 = _T_1858 | _T_1804; // @[Mux.scala 27:72] + wire _T_1860 = _T_1859 | _T_1805; // @[Mux.scala 27:72] + wire [5:0] _GEN_40 = {{5'd0}, _T_1860}; // @[Mux.scala 27:72] + wire [5:0] _T_1861 = _GEN_40 | _T_1806; // @[Mux.scala 27:72] + wire [5:0] _GEN_41 = {{5'd0}, _T_1807}; // @[Mux.scala 27:72] + wire [5:0] _T_1862 = _T_1861 | _GEN_41; // @[Mux.scala 27:72] + wire [5:0] _GEN_42 = {{5'd0}, _T_1808}; // @[Mux.scala 27:72] + wire [5:0] _T_1863 = _T_1862 | _GEN_42; // @[Mux.scala 27:72] + wire [5:0] _GEN_43 = {{5'd0}, _T_1809}; // @[Mux.scala 27:72] + wire [5:0] _T_1864 = _T_1863 | _GEN_43; // @[Mux.scala 27:72] + wire [5:0] _GEN_44 = {{5'd0}, _T_1810}; // @[Mux.scala 27:72] + wire [5:0] _T_1865 = _T_1864 | _GEN_44; // @[Mux.scala 27:72] + wire [5:0] _GEN_45 = {{5'd0}, _T_1811}; // @[Mux.scala 27:72] + wire [5:0] _T_1866 = _T_1865 | _GEN_45; // @[Mux.scala 27:72] + wire [5:0] _GEN_46 = {{5'd0}, _T_1812}; // @[Mux.scala 27:72] + wire [5:0] _T_1867 = _T_1866 | _GEN_46; // @[Mux.scala 27:72] + wire [5:0] _GEN_47 = {{5'd0}, _T_1813}; // @[Mux.scala 27:72] + wire [5:0] _T_1868 = _T_1867 | _GEN_47; // @[Mux.scala 27:72] + wire [5:0] _GEN_48 = {{5'd0}, _T_1814}; // @[Mux.scala 27:72] + wire [5:0] _T_1869 = _T_1868 | _GEN_48; // @[Mux.scala 27:72] + wire [5:0] _GEN_49 = {{5'd0}, _T_1590}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_1871 = _GEN_49 & _T_1869; // @[el2_dec_tlu_ctl.scala 2351:45] + wire _T_1873 = ~mcountinhibit[6]; // @[el2_dec_tlu_ctl.scala 2351:25] + reg [9:0] mhpme6; // @[Reg.scala 27:20] + wire _T_1874 = mhpme6 == 10'h1; // @[el2_dec_tlu_ctl.scala 2352:21] + wire _T_1876 = mhpme6 == 10'h2; // @[el2_dec_tlu_ctl.scala 2353:21] + wire _T_1878 = mhpme6 == 10'h3; // @[el2_dec_tlu_ctl.scala 2354:21] + wire _T_1880 = mhpme6 == 10'h4; // @[el2_dec_tlu_ctl.scala 2355:21] + wire _T_1884 = mhpme6 == 10'h5; // @[el2_dec_tlu_ctl.scala 2356:21] + wire _T_1890 = mhpme6 == 10'h6; // @[el2_dec_tlu_ctl.scala 2357:21] + wire _T_1895 = mhpme6 == 10'h7; // @[el2_dec_tlu_ctl.scala 2358:21] + wire _T_1897 = mhpme6 == 10'h8; // @[el2_dec_tlu_ctl.scala 2359:21] + wire _T_1899 = mhpme6 == 10'h1e; // @[el2_dec_tlu_ctl.scala 2360:21] + wire _T_1901 = mhpme6 == 10'h9; // @[el2_dec_tlu_ctl.scala 2361:21] + wire _T_1904 = mhpme6 == 10'ha; // @[el2_dec_tlu_ctl.scala 2362:21] + wire _T_1907 = mhpme6 == 10'hb; // @[el2_dec_tlu_ctl.scala 2363:21] + wire _T_1910 = mhpme6 == 10'hc; // @[el2_dec_tlu_ctl.scala 2364:21] + wire _T_1913 = mhpme6 == 10'hd; // @[el2_dec_tlu_ctl.scala 2365:21] + wire _T_1916 = mhpme6 == 10'he; // @[el2_dec_tlu_ctl.scala 2366:21] + wire _T_1917 = io_dec_tlu_packet_r_pmu_lsu_misaligned >> _T_1916; // @[el2_dec_tlu_ctl.scala 2366:7] + wire _T_1919 = _T_1060 & _T_1917; // @[el2_dec_tlu_ctl.scala 2365:89] + wire _T_1921 = _T_1919 & _T_1063; // @[el2_dec_tlu_ctl.scala 2366:45] + wire _T_1923 = _T_1921 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 2366:77] + wire _T_1924 = mhpme6 == 10'hf; // @[el2_dec_tlu_ctl.scala 2368:21] + wire _T_1927 = mhpme6 == 10'h10; // @[el2_dec_tlu_ctl.scala 2369:21] + wire _T_1930 = mhpme6 == 10'h12; // @[el2_dec_tlu_ctl.scala 2370:21] + wire _T_1933 = mhpme6 == 10'h11; // @[el2_dec_tlu_ctl.scala 2371:21] + wire _T_1936 = mhpme6 == 10'h13; // @[el2_dec_tlu_ctl.scala 2372:21] + wire _T_1939 = mhpme6 == 10'h14; // @[el2_dec_tlu_ctl.scala 2373:21] + wire _T_1942 = mhpme6 == 10'h15; // @[el2_dec_tlu_ctl.scala 2374:21] + wire _T_1945 = mhpme6 == 10'h16; // @[el2_dec_tlu_ctl.scala 2375:21] + wire _T_1948 = mhpme6 == 10'h17; // @[el2_dec_tlu_ctl.scala 2376:21] + wire _T_1951 = mhpme6 == 10'h18; // @[el2_dec_tlu_ctl.scala 2377:21] + wire _T_1956 = mhpme6 == 10'h19; // @[el2_dec_tlu_ctl.scala 2378:21] + wire _T_1959 = mhpme6 == 10'h1a; // @[el2_dec_tlu_ctl.scala 2379:21] + wire _T_1962 = mhpme6 == 10'h1b; // @[el2_dec_tlu_ctl.scala 2380:21] + wire _T_1965 = mhpme6 == 10'h1c; // @[el2_dec_tlu_ctl.scala 2381:21] + wire _T_1969 = mhpme6 == 10'h1f; // @[el2_dec_tlu_ctl.scala 2383:21] + wire _T_1971 = mhpme6 == 10'h20; // @[el2_dec_tlu_ctl.scala 2384:21] + wire _T_1973 = mhpme6 == 10'h22; // @[el2_dec_tlu_ctl.scala 2385:21] + wire _T_1975 = mhpme6 == 10'h23; // @[el2_dec_tlu_ctl.scala 2386:21] + wire _T_1977 = mhpme6 == 10'h24; // @[el2_dec_tlu_ctl.scala 2387:21] + wire _T_1979 = mhpme6 == 10'h25; // @[el2_dec_tlu_ctl.scala 2388:21] + wire _T_1983 = mhpme6 == 10'h26; // @[el2_dec_tlu_ctl.scala 2389:21] + wire _T_1987 = mhpme6 == 10'h27; // @[el2_dec_tlu_ctl.scala 2390:21] + wire _T_1989 = mhpme6 == 10'h28; // @[el2_dec_tlu_ctl.scala 2391:21] + wire _T_1991 = mhpme6 == 10'h29; // @[el2_dec_tlu_ctl.scala 2392:21] + wire _T_1995 = mhpme6 == 10'h2a; // @[el2_dec_tlu_ctl.scala 2393:21] + wire _T_1997 = mhpme6 == 10'h2b; // @[el2_dec_tlu_ctl.scala 2394:21] + wire _T_1999 = mhpme6 == 10'h2c; // @[el2_dec_tlu_ctl.scala 2395:21] + wire _T_2001 = mhpme6 == 10'h2d; // @[el2_dec_tlu_ctl.scala 2396:21] + wire _T_2003 = mhpme6 == 10'h2e; // @[el2_dec_tlu_ctl.scala 2397:21] + wire _T_2005 = mhpme6 == 10'h2f; // @[el2_dec_tlu_ctl.scala 2398:21] + wire _T_2007 = mhpme6 == 10'h30; // @[el2_dec_tlu_ctl.scala 2399:21] + wire _T_2009 = mhpme6 == 10'h31; // @[el2_dec_tlu_ctl.scala 2400:21] + wire _T_2014 = mhpme6 == 10'h32; // @[el2_dec_tlu_ctl.scala 2401:21] + wire _T_2023 = mhpme6 == 10'h36; // @[el2_dec_tlu_ctl.scala 2402:21] + wire _T_2026 = mhpme6 == 10'h37; // @[el2_dec_tlu_ctl.scala 2403:21] + wire _T_2029 = mhpme6 == 10'h38; // @[el2_dec_tlu_ctl.scala 2404:21] + wire _T_2032 = mhpme6 == 10'h200; // @[el2_dec_tlu_ctl.scala 2406:21] + wire _T_2034 = mhpme6 == 10'h201; // @[el2_dec_tlu_ctl.scala 2407:21] + wire _T_2036 = mhpme6 == 10'h202; // @[el2_dec_tlu_ctl.scala 2408:21] + wire _T_2038 = mhpme6 == 10'h203; // @[el2_dec_tlu_ctl.scala 2409:21] + wire _T_2040 = mhpme6 == 10'h204; // @[el2_dec_tlu_ctl.scala 2410:21] + wire _T_2043 = _T_1876 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2044 = _T_1878 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2045 = _T_1880 & _T_1034; // @[Mux.scala 27:72] + wire _T_2046 = _T_1884 & _T_1040; // @[Mux.scala 27:72] + wire _T_2047 = _T_1890 & _T_1045; // @[Mux.scala 27:72] + wire _T_2048 = _T_1895 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2049 = _T_1897 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2050 = _T_1899 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2051 = _T_1901 & _T_1054; // @[Mux.scala 27:72] + wire _T_2052 = _T_1904 & _T_1057; // @[Mux.scala 27:72] + wire _T_2053 = _T_1907 & _T_1060; // @[Mux.scala 27:72] + wire _T_2054 = _T_1910 & _T_1063; // @[Mux.scala 27:72] + wire _T_2055 = _T_1913 & _T_1923; // @[Mux.scala 27:72] + wire _T_2056 = _T_1924 & _T_1077; // @[Mux.scala 27:72] + wire _T_2057 = _T_1927 & _T_1080; // @[Mux.scala 27:72] + wire _T_2058 = _T_1930 & _T_1083; // @[Mux.scala 27:72] + wire _T_2059 = _T_1933 & _T_1086; // @[Mux.scala 27:72] + wire _T_2060 = _T_1936 & _T_1089; // @[Mux.scala 27:72] + wire _T_2061 = _T_1939 & _T_1092; // @[Mux.scala 27:72] + wire _T_2062 = _T_1942 & _T_1095; // @[Mux.scala 27:72] + wire _T_2063 = _T_1945 & _T_1098; // @[Mux.scala 27:72] + wire _T_2064 = _T_1948 & _T_1101; // @[Mux.scala 27:72] + wire _T_2065 = _T_1951 & _T_1106; // @[Mux.scala 27:72] + wire _T_2066 = _T_1956 & _T_1109; // @[Mux.scala 27:72] + wire _T_2067 = _T_1959 & _T_1112; // @[Mux.scala 27:72] + wire _T_2068 = _T_1962 & _T_1115; // @[Mux.scala 27:72] + wire _T_2069 = _T_1965 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2071 = _T_1969 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2072 = _T_1971 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2073 = _T_1973 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2074 = _T_1975 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2075 = _T_1977 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2076 = _T_1979 & _T_1133; // @[Mux.scala 27:72] + wire _T_2077 = _T_1983 & _T_1137; // @[Mux.scala 27:72] + wire _T_2078 = _T_1987 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2079 = _T_1989 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2080 = _T_1991 & _T_1145; // @[Mux.scala 27:72] + wire _T_2081 = _T_1995 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2082 = _T_1997 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2083 = _T_1999 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2084 = _T_2001 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2085 = _T_2003 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2086 = _T_2005 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2087 = _T_2007 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2088 = _T_2009 & _T_1164; // @[Mux.scala 27:72] + wire [5:0] _T_2089 = _T_2014 ? _T_1173 : 6'h0; // @[Mux.scala 27:72] + wire _T_2090 = _T_2023 & _T_1176; // @[Mux.scala 27:72] + wire _T_2091 = _T_2026 & _T_1179; // @[Mux.scala 27:72] + wire _T_2092 = _T_2029 & _T_1182; // @[Mux.scala 27:72] + wire _T_2093 = _T_2032 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2094 = _T_2034 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2095 = _T_2036 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2096 = _T_2038 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2097 = _T_2040 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2098 = _T_1874 | _T_2043; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2044; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2045; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2046; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2047; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2048; // @[Mux.scala 27:72] + wire _T_2104 = _T_2103 | _T_2049; // @[Mux.scala 27:72] + wire _T_2105 = _T_2104 | _T_2050; // @[Mux.scala 27:72] + wire _T_2106 = _T_2105 | _T_2051; // @[Mux.scala 27:72] + wire _T_2107 = _T_2106 | _T_2052; // @[Mux.scala 27:72] + wire _T_2108 = _T_2107 | _T_2053; // @[Mux.scala 27:72] + wire _T_2109 = _T_2108 | _T_2054; // @[Mux.scala 27:72] + wire _T_2110 = _T_2109 | _T_2055; // @[Mux.scala 27:72] + wire _T_2111 = _T_2110 | _T_2056; // @[Mux.scala 27:72] + wire _T_2112 = _T_2111 | _T_2057; // @[Mux.scala 27:72] + wire _T_2113 = _T_2112 | _T_2058; // @[Mux.scala 27:72] + wire _T_2114 = _T_2113 | _T_2059; // @[Mux.scala 27:72] + wire _T_2115 = _T_2114 | _T_2060; // @[Mux.scala 27:72] + wire _T_2116 = _T_2115 | _T_2061; // @[Mux.scala 27:72] + wire _T_2117 = _T_2116 | _T_2062; // @[Mux.scala 27:72] + wire _T_2118 = _T_2117 | _T_2063; // @[Mux.scala 27:72] + wire _T_2119 = _T_2118 | _T_2064; // @[Mux.scala 27:72] + wire _T_2120 = _T_2119 | _T_2065; // @[Mux.scala 27:72] + wire _T_2121 = _T_2120 | _T_2066; // @[Mux.scala 27:72] + wire _T_2122 = _T_2121 | _T_2067; // @[Mux.scala 27:72] + wire _T_2123 = _T_2122 | _T_2068; // @[Mux.scala 27:72] + wire _T_2124 = _T_2123 | _T_2069; // @[Mux.scala 27:72] + wire _T_2125 = _T_2124 | _T_2050; // @[Mux.scala 27:72] + wire _T_2126 = _T_2125 | _T_2071; // @[Mux.scala 27:72] + wire _T_2127 = _T_2126 | _T_2072; // @[Mux.scala 27:72] + wire _T_2128 = _T_2127 | _T_2073; // @[Mux.scala 27:72] + wire _T_2129 = _T_2128 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2075; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2076; // @[Mux.scala 27:72] + wire _T_2132 = _T_2131 | _T_2077; // @[Mux.scala 27:72] + wire _T_2133 = _T_2132 | _T_2078; // @[Mux.scala 27:72] + wire _T_2134 = _T_2133 | _T_2079; // @[Mux.scala 27:72] + wire _T_2135 = _T_2134 | _T_2080; // @[Mux.scala 27:72] + wire _T_2136 = _T_2135 | _T_2081; // @[Mux.scala 27:72] + wire _T_2137 = _T_2136 | _T_2082; // @[Mux.scala 27:72] + wire _T_2138 = _T_2137 | _T_2083; // @[Mux.scala 27:72] + wire _T_2139 = _T_2138 | _T_2084; // @[Mux.scala 27:72] + wire _T_2140 = _T_2139 | _T_2085; // @[Mux.scala 27:72] + wire _T_2141 = _T_2140 | _T_2086; // @[Mux.scala 27:72] + wire _T_2142 = _T_2141 | _T_2087; // @[Mux.scala 27:72] + wire _T_2143 = _T_2142 | _T_2088; // @[Mux.scala 27:72] + wire [5:0] _GEN_51 = {{5'd0}, _T_2143}; // @[Mux.scala 27:72] + wire [5:0] _T_2144 = _GEN_51 | _T_2089; // @[Mux.scala 27:72] + wire [5:0] _GEN_52 = {{5'd0}, _T_2090}; // @[Mux.scala 27:72] + wire [5:0] _T_2145 = _T_2144 | _GEN_52; // @[Mux.scala 27:72] + wire [5:0] _GEN_53 = {{5'd0}, _T_2091}; // @[Mux.scala 27:72] + wire [5:0] _T_2146 = _T_2145 | _GEN_53; // @[Mux.scala 27:72] + wire [5:0] _GEN_54 = {{5'd0}, _T_2092}; // @[Mux.scala 27:72] + wire [5:0] _T_2147 = _T_2146 | _GEN_54; // @[Mux.scala 27:72] + wire [5:0] _GEN_55 = {{5'd0}, _T_2093}; // @[Mux.scala 27:72] + wire [5:0] _T_2148 = _T_2147 | _GEN_55; // @[Mux.scala 27:72] + wire [5:0] _GEN_56 = {{5'd0}, _T_2094}; // @[Mux.scala 27:72] + wire [5:0] _T_2149 = _T_2148 | _GEN_56; // @[Mux.scala 27:72] + wire [5:0] _GEN_57 = {{5'd0}, _T_2095}; // @[Mux.scala 27:72] + wire [5:0] _T_2150 = _T_2149 | _GEN_57; // @[Mux.scala 27:72] + wire [5:0] _GEN_58 = {{5'd0}, _T_2096}; // @[Mux.scala 27:72] + wire [5:0] _T_2151 = _T_2150 | _GEN_58; // @[Mux.scala 27:72] + wire [5:0] _GEN_59 = {{5'd0}, _T_2097}; // @[Mux.scala 27:72] + wire [5:0] _T_2152 = _T_2151 | _GEN_59; // @[Mux.scala 27:72] + wire [5:0] _GEN_60 = {{5'd0}, _T_1873}; // @[el2_dec_tlu_ctl.scala 2351:45] + wire [5:0] _T_2154 = _GEN_60 & _T_2152; // @[el2_dec_tlu_ctl.scala 2351:45] + reg mhpmc_inc_r_d1_0; // @[el2_dec_tlu_ctl.scala 2413:54] + reg mhpmc_inc_r_d1_1; // @[el2_dec_tlu_ctl.scala 2414:54] + reg mhpmc_inc_r_d1_2; // @[el2_dec_tlu_ctl.scala 2415:54] + reg mhpmc_inc_r_d1_3; // @[el2_dec_tlu_ctl.scala 2416:54] + reg perfcnt_halted_d1; // @[el2_dec_tlu_ctl.scala 2417:57] + wire perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 2420:68] + wire _T_2164 = ~_T_83; // @[el2_dec_tlu_ctl.scala 2421:38] + wire [3:0] _T_2166 = _T_2164 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2173 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2166 & _T_2173; // @[el2_dec_tlu_ctl.scala 2421:87] + wire _T_2175 = ~perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2423:68] + wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[el2_dec_tlu_ctl.scala 2423:66] + wire _T_2177 = ~_T_2176; // @[el2_dec_tlu_ctl.scala 2423:46] + wire _T_2180 = ~perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2424:68] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[el2_dec_tlu_ctl.scala 2424:66] + wire _T_2182 = ~_T_2181; // @[el2_dec_tlu_ctl.scala 2424:46] + wire _T_2185 = ~perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2425:68] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[el2_dec_tlu_ctl.scala 2425:66] + wire _T_2187 = ~_T_2186; // @[el2_dec_tlu_ctl.scala 2425:46] + wire _T_2190 = ~perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2426:68] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[el2_dec_tlu_ctl.scala 2426:66] + wire _T_2192 = ~_T_2191; // @[el2_dec_tlu_ctl.scala 2426:46] + wire _T_2195 = io_dec_csr_wraddr_r == 12'hb03; // @[el2_dec_tlu_ctl.scala 2432:73] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2195; // @[el2_dec_tlu_ctl.scala 2432:44] + wire _T_2196 = ~perfcnt_halted; // @[el2_dec_tlu_ctl.scala 2433:24] + wire _T_2198 = _T_2196 | perfcnt_during_sleep[0]; // @[el2_dec_tlu_ctl.scala 2433:40] + wire mhpmc_inc_r_0 = _T_1305[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2199 = |mhpmc_inc_r_0; // @[el2_dec_tlu_ctl.scala 2433:87] + wire mhpmc3_wr_en1 = _T_2198 & _T_2199; // @[el2_dec_tlu_ctl.scala 2433:67] + reg [31:0] mhpmc3h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc3; // @[el2_lib.scala 491:16] + wire [63:0] _T_2202 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2203 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2202 + _T_2203; // @[el2_dec_tlu_ctl.scala 2437:50] + wire _T_2211 = io_dec_csr_wraddr_r == 12'hb83; // @[el2_dec_tlu_ctl.scala 2442:74] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2211; // @[el2_dec_tlu_ctl.scala 2442:45] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb04; // @[el2_dec_tlu_ctl.scala 2451:73] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[el2_dec_tlu_ctl.scala 2451:44] + wire _T_2220 = _T_2196 | perfcnt_during_sleep[1]; // @[el2_dec_tlu_ctl.scala 2452:40] + wire mhpmc_inc_r_1 = _T_1588[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2221 = |mhpmc_inc_r_1; // @[el2_dec_tlu_ctl.scala 2452:87] + wire mhpmc4_wr_en1 = _T_2220 & _T_2221; // @[el2_dec_tlu_ctl.scala 2452:67] + reg [31:0] mhpmc4h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc4; // @[el2_lib.scala 491:16] + wire [63:0] _T_2224 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2225 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2224 + _T_2225; // @[el2_dec_tlu_ctl.scala 2457:50] + wire _T_2234 = io_dec_csr_wraddr_r == 12'hb84; // @[el2_dec_tlu_ctl.scala 2461:74] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2234; // @[el2_dec_tlu_ctl.scala 2461:45] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb05; // @[el2_dec_tlu_ctl.scala 2470:73] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[el2_dec_tlu_ctl.scala 2470:44] + wire _T_2243 = _T_2196 | perfcnt_during_sleep[2]; // @[el2_dec_tlu_ctl.scala 2471:40] + wire mhpmc_inc_r_2 = _T_1871[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2244 = |mhpmc_inc_r_2; // @[el2_dec_tlu_ctl.scala 2471:87] + wire mhpmc5_wr_en1 = _T_2243 & _T_2244; // @[el2_dec_tlu_ctl.scala 2471:67] + reg [31:0] mhpmc5h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc5; // @[el2_lib.scala 491:16] + wire [63:0] _T_2247 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2248 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2247 + _T_2248; // @[el2_dec_tlu_ctl.scala 2474:50] + wire _T_2256 = io_dec_csr_wraddr_r == 12'hb85; // @[el2_dec_tlu_ctl.scala 2479:74] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2256; // @[el2_dec_tlu_ctl.scala 2479:45] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb06; // @[el2_dec_tlu_ctl.scala 2488:73] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[el2_dec_tlu_ctl.scala 2488:44] + wire _T_2265 = _T_2196 | perfcnt_during_sleep[3]; // @[el2_dec_tlu_ctl.scala 2489:40] + wire mhpmc_inc_r_3 = _T_2154[0]; // @[el2_dec_tlu_ctl.scala 2346:25 el2_dec_tlu_ctl.scala 2351:20] + wire _T_2266 = |mhpmc_inc_r_3; // @[el2_dec_tlu_ctl.scala 2489:87] + wire mhpmc6_wr_en1 = _T_2265 & _T_2266; // @[el2_dec_tlu_ctl.scala 2489:67] + reg [31:0] mhpmc6h; // @[el2_lib.scala 491:16] + reg [31:0] mhpmc6; // @[el2_lib.scala 491:16] + wire [63:0] _T_2269 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2270 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2269 + _T_2270; // @[el2_dec_tlu_ctl.scala 2492:50] + wire _T_2278 = io_dec_csr_wraddr_r == 12'hb86; // @[el2_dec_tlu_ctl.scala 2497:74] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2278; // @[el2_dec_tlu_ctl.scala 2497:45] + wire _T_2284 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[el2_dec_tlu_ctl.scala 2508:57] + wire _T_2286 = |io_dec_csr_wrdata_r[31:10]; // @[el2_dec_tlu_ctl.scala 2508:103] + wire _T_2287 = _T_2284 | _T_2286; // @[el2_dec_tlu_ctl.scala 2508:72] + wire _T_2290 = io_dec_csr_wraddr_r == 12'h323; // @[el2_dec_tlu_ctl.scala 2510:71] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2290; // @[el2_dec_tlu_ctl.scala 2510:42] + wire _T_2294 = io_dec_csr_wraddr_r == 12'h324; // @[el2_dec_tlu_ctl.scala 2517:71] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2294; // @[el2_dec_tlu_ctl.scala 2517:42] + wire _T_2298 = io_dec_csr_wraddr_r == 12'h325; // @[el2_dec_tlu_ctl.scala 2524:71] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2298; // @[el2_dec_tlu_ctl.scala 2524:42] + wire _T_2302 = io_dec_csr_wraddr_r == 12'h326; // @[el2_dec_tlu_ctl.scala 2531:71] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2302; // @[el2_dec_tlu_ctl.scala 2531:42] + wire _T_2306 = io_dec_csr_wraddr_r == 12'h320; // @[el2_dec_tlu_ctl.scala 2548:78] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2306; // @[el2_dec_tlu_ctl.scala 2548:49] + wire _T_2318 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:52] + wire _T_2319 = _T_2318 | io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 2563:79] + wire _T_2320 = _T_2319 | io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:105] + wire _T_2321 = _T_2320 | io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 2563:131] + wire _T_2322 = _T_2321 | io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 2564:33] + reg _T_2325; // @[el2_dec_tlu_ctl.scala 2566:63] + wire _T_2326 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 2567:92] + wire _T_2327 = ~io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 2567:138] + wire _T_2328 = io_trigger_hit_r_d1 & _T_2327; // @[el2_dec_tlu_ctl.scala 2567:136] + reg _T_2330; // @[el2_dec_tlu_ctl.scala 2567:63] + reg [4:0] _T_2331; // @[el2_dec_tlu_ctl.scala 2568:63] + reg _T_2332; // @[el2_dec_tlu_ctl.scala 2569:63] + wire [31:0] _T_2338 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2347 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2365 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2378 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2390 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2403 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {13'h0,_T_348,4'h0,mfdc_int[11:7],_T_351,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2425 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2443 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2446 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2475 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2478 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mhartid ? _T_2338 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mstatus ? _T_2347 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mtvec ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mip ? _T_2365 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mie ? _T_2378 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mepc ? _T_2390 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mscause ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_meivt ? _T_2403 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_meihap ? _T_615 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_meicurpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_meicidpl ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_meipt ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mcgc ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_mfdc ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dcsr ? _T_2425 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_dpc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dicawics ? _T_2443 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_mtsel ? _T_2446 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mfdht ? _T_2475 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mfdhs ? _T_2478 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme3 ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpme4 ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpme5 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpme6 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mcountinhibit ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mpmc ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2499 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] + wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] + wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] + wire [31:0] _T_2565 = _T_2564 | _T_2510; // @[Mux.scala 27:72] + wire [31:0] _T_2566 = _T_2565 | _T_2511; // @[Mux.scala 27:72] + wire [31:0] _T_2567 = _T_2566 | _T_2512; // @[Mux.scala 27:72] + wire [31:0] _T_2568 = _T_2567 | _T_2513; // @[Mux.scala 27:72] + wire [31:0] _T_2569 = _T_2568 | _T_2514; // @[Mux.scala 27:72] + wire [31:0] _T_2570 = _T_2569 | _T_2515; // @[Mux.scala 27:72] + wire [31:0] _T_2571 = _T_2570 | _T_2516; // @[Mux.scala 27:72] + wire [31:0] _T_2572 = _T_2571 | _T_2517; // @[Mux.scala 27:72] + wire [31:0] _T_2573 = _T_2572 | _T_2518; // @[Mux.scala 27:72] + wire [31:0] _T_2574 = _T_2573 | _T_2519; // @[Mux.scala 27:72] + wire [31:0] _T_2575 = _T_2574 | _T_2520; // @[Mux.scala 27:72] + wire [31:0] _T_2576 = _T_2575 | _T_2521; // @[Mux.scala 27:72] + wire [31:0] _T_2577 = _T_2576 | _T_2522; // @[Mux.scala 27:72] + wire [31:0] _T_2578 = _T_2577 | _T_2523; // @[Mux.scala 27:72] + wire [31:0] _T_2579 = _T_2578 | _T_2524; // @[Mux.scala 27:72] + wire [31:0] _T_2580 = _T_2579 | _T_2525; // @[Mux.scala 27:72] + wire [31:0] _T_2581 = _T_2580 | _T_2526; // @[Mux.scala 27:72] + wire [31:0] _T_2582 = _T_2581 | _T_2527; // @[Mux.scala 27:72] + wire [31:0] _T_2583 = _T_2582 | _T_2528; // @[Mux.scala 27:72] + wire [31:0] _T_2584 = _T_2583 | _T_2529; // @[Mux.scala 27:72] + wire [31:0] _T_2585 = _T_2584 | _T_2530; // @[Mux.scala 27:72] + wire [31:0] _T_2586 = _T_2585 | _T_2531; // @[Mux.scala 27:72] + wire [31:0] _T_2587 = _T_2586 | _T_2532; // @[Mux.scala 27:72] + wire [31:0] _T_2588 = _T_2587 | _T_2533; // @[Mux.scala 27:72] + wire [31:0] _T_2589 = _T_2588 | _T_2534; // @[Mux.scala 27:72] + wire [31:0] _T_2590 = _T_2589 | _T_2535; // @[Mux.scala 27:72] + wire [31:0] _T_2591 = _T_2590 | _T_2536; // @[Mux.scala 27:72] + wire [31:0] _T_2592 = _T_2591 | _T_2537; // @[Mux.scala 27:72] + wire [31:0] _T_2593 = _T_2592 | _T_2538; // @[Mux.scala 27:72] + wire [31:0] _T_2594 = _T_2593 | _T_2539; // @[Mux.scala 27:72] + wire [31:0] _T_2595 = _T_2594 | _T_2540; // @[Mux.scala 27:72] + wire [31:0] _T_2596 = _T_2595 | _T_2541; // @[Mux.scala 27:72] + wire [31:0] _T_2597 = _T_2596 | _T_2542; // @[Mux.scala 27:72] + wire [31:0] _T_2598 = _T_2597 | _T_2543; // @[Mux.scala 27:72] + wire [31:0] _T_2599 = _T_2598 | _T_2544; // @[Mux.scala 27:72] + wire [31:0] _T_2600 = _T_2599 | _T_2545; // @[Mux.scala 27:72] + wire [31:0] _T_2601 = _T_2600 | _T_2546; // @[Mux.scala 27:72] + wire [31:0] _T_2602 = _T_2601 | _T_2547; // @[Mux.scala 27:72] + wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] + wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] + wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_20_io_l1clk), + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en), + .io_scan_mode(rvclkhdr_20_io_scan_mode) + ); + rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_21_io_l1clk), + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en), + .io_scan_mode(rvclkhdr_21_io_scan_mode) + ); + rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_22_io_l1clk), + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en), + .io_scan_mode(rvclkhdr_22_io_scan_mode) + ); + rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_23_io_l1clk), + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en), + .io_scan_mode(rvclkhdr_23_io_scan_mode) + ); + rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_24_io_l1clk), + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en), + .io_scan_mode(rvclkhdr_24_io_scan_mode) + ); + rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_25_io_l1clk), + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en), + .io_scan_mode(rvclkhdr_25_io_scan_mode) + ); + rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_26_io_l1clk), + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en), + .io_scan_mode(rvclkhdr_26_io_scan_mode) + ); + rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_27_io_l1clk), + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en), + .io_scan_mode(rvclkhdr_27_io_scan_mode) + ); + rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_28_io_l1clk), + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en), + .io_scan_mode(rvclkhdr_28_io_scan_mode) + ); + rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_29_io_l1clk), + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en), + .io_scan_mode(rvclkhdr_29_io_scan_mode) + ); + rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_30_io_l1clk), + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en), + .io_scan_mode(rvclkhdr_30_io_scan_mode) + ); + rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_31_io_l1clk), + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en), + .io_scan_mode(rvclkhdr_31_io_scan_mode) + ); + rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_32_io_l1clk), + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en), + .io_scan_mode(rvclkhdr_32_io_scan_mode) + ); + rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 485:23] + .io_l1clk(rvclkhdr_33_io_l1clk), + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en), + .io_scan_mode(rvclkhdr_33_io_scan_mode) + ); + rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_34_io_l1clk), + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en), + .io_scan_mode(rvclkhdr_34_io_scan_mode) + ); + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_762,dicad0[31:0]}; // @[el2_dec_tlu_ctl.scala 2232:65] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[el2_dec_tlu_ctl.scala 2235:42] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_0_match_ = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_1_match_ = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_2_match_ = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] + assign io_trigger_pkt_any_3_match_ = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 2313:36] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[el2_dec_tlu_ctl.scala 2326:53] + assign io_dec_tlu_int_valid_wb1 = _T_2332; // @[el2_dec_tlu_ctl.scala 2569:31] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2330; // @[el2_dec_tlu_ctl.scala 2567:31] + assign io_dec_tlu_i0_valid_wb1 = _T_2325; // @[el2_dec_tlu_ctl.scala 2566:31] + assign io_dec_tlu_mtval_wb1 = mtval; // @[el2_dec_tlu_ctl.scala 2571:25] + assign io_dec_tlu_exc_cause_wb1 = _T_2331; // @[el2_dec_tlu_ctl.scala 2568:31] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2177; // @[el2_dec_tlu_ctl.scala 2423:23] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2182; // @[el2_dec_tlu_ctl.scala 2424:23] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2187; // @[el2_dec_tlu_ctl.scala 2425:23] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2192; // @[el2_dec_tlu_ctl.scala 2426:23] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[el2_dec_tlu_ctl.scala 1797:32] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[el2_dec_tlu_ctl.scala 1798:32] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[el2_dec_tlu_ctl.scala 1799:32] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[el2_dec_tlu_ctl.scala 1800:32] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[el2_dec_tlu_ctl.scala 1801:32] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[el2_dec_tlu_ctl.scala 1802:32] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[el2_dec_tlu_ctl.scala 1803:32] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[el2_dec_tlu_ctl.scala 1804:32] + assign io_dec_csr_rddata_d = _T_2608 | _T_2554; // @[el2_dec_tlu_ctl.scala 2576:22] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[el2_dec_tlu_ctl.scala 1847:40] + assign io_dec_tlu_wr_pause_r = _T_368 & _T_369; // @[el2_dec_tlu_ctl.scala 1856:25] + assign io_dec_tlu_meipt = meipt; // @[el2_dec_tlu_ctl.scala 2083:20] + assign io_dec_tlu_meicurpl = meicurpl; // @[el2_dec_tlu_ctl.scala 2047:23] + assign io_dec_tlu_meihap = _T_615[29:0]; // @[el2_dec_tlu_ctl.scala 2033:21] + assign io_dec_tlu_mrac_ff = mrac; // @[el2_dec_tlu_ctl.scala 1886:22] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[el2_dec_tlu_ctl.scala 1846:40] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[el2_dec_tlu_ctl.scala 1845:40] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[el2_dec_tlu_ctl.scala 1844:40] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[el2_dec_tlu_ctl.scala 1843:40] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[el2_dec_tlu_ctl.scala 1842:40] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[el2_dec_tlu_ctl.scala 1841:40] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[el2_dec_tlu_ctl.scala 1530:24] + assign io_fw_halt_req = _T_500 & _T_501; // @[el2_dec_tlu_ctl.scala 1921:18] + assign io_mstatus = _T_54; // @[el2_dec_tlu_ctl.scala 1546:14] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_52; // @[el2_dec_tlu_ctl.scala 1545:21] + assign io_dcsr = _T_700; // @[el2_dec_tlu_ctl.scala 2130:11] + assign io_mtvec = _T_60; // @[el2_dec_tlu_ctl.scala 1558:12] + assign io_mip = _T_66; // @[el2_dec_tlu_ctl.scala 1573:10] + assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[el2_dec_tlu_ctl.scala 1587:13] + assign io_npc_r = _T_159 | _T_157; // @[el2_dec_tlu_ctl.scala 1681:12] + assign io_npc_r_d1 = _T_165; // @[el2_dec_tlu_ctl.scala 1687:15] + assign io_mepc = _T_194; // @[el2_dec_tlu_ctl.scala 1706:11] + assign io_mdseac_locked_ns = mdseac_en | _T_487; // @[el2_dec_tlu_ctl.scala 1904:23] + assign io_force_halt = mfdht[0] & _T_607; // @[el2_dec_tlu_ctl.scala 2010:17] + assign io_dpc = _T_725; // @[el2_dec_tlu_ctl.scala 2147:10] + assign io_mtdata1_t_0 = _T_871; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_1 = _T_872; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_2 = _T_873; // @[el2_dec_tlu_ctl.scala 2303:41] + assign io_mtdata1_t_3 = _T_874; // @[el2_dec_tlu_ctl.scala 2303:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_56; // @[el2_lib.scala 488:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[el2_lib.scala 488:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[el2_lib.scala 488:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_137; // @[el2_lib.scala 488:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_6_io_en = _T_162 | io_reset_delayed; // @[el2_lib.scala 488:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_7_io_en = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_lib.scala 488:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_323; // @[el2_lib.scala 488:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_335; // @[el2_lib.scala 488:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_372; // @[el2_lib.scala 488:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_11_io_en = _T_491 & _T_492; // @[el2_lib.scala 488:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[el2_lib.scala 488:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_13_io_en = _T_547 | io_iccm_dma_sb_error; // @[el2_lib.scala 488:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[el2_lib.scala 488:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_610; // @[el2_lib.scala 488:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_16_io_en = _T_631 | io_take_ext_int_start; // @[el2_lib.scala 488:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_17_io_en = _T_697 | io_take_nmi; // @[el2_lib.scala 488:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_18_io_en = _T_722 | dpc_capture_npc; // @[el2_lib.scala 488:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_19_io_en = _T_662 & _T_732; // @[el2_lib.scala 488:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 488:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 488:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_22_io_en = _T_970 & _T_806; // @[el2_lib.scala 488:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_23_io_en = _T_979 & _T_815; // @[el2_lib.scala 488:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_24_io_en = _T_988 & _T_824; // @[el2_lib.scala 488:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_25_io_en = _T_997 & _T_833; // @[el2_lib.scala 488:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 487:18] + assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 488:17] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24] + assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_34_io_en = _T_2322 | io_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mpmc_b = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_54 = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + _T_60 = _RAND_2[30:0]; + _RAND_3 = {1{`RANDOM}}; + mdccmect = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + miccmect = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + micect = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_66 = _RAND_6[5:0]; + _RAND_7 = {1{`RANDOM}}; + mie = _RAND_7[5:0]; + _RAND_8 = {1{`RANDOM}}; + temp_ncount6_2 = _RAND_8[4:0]; + _RAND_9 = {1{`RANDOM}}; + temp_ncount0 = _RAND_9[0:0]; + _RAND_10 = {2{`RANDOM}}; + _T_95 = _RAND_10[32:0]; + _RAND_11 = {1{`RANDOM}}; + mcyclel_cout_f = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + mcycleh = _RAND_12[31:0]; + _RAND_13 = {2{`RANDOM}}; + _T_122 = _RAND_13[32:0]; + _RAND_14 = {1{`RANDOM}}; + minstret_enable_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + minstretl_cout_f = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + minstreth = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + mscratch = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + _T_165 = _RAND_18[30:0]; + _RAND_19 = {1{`RANDOM}}; + pc_r_d1 = _RAND_19[30:0]; + _RAND_20 = {1{`RANDOM}}; + _T_194 = _RAND_20[30:0]; + _RAND_21 = {1{`RANDOM}}; + mcause = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + mscause = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + mtval = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + mcgc = _RAND_24[8:0]; + _RAND_25 = {1{`RANDOM}}; + mfdc_int = _RAND_25[14:0]; + _RAND_26 = {1{`RANDOM}}; + mrac = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + mdseac = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + mfdht = _RAND_28[5:0]; + _RAND_29 = {1{`RANDOM}}; + mfdhs = _RAND_29[1:0]; + _RAND_30 = {1{`RANDOM}}; + force_halt_ctr_f = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + meivt = _RAND_31[21:0]; + _RAND_32 = {1{`RANDOM}}; + meihap = _RAND_32[7:0]; + _RAND_33 = {1{`RANDOM}}; + meicurpl = _RAND_33[3:0]; + _RAND_34 = {1{`RANDOM}}; + meicidpl = _RAND_34[3:0]; + _RAND_35 = {1{`RANDOM}}; + meipt = _RAND_35[3:0]; + _RAND_36 = {1{`RANDOM}}; + _T_700 = _RAND_36[15:0]; + _RAND_37 = {1{`RANDOM}}; + _T_725 = _RAND_37[30:0]; + _RAND_38 = {1{`RANDOM}}; + dicawics = _RAND_38[16:0]; + _RAND_39 = {3{`RANDOM}}; + dicad0 = _RAND_39[70:0]; + _RAND_40 = {1{`RANDOM}}; + dicad0h = _RAND_40[31:0]; + _RAND_41 = {1{`RANDOM}}; + _T_757 = _RAND_41[31:0]; + _RAND_42 = {1{`RANDOM}}; + icache_rd_valid_f = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + icache_wr_valid_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + mtsel = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + _T_871 = _RAND_45[9:0]; + _RAND_46 = {1{`RANDOM}}; + _T_872 = _RAND_46[9:0]; + _RAND_47 = {1{`RANDOM}}; + _T_873 = _RAND_47[9:0]; + _RAND_48 = {1{`RANDOM}}; + _T_874 = _RAND_48[9:0]; + _RAND_49 = {1{`RANDOM}}; + mtdata2_t_0 = _RAND_49[31:0]; + _RAND_50 = {1{`RANDOM}}; + mtdata2_t_1 = _RAND_50[31:0]; + _RAND_51 = {1{`RANDOM}}; + mtdata2_t_2 = _RAND_51[31:0]; + _RAND_52 = {1{`RANDOM}}; + mtdata2_t_3 = _RAND_52[31:0]; + _RAND_53 = {1{`RANDOM}}; + mhpme3 = _RAND_53[9:0]; + _RAND_54 = {1{`RANDOM}}; + mhpme4 = _RAND_54[9:0]; + _RAND_55 = {1{`RANDOM}}; + mhpme5 = _RAND_55[9:0]; + _RAND_56 = {1{`RANDOM}}; + mhpme6 = _RAND_56[9:0]; + _RAND_57 = {1{`RANDOM}}; + mhpmc_inc_r_d1_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mhpmc_inc_r_d1_1 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mhpmc_inc_r_d1_2 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + mhpmc_inc_r_d1_3 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + perfcnt_halted_d1 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + mhpmc3h = _RAND_62[31:0]; + _RAND_63 = {1{`RANDOM}}; + mhpmc3 = _RAND_63[31:0]; + _RAND_64 = {1{`RANDOM}}; + mhpmc4h = _RAND_64[31:0]; + _RAND_65 = {1{`RANDOM}}; + mhpmc4 = _RAND_65[31:0]; + _RAND_66 = {1{`RANDOM}}; + mhpmc5h = _RAND_66[31:0]; + _RAND_67 = {1{`RANDOM}}; + mhpmc5 = _RAND_67[31:0]; + _RAND_68 = {1{`RANDOM}}; + mhpmc6h = _RAND_68[31:0]; + _RAND_69 = {1{`RANDOM}}; + mhpmc6 = _RAND_69[31:0]; + _RAND_70 = {1{`RANDOM}}; + _T_2325 = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + _T_2330 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + _T_2331 = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + _T_2332 = _RAND_73[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mpmc_b = 1'h0; + end + if (reset) begin + _T_54 = 2'h0; + end + if (reset) begin + _T_60 = 31'h0; + end + if (reset) begin + mdccmect = 32'h0; + end + if (reset) begin + miccmect = 32'h0; + end + if (reset) begin + micect = 32'h0; + end + if (reset) begin + _T_66 = 6'h0; + end + if (reset) begin + mie = 6'h0; + end + if (reset) begin + temp_ncount6_2 = 5'h0; + end + if (reset) begin + temp_ncount0 = 1'h0; + end + if (reset) begin + _T_95 = 33'h0; + end + if (reset) begin + mcyclel_cout_f = 1'h0; + end + if (reset) begin + mcycleh = 32'h0; + end + if (reset) begin + _T_122 = 33'h0; + end + if (reset) begin + minstret_enable_f = 1'h0; + end + if (reset) begin + minstretl_cout_f = 1'h0; + end + if (reset) begin + minstreth = 32'h0; + end + if (reset) begin + mscratch = 32'h0; + end + if (reset) begin + _T_165 = 31'h0; + end + if (reset) begin + pc_r_d1 = 31'h0; + end + if (reset) begin + _T_194 = 31'h0; + end + if (reset) begin + mcause = 32'h0; + end + if (reset) begin + mscause = 4'h0; + end + if (reset) begin + mtval = 32'h0; + end + if (reset) begin + mcgc = 9'h0; + end + if (reset) begin + mfdc_int = 15'h0; + end + if (reset) begin + mrac = 32'h0; + end + if (reset) begin + mdseac = 32'h0; + end + if (reset) begin + mfdht = 6'h0; + end + if (reset) begin + mfdhs = 2'h0; + end + if (reset) begin + force_halt_ctr_f = 32'h0; + end + if (reset) begin + meivt = 22'h0; + end + if (reset) begin + meihap = 8'h0; + end + if (reset) begin + meicurpl = 4'h0; + end + if (reset) begin + meicidpl = 4'h0; + end + if (reset) begin + meipt = 4'h0; + end + if (reset) begin + _T_700 = 16'h0; + end + if (reset) begin + _T_725 = 31'h0; + end + if (reset) begin + dicawics = 17'h0; + end + if (reset) begin + dicad0 = 71'h0; + end + if (reset) begin + dicad0h = 32'h0; + end + if (reset) begin + _T_757 = 32'h0; + end + if (reset) begin + icache_rd_valid_f = 1'h0; + end + if (reset) begin + icache_wr_valid_f = 1'h0; + end + if (reset) begin + mtsel = 2'h0; + end + if (reset) begin + _T_871 = 10'h0; + end + if (reset) begin + _T_872 = 10'h0; + end + if (reset) begin + _T_873 = 10'h0; + end + if (reset) begin + _T_874 = 10'h0; + end + if (reset) begin + mtdata2_t_0 = 32'h0; + end + if (reset) begin + mtdata2_t_1 = 32'h0; + end + if (reset) begin + mtdata2_t_2 = 32'h0; + end + if (reset) begin + mtdata2_t_3 = 32'h0; + end + if (reset) begin + mhpme3 = 10'h0; + end + if (reset) begin + mhpme4 = 10'h0; + end + if (reset) begin + mhpme5 = 10'h0; + end + if (reset) begin + mhpme6 = 10'h0; + end + if (reset) begin + mhpmc_inc_r_d1_0 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_1 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_2 = 1'h0; + end + if (reset) begin + mhpmc_inc_r_d1_3 = 1'h0; + end + if (reset) begin + perfcnt_halted_d1 = 1'h0; + end + if (reset) begin + mhpmc3h = 32'h0; + end + if (reset) begin + mhpmc3 = 32'h0; + end + if (reset) begin + mhpmc4h = 32'h0; + end + if (reset) begin + mhpmc4 = 32'h0; + end + if (reset) begin + mhpmc5h = 32'h0; + end + if (reset) begin + mhpmc5 = 32'h0; + end + if (reset) begin + mhpmc6h = 32'h0; + end + if (reset) begin + mhpmc6 = 32'h0; + end + if (reset) begin + _T_2325 = 1'h0; + end + if (reset) begin + _T_2330 = 1'h0; + end + if (reset) begin + _T_2331 = 5'h0; + end + if (reset) begin + _T_2332 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mpmc_b <= 1'h0; + end else if (wr_mpmc_r) begin + mpmc_b <= _T_507; + end else begin + mpmc_b <= _T_508; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_54 <= 2'h0; + end else begin + _T_54 <= _T_46 | _T_42; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_60 <= 31'h0; + end else begin + _T_60 <= {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + mdccmect <= 32'h0; + end else if (wr_mdccmect_r) begin + mdccmect <= _T_523; + end else begin + mdccmect <= _T_567; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + miccmect <= 32'h0; + end else if (wr_miccmect_r) begin + miccmect <= _T_523; + end else begin + miccmect <= _T_546; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + micect <= 32'h0; + end else if (wr_micect_r) begin + micect <= _T_523; + end else begin + micect <= _T_525; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_66 <= 6'h0; + end else begin + _T_66 <= {_T_65,_T_63}; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mie <= 6'h0; + end else begin + mie <= io_mie_ns; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount6_2 <= 5'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + temp_ncount0 <= 1'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount0 <= io_dec_csr_wrdata_r[0]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_95 <= 33'h0; + end else if (wr_mcyclel_r) begin + _T_95 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_95 <= mcyclel_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mcyclel_cout_f <= 1'h0; + end else begin + mcyclel_cout_f <= mcyclel_cout & _T_96; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + mcycleh <= 32'h0; + end else if (wr_mcycleh_r) begin + mcycleh <= io_dec_csr_wrdata_r; + end else begin + mcycleh <= mcycleh_inc; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + _T_122 <= 33'h0; + end else if (wr_minstretl_r) begin + _T_122 <= {{1'd0}, io_dec_csr_wrdata_r}; + end else begin + _T_122 <= minstretl_inc; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstret_enable_f <= 1'h0; + end else begin + minstret_enable_f <= i0_valid_no_ebreak_ecall_r | wr_minstretl_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + minstretl_cout_f <= 1'h0; + end else begin + minstretl_cout_f <= minstretl_cout & _T_123; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + minstreth <= 32'h0; + end else if (wr_minstreth_r) begin + minstreth <= io_dec_csr_wrdata_r; + end else begin + minstreth <= minstreth_inc; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + mscratch <= 32'h0; + end else begin + mscratch <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + _T_165 <= 31'h0; + end else begin + _T_165 <= io_npc_r; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else begin + pc_r_d1 <= _T_169 | _T_170; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + _T_194 <= 31'h0; + end else begin + _T_194 <= _T_192 | _T_190; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mcause <= 32'h0; + end else begin + mcause <= _T_232 | _T_228; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mscause <= 4'h0; + end else begin + mscause <= _T_262 | _T_261; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mtval <= 32'h0; + end else begin + mtval <= _T_319 | _T_315; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + mcgc <= 9'h0; + end else begin + mcgc <= io_dec_csr_wrdata_r[8:0]; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + mfdc_int <= 15'h0; + end else begin + mfdc_int <= {_T_345,_T_344}; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + mrac <= 32'h0; + end else begin + mrac <= {_T_482,_T_467}; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + mdseac <= 32'h0; + end else begin + mdseac <= io_lsu_imprecise_error_addr_any; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdht <= 6'h0; + end else if (wr_mfdht_r) begin + mfdht <= io_dec_csr_wrdata_r[5:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mfdhs <= 2'h0; + end else if (_T_593) begin + if (wr_mfdhs_r) begin + mfdhs <= io_dec_csr_wrdata_r[1:0]; + end else if (_T_587) begin + mfdhs <= _T_591; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + force_halt_ctr_f <= 32'h0; + end else if (mfdht[0]) begin + if (io_debug_halt_req_f) begin + force_halt_ctr_f <= _T_598; + end else if (io_dbg_tlu_halted_f) begin + force_halt_ctr_f <= 32'h0; + end + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + meivt <= 22'h0; + end else begin + meivt <= io_dec_csr_wrdata_r[31:10]; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + meihap <= 8'h0; + end else begin + meihap <= io_pic_claimid; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meicurpl <= 4'h0; + end else if (wr_meicurpl_r) begin + meicurpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + meicidpl <= 4'h0; + end else if (wr_meicpct_r) begin + meicidpl <= io_pic_pl; + end else if (wr_meicidpl_r) begin + meicidpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + meipt <= 4'h0; + end else if (wr_meipt_r) begin + meipt <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + _T_700 <= 16'h0; + end else if (enter_debug_halt_req_le) begin + _T_700 <= _T_674; + end else if (wr_dcsr_r) begin + _T_700 <= _T_689; + end else begin + _T_700 <= _T_694; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + _T_725 <= 31'h0; + end else begin + _T_725 <= _T_720 | _T_719; + end + end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + dicawics <= 17'h0; + end else begin + dicawics <= {_T_729,io_dec_csr_wrdata_r[16:3]}; + end + end + always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin + if (reset) begin + dicad0 <= 71'h0; + end else if (wr_dicad0_r) begin + dicad0 <= {{39'd0}, io_dec_csr_wrdata_r}; + end else begin + dicad0 <= io_ifu_ic_debug_rd_data; + end + end + always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin + if (reset) begin + dicad0h <= 32'h0; + end else if (wr_dicad0h_r) begin + dicad0h <= io_dec_csr_wrdata_r; + end else begin + dicad0h <= io_ifu_ic_debug_rd_data[63:32]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_757 <= 32'h0; + end else if (_T_755) begin + if (_T_751) begin + _T_757 <= io_dec_csr_wrdata_r; + end else begin + _T_757 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_rd_valid_f <= 1'h0; + end else begin + icache_rd_valid_f <= _T_767 & _T_769; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + icache_wr_valid_f <= 1'h0; + end else begin + icache_wr_valid_f <= _T_662 & _T_772; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mtsel <= 2'h0; + end else if (wr_mtsel_r) begin + mtsel <= io_dec_csr_wrdata_r[1:0]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_871 <= 10'h0; + end else if (wr_mtdata1_t_r_0) begin + _T_871 <= tdata_wrdata_r; + end else begin + _T_871 <= _T_842; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_872 <= 10'h0; + end else if (wr_mtdata1_t_r_1) begin + _T_872 <= tdata_wrdata_r; + end else begin + _T_872 <= _T_851; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_873 <= 10'h0; + end else if (wr_mtdata1_t_r_2) begin + _T_873 <= tdata_wrdata_r; + end else begin + _T_873 <= _T_860; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_874 <= 10'h0; + end else if (wr_mtdata1_t_r_3) begin + _T_874 <= tdata_wrdata_r; + end else begin + _T_874 <= _T_869; + end + end + always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_0 <= 32'h0; + end else begin + mtdata2_t_0 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_1 <= 32'h0; + end else begin + mtdata2_t_1 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_2 <= 32'h0; + end else begin + mtdata2_t_2 <= io_dec_csr_wrdata_r; + end + end + always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin + if (reset) begin + mtdata2_t_3 <= 32'h0; + end else begin + mtdata2_t_3 <= io_dec_csr_wrdata_r; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme3 <= 10'h0; + end else if (wr_mhpme3_r) begin + if (_T_2287) begin + mhpme3 <= 10'h204; + end else begin + mhpme3 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme4 <= 10'h0; + end else if (wr_mhpme4_r) begin + if (_T_2287) begin + mhpme4 <= 10'h204; + end else begin + mhpme4 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme5 <= 10'h0; + end else if (wr_mhpme5_r) begin + if (_T_2287) begin + mhpme5 <= 10'h204; + end else begin + mhpme5 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + mhpme6 <= 10'h0; + end else if (wr_mhpme6_r) begin + if (_T_2287) begin + mhpme6 <= 10'h204; + end else begin + mhpme6 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_0 <= 1'h0; + end else begin + mhpmc_inc_r_d1_0 <= _T_1305[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_1 <= 1'h0; + end else begin + mhpmc_inc_r_d1_1 <= _T_1588[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_2 <= 1'h0; + end else begin + mhpmc_inc_r_d1_2 <= _T_1871[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mhpmc_inc_r_d1_3 <= 1'h0; + end else begin + mhpmc_inc_r_d1_3 <= _T_2154[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + perfcnt_halted_d1 <= 1'h0; + end else begin + perfcnt_halted_d1 <= _T_83 | io_dec_tlu_pmu_fw_halted; + end + end + always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3h <= 32'h0; + end else if (mhpmc3h_wr_en0) begin + mhpmc3h <= io_dec_csr_wrdata_r; + end else begin + mhpmc3h <= mhpmc3_incr[63:32]; + end + end + always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc3 <= 32'h0; + end else if (mhpmc3_wr_en0) begin + mhpmc3 <= io_dec_csr_wrdata_r; + end else begin + mhpmc3 <= mhpmc3_incr[31:0]; + end + end + always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4h <= 32'h0; + end else if (mhpmc4h_wr_en0) begin + mhpmc4h <= io_dec_csr_wrdata_r; + end else begin + mhpmc4h <= mhpmc4_incr[63:32]; + end + end + always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc4 <= 32'h0; + end else if (mhpmc4_wr_en0) begin + mhpmc4 <= io_dec_csr_wrdata_r; + end else begin + mhpmc4 <= mhpmc4_incr[31:0]; + end + end + always @(posedge rvclkhdr_31_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5h <= 32'h0; + end else if (mhpmc5h_wr_en0) begin + mhpmc5h <= io_dec_csr_wrdata_r; + end else begin + mhpmc5h <= mhpmc5_incr[63:32]; + end + end + always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc5 <= 32'h0; + end else if (mhpmc5_wr_en0) begin + mhpmc5 <= io_dec_csr_wrdata_r; + end else begin + mhpmc5 <= mhpmc5_incr[31:0]; + end + end + always @(posedge rvclkhdr_33_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6h <= 32'h0; + end else if (mhpmc6h_wr_en0) begin + mhpmc6h <= io_dec_csr_wrdata_r; + end else begin + mhpmc6h <= mhpmc6_incr[63:32]; + end + end + always @(posedge rvclkhdr_32_io_l1clk or posedge reset) begin + if (reset) begin + mhpmc6 <= 32'h0; + end else if (mhpmc6_wr_en0) begin + mhpmc6 <= io_dec_csr_wrdata_r; + end else begin + mhpmc6 <= mhpmc6_incr[31:0]; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2325 <= 1'h0; + end else begin + _T_2325 <= io_i0_valid_wb; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2330 <= 1'h0; + end else begin + _T_2330 <= _T_2326 | _T_2328; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2331 <= 5'h0; + end else begin + _T_2331 <= io_exc_cause_wb; + end + end + always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin + if (reset) begin + _T_2332 <= 1'h0; + end else begin + _T_2332 <= io_interrupt_valid_r_d1; + end + end +endmodule +module el2_dec_decode_csr_read( + input [11:0] io_dec_csr_rdaddr_d, + output io_csr_pkt_csr_misa, + output io_csr_pkt_csr_mvendorid, + output io_csr_pkt_csr_marchid, + output io_csr_pkt_csr_mimpid, + output io_csr_pkt_csr_mhartid, + output io_csr_pkt_csr_mstatus, + output io_csr_pkt_csr_mtvec, + output io_csr_pkt_csr_mip, + output io_csr_pkt_csr_mie, + output io_csr_pkt_csr_mcyclel, + output io_csr_pkt_csr_mcycleh, + output io_csr_pkt_csr_minstretl, + output io_csr_pkt_csr_minstreth, + output io_csr_pkt_csr_mscratch, + output io_csr_pkt_csr_mepc, + output io_csr_pkt_csr_mcause, + output io_csr_pkt_csr_mscause, + output io_csr_pkt_csr_mtval, + output io_csr_pkt_csr_mrac, + output io_csr_pkt_csr_dmst, + output io_csr_pkt_csr_mdseac, + output io_csr_pkt_csr_meihap, + output io_csr_pkt_csr_meivt, + output io_csr_pkt_csr_meipt, + output io_csr_pkt_csr_meicurpl, + output io_csr_pkt_csr_meicidpl, + output io_csr_pkt_csr_dcsr, + output io_csr_pkt_csr_mcgc, + output io_csr_pkt_csr_mfdc, + output io_csr_pkt_csr_dpc, + output io_csr_pkt_csr_mtsel, + output io_csr_pkt_csr_mtdata1, + output io_csr_pkt_csr_mtdata2, + output io_csr_pkt_csr_mhpmc3, + output io_csr_pkt_csr_mhpmc4, + output io_csr_pkt_csr_mhpmc5, + output io_csr_pkt_csr_mhpmc6, + output io_csr_pkt_csr_mhpmc3h, + output io_csr_pkt_csr_mhpmc4h, + output io_csr_pkt_csr_mhpmc5h, + output io_csr_pkt_csr_mhpmc6h, + output io_csr_pkt_csr_mhpme3, + output io_csr_pkt_csr_mhpme4, + output io_csr_pkt_csr_mhpme5, + output io_csr_pkt_csr_mhpme6, + output io_csr_pkt_csr_mcountinhibit, + output io_csr_pkt_csr_mitctl0, + output io_csr_pkt_csr_mitctl1, + output io_csr_pkt_csr_mitb0, + output io_csr_pkt_csr_mitb1, + output io_csr_pkt_csr_mitcnt0, + output io_csr_pkt_csr_mitcnt1, + output io_csr_pkt_csr_mpmc, + output io_csr_pkt_csr_meicpct, + output io_csr_pkt_csr_micect, + output io_csr_pkt_csr_miccmect, + output io_csr_pkt_csr_mdccmect, + output io_csr_pkt_csr_mfdht, + output io_csr_pkt_csr_mfdhs, + output io_csr_pkt_csr_dicawics, + output io_csr_pkt_csr_dicad0h, + output io_csr_pkt_csr_dicad0, + output io_csr_pkt_csr_dicad1, + output io_csr_pkt_csr_dicago, + output io_csr_pkt_presync, + output io_csr_pkt_postsync, + output io_csr_pkt_legal +); + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_9 = _T_1 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_10 = _T_9 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_11 = _T_10 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_20 = _T_19 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:159] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_102 = _T_101 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_103 = _T_102 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_104 = _T_103 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_120 = _T_119 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_121 = _T_120 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_122 = _T_121 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_123 = _T_122 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_138 = _T_15 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_139 = _T_138 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_140 = _T_139 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_141 = _T_140 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:123] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_157 = _T_156 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_158 = _T_157 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_159 = _T_158 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_172 = _T_75 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_173 = _T_172 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_182 = _T_75 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_218 = _T_217 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_219 = _T_218 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_220 = _T_219 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_231 = _T_230 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_241 = _T_240 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_260 = _T_259 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_261 = _T_260 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_269 = _T_268 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_310 = _T_300 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_331 = _T_330 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_332 = _T_331 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_382 = _T_381 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_397 = _T_103 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_411 = _T_15 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_412 = _T_411 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_413 = _T_412 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_427 = _T_426 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_428 = _T_427 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_444 = _T_119 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_445 = _T_444 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_447 = _T_446 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_461 = _T_460 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_491 = _T_490 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_492 = _T_491 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_493 = _T_492 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_506 = _T_505 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_508 = _T_507 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_553 = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_564 = _T_563 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_585 = _T_563 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_615 = _T_614 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_625 = _T_624 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_668 = _T_196 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_669 = _T_668 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_716 = _T_1 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_718 = _T_717 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_719 = _T_718 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_738 = _T_737 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_748 = _T_726 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_787 = _T_311 | _T_553; // @[el2_dec_tlu_ctl.scala 2716:73] + wire _T_799 = _T_3 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_800 = _T_799 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_801 = _T_800 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_802 = _T_801 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_804 = _T_787 | _T_803; // @[el2_dec_tlu_ctl.scala 2716:113] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_814 = _T_813 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_816 = _T_815 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_817 = _T_804 | _T_816; // @[el2_dec_tlu_ctl.scala 2716:147] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_829 = _T_828 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_830 = _T_817 | _T_829; // @[el2_dec_tlu_ctl.scala 2717:41] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_842 = _T_841 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_843 = _T_842 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_844 = _T_843 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_869 = _T_311 | _T_70; // @[el2_dec_tlu_ctl.scala 2718:73] + wire _T_879 = _T_869 | _T_183; // @[el2_dec_tlu_ctl.scala 2718:113] + wire _T_889 = _T_879 | _T_342; // @[el2_dec_tlu_ctl.scala 2718:154] + wire _T_904 = _T_1 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_905 = _T_904 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_906 = _T_905 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_907 = _T_906 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_908 = _T_907 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_909 = _T_908 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_910 = _T_889 | _T_909; // @[el2_dec_tlu_ctl.scala 2719:41] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_923 = _T_922 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_924 = _T_923 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_925 = _T_924 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_926 = _T_910 | _T_925; // @[el2_dec_tlu_ctl.scala 2719:81] + wire _T_937 = _T_231 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_961 = _T_960 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_962 = _T_961 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_964 = _T_963 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_983 = _T_1 & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_986 = _T_985 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_987 = _T_986 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_988 = _T_987 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_989 = _T_988 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_990 = _T_989 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_991 = _T_990 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_992 = _T_964 | _T_991; // @[el2_dec_tlu_ctl.scala 2721:73] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1014 = _T_1013 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1015 = _T_1014 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1016 = _T_992 | _T_1015; // @[el2_dec_tlu_ctl.scala 2721:121] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1036 = _T_1035 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1037 = _T_1036 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1038 = _T_1037 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1039 = _T_1038 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1040 = _T_1039 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1041 = _T_1016 | _T_1040; // @[el2_dec_tlu_ctl.scala 2722:57] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1056 = _T_1055 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1057 = _T_1056 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1058 = _T_1057 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1059 = _T_1041 | _T_1058; // @[el2_dec_tlu_ctl.scala 2722:105] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1084 = _T_1059 | _T_1083; // @[el2_dec_tlu_ctl.scala 2723:65] + wire _T_1105 = _T_1079 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1106 = _T_1105 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1107 = _T_1084 | _T_1106; // @[el2_dec_tlu_ctl.scala 2723:113] + wire _T_1125 = _T_1033 & _T_15; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1126 = _T_1125 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1127 = _T_1126 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1129 = _T_1128 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1130 = _T_1129 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1132 = _T_1107 | _T_1131; // @[el2_dec_tlu_ctl.scala 2724:57] + wire _T_1152 = _T_958 & _T_3; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1154 = _T_1153 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1155 = _T_1154 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1156 = _T_1155 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1157 = _T_1132 | _T_1156; // @[el2_dec_tlu_ctl.scala 2724:113] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1177 = _T_1157 | _T_1176; // @[el2_dec_tlu_ctl.scala 2725:57] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1203 = _T_1202 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1204 = _T_1203 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1205 = _T_1177 | _T_1204; // @[el2_dec_tlu_ctl.scala 2725:113] + wire _T_1224 = _T_959 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1225 = _T_1224 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1228 = _T_1205 | _T_1227; // @[el2_dec_tlu_ctl.scala 2726:57] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1249 = _T_1248 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1251 = _T_1228 | _T_1250; // @[el2_dec_tlu_ctl.scala 2726:113] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1276 = _T_1251 | _T_1275; // @[el2_dec_tlu_ctl.scala 2727:57] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1298 = _T_1276 | _T_1297; // @[el2_dec_tlu_ctl.scala 2727:113] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1316 = _T_1315 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1317 = _T_1316 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1319 = _T_1318 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1320 = _T_1298 | _T_1319; // @[el2_dec_tlu_ctl.scala 2728:65] + wire _T_1343 = _T_1318 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1344 = _T_1343 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1345 = _T_1320 | _T_1344; // @[el2_dec_tlu_ctl.scala 2728:121] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1362 = _T_1345 | _T_1361; // @[el2_dec_tlu_ctl.scala 2729:57] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1385 = _T_1362 | _T_1384; // @[el2_dec_tlu_ctl.scala 2729:113] + wire _T_1406 = _T_1225 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1407 = _T_1385 | _T_1406; // @[el2_dec_tlu_ctl.scala 2730:57] + wire _T_1430 = _T_1226 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1431 = _T_1407 | _T_1430; // @[el2_dec_tlu_ctl.scala 2730:113] + wire _T_1455 = _T_1153 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1456 = _T_1455 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1457 = _T_1456 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1458 = _T_1457 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1459 = _T_1431 | _T_1458; // @[el2_dec_tlu_ctl.scala 2731:57] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1476 = _T_1459 | _T_1475; // @[el2_dec_tlu_ctl.scala 2731:105] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1499 = _T_1498 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1500 = _T_1499 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1501 = _T_1500 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1502 = _T_1501 & _T_7; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1503 = _T_1476 | _T_1502; // @[el2_dec_tlu_ctl.scala 2732:65] + wire _T_1526 = _T_986 & _T_5; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1527 = _T_1526 & _T_94; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1528 = _T_1527 & _T_96; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1529 = _T_1528 & _T_17; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1530 = _T_1529 & _T_27; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1531 = _T_1503 | _T_1530; // @[el2_dec_tlu_ctl.scala 2732:113] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1551 = _T_1531 | _T_1550; // @[el2_dec_tlu_ctl.scala 2733:57] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1568 = _T_1551 | _T_1567; // @[el2_dec_tlu_ctl.scala 2733:113] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + wire _T_1588 = _T_1568 | _T_1587; // @[el2_dec_tlu_ctl.scala 2734:65] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[el2_dec_tlu_ctl.scala 2648:192] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2650:49] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2651:49] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[el2_dec_tlu_ctl.scala 2652:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2653:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2654:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[el2_dec_tlu_ctl.scala 2655:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2656:49] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2657:57] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[el2_dec_tlu_ctl.scala 2658:57] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[el2_dec_tlu_ctl.scala 2659:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[el2_dec_tlu_ctl.scala 2660:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[el2_dec_tlu_ctl.scala 2661:49] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[el2_dec_tlu_ctl.scala 2662:49] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[el2_dec_tlu_ctl.scala 2663:49] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2664:49] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[el2_dec_tlu_ctl.scala 2665:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2666:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2667:49] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[el2_dec_tlu_ctl.scala 2668:49] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[el2_dec_tlu_ctl.scala 2669:49] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[el2_dec_tlu_ctl.scala 2670:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[el2_dec_tlu_ctl.scala 2671:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[el2_dec_tlu_ctl.scala 2672:49] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2673:49] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[el2_dec_tlu_ctl.scala 2674:49] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2675:49] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[el2_dec_tlu_ctl.scala 2676:49] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[el2_dec_tlu_ctl.scala 2677:49] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2678:49] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2679:57] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[el2_dec_tlu_ctl.scala 2680:49] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2681:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2682:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2683:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[el2_dec_tlu_ctl.scala 2684:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2685:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[el2_dec_tlu_ctl.scala 2686:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2687:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[el2_dec_tlu_ctl.scala 2688:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2689:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[el2_dec_tlu_ctl.scala 2690:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2691:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[el2_dec_tlu_ctl.scala 2692:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2693:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[el2_dec_tlu_ctl.scala 2694:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[el2_dec_tlu_ctl.scala 2695:41] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[el2_dec_tlu_ctl.scala 2696:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2697:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2698:49] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[el2_dec_tlu_ctl.scala 2699:49] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[el2_dec_tlu_ctl.scala 2700:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2701:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[el2_dec_tlu_ctl.scala 2702:49] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[el2_dec_tlu_ctl.scala 2704:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[el2_dec_tlu_ctl.scala 2706:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2707:49] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[el2_dec_tlu_ctl.scala 2708:49] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[el2_dec_tlu_ctl.scala 2709:49] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2710:49] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[el2_dec_tlu_ctl.scala 2711:49] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[el2_dec_tlu_ctl.scala 2712:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2713:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[el2_dec_tlu_ctl.scala 2714:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[el2_dec_tlu_ctl.scala 2715:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[el2_dec_tlu_ctl.scala 2716:26] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[el2_dec_tlu_ctl.scala 2718:24] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[el2_dec_tlu_ctl.scala 2721:20] +endmodule +module el2_dec_tlu_ctl( + input clock, + input reset, + input io_active_clk, + input io_free_clk, + input io_scan_mode, + input [30:0] io_rst_vec, + input io_nmi_int, + input [30:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + input io_lsu_fastint_stall_any, + input io_ifu_pmu_instr_aligned, + input io_ifu_pmu_fetch_stall, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_ifu_pmu_bus_trxn, + input io_dec_pmu_instr_decoded, + input io_dec_pmu_decode_stall, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_exu_pmu_i0_br_misp, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_pc4, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_error, + input io_lsu_pmu_bus_busy, + input io_lsu_pmu_load_external_m, + input io_lsu_pmu_store_external_m, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_iccm_dma_sb_error, + input io_lsu_error_pkt_r_exc_valid, + input io_lsu_error_pkt_r_single_ecc_error, + input io_lsu_error_pkt_r_inst_type, + input io_lsu_error_pkt_r_exc_type, + input io_lsu_error_pkt_r_mscause, + input io_lsu_error_pkt_r_addr, + input io_lsu_single_ecc_error_incr, + input io_dec_pause_state, + input io_lsu_imprecise_error_store_any, + input io_lsu_imprecise_error_load_any, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_dec_csr_wen_unq_d, + input io_dec_csr_any_unq_d, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_r, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_dec_csr_stall_int_ff, + input io_dec_tlu_i0_valid_r, + input [30:0] io_exu_npc_r, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_packet_r_legal, + input io_dec_tlu_packet_r_icaf, + input io_dec_tlu_packet_r_icaf_f1, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input io_dec_tlu_packet_r_fence_i, + input [3:0] io_dec_tlu_packet_r_i0trigger, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input [31:0] io_dec_illegal_inst, + input io_dec_i0_decode_d, + input [1:0] io_exu_i0_br_hist_r, + input io_exu_i0_br_error_r, + input io_exu_i0_br_start_error_r, + input io_exu_i0_br_valid_r, + input io_exu_i0_br_mp_r, + input io_exu_i0_br_middle_r, + input io_exu_i0_br_way_r, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_debug_stall, + output io_dec_tlu_flush_noredir_r, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_leak_one_r, + output io_dec_tlu_flush_err_r, + output io_dec_tlu_flush_extint, + output [29:0] io_dec_tlu_meihap, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_ifu_miss_state_idle, + input io_lsu_idle_any, + input io_dec_div_active, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_ic_error_start, + input io_ifu_iccm_rd_ecc_single_err, + input [70:0] io_ifu_ic_debug_rd_data, + input io_ifu_ic_debug_rd_data_valid, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input [7:0] io_pic_claimid, + input [3:0] io_pic_pl, + input io_mhwakeup, + input io_mexintpend, + input io_timer_int, + input io_soft_int, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + output [3:0] io_dec_tlu_meicurpl, + output [3:0] io_dec_tlu_meipt, + output [31:0] io_dec_csr_rddata_d, + output io_dec_csr_legal_d, + output io_dec_tlu_br0_r_pkt_valid, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, + output io_dec_tlu_i0_kill_writeb_wb, + output io_dec_tlu_flush_lower_wb, + output io_dec_tlu_i0_commit_cmt, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_flush_lower_r, + output [30:0] io_dec_tlu_flush_path_r, + output io_dec_tlu_fence_i_r, + output io_dec_tlu_wr_pause_r, + output io_dec_tlu_flush_pause_r, + output io_dec_tlu_presync_d, + output io_dec_tlu_postsync_d, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_force_halt, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + output io_dec_tlu_int_valid_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output [31:0] io_dec_tlu_mtval_wb1, + output io_dec_tlu_external_ldfwd_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_pipelining_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; +`endif // RANDOMIZE_REG_INIT + wire int_timers_clock; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_reset; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_free_clk; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_scan_mode; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 355:24] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitb1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 355:24] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 355:24] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 474:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 474:22] + wire csr_clock; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_reset; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_free_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_active_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_scan_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 897:17] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 897:17] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_pic_pl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire [29:0] csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire [7:0] csr_io_pic_claimid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_error_pkt_r_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_rst_vec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [27:0] csr_io_core_id; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_trigger_hit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mret_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire [15:0] csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_timer_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_soft_int_sync; // @[el2_dec_tlu_ctl.scala 897:17] + wire [5:0] csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_wr_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_pmu_fw_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire [1:0] csr_io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_reset_delayed; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_e4e5_int_clk; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_inst_acc_second_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_nmi; // @[el2_dec_tlu_ctl.scala 897:17] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_exc_cause_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_valid_wb; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [4:0] csr_io_exc_cause_wb; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_store_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_lsu_load_type; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_i0_commit_cmt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ecall_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_illegal_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_ns; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int_start; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_allow_dbg_halt_csr_write; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode_f; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_done; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_update_hit_bit_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_timer_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_take_ext_int; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_dec_tlu_br0_start_error_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 897:17] + wire [9:0] csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 897:17] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 1090:22] + wire csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 1090:22] + reg dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 447:81] + wire _T = ~dbg_halt_state_f; // @[el2_dec_tlu_ctl.scala 354:33] + reg mpc_halt_state_f; // @[el2_dec_tlu_ctl.scala 442:81] + wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] + wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] + reg [6:0] _T_8; // @[el2_lib.scala 174:81] + reg [6:0] syncro_ff; // @[el2_lib.scala 174:58] + wire nmi_int_sync = syncro_ff[6]; // @[el2_dec_tlu_ctl.scala 382:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[el2_dec_tlu_ctl.scala 385:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 345:41 el2_dec_tlu_ctl.scala 1083:31] + reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] + wire _T_11 = io_lsu_error_pkt_r_exc_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:65] + reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[el2_dec_tlu_ctl.scala 395:29] + reg debug_mode_status; // @[el2_dec_tlu_ctl.scala 405:73] + reg i_cpu_run_req_d1_raw; // @[el2_dec_tlu_ctl.scala 653:72] + reg nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 420:64] + wire _T_37 = ~nmi_int_delayed; // @[el2_dec_tlu_ctl.scala 429:39] + wire _T_38 = nmi_int_sync & _T_37; // @[el2_dec_tlu_ctl.scala 429:37] + reg mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 686:89] + wire _T_35 = ~mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 427:26] + wire _T_36 = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 427:78] + wire nmi_lsu_detected = _T_35 & _T_36; // @[el2_dec_tlu_ctl.scala 427:43] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[el2_dec_tlu_ctl.scala 429:57] + reg nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 421:72] + reg take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 894:90] + wire _T_40 = ~take_nmi_r_d1; // @[el2_dec_tlu_ctl.scala 429:100] + wire _T_41 = nmi_int_detected_f & _T_40; // @[el2_dec_tlu_ctl.scala 429:98] + wire _T_42 = _T_39 | _T_41; // @[el2_dec_tlu_ctl.scala 429:76] + reg take_ext_int_start_d3; // @[el2_dec_tlu_ctl.scala 826:58] + wire _T_43 = |io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 429:159] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] + wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 344:41 el2_dec_tlu_ctl.scala 1082:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 350:41 el2_dec_tlu_ctl.scala 1088:31] + wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 339:41 el2_dec_tlu_ctl.scala 1077:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] + wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[el2_dec_tlu_ctl.scala 802:82] + wire _T_392 = _T_391 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 680:83] + reg int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 660:65] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:100] + reg int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 661:65] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 680:124] + wire _T_608 = _T_632 & mip[2]; // @[el2_dec_tlu_ctl.scala 799:65] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[el2_dec_tlu_ctl.scala 799:83] + wire _T_395 = io_mhwakeup & mhwakeup_ready; // @[el2_dec_tlu_ctl.scala 680:163] + wire _T_396 = _T_394 | _T_395; // @[el2_dec_tlu_ctl.scala 680:148] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[el2_dec_tlu_ctl.scala 680:182] + reg i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 652:80] + wire _T_398 = ~i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 680:207] + wire _T_399 = _T_397 & _T_398; // @[el2_dec_tlu_ctl.scala 680:205] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[el2_dec_tlu_ctl.scala 680:44] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 396:49] + wire _T_685 = ~_T_43; // @[el2_dec_tlu_ctl.scala 831:45] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 831:43] + wire _T_698 = ~soft_int_ready; // @[el2_dec_tlu_ctl.scala 848:39] + wire _T_699 = timer_int_ready & _T_698; // @[el2_dec_tlu_ctl.scala 848:37] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[el2_dec_tlu_ctl.scala 800:103] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[el2_dec_tlu_ctl.scala 800:101] + wire _T_700 = ~ext_int_ready; // @[el2_dec_tlu_ctl.scala 848:57] + wire _T_701 = _T_699 & _T_700; // @[el2_dec_tlu_ctl.scala 848:55] + wire _T_622 = _T_632 & mip[5]; // @[el2_dec_tlu_ctl.scala 801:64] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[el2_dec_tlu_ctl.scala 801:82] + wire _T_702 = ~ce_int_ready; // @[el2_dec_tlu_ctl.scala 848:74] + wire _T_703 = _T_701 & _T_702; // @[el2_dec_tlu_ctl.scala 848:72] + wire _T_152 = ~debug_mode_status; // @[el2_dec_tlu_ctl.scala 503:31] + reg dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 546:81] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[el2_dec_tlu_ctl.scala 480:42] + reg ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 827:58] + wire _T_107 = ~ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 480:65] + wire dbg_halt_req_final = _T_106 & _T_107; // @[el2_dec_tlu_ctl.scala 480:63] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[el2_dec_tlu_ctl.scala 439:61] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 483:44] + reg reset_detect; // @[el2_dec_tlu_ctl.scala 416:80] + reg reset_detected; // @[el2_dec_tlu_ctl.scala 417:80] + wire reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 418:64] + wire _T_110 = ~io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 483:89] + wire _T_111 = reset_delayed & _T_110; // @[el2_dec_tlu_ctl.scala 483:87] + wire _T_112 = _T_109 | _T_111; // @[el2_dec_tlu_ctl.scala 483:70] + wire _T_114 = _T_112 & _T_152; // @[el2_dec_tlu_ctl.scala 483:113] + wire debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 483:141] + wire _T_153 = _T_152 & debug_halt_req; // @[el2_dec_tlu_ctl.scala 503:57] + reg dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 538:81] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 503:75] + reg trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 537:81] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 503:101] + reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] + reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 342:57 el2_dec_tlu_ctl.scala 1080:31] + reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] + wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] + reg ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 532:73] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 497:89] + wire _T_145 = ~debug_halt_req; // @[el2_dec_tlu_ctl.scala 497:115] + wire _T_146 = _T_144 & _T_145; // @[el2_dec_tlu_ctl.scala 497:113] + reg debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 539:81] + wire _T_147 = ~debug_halt_req_d1; // @[el2_dec_tlu_ctl.scala 497:133] + wire _T_148 = _T_146 & _T_147; // @[el2_dec_tlu_ctl.scala 497:131] + wire _T_149 = ~io_dec_div_active; // @[el2_dec_tlu_ctl.scala 497:154] + wire _T_150 = _T_148 & _T_149; // @[el2_dec_tlu_ctl.scala 497:152] + wire core_empty = force_halt | _T_150; // @[el2_dec_tlu_ctl.scala 497:28] + wire _T_163 = debug_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 513:42] + reg dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 529:73] + reg dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 545:73] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[el2_dec_tlu_ctl.scala 493:50] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[el2_dec_tlu_ctl.scala 493:48] + reg take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 824:58] + wire _T_134 = ~take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 493:78] + wire _T_135 = _T_133 & _T_134; // @[el2_dec_tlu_ctl.scala 493:76] + reg halt_taken_f; // @[el2_dec_tlu_ctl.scala 530:81] + reg dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 533:81] + wire _T_136 = ~dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:120] + wire _T_137 = halt_taken_f & _T_136; // @[el2_dec_tlu_ctl.scala 493:118] + reg pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 659:73] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 493:140] + wire _T_139 = _T_137 & _T_138; // @[el2_dec_tlu_ctl.scala 493:138] + reg interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 888:82] + wire _T_140 = ~interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 493:163] + wire _T_141 = _T_139 & _T_140; // @[el2_dec_tlu_ctl.scala 493:161] + wire halt_taken = _T_135 | _T_141; // @[el2_dec_tlu_ctl.scala 493:102] + wire _T_164 = _T_163 & halt_taken; // @[el2_dec_tlu_ctl.scala 513:55] + reg debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 536:81] + wire _T_165 = ~debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 513:91] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[el2_dec_tlu_ctl.scala 513:89] + wire dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 513:69] + wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] + wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 348:41 el2_dec_tlu_ctl.scala 1086:31] + wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] + wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] + wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] + wire _T_160 = debug_mode_status & _T_159; // @[el2_dec_tlu_ctl.scala 506:75] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 506:47] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[el2_dec_tlu_ctl.scala 519:54] + reg dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 544:73] + wire _T_178 = ~dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 519:105] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[el2_dec_tlu_ctl.scala 519:103] + wire dcsr_single_step_running = _T_177 | _T_179; // @[el2_dec_tlu_ctl.scala 519:73] + wire _T_665 = ~dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 820:54] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 820:80] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[el2_dec_tlu_ctl.scala 820:51] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[el2_dec_tlu_ctl.scala 649:56] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 346:41 el2_dec_tlu_ctl.scala 1084:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] + reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] + wire _T_372 = _T_371 & halt_taken; // @[el2_dec_tlu_ctl.scala 671:57] + wire _T_373 = ~enter_debug_halt_req; // @[el2_dec_tlu_ctl.scala 671:72] + wire _T_374 = _T_372 & _T_373; // @[el2_dec_tlu_ctl.scala 671:70] + wire _T_375 = ~i_cpu_run_req_d1; // @[el2_dec_tlu_ctl.scala 671:120] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[el2_dec_tlu_ctl.scala 671:118] + wire _T_377 = _T_374 | _T_376; // @[el2_dec_tlu_ctl.scala 671:95] + wire _T_378 = ~debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 671:142] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[el2_dec_tlu_ctl.scala 671:140] + wire _T_361 = ~pmu_fw_tlu_halted; // @[el2_dec_tlu_ctl.scala 667:71] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[el2_dec_tlu_ctl.scala 667:69] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[el2_dec_tlu_ctl.scala 667:48] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[el2_dec_tlu_ctl.scala 667:92] + reg internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 657:66] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[el2_dec_tlu_ctl.scala 668:82] + wire _T_369 = _T_367 & _T_378; // @[el2_dec_tlu_ctl.scala 668:102] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[el2_dec_tlu_ctl.scala 668:51] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 820:106] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[el2_dec_tlu_ctl.scala 820:134] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[el2_dec_tlu_ctl.scala 852:34] + wire _T_739 = nmi_int_detected & _T_738; // @[el2_dec_tlu_ctl.scala 852:32] + wire _T_740 = ~internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 852:64] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[el2_dec_tlu_ctl.scala 852:118] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 852:140] + wire _T_744 = _T_742 & _T_743; // @[el2_dec_tlu_ctl.scala 852:138] + wire _T_746 = _T_744 & _T_178; // @[el2_dec_tlu_ctl.scala 852:163] + wire _T_747 = _T_740 | _T_746; // @[el2_dec_tlu_ctl.scala 852:88] + wire _T_748 = _T_739 & _T_747; // @[el2_dec_tlu_ctl.scala 852:61] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[el2_dec_tlu_ctl.scala 738:51] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 738:64] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 600:57] + wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_300 = ~_T_299; // @[el2_dec_tlu_ctl.scala 600:22] + wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[el2_dec_tlu_ctl.scala 598:52] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[el2_dec_tlu_ctl.scala 236:59 el2_dec_tlu_ctl.scala 1089:33] + wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] + wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[el2_dec_tlu_ctl.scala 590:56] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 746:48] + wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_282 = _T_279 & _T_281; // @[el2_dec_tlu_ctl.scala 590:71] + wire _T_283 = io_exu_i0_br_error_r | io_exu_i0_br_start_error_r; // @[el2_dec_tlu_ctl.scala 590:128] + wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_286 = _T_282 | _T_285; // @[el2_dec_tlu_ctl.scala 590:97] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[el2_dec_tlu_ctl.scala 590:37] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:89] + wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[el2_dec_tlu_ctl.scala 593:50] + wire [3:0] _T_289 = io_lsu_error_pkt_r_exc_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 347:41 el2_dec_tlu_ctl.scala 1085:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 587:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 587:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 587:352] + wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[el2_dec_tlu_ctl.scala 598:145] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[el2_dec_tlu_ctl.scala 600:83] + wire _T_303 = ~mtdata1_t_2[5]; // @[el2_dec_tlu_ctl.scala 603:59] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[el2_dec_tlu_ctl.scala 603:88] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[el2_dec_tlu_ctl.scala 603:56] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[el2_dec_tlu_ctl.scala 603:156] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[el2_dec_tlu_ctl.scala 603:124] + wire _T_315 = ~mtdata1_t_0[5]; // @[el2_dec_tlu_ctl.scala 603:195] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[el2_dec_tlu_ctl.scala 603:224] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[el2_dec_tlu_ctl.scala 603:192] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[el2_dec_tlu_ctl.scala 603:292] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[el2_dec_tlu_ctl.scala 603:260] + wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 606:56] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 738:90] + wire _T_466 = _T_464 & _T_465; // @[el2_dec_tlu_ctl.scala 738:88] + wire _T_468 = ~dcsr[15]; // @[el2_dec_tlu_ctl.scala 738:110] + wire _T_469 = _T_466 & _T_468; // @[el2_dec_tlu_ctl.scala 738:108] + reg tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 408:72] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 713:43] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[el2_dec_tlu_ctl.scala 713:41] + wire _T_432 = _T_430 & _T_283; // @[el2_dec_tlu_ctl.scala 713:65] + reg ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 402:81] + reg iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 403:89] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 713:137] + wire _T_435 = _T_433 & _T_107; // @[el2_dec_tlu_ctl.scala 713:156] + wire _T_436 = _T_432 | _T_435; // @[el2_dec_tlu_ctl.scala 713:120] + wire _T_438 = _T_436 & _T_465; // @[el2_dec_tlu_ctl.scala 713:179] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[el2_dec_tlu_ctl.scala 701:46] + wire _T_411 = ~io_lsu_error_pkt_r_inst_type; // @[el2_dec_tlu_ctl.scala 701:69] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_single_ecc_error; // @[el2_dec_tlu_ctl.scala 701:99] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[el2_dec_tlu_ctl.scala 701:66] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 713:203] + wire rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 713:200] + wire _T_470 = ~rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 738:132] + wire ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 738:130] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[el2_dec_tlu_ctl.scala 739:51] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 739:64] + wire _T_475 = _T_473 & _T_465; // @[el2_dec_tlu_ctl.scala 739:88] + wire ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 739:108] + wire _T_523 = ebreak_r | ecall_r; // @[el2_dec_tlu_ctl.scala 766:40] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[el2_dec_tlu_ctl.scala 740:17] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 740:46] + wire _T_481 = _T_479 & _T_465; // @[el2_dec_tlu_ctl.scala 740:70] + wire illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 740:90] + wire _T_524 = _T_523 | illegal_r; // @[el2_dec_tlu_ctl.scala 766:50] + wire _T_511 = inst_acc_r_raw & _T_470; // @[el2_dec_tlu_ctl.scala 747:32] + wire inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 747:45] + wire _T_525 = _T_524 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 766:62] + wire _T_527 = _T_525 & _T_470; // @[el2_dec_tlu_ctl.scala 766:76] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 766:91] + wire i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 766:89] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 865:48] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_tlu_ctl.scala 689:60] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_exc_valid & _T_402; // @[el2_dec_tlu_ctl.scala 689:58] + wire _T_403 = io_lsu_error_pkt_r_exc_valid & lsu_exc_valid_r_raw; // @[el2_dec_tlu_ctl.scala 691:39] + wire _T_405 = _T_403 & _T_465; // @[el2_dec_tlu_ctl.scala 691:61] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 691:81] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 865:60] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 743:49] + wire _T_492 = _T_490 & _T_465; // @[el2_dec_tlu_ctl.scala 743:73] + wire fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 743:94] + wire _T_791 = _T_790 | fence_i_r; // @[el2_dec_tlu_ctl.scala 865:78] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[el2_dec_tlu_ctl.scala 865:90] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[el2_dec_tlu_ctl.scala 704:49] + wire _T_415 = ~lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 704:64] + wire _T_416 = _T_414 & _T_415; // @[el2_dec_tlu_ctl.scala 704:62] + wire _T_417 = ~inst_acc_r; // @[el2_dec_tlu_ctl.scala 704:81] + wire _T_418 = _T_416 & _T_417; // @[el2_dec_tlu_ctl.scala 704:78] + wire _T_420 = _T_418 & _T_528; // @[el2_dec_tlu_ctl.scala 704:93] + reg request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 542:81] + wire _T_421 = ~request_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 704:120] + wire _T_422 = _T_420 & _T_421; // @[el2_dec_tlu_ctl.scala 704:118] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 704:145] + reg iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 401:72] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[el2_dec_tlu_ctl.scala 722:51] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[el2_dec_tlu_ctl.scala 741:51] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 741:64] + wire _T_487 = _T_485 & _T_465; // @[el2_dec_tlu_ctl.scala 741:88] + wire mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 741:108] + wire _T_446 = _T_523 | mret_r; // @[el2_dec_tlu_ctl.scala 722:97] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 851:31] + wire _T_447 = _T_446 | take_reset; // @[el2_dec_tlu_ctl.scala 722:106] + wire _T_448 = _T_447 | illegal_r; // @[el2_dec_tlu_ctl.scala 722:119] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[el2_dec_tlu_ctl.scala 722:175] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[el2_dec_tlu_ctl.scala 722:152] + wire _T_451 = _T_448 | _T_450; // @[el2_dec_tlu_ctl.scala 722:131] + wire _T_452 = ~_T_451; // @[el2_dec_tlu_ctl.scala 722:76] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[el2_dec_tlu_ctl.scala 722:74] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 865:107] + wire _T_794 = _T_793 | debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 865:134] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 863:42] + wire _T_211 = ~io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 562:22] + reg dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 541:73] + wire _T_212 = _T_211 & dec_pause_state_f; // @[el2_dec_tlu_ctl.scala 562:42] + wire _T_213 = ext_int_ready | ce_int_ready; // @[el2_dec_tlu_ctl.scala 562:80] + wire _T_214 = _T_213 | timer_int_ready; // @[el2_dec_tlu_ctl.scala 562:95] + wire _T_215 = _T_214 | soft_int_ready; // @[el2_dec_tlu_ctl.scala 562:113] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:130] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 562:154] + wire _T_218 = _T_217 | nmi_int_detected; // @[el2_dec_tlu_ctl.scala 562:178] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 562:197] + wire _T_220 = ~_T_219; // @[el2_dec_tlu_ctl.scala 562:64] + wire _T_221 = _T_212 & _T_220; // @[el2_dec_tlu_ctl.scala 562:62] + wire _T_223 = _T_221 & _T_140; // @[el2_dec_tlu_ctl.scala 562:218] + wire _T_225 = _T_223 & _T_378; // @[el2_dec_tlu_ctl.scala 562:242] + wire _T_226 = ~pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 562:264] + wire _T_227 = _T_225 & _T_226; // @[el2_dec_tlu_ctl.scala 562:262] + wire _T_228 = ~halt_taken_f; // @[el2_dec_tlu_ctl.scala 562:285] + wire pause_expired_r = _T_227 & _T_228; // @[el2_dec_tlu_ctl.scala 562:283] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 863:65] + wire _T_795 = _T_794 | sel_npc_resume; // @[el2_dec_tlu_ctl.scala 865:156] + reg dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 540:73] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[el2_dec_tlu_ctl.scala 865:174] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 865:200] + wire _T_749 = ~synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 852:194] + wire _T_750 = _T_748 & _T_749; // @[el2_dec_tlu_ctl.scala 852:192] + wire _T_751 = ~mret_r; // @[el2_dec_tlu_ctl.scala 852:217] + wire _T_752 = _T_750 & _T_751; // @[el2_dec_tlu_ctl.scala 852:215] + wire _T_753 = ~take_reset; // @[el2_dec_tlu_ctl.scala 852:227] + wire _T_754 = _T_752 & _T_753; // @[el2_dec_tlu_ctl.scala 852:225] + wire _T_519 = _T_466 & dcsr[15]; // @[el2_dec_tlu_ctl.scala 750:120] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 750:141] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 852:241] + wire _T_756 = _T_754 & _T_755; // @[el2_dec_tlu_ctl.scala 852:239] + wire _T_760 = _T_107 | _T_44; // @[el2_dec_tlu_ctl.scala 852:287] + wire take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 852:265] + wire _T_670 = _T_669 | take_nmi; // @[el2_dec_tlu_ctl.scala 820:154] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 820:165] + wire _T_672 = _T_671 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 820:190] + reg exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 890:82] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 820:213] + wire _T_674 = _T_673 | mret_r; // @[el2_dec_tlu_ctl.scala 820:237] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 820:246] + wire _T_704 = ~block_interrupts; // @[el2_dec_tlu_ctl.scala 848:90] + wire take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 848:88] + wire _T_762 = take_ext_int | take_timer_int; // @[el2_dec_tlu_ctl.scala 855:37] + wire _T_693 = soft_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 847:35] + wire _T_695 = _T_693 & _T_702; // @[el2_dec_tlu_ctl.scala 847:52] + wire take_soft_int = _T_695 & _T_704; // @[el2_dec_tlu_ctl.scala 847:68] + wire _T_763 = _T_762 | take_soft_int; // @[el2_dec_tlu_ctl.scala 855:54] + wire _T_764 = _T_763 | take_nmi; // @[el2_dec_tlu_ctl.scala 855:70] + wire _T_689 = ce_int_ready & _T_700; // @[el2_dec_tlu_ctl.scala 846:32] + wire take_ce_int = _T_689 & _T_704; // @[el2_dec_tlu_ctl.scala 846:49] + wire _T_765 = _T_764 | take_ce_int; // @[el2_dec_tlu_ctl.scala 855:81] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[el2_dec_tlu_ctl.scala 806:48] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 807:46] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 849:48] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[el2_dec_tlu_ctl.scala 849:73] + wire _T_709 = _T_707 & _T_631; // @[el2_dec_tlu_ctl.scala 849:99] + wire _T_710 = ~timer_int_ready; // @[el2_dec_tlu_ctl.scala 849:128] + wire _T_711 = _T_709 & _T_710; // @[el2_dec_tlu_ctl.scala 849:126] + wire _T_713 = _T_711 & _T_698; // @[el2_dec_tlu_ctl.scala 849:145] + wire _T_715 = _T_713 & _T_700; // @[el2_dec_tlu_ctl.scala 849:163] + wire _T_717 = _T_715 & _T_702; // @[el2_dec_tlu_ctl.scala 849:180] + wire take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 849:196] + wire _T_766 = _T_765 | take_int_timer0_int; // @[el2_dec_tlu_ctl.scala 855:95] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[el2_dec_tlu_ctl.scala 808:48] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 809:46] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 850:48] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[el2_dec_tlu_ctl.scala 850:73] + wire _T_723 = _T_721 & _T_631; // @[el2_dec_tlu_ctl.scala 850:99] + wire _T_725 = ~_T_706; // @[el2_dec_tlu_ctl.scala 850:128] + wire _T_726 = _T_723 & _T_725; // @[el2_dec_tlu_ctl.scala 850:126] + wire _T_728 = _T_726 & _T_710; // @[el2_dec_tlu_ctl.scala 850:176] + wire _T_730 = _T_728 & _T_698; // @[el2_dec_tlu_ctl.scala 850:195] + wire _T_732 = _T_730 & _T_700; // @[el2_dec_tlu_ctl.scala 850:213] + wire _T_734 = _T_732 & _T_702; // @[el2_dec_tlu_ctl.scala 850:230] + wire take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 850:246] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 855:117] + wire _T_15 = _T_14 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 396:68] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 396:88] + wire _T_17 = _T_16 | reset_delayed; // @[el2_dec_tlu_ctl.scala 396:111] + wire _T_18 = _T_17 | pause_expired_r; // @[el2_dec_tlu_ctl.scala 396:127] + reg pause_expired_wb; // @[el2_dec_tlu_ctl.scala 895:90] + wire _T_19 = _T_18 | pause_expired_wb; // @[el2_dec_tlu_ctl.scala 396:145] + wire _T_496 = io_ifu_ic_error_start & _T_107; // @[el2_dec_tlu_ctl.scala 744:42] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 744:92] + wire _T_499 = _T_496 & _T_498; // @[el2_dec_tlu_ctl.scala 744:63] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[el2_dec_tlu_ctl.scala 744:122] + wire ic_perr_r = _T_499 & _T_500; // @[el2_dec_tlu_ctl.scala 744:120] + wire _T_20 = _T_19 | ic_perr_r; // @[el2_dec_tlu_ctl.scala 396:164] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 396:176] + wire _T_503 = io_ifu_iccm_rd_ecc_single_err & _T_107; // @[el2_dec_tlu_ctl.scala 745:50] + wire _T_506 = _T_503 & _T_498; // @[el2_dec_tlu_ctl.scala 745:71] + wire iccm_sbecc_r = _T_506 & _T_500; // @[el2_dec_tlu_ctl.scala 745:128] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[el2_dec_tlu_ctl.scala 396:191] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 396:206] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 396:224] + reg lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 406:72] + reg lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 407:64] + reg _T_32; // @[el2_dec_tlu_ctl.scala 409:65] + reg internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 410:64] + reg _T_33; // @[el2_dec_tlu_ctl.scala 411:73] + reg nmi_lsu_load_type_f; // @[el2_dec_tlu_ctl.scala 422:72] + reg nmi_lsu_store_type_f; // @[el2_dec_tlu_ctl.scala 423:64] + wire _T_46 = nmi_lsu_detected & io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 431:42] + wire _T_49 = ~_T_41; // @[el2_dec_tlu_ctl.scala 431:78] + wire _T_50 = _T_46 & _T_49; // @[el2_dec_tlu_ctl.scala 431:76] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 431:141] + wire _T_54 = nmi_lsu_detected & io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 432:43] + wire _T_58 = _T_54 & _T_49; // @[el2_dec_tlu_ctl.scala 432:78] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[el2_dec_tlu_ctl.scala 432:144] + reg mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 440:64] + reg mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 441:64] + reg mpc_run_state_f; // @[el2_dec_tlu_ctl.scala 443:80] + reg debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 444:72] + reg mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 445:72] + reg mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 446:80] + reg dbg_run_state_f; // @[el2_dec_tlu_ctl.scala 448:80] + reg _T_65; // @[el2_dec_tlu_ctl.scala 449:73] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[el2_dec_tlu_ctl.scala 453:65] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[el2_dec_tlu_ctl.scala 453:63] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[el2_dec_tlu_ctl.scala 454:64] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[el2_dec_tlu_ctl.scala 454:62] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[el2_dec_tlu_ctl.scala 456:42] + wire _T_71 = _T_68 | _T_111; // @[el2_dec_tlu_ctl.scala 456:74] + wire _T_72 = ~mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 456:119] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[el2_dec_tlu_ctl.scala 456:117] + wire _T_74 = ~mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 457:74] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[el2_dec_tlu_ctl.scala 457:72] + wire _T_76 = mpc_run_state_f | _T_75; // @[el2_dec_tlu_ctl.scala 457:40] + wire _T_77 = ~dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 457:127] + wire _T_78 = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 457:125] + wire mpc_run_state_ns = _T_76 & _T_78; // @[el2_dec_tlu_ctl.scala 457:97] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 459:64] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 459:90] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 459:115] + wire _T_83 = dbg_halt_state_f | _T_82; // @[el2_dec_tlu_ctl.scala 459:42] + wire _T_84 = ~io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 459:147] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[el2_dec_tlu_ctl.scala 459:145] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[el2_dec_tlu_ctl.scala 460:40] + wire dbg_run_state_ns = _T_86 & _T_78; // @[el2_dec_tlu_ctl.scala 460:61] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 466:53] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 467:47] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[el2_dec_tlu_ctl.scala 467:97] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[el2_dec_tlu_ctl.scala 470:45] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 470:72] + wire _T_99 = ~dbg_halt_state_ns; // @[el2_dec_tlu_ctl.scala 471:53] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[el2_dec_tlu_ctl.scala 471:51] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[el2_dec_tlu_ctl.scala 471:74] + wire _T_102 = _T_100 & _T_101; // @[el2_dec_tlu_ctl.scala 471:72] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[el2_dec_tlu_ctl.scala 471:123] + wire _T_118 = mpc_run_state_ns & _T_99; // @[el2_dec_tlu_ctl.scala 485:67] + wire _T_119 = ~mpc_halt_state_ns; // @[el2_dec_tlu_ctl.scala 485:111] + wire _T_120 = dbg_run_state_ns & _T_119; // @[el2_dec_tlu_ctl.scala 485:109] + wire _T_121 = _T_118 | _T_120; // @[el2_dec_tlu_ctl.scala 485:89] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 490:37] + wire _T_124 = _T_122 & _T_749; // @[el2_dec_tlu_ctl.scala 490:58] + wire _T_126 = _T_124 & _T_751; // @[el2_dec_tlu_ctl.scala 490:81] + wire _T_128 = _T_126 & _T_228; // @[el2_dec_tlu_ctl.scala 490:91] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 490:109] + wire _T_130 = _T_128 & _T_129; // @[el2_dec_tlu_ctl.scala 490:107] + wire take_halt = _T_130 & _T_753; // @[el2_dec_tlu_ctl.scala 490:137] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 515:43] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[el2_dec_tlu_ctl.scala 517:53] + wire _T_174 = _T_172 & dcsr[2]; // @[el2_dec_tlu_ctl.scala 517:78] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[el2_dec_tlu_ctl.scala 612:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[el2_dec_tlu_ctl.scala 612:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[el2_dec_tlu_ctl.scala 612:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[el2_dec_tlu_ctl.scala 612:241] + wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[el2_dec_tlu_ctl.scala 618:56] + wire i0_trigger_action_r = |_T_343; // @[el2_dec_tlu_ctl.scala 618:74] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[el2_dec_tlu_ctl.scala 620:44] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[el2_dec_tlu_ctl.scala 524:51] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[el2_dec_tlu_ctl.scala 524:104] + reg request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 543:73] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[el2_dec_tlu_ctl.scala 526:58] + reg _T_190; // @[el2_dec_tlu_ctl.scala 534:73] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[el2_dec_tlu_ctl.scala 555:56] + wire _T_202 = take_halt | _T_201; // @[el2_dec_tlu_ctl.scala 555:43] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[el2_dec_tlu_ctl.scala 555:82] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 555:129] + wire _T_205 = _T_203 | _T_204; // @[el2_dec_tlu_ctl.scala 555:109] + wire take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 828:41] + wire _T_207 = ~interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 560:55] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 560:53] + wire _T_209 = ~take_ext_int_start; // @[el2_dec_tlu_ctl.scala 560:76] + wire _T_231 = io_dec_tlu_flush_lower_r & dcsr[2]; // @[el2_dec_tlu_ctl.scala 564:60] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[el2_dec_tlu_ctl.scala 564:103] + wire _T_233 = _T_231 & _T_232; // @[el2_dec_tlu_ctl.scala 564:78] + wire _T_234 = ~io_dec_tlu_flush_noredir_r; // @[el2_dec_tlu_ctl.scala 564:133] + wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire _T_345 = ~trigger_hit_dmode_r; // @[el2_dec_tlu_ctl.scala 622:54] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 622:52] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 650:52] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 650:77] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[el2_dec_tlu_ctl.scala 650:99] + reg _T_353; // @[el2_dec_tlu_ctl.scala 654:73] + reg _T_354; // @[el2_dec_tlu_ctl.scala 655:81] + reg _T_355; // @[el2_dec_tlu_ctl.scala 656:81] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[el2_dec_tlu_ctl.scala 674:88] + wire _T_386 = _T_384 & _T_152; // @[el2_dec_tlu_ctl.scala 674:108] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:40] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[el2_dec_tlu_ctl.scala 675:87] + reg lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 687:64] + reg lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 694:73] + wire _T_408 = ~io_lsu_error_pkt_r_exc_type; // @[el2_dec_tlu_ctl.scala 695:39] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[el2_dec_tlu_ctl.scala 695:37] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_exc_type; // @[el2_dec_tlu_ctl.scala 696:37] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_inst_type; // @[el2_dec_tlu_ctl.scala 697:37] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 707:37] + wire _T_425 = _T_424 | inst_acc_r; // @[el2_dec_tlu_ctl.scala 707:52] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 707:78] + wire _T_427 = _T_425 | _T_426; // @[el2_dec_tlu_ctl.scala 707:65] + wire _T_441 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_tlu_ctl.scala 716:69] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[el2_dec_tlu_ctl.scala 716:67] + wire _T_453 = io_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 725:50] + wire _T_455 = io_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 726:62] + wire _T_457 = io_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 727:46] + wire _T_459 = _T_457 & _T_429; // @[el2_dec_tlu_ctl.scala 727:70] + wire _T_460 = ~io_exu_i0_br_mp_r; // @[el2_dec_tlu_ctl.scala 727:97] + wire _T_461 = ~io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 727:118] + wire _T_462 = _T_460 | _T_461; // @[el2_dec_tlu_ctl.scala 727:116] + wire _T_529 = ~take_nmi; // @[el2_dec_tlu_ctl.scala 775:21] + wire _T_530 = take_ext_int & _T_529; // @[el2_dec_tlu_ctl.scala 775:19] + wire _T_533 = take_timer_int & _T_529; // @[el2_dec_tlu_ctl.scala 776:21] + wire _T_536 = take_soft_int & _T_529; // @[el2_dec_tlu_ctl.scala 777:20] + wire _T_539 = take_int_timer0_int & _T_529; // @[el2_dec_tlu_ctl.scala 778:26] + wire _T_542 = take_int_timer1_int & _T_529; // @[el2_dec_tlu_ctl.scala 779:26] + wire _T_545 = take_ce_int & _T_529; // @[el2_dec_tlu_ctl.scala 780:18] + wire _T_548 = illegal_r & _T_529; // @[el2_dec_tlu_ctl.scala 781:16] + wire _T_551 = ecall_r & _T_529; // @[el2_dec_tlu_ctl.scala 782:15] + wire _T_554 = inst_acc_r & _T_529; // @[el2_dec_tlu_ctl.scala 783:18] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 784:16] + wire _T_558 = _T_556 & _T_529; // @[el2_dec_tlu_ctl.scala 784:36] + wire _T_560 = ~lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 785:21] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[el2_dec_tlu_ctl.scala 785:19] + wire _T_563 = _T_561 & _T_529; // @[el2_dec_tlu_ctl.scala 785:35] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[el2_dec_tlu_ctl.scala 786:20] + wire _T_568 = _T_566 & _T_529; // @[el2_dec_tlu_ctl.scala 786:36] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 787:19] + wire _T_572 = _T_570 & _T_529; // @[el2_dec_tlu_ctl.scala 787:34] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[el2_dec_tlu_ctl.scala 788:20] + wire _T_576 = _T_574 & _T_529; // @[el2_dec_tlu_ctl.scala 788:35] + wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_581 = _T_539 ? 5'h1d : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_582 = _T_542 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_583 = _T_545 ? 5'h1e : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_584 = _T_548 ? 5'h2 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_585 = _T_551 ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_586 = _T_554 ? 5'h1 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_587 = _T_558 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_588 = _T_563 ? 5'h4 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_589 = _T_568 ? 5'h5 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_590 = _T_572 ? 5'h6 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_591 = _T_576 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_592 = _T_578 | _T_579; // @[Mux.scala 27:72] + wire [4:0] _T_593 = _T_592 | _T_580; // @[Mux.scala 27:72] + wire [4:0] _T_594 = _T_593 | _T_581; // @[Mux.scala 27:72] + wire [4:0] _T_595 = _T_594 | _T_582; // @[Mux.scala 27:72] + wire [4:0] _T_596 = _T_595 | _T_583; // @[Mux.scala 27:72] + wire [4:0] _T_597 = _T_596 | _T_584; // @[Mux.scala 27:72] + wire [4:0] _T_598 = _T_597 | _T_585; // @[Mux.scala 27:72] + wire [4:0] _T_599 = _T_598 | _T_586; // @[Mux.scala 27:72] + wire [4:0] _T_600 = _T_599 | _T_587; // @[Mux.scala 27:72] + wire [4:0] _T_601 = _T_600 | _T_588; // @[Mux.scala 27:72] + wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] + wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] + wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 813:51] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 813:73] + wire int_timer_stalled = _T_642 | mret_r; // @[el2_dec_tlu_ctl.scala 813:97] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[el2_dec_tlu_ctl.scala 815:71] + wire _T_644 = int_timer0_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 815:48] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[el2_dec_tlu_ctl.scala 815:120] + wire _T_647 = _T_645 & _T_207; // @[el2_dec_tlu_ctl.scala 815:144] + wire _T_649 = _T_647 & _T_209; // @[el2_dec_tlu_ctl.scala 815:165] + wire _T_651 = _T_649 & _T_152; // @[el2_dec_tlu_ctl.scala 815:187] + wire _T_654 = int_timer1_int_ready & _T_643; // @[el2_dec_tlu_ctl.scala 816:48] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[el2_dec_tlu_ctl.scala 816:120] + wire _T_657 = _T_655 & _T_207; // @[el2_dec_tlu_ctl.scala 816:144] + wire _T_659 = _T_657 & _T_209; // @[el2_dec_tlu_ctl.scala 816:165] + wire _T_661 = _T_659 & _T_152; // @[el2_dec_tlu_ctl.scala 816:187] + reg take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 825:58] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[el2_dec_tlu_ctl.scala 830:42] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 349:41 el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[el2_dec_tlu_ctl.scala 861:60] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[el2_dec_tlu_ctl.scala 861:27] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[el2_dec_tlu_ctl.scala 862:35] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[el2_dec_tlu_ctl.scala 862:47] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[el2_dec_tlu_ctl.scala 862:93] + wire _T_783 = _T_780 | _T_782; // @[el2_dec_tlu_ctl.scala 862:73] + wire _T_785 = rfpc_i0_r & _T_743; // @[el2_dec_tlu_ctl.scala 862:128] + wire sel_npc_r = _T_783 | _T_785; // @[el2_dec_tlu_ctl.scala 862:115] + wire _T_798 = interrupt_valid_r | mret_r; // @[el2_dec_tlu_ctl.scala 866:42] + wire _T_799 = _T_798 | synchronous_flush_r; // @[el2_dec_tlu_ctl.scala 866:51] + wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73] + wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85] + wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21] + wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39] + wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69] + wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44] + wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 873:46] + wire _T_823 = _T_821 & _T_207; // @[el2_dec_tlu_ctl.scala 873:91] + wire _T_825 = _T_823 & _T_816; // @[el2_dec_tlu_ctl.scala 873:112] + wire _T_830 = _T_529 & mret_r; // @[el2_dec_tlu_ctl.scala 874:16] + wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] + wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] + wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 343:41 el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] + wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] + wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72] + wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72] + wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] + wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] + wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] + reg [30:0] tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 879:58] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[el2_dec_tlu_ctl.scala 886:44] + wire _T_855 = _T_854 | interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 886:67] + reg i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 889:81] + reg [4:0] exc_cause_wb; // @[el2_dec_tlu_ctl.scala 891:89] + wire _T_860 = ~illegal_r; // @[el2_dec_tlu_ctl.scala 892:119] + reg i0_valid_wb; // @[el2_dec_tlu_ctl.scala 892:97] + reg trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 893:81] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1094:44] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 1094:69] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1099:57] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[el2_dec_tlu_ctl.scala 1099:75] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1099:94] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1099:117] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1099:138] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1099:160] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[el2_dec_tlu_ctl.scala 1099:181] + wire _T_881 = ~_T_880; // @[el2_dec_tlu_ctl.scala 1099:38] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1099:203] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_883 = csr_pkt_legal & _T_882; // @[el2_dec_tlu_ctl.scala 1099:35] + wire _T_884 = ~fast_int_meicpct; // @[el2_dec_tlu_ctl.scala 1099:225] + wire valid_csr = _T_883 & _T_884; // @[el2_dec_tlu_ctl.scala 1099:223] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[el2_dec_tlu_ctl.scala 1101:48] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1101:109] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1101:131] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1101:152] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1101:174] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1101:195] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[el2_dec_tlu_ctl.scala 1101:84] + wire _T_894 = ~_T_893; // @[el2_dec_tlu_ctl.scala 1101:61] + el2_dec_timer_ctl int_timers ( // @[el2_dec_tlu_ctl.scala 355:24] + .clock(int_timers_clock), + .reset(int_timers_reset), + .io_free_clk(int_timers_io_free_clk), + .io_scan_mode(int_timers_io_scan_mode), + .io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r), + .io_csr_mitctl0(int_timers_io_csr_mitctl0), + .io_csr_mitctl1(int_timers_io_csr_mitctl1), + .io_csr_mitb0(int_timers_io_csr_mitb0), + .io_csr_mitb1(int_timers_io_csr_mitb1), + .io_csr_mitcnt0(int_timers_io_csr_mitcnt0), + .io_csr_mitcnt1(int_timers_io_csr_mitcnt1), + .io_dec_pause_state(int_timers_io_dec_pause_state), + .io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted), + .io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers), + .io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d), + .io_dec_timer_read_d(int_timers_io_dec_timer_read_d), + .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) + ); + rvclkhdr rvclkhdr ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 474:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + csr_tlu csr ( // @[el2_dec_tlu_ctl.scala 897:17] + .clock(csr_clock), + .reset(csr_reset), + .io_free_clk(csr_io_free_clk), + .io_active_clk(csr_io_active_clk), + .io_scan_mode(csr_io_scan_mode), + .io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r), + .io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r), + .io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d), + .io_dec_i0_decode_d(csr_io_dec_i0_decode_d), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), + .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_(csr_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_(csr_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_(csr_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_(csr_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2), + .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn), + .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any), + .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any), + .io_lsu_store_stall_any(csr_io_lsu_store_stall_any), + .io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall), + .io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall), + .io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall), + .io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp), + .io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded), + .io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned), + .io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4), + .io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit), + .io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1), + .io_dec_csr_wen_r(csr_io_dec_csr_wen_r), + .io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1), + .io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1), + .io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3), + .io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted), + .io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write), + .io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read), + .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), + .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), + .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), + .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), + .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), + .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), + .io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d), + .io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable), + .io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r), + .io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn), + .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data), + .io_dec_tlu_meipt(csr_io_dec_tlu_meipt), + .io_pic_pl(csr_io_pic_pl), + .io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl), + .io_dec_tlu_meihap(csr_io_dec_tlu_meihap), + .io_pic_claimid(csr_io_pic_claimid), + .io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error), + .io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any), + .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), + .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), + .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty), + .io_dec_illegal_inst(csr_io_dec_illegal_inst), + .io_lsu_error_pkt_r_mscause(csr_io_lsu_error_pkt_r_mscause), + .io_mexintpend(csr_io_mexintpend), + .io_exu_npc_r(csr_io_exu_npc_r), + .io_mpc_reset_run_req(csr_io_mpc_reset_run_req), + .io_rst_vec(csr_io_rst_vec), + .io_core_id(csr_io_core_id), + .io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d), + .io_dec_timer_read_d(csr_io_dec_timer_read_d), + .io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod), + .io_rfpc_i0_r(csr_io_rfpc_i0_r), + .io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r), + .io_fw_halt_req(csr_io_fw_halt_req), + .io_mstatus(csr_io_mstatus), + .io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r), + .io_mret_r(csr_io_mret_r), + .io_mstatus_mie_ns(csr_io_mstatus_mie_ns), + .io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f), + .io_dcsr(csr_io_dcsr), + .io_mtvec(csr_io_mtvec), + .io_mip(csr_io_mip), + .io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse), + .io_timer_int_sync(csr_io_timer_int_sync), + .io_soft_int_sync(csr_io_soft_int_sync), + .io_mie_ns(csr_io_mie_ns), + .io_csr_wr_clk(csr_io_csr_wr_clk), + .io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r), + .io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted), + .io_lsu_fir_error(csr_io_lsu_fir_error), + .io_npc_r(csr_io_npc_r), + .io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1), + .io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1), + .io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1), + .io_npc_r_d1(csr_io_npc_r_d1), + .io_reset_delayed(csr_io_reset_delayed), + .io_mepc(csr_io_mepc), + .io_interrupt_valid_r(csr_io_interrupt_valid_r), + .io_i0_exception_valid_r(csr_io_i0_exception_valid_r), + .io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r), + .io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r), + .io_e4e5_int_clk(csr_io_e4e5_int_clk), + .io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r), + .io_inst_acc_r(csr_io_inst_acc_r), + .io_inst_acc_second_r(csr_io_inst_acc_second_r), + .io_take_nmi(csr_io_take_nmi), + .io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r), + .io_exc_cause_r(csr_io_exc_cause_r), + .io_i0_valid_wb(csr_io_i0_valid_wb), + .io_exc_or_int_valid_r_d1(csr_io_exc_or_int_valid_r_d1), + .io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1), + .io_clk_override(csr_io_clk_override), + .io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1), + .io_lsu_i0_exc_r_d1(csr_io_lsu_i0_exc_r_d1), + .io_exc_cause_wb(csr_io_exc_cause_wb), + .io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type), + .io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type), + .io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt), + .io_ebreak_r(csr_io_ebreak_r), + .io_ecall_r(csr_io_ecall_r), + .io_illegal_r(csr_io_illegal_r), + .io_mdseac_locked_ns(csr_io_mdseac_locked_ns), + .io_mdseac_locked_f(csr_io_mdseac_locked_f), + .io_nmi_int_detected_f(csr_io_nmi_int_detected_f), + .io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2), + .io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1), + .io_ic_perr_r_d1(csr_io_ic_perr_r_d1), + .io_iccm_sbecc_r_d1(csr_io_iccm_sbecc_r_d1), + .io_lsu_single_ecc_error_r_d1(csr_io_lsu_single_ecc_error_r_d1), + .io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f), + .io_lsu_idle_any_f(csr_io_lsu_idle_any_f), + .io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f), + .io_dbg_tlu_halted(csr_io_dbg_tlu_halted), + .io_debug_halt_req_f(csr_io_debug_halt_req_f), + .io_force_halt(csr_io_force_halt), + .io_take_ext_int_start(csr_io_take_ext_int_start), + .io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1), + .io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1), + .io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f), + .io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1), + .io_debug_halt_req(csr_io_debug_halt_req), + .io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write), + .io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f), + .io_enter_debug_halt_req(csr_io_enter_debug_halt_req), + .io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode), + .io_request_debug_mode_done(csr_io_request_debug_mode_done), + .io_request_debug_mode_r(csr_io_request_debug_mode_r), + .io_dpc(csr_io_dpc), + .io_update_hit_bit_r(csr_io_update_hit_bit_r), + .io_take_timer_int(csr_io_take_timer_int), + .io_take_int_timer0_int(csr_io_take_int_timer0_int), + .io_take_int_timer1_int(csr_io_take_int_timer1_int), + .io_take_ext_int(csr_io_take_ext_int), + .io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r), + .io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r), + .io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r), + .io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1), + .io_mtdata1_t_0(csr_io_mtdata1_t_0), + .io_mtdata1_t_1(csr_io_mtdata1_t_1), + .io_mtdata1_t_2(csr_io_mtdata1_t_2), + .io_mtdata1_t_3(csr_io_mtdata1_t_3) + ); + el2_dec_decode_csr_read csr_read ( // @[el2_dec_tlu_ctl.scala 1090:22] + .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), + .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst), + .io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0), + .io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1), + .io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0), + .io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1), + .io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0), + .io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1), + .io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct), + .io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1), + .io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago), + .io_csr_pkt_presync(csr_read_io_csr_pkt_presync), + .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), + .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) + ); + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 568:23] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[el2_dec_tlu_ctl.scala 569:23] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 550:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[el2_dec_tlu_ctl.scala 551:41] + assign io_dec_tlu_resume_ack = _T_190; // @[el2_dec_tlu_ctl.scala 534:41] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 549:41] + assign io_dec_tlu_flush_noredir_r = _T_205 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 555:30] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[el2_dec_tlu_ctl.scala 449:41] + assign io_dec_tlu_flush_leak_one_r = _T_233 & _T_234; // @[el2_dec_tlu_ctl.scala 564:31] + assign io_dec_tlu_flush_err_r = io_dec_tlu_flush_lower_r & _T_433; // @[el2_dec_tlu_ctl.scala 565:26] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] + assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_ = csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_ = csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_ = csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_ = csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 961:44] + assign io_o_cpu_halt_status = _T_353; // @[el2_dec_tlu_ctl.scala 654:41] + assign io_o_cpu_halt_ack = _T_354; // @[el2_dec_tlu_ctl.scala 655:49] + assign io_o_cpu_run_ack = _T_355; // @[el2_dec_tlu_ctl.scala 656:49] + assign io_o_debug_mode_status = debug_mode_status; // @[el2_dec_tlu_ctl.scala 677:26] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[el2_dec_tlu_ctl.scala 474:25] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[el2_dec_tlu_ctl.scala 475:25] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[el2_dec_tlu_ctl.scala 476:25] + assign io_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[el2_dec_tlu_ctl.scala 955:44] + assign io_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[el2_dec_tlu_ctl.scala 957:44] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] + assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] + assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49] + assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41] + assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49] + assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] + assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[el2_dec_tlu_ctl.scala 415:33] + assign io_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 882:33] + assign io_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[el2_dec_tlu_ctl.scala 883:33] + assign io_dec_tlu_fence_i_r = _T_492 & _T_470; // @[el2_dec_tlu_ctl.scala 753:24] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[el2_dec_tlu_ctl.scala 979:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[el2_dec_tlu_ctl.scala 560:28] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[el2_dec_tlu_ctl.scala 1094:25] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 1095:25] + assign io_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[el2_dec_tlu_ctl.scala 980:40] + assign io_dec_tlu_force_halt = _T_33; // @[el2_dec_tlu_ctl.scala 411:41] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[el2_dec_tlu_ctl.scala 965:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[el2_dec_tlu_ctl.scala 966:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[el2_dec_tlu_ctl.scala 967:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[el2_dec_tlu_ctl.scala 968:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec_tlu_ctl.scala 959:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[el2_dec_tlu_ctl.scala 960:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[el2_dec_tlu_ctl.scala 958:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[el2_dec_tlu_ctl.scala 964:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[el2_dec_tlu_ctl.scala 963:40] + assign io_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 985:40] + assign io_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec_tlu_ctl.scala 983:40] + assign io_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[el2_dec_tlu_ctl.scala 984:40] + assign io_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[el2_dec_tlu_ctl.scala 982:40] + assign io_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[el2_dec_tlu_ctl.scala 981:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[el2_dec_tlu_ctl.scala 978:40] + assign io_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 986:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 969:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 970:40] + assign io_dec_tlu_ifu_clk_override = csr_io_dec_tlu_ifu_clk_override; // @[el2_dec_tlu_ctl.scala 971:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[el2_dec_tlu_ctl.scala 972:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[el2_dec_tlu_ctl.scala 973:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[el2_dec_tlu_ctl.scala 974:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[el2_dec_tlu_ctl.scala 975:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[el2_dec_tlu_ctl.scala 976:40] + assign int_timers_clock = clock; + assign int_timers_reset = reset; + assign int_timers_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 356:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 357:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 358:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 360:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 361:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[el2_dec_tlu_ctl.scala 362:49] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[el2_dec_tlu_ctl.scala 363:49] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[el2_dec_tlu_ctl.scala 364:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[el2_dec_tlu_ctl.scala 365:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[el2_dec_tlu_ctl.scala 366:49] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[el2_dec_tlu_ctl.scala 367:49] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[el2_dec_tlu_ctl.scala 368:41] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 369:41] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[el2_dec_tlu_ctl.scala 370:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 476:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 475:17] + assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[el2_lib.scala 476:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23] + assign csr_clock = clock; + assign csr_reset = reset; + assign csr_io_free_clk = io_free_clk; // @[el2_dec_tlu_ctl.scala 898:44] + assign csr_io_active_clk = io_active_clk; // @[el2_dec_tlu_ctl.scala 899:44] + assign csr_io_scan_mode = io_scan_mode; // @[el2_dec_tlu_ctl.scala 900:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[el2_dec_tlu_ctl.scala 901:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[el2_dec_tlu_ctl.scala 902:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 903:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[el2_dec_tlu_ctl.scala 904:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[el2_dec_tlu_ctl.scala 905:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 906:44] + assign csr_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 907:44] + assign csr_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec_tlu_ctl.scala 908:44] + assign csr_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec_tlu_ctl.scala 909:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec_tlu_ctl.scala 910:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[el2_dec_tlu_ctl.scala 911:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[el2_dec_tlu_ctl.scala 912:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[el2_dec_tlu_ctl.scala 913:44] + assign csr_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec_tlu_ctl.scala 914:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec_tlu_ctl.scala 915:44] + assign csr_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec_tlu_ctl.scala 916:44] + assign csr_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec_tlu_ctl.scala 917:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[el2_dec_tlu_ctl.scala 918:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec_tlu_ctl.scala 919:44] + assign csr_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec_tlu_ctl.scala 920:44] + assign csr_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec_tlu_ctl.scala 921:44] + assign csr_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec_tlu_ctl.scala 922:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[el2_dec_tlu_ctl.scala 923:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[el2_dec_tlu_ctl.scala 924:44] + assign csr_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec_tlu_ctl.scala 925:44] + assign csr_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec_tlu_ctl.scala 926:44] + assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44] + assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44] + assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44] + assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44] + assign csr_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 935:44] + assign csr_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec_tlu_ctl.scala 936:44] + assign csr_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec_tlu_ctl.scala 937:44] + assign csr_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec_tlu_ctl.scala 938:44] + assign csr_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec_tlu_ctl.scala 939:44] + assign csr_io_pic_pl = io_pic_pl; // @[el2_dec_tlu_ctl.scala 940:44] + assign csr_io_pic_claimid = io_pic_claimid; // @[el2_dec_tlu_ctl.scala 941:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec_tlu_ctl.scala 942:44] + assign csr_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec_tlu_ctl.scala 943:44] + assign csr_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec_tlu_ctl.scala 944:44] + assign csr_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec_tlu_ctl.scala 945:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 946:44 el2_dec_tlu_ctl.scala 987:44] + assign csr_io_lsu_error_pkt_r_mscause = io_lsu_error_pkt_r_mscause; // @[el2_dec_tlu_ctl.scala 947:44 el2_dec_tlu_ctl.scala 988:44] + assign csr_io_mexintpend = io_mexintpend; // @[el2_dec_tlu_ctl.scala 948:44 el2_dec_tlu_ctl.scala 989:44] + assign csr_io_exu_npc_r = io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 949:44 el2_dec_tlu_ctl.scala 990:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 950:44 el2_dec_tlu_ctl.scala 991:44] + assign csr_io_rst_vec = io_rst_vec; // @[el2_dec_tlu_ctl.scala 951:44 el2_dec_tlu_ctl.scala 992:44] + assign csr_io_core_id = io_core_id; // @[el2_dec_tlu_ctl.scala 952:44 el2_dec_tlu_ctl.scala 993:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[el2_dec_tlu_ctl.scala 953:44 el2_dec_tlu_ctl.scala 994:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[el2_dec_tlu_ctl.scala 954:44 el2_dec_tlu_ctl.scala 995:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[el2_dec_tlu_ctl.scala 998:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 999:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1000:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[el2_dec_tlu_ctl.scala 1001:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[el2_dec_tlu_ctl.scala 1002:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[el2_dec_tlu_ctl.scala 1003:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[el2_dec_tlu_ctl.scala 1004:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[el2_dec_tlu_ctl.scala 1005:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[el2_dec_tlu_ctl.scala 1006:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[el2_dec_tlu_ctl.scala 1007:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[el2_dec_tlu_ctl.scala 1008:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1009:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec_tlu_ctl.scala 1010:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 1011:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[el2_dec_tlu_ctl.scala 1012:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[el2_dec_tlu_ctl.scala 1013:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[el2_dec_tlu_ctl.scala 1014:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[el2_dec_tlu_ctl.scala 1015:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[el2_dec_tlu_ctl.scala 1016:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1017:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[el2_dec_tlu_ctl.scala 1018:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[el2_dec_tlu_ctl.scala 1019:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[el2_dec_tlu_ctl.scala 1020:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] + assign csr_io_lsu_error_pkt_addr_r = {{31'd0}, io_lsu_error_pkt_r_addr}; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1028:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[el2_dec_tlu_ctl.scala 1029:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1030:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[el2_dec_tlu_ctl.scala 1031:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[el2_dec_tlu_ctl.scala 1032:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[el2_dec_tlu_ctl.scala 1033:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[el2_dec_tlu_ctl.scala 1034:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 1035:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[el2_dec_tlu_ctl.scala 1036:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[el2_dec_tlu_ctl.scala 1037:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[el2_dec_tlu_ctl.scala 1038:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[el2_dec_tlu_ctl.scala 1039:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[el2_dec_tlu_ctl.scala 1040:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[el2_dec_tlu_ctl.scala 1041:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[el2_dec_tlu_ctl.scala 1042:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[el2_dec_tlu_ctl.scala 1043:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[el2_dec_tlu_ctl.scala 1044:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[el2_dec_tlu_ctl.scala 1045:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[el2_dec_tlu_ctl.scala 1046:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 1047:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[el2_dec_tlu_ctl.scala 1048:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[el2_dec_tlu_ctl.scala 1049:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 1050:51] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 1051:47] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[el2_dec_tlu_ctl.scala 1052:43] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[el2_dec_tlu_ctl.scala 1053:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[el2_dec_tlu_ctl.scala 1054:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1055:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[el2_dec_tlu_ctl.scala 1056:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[el2_dec_tlu_ctl.scala 1057:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[el2_dec_tlu_ctl.scala 1058:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 1059:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[el2_dec_tlu_ctl.scala 1060:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[el2_dec_tlu_ctl.scala 1061:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[el2_dec_tlu_ctl.scala 1062:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[el2_dec_tlu_ctl.scala 1063:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[el2_dec_tlu_ctl.scala 1064:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[el2_dec_tlu_ctl.scala 1065:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[el2_dec_tlu_ctl.scala 1066:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[el2_dec_tlu_ctl.scala 1067:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[el2_dec_tlu_ctl.scala 1068:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 1069:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 1070:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[el2_dec_tlu_ctl.scala 1071:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[el2_dec_tlu_ctl.scala 1072:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[el2_dec_tlu_ctl.scala 1073:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[el2_dec_tlu_ctl.scala 1091:31] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_halt_state_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + mpc_halt_state_f = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_8 = _RAND_2[6:0]; + _RAND_3 = {1{`RANDOM}}; + syncro_ff = _RAND_3[6:0]; + _RAND_4 = {1{`RANDOM}}; + lsu_exc_valid_r_d1 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + e5_valid = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + debug_mode_status = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + i_cpu_run_req_d1_raw = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + nmi_int_delayed = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + mdseac_locked_f = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + nmi_int_detected_f = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + take_nmi_r_d1 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + take_ext_int_start_d3 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + int_timer0_int_hold_f = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + int_timer1_int_hold_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + i_cpu_halt_req_d1 = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + dbg_halt_req_held = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + ext_int_freeze_d1 = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + reset_detect = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + reset_detected = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + dcsr_single_step_done_f = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + trigger_hit_dmode_r_d1 = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ebreak_to_debug_mode_r_d1 = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + debug_halt_req_f = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + lsu_idle_any_f = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ifu_miss_state_idle_f = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + debug_halt_req_d1 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + dec_tlu_flush_noredir_r_d1 = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + dec_tlu_flush_pause_r_d1 = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + take_ext_int_start_d1 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + halt_taken_f = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + dbg_tlu_halted_f = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + pmu_fw_tlu_halted_f = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + interrupt_valid_r_d1 = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + debug_resume_req_f = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + dcsr_single_step_running_f = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + pmu_fw_halt_req_f = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + internal_pmu_fw_halt_mode_f = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + tlu_flush_lower_r_d1 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + ic_perr_r_d1 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + iccm_sbecc_r_d1 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + request_debug_mode_r_d1 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + iccm_repair_state_d1 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + dec_pause_state_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + dec_tlu_wr_pause_r_d1 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + exc_or_int_valid_r_d1 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + pause_expired_wb = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + lsu_pmu_load_external_r = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + lsu_pmu_store_external_r = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_32 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + internal_dbg_halt_mode_f2 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_33 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + nmi_lsu_load_type_f = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + nmi_lsu_store_type_f = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + mpc_debug_halt_req_sync_f = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + mpc_debug_run_req_sync_f = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + mpc_run_state_f = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + debug_brkpt_status_f = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + mpc_debug_halt_ack_f = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + mpc_debug_run_ack_f = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + dbg_run_state_f = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + _T_65 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + request_debug_mode_done_f = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + _T_190 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + _T_353 = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + _T_354 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + _T_355 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + lsu_single_ecc_error_r_d1 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + lsu_i0_exc_r_d1 = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + take_ext_int_start_d2 = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + tlu_flush_path_r_d1 = _RAND_70[30:0]; + _RAND_71 = {1{`RANDOM}}; + i0_exception_valid_r_d1 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + exc_cause_wb = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + i0_valid_wb = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + trigger_hit_r_d1 = _RAND_74[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dbg_halt_state_f = 1'h0; + end + if (reset) begin + mpc_halt_state_f = 1'h0; + end + if (reset) begin + _T_8 = 7'h0; + end + if (reset) begin + syncro_ff = 7'h0; + end + if (reset) begin + lsu_exc_valid_r_d1 = 1'h0; + end + if (reset) begin + e5_valid = 1'h0; + end + if (reset) begin + debug_mode_status = 1'h0; + end + if (reset) begin + i_cpu_run_req_d1_raw = 1'h0; + end + if (reset) begin + nmi_int_delayed = 1'h0; + end + if (reset) begin + mdseac_locked_f = 1'h0; + end + if (reset) begin + nmi_int_detected_f = 1'h0; + end + if (reset) begin + take_nmi_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d3 = 1'h0; + end + if (reset) begin + int_timer0_int_hold_f = 1'h0; + end + if (reset) begin + int_timer1_int_hold_f = 1'h0; + end + if (reset) begin + i_cpu_halt_req_d1 = 1'h0; + end + if (reset) begin + dbg_halt_req_held = 1'h0; + end + if (reset) begin + ext_int_freeze_d1 = 1'h0; + end + if (reset) begin + reset_detect = 1'h0; + end + if (reset) begin + reset_detected = 1'h0; + end + if (reset) begin + dcsr_single_step_done_f = 1'h0; + end + if (reset) begin + trigger_hit_dmode_r_d1 = 1'h0; + end + if (reset) begin + ebreak_to_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + debug_halt_req_f = 1'h0; + end + if (reset) begin + lsu_idle_any_f = 1'h0; + end + if (reset) begin + ifu_miss_state_idle_f = 1'h0; + end + if (reset) begin + debug_halt_req_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_noredir_r_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_pause_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d1 = 1'h0; + end + if (reset) begin + halt_taken_f = 1'h0; + end + if (reset) begin + dbg_tlu_halted_f = 1'h0; + end + if (reset) begin + pmu_fw_tlu_halted_f = 1'h0; + end + if (reset) begin + interrupt_valid_r_d1 = 1'h0; + end + if (reset) begin + debug_resume_req_f = 1'h0; + end + if (reset) begin + dcsr_single_step_running_f = 1'h0; + end + if (reset) begin + pmu_fw_halt_req_f = 1'h0; + end + if (reset) begin + internal_pmu_fw_halt_mode_f = 1'h0; + end + if (reset) begin + tlu_flush_lower_r_d1 = 1'h0; + end + if (reset) begin + ic_perr_r_d1 = 1'h0; + end + if (reset) begin + iccm_sbecc_r_d1 = 1'h0; + end + if (reset) begin + request_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + iccm_repair_state_d1 = 1'h0; + end + if (reset) begin + dec_pause_state_f = 1'h0; + end + if (reset) begin + dec_tlu_wr_pause_r_d1 = 1'h0; + end + if (reset) begin + exc_or_int_valid_r_d1 = 1'h0; + end + if (reset) begin + pause_expired_wb = 1'h0; + end + if (reset) begin + lsu_pmu_load_external_r = 1'h0; + end + if (reset) begin + lsu_pmu_store_external_r = 1'h0; + end + if (reset) begin + _T_32 = 1'h0; + end + if (reset) begin + internal_dbg_halt_mode_f2 = 1'h0; + end + if (reset) begin + _T_33 = 1'h0; + end + if (reset) begin + nmi_lsu_load_type_f = 1'h0; + end + if (reset) begin + nmi_lsu_store_type_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_req_sync_f = 1'h0; + end + if (reset) begin + mpc_debug_run_req_sync_f = 1'h0; + end + if (reset) begin + mpc_run_state_f = 1'h0; + end + if (reset) begin + debug_brkpt_status_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_ack_f = 1'h0; + end + if (reset) begin + mpc_debug_run_ack_f = 1'h0; + end + if (reset) begin + dbg_run_state_f = 1'h0; + end + if (reset) begin + _T_65 = 1'h0; + end + if (reset) begin + request_debug_mode_done_f = 1'h0; + end + if (reset) begin + _T_190 = 1'h0; + end + if (reset) begin + _T_353 = 1'h0; + end + if (reset) begin + _T_354 = 1'h0; + end + if (reset) begin + _T_355 = 1'h0; + end + if (reset) begin + lsu_single_ecc_error_r_d1 = 1'h0; + end + if (reset) begin + lsu_i0_exc_r_d1 = 1'h0; + end + if (reset) begin + take_ext_int_start_d2 = 1'h0; + end + if (reset) begin + tlu_flush_path_r_d1 = 31'h0; + end + if (reset) begin + i0_exception_valid_r_d1 = 1'h0; + end + if (reset) begin + exc_cause_wb = 5'h0; + end + if (reset) begin + i0_valid_wb = 1'h0; + end + if (reset) begin + trigger_hit_r_d1 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_state_f <= 1'h0; + end else begin + dbg_halt_state_f <= _T_83 & _T_84; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_halt_state_f <= 1'h0; + end else begin + mpc_halt_state_f <= _T_71 & _T_72; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_8 <= 7'h0; + end else begin + _T_8 <= {_T_6,_T_3}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + syncro_ff <= 7'h0; + end else begin + syncro_ff <= _T_8; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_exc_valid_r_d1 <= 1'h0; + end else begin + lsu_exc_valid_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + e5_valid <= 1'h0; + end else begin + e5_valid <= io_dec_tlu_i0_valid_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_mode_status <= 1'h0; + end else begin + debug_mode_status <= debug_halt_req_ns | _T_160; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_run_req_d1_raw <= 1'h0; + end else begin + i_cpu_run_req_d1_raw <= _T_351 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_delayed <= 1'h0; + end else begin + nmi_int_delayed <= syncro_ff[6]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mdseac_locked_f <= 1'h0; + end else begin + mdseac_locked_f <= csr_io_mdseac_locked_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_int_detected_f <= 1'h0; + end else begin + nmi_int_detected_f <= _T_42 | _T_44; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + take_nmi_r_d1 <= 1'h0; + end else begin + take_nmi_r_d1 <= _T_756 & _T_760; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d3 <= 1'h0; + end else begin + take_ext_int_start_d3 <= take_ext_int_start_d2; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer0_int_hold_f <= 1'h0; + end else begin + int_timer0_int_hold_f <= _T_644 | _T_651; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + int_timer1_int_hold_f <= 1'h0; + end else begin + int_timer1_int_hold_f <= _T_654 | _T_661; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + i_cpu_halt_req_d1 <= 1'h0; + end else begin + i_cpu_halt_req_d1 <= _T_347 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_halt_req_held <= 1'h0; + end else begin + dbg_halt_req_held <= _T_106 & ext_int_freeze_d1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ext_int_freeze_d1 <= 1'h0; + end else begin + ext_int_freeze_d1 <= _T_682 | take_ext_int_start_d3; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detect <= 1'h0; + end else begin + reset_detect <= 1'h1; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + reset_detected <= 1'h0; + end else begin + reset_detected <= reset_detect; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_done_f <= 1'h0; + end else begin + dcsr_single_step_done_f <= _T_174 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + trigger_hit_dmode_r_d1 <= 1'h0; + end else begin + trigger_hit_dmode_r_d1 <= i0_trigger_hit_raw_r & i0_trigger_action_r; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + ebreak_to_debug_mode_r_d1 <= 1'h0; + end else begin + ebreak_to_debug_mode_r_d1 <= _T_519 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_f <= 1'h0; + end else begin + debug_halt_req_f <= enter_debug_halt_req | _T_168; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_idle_any_f <= 1'h0; + end else begin + lsu_idle_any_f <= io_lsu_idle_any; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ifu_miss_state_idle_f <= 1'h0; + end else begin + ifu_miss_state_idle_f <= io_ifu_miss_state_idle; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_halt_req_d1 <= 1'h0; + end else begin + debug_halt_req_d1 <= _T_114 & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_noredir_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_noredir_r_d1 <= io_dec_tlu_flush_noredir_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d1 <= 1'h0; + end else begin + take_ext_int_start_d1 <= ext_int_ready & _T_704; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + halt_taken_f <= 1'h0; + end else begin + halt_taken_f <= _T_135 | _T_141; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_tlu_halted_f <= 1'h0; + end else begin + dbg_tlu_halted_f <= _T_164 | _T_166; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_tlu_halted_f <= 1'h0; + end else begin + pmu_fw_tlu_halted_f <= _T_377 & _T_378; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + interrupt_valid_r_d1 <= 1'h0; + end else begin + interrupt_valid_r_d1 <= _T_766 | take_int_timer1_int; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_resume_req_f <= 1'h0; + end else begin + debug_resume_req_f <= _T_165 & _T_121; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dcsr_single_step_running_f <= 1'h0; + end else begin + dcsr_single_step_running_f <= _T_177 | _T_179; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + pmu_fw_halt_req_f <= 1'h0; + end else begin + pmu_fw_halt_req_f <= _T_363 & _T_378; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_pmu_fw_halt_mode_f <= 1'h0; + end else begin + internal_pmu_fw_halt_mode_f <= pmu_fw_halt_req_ns | _T_369; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + tlu_flush_lower_r_d1 <= 1'h0; + end else begin + tlu_flush_lower_r_d1 <= _T_801 | take_ext_int_start; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + ic_perr_r_d1 <= 1'h0; + end else begin + ic_perr_r_d1 <= _T_499 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_sbecc_r_d1 <= 1'h0; + end else begin + iccm_sbecc_r_d1 <= _T_506 & _T_500; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_r_d1 <= 1'h0; + end else begin + request_debug_mode_r_d1 <= _T_180 | _T_182; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + iccm_repair_state_d1 <= 1'h0; + end else begin + iccm_repair_state_d1 <= iccm_sbecc_r_d1 | _T_442; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_pause_state_f <= 1'h0; + end else begin + dec_pause_state_f <= io_dec_pause_state; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_wr_pause_r_d1 <= 1'h0; + end else begin + dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + exc_or_int_valid_r_d1 <= 1'h0; + end else begin + exc_or_int_valid_r_d1 <= _T_855 | mepc_trigger_hit_sel_pc_r; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + pause_expired_wb <= 1'h0; + end else begin + pause_expired_wb <= _T_227 & _T_228; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_load_external_r <= 1'h0; + end else begin + lsu_pmu_load_external_r <= io_lsu_pmu_load_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_pmu_store_external_r <= 1'h0; + end else begin + lsu_pmu_store_external_r <= io_lsu_pmu_store_external_m; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_32 <= 1'h0; + end else begin + _T_32 <= _T_427 | i0_trigger_hit_raw_r; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + internal_dbg_halt_mode_f2 <= 1'h0; + end else begin + internal_dbg_halt_mode_f2 <= debug_mode_status; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_33 <= 1'h0; + end else begin + _T_33 <= csr_io_force_halt; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_load_type_f <= 1'h0; + end else begin + nmi_lsu_load_type_f <= _T_50 | _T_52; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + nmi_lsu_store_type_f <= 1'h0; + end else begin + nmi_lsu_store_type_f <= _T_58 | _T_60; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_req_sync_f <= 1'h0; + end else begin + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync_raw & _T_107; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_req_sync_f <= 1'h0; + end else begin + mpc_debug_run_req_sync_f <= syncro_ff[0]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_run_state_f <= 1'h0; + end else begin + mpc_run_state_f <= _T_76 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + debug_brkpt_status_f <= 1'h0; + end else begin + debug_brkpt_status_f <= _T_92 & _T_94; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_ack_f <= 1'h0; + end else begin + mpc_debug_halt_ack_f <= _T_97 & core_empty; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mpc_debug_run_ack_f <= 1'h0; + end else begin + mpc_debug_run_ack_f <= _T_102 | _T_103; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dbg_run_state_f <= 1'h0; + end else begin + dbg_run_state_f <= _T_86 & _T_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_65 <= 1'h0; + end else begin + _T_65 <= _T & mpc_halt_state_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + request_debug_mode_done_f <= 1'h0; + end else begin + request_debug_mode_done_f <= _T_183 & _T_136; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_190 <= 1'h0; + end else begin + _T_190 <= _T_170 & dbg_run_state_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_353 <= 1'h0; + end else begin + _T_353 <= _T_376 | _T_386; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_354 <= 1'h0; + end else begin + _T_354 <= i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_355 <= 1'h0; + end else begin + _T_355 <= _T_388 | _T_389; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_single_ecc_error_r_d1 <= 1'h0; + end else begin + lsu_single_ecc_error_r_d1 <= io_lsu_single_ecc_error_incr; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + lsu_i0_exc_r_d1 <= 1'h0; + end else begin + lsu_i0_exc_r_d1 <= _T_405 & _T_470; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + take_ext_int_start_d2 <= 1'h0; + end else begin + take_ext_int_start_d2 <= take_ext_int_start_d1; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + tlu_flush_path_r_d1 <= 31'h0; + end else if (take_reset) begin + tlu_flush_path_r_d1 <= io_rst_vec; + end else begin + tlu_flush_path_r_d1 <= _T_852; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_exception_valid_r_d1 <= 1'h0; + end else begin + i0_exception_valid_r_d1 <= _T_527 & _T_528; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + exc_cause_wb <= 5'h0; + end else begin + exc_cause_wb <= _T_603 | _T_591; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + i0_valid_wb <= 1'h0; + end else begin + i0_valid_wb <= tlu_i0_commit_cmt & _T_860; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + trigger_hit_r_d1 <= 1'h0; + end else begin + trigger_hit_r_d1 <= |i0_trigger_chain_masked_r; + end + end +endmodule diff --git a/el2_dec_trigger.anno.json b/el2_dec_trigger.anno.json new file mode 100644 index 00000000..66d7424a --- /dev/null +++ b/el2_dec_trigger.anno.json @@ -0,0 +1,45 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_trigger_match_d", + "sources":[ + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_execute", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_m", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_execute", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_m", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_execute", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_m", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_", + "~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_select", + "~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_trigger" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_trigger.fir b/el2_dec_trigger.fir new file mode 100644 index 00000000..34be29e2 --- /dev/null +++ b/el2_dec_trigger.fir @@ -0,0 +1,1457 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_trigger : + module el2_dec_trigger : + input clock : Clock + input reset : UInt<1> + output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + + node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] + wire _T_2 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_2[0] <= _T_1 @[el2_lib.scala 161:48] + _T_2[1] <= _T_1 @[el2_lib.scala 161:48] + _T_2[2] <= _T_1 @[el2_lib.scala 161:48] + _T_2[3] <= _T_1 @[el2_lib.scala 161:48] + _T_2[4] <= _T_1 @[el2_lib.scala 161:48] + _T_2[5] <= _T_1 @[el2_lib.scala 161:48] + _T_2[6] <= _T_1 @[el2_lib.scala 161:48] + _T_2[7] <= _T_1 @[el2_lib.scala 161:48] + _T_2[8] <= _T_1 @[el2_lib.scala 161:48] + _T_2[9] <= _T_1 @[el2_lib.scala 161:48] + _T_2[10] <= _T_1 @[el2_lib.scala 161:48] + _T_2[11] <= _T_1 @[el2_lib.scala 161:48] + _T_2[12] <= _T_1 @[el2_lib.scala 161:48] + _T_2[13] <= _T_1 @[el2_lib.scala 161:48] + _T_2[14] <= _T_1 @[el2_lib.scala 161:48] + _T_2[15] <= _T_1 @[el2_lib.scala 161:48] + _T_2[16] <= _T_1 @[el2_lib.scala 161:48] + _T_2[17] <= _T_1 @[el2_lib.scala 161:48] + _T_2[18] <= _T_1 @[el2_lib.scala 161:48] + _T_2[19] <= _T_1 @[el2_lib.scala 161:48] + _T_2[20] <= _T_1 @[el2_lib.scala 161:48] + _T_2[21] <= _T_1 @[el2_lib.scala 161:48] + _T_2[22] <= _T_1 @[el2_lib.scala 161:48] + _T_2[23] <= _T_1 @[el2_lib.scala 161:48] + _T_2[24] <= _T_1 @[el2_lib.scala 161:48] + _T_2[25] <= _T_1 @[el2_lib.scala 161:48] + _T_2[26] <= _T_1 @[el2_lib.scala 161:48] + _T_2[27] <= _T_1 @[el2_lib.scala 161:48] + _T_2[28] <= _T_1 @[el2_lib.scala 161:48] + _T_2[29] <= _T_1 @[el2_lib.scala 161:48] + _T_2[30] <= _T_1 @[el2_lib.scala 161:48] + _T_2[31] <= _T_1 @[el2_lib.scala 161:48] + node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58] + node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58] + node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_2[4]) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_2[5]) @[Cat.scala 29:58] + node _T_8 = cat(_T_7, _T_2[6]) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, _T_2[7]) @[Cat.scala 29:58] + node _T_10 = cat(_T_9, _T_2[8]) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T_2[9]) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T_2[10]) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T_2[11]) @[Cat.scala 29:58] + node _T_14 = cat(_T_13, _T_2[12]) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T_2[13]) @[Cat.scala 29:58] + node _T_16 = cat(_T_15, _T_2[14]) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, _T_2[15]) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T_2[16]) @[Cat.scala 29:58] + node _T_19 = cat(_T_18, _T_2[17]) @[Cat.scala 29:58] + node _T_20 = cat(_T_19, _T_2[18]) @[Cat.scala 29:58] + node _T_21 = cat(_T_20, _T_2[19]) @[Cat.scala 29:58] + node _T_22 = cat(_T_21, _T_2[20]) @[Cat.scala 29:58] + node _T_23 = cat(_T_22, _T_2[21]) @[Cat.scala 29:58] + node _T_24 = cat(_T_23, _T_2[22]) @[Cat.scala 29:58] + node _T_25 = cat(_T_24, _T_2[23]) @[Cat.scala 29:58] + node _T_26 = cat(_T_25, _T_2[24]) @[Cat.scala 29:58] + node _T_27 = cat(_T_26, _T_2[25]) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, _T_2[26]) @[Cat.scala 29:58] + node _T_29 = cat(_T_28, _T_2[27]) @[Cat.scala 29:58] + node _T_30 = cat(_T_29, _T_2[28]) @[Cat.scala 29:58] + node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58] + node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58] + node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58] + node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58] + node _T_36 = and(_T_33, _T_35) @[el2_dec_trigger.scala 14:127] + node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[el2_dec_trigger.scala 14:93] + wire _T_39 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_39[0] <= _T_38 @[el2_lib.scala 161:48] + _T_39[1] <= _T_38 @[el2_lib.scala 161:48] + _T_39[2] <= _T_38 @[el2_lib.scala 161:48] + _T_39[3] <= _T_38 @[el2_lib.scala 161:48] + _T_39[4] <= _T_38 @[el2_lib.scala 161:48] + _T_39[5] <= _T_38 @[el2_lib.scala 161:48] + _T_39[6] <= _T_38 @[el2_lib.scala 161:48] + _T_39[7] <= _T_38 @[el2_lib.scala 161:48] + _T_39[8] <= _T_38 @[el2_lib.scala 161:48] + _T_39[9] <= _T_38 @[el2_lib.scala 161:48] + _T_39[10] <= _T_38 @[el2_lib.scala 161:48] + _T_39[11] <= _T_38 @[el2_lib.scala 161:48] + _T_39[12] <= _T_38 @[el2_lib.scala 161:48] + _T_39[13] <= _T_38 @[el2_lib.scala 161:48] + _T_39[14] <= _T_38 @[el2_lib.scala 161:48] + _T_39[15] <= _T_38 @[el2_lib.scala 161:48] + _T_39[16] <= _T_38 @[el2_lib.scala 161:48] + _T_39[17] <= _T_38 @[el2_lib.scala 161:48] + _T_39[18] <= _T_38 @[el2_lib.scala 161:48] + _T_39[19] <= _T_38 @[el2_lib.scala 161:48] + _T_39[20] <= _T_38 @[el2_lib.scala 161:48] + _T_39[21] <= _T_38 @[el2_lib.scala 161:48] + _T_39[22] <= _T_38 @[el2_lib.scala 161:48] + _T_39[23] <= _T_38 @[el2_lib.scala 161:48] + _T_39[24] <= _T_38 @[el2_lib.scala 161:48] + _T_39[25] <= _T_38 @[el2_lib.scala 161:48] + _T_39[26] <= _T_38 @[el2_lib.scala 161:48] + _T_39[27] <= _T_38 @[el2_lib.scala 161:48] + _T_39[28] <= _T_38 @[el2_lib.scala 161:48] + _T_39[29] <= _T_38 @[el2_lib.scala 161:48] + _T_39[30] <= _T_38 @[el2_lib.scala 161:48] + _T_39[31] <= _T_38 @[el2_lib.scala 161:48] + node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58] + node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_39[4]) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_39[5]) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_39[6]) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_39[7]) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_39[8]) @[Cat.scala 29:58] + node _T_48 = cat(_T_47, _T_39[9]) @[Cat.scala 29:58] + node _T_49 = cat(_T_48, _T_39[10]) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_39[11]) @[Cat.scala 29:58] + node _T_51 = cat(_T_50, _T_39[12]) @[Cat.scala 29:58] + node _T_52 = cat(_T_51, _T_39[13]) @[Cat.scala 29:58] + node _T_53 = cat(_T_52, _T_39[14]) @[Cat.scala 29:58] + node _T_54 = cat(_T_53, _T_39[15]) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, _T_39[16]) @[Cat.scala 29:58] + node _T_56 = cat(_T_55, _T_39[17]) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, _T_39[18]) @[Cat.scala 29:58] + node _T_58 = cat(_T_57, _T_39[19]) @[Cat.scala 29:58] + node _T_59 = cat(_T_58, _T_39[20]) @[Cat.scala 29:58] + node _T_60 = cat(_T_59, _T_39[21]) @[Cat.scala 29:58] + node _T_61 = cat(_T_60, _T_39[22]) @[Cat.scala 29:58] + node _T_62 = cat(_T_61, _T_39[23]) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, _T_39[24]) @[Cat.scala 29:58] + node _T_64 = cat(_T_63, _T_39[25]) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, _T_39[26]) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, _T_39[27]) @[Cat.scala 29:58] + node _T_67 = cat(_T_66, _T_39[28]) @[Cat.scala 29:58] + node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58] + node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58] + node _T_73 = and(_T_70, _T_72) @[el2_dec_trigger.scala 14:127] + node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[el2_dec_trigger.scala 14:93] + wire _T_76 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_76[0] <= _T_75 @[el2_lib.scala 161:48] + _T_76[1] <= _T_75 @[el2_lib.scala 161:48] + _T_76[2] <= _T_75 @[el2_lib.scala 161:48] + _T_76[3] <= _T_75 @[el2_lib.scala 161:48] + _T_76[4] <= _T_75 @[el2_lib.scala 161:48] + _T_76[5] <= _T_75 @[el2_lib.scala 161:48] + _T_76[6] <= _T_75 @[el2_lib.scala 161:48] + _T_76[7] <= _T_75 @[el2_lib.scala 161:48] + _T_76[8] <= _T_75 @[el2_lib.scala 161:48] + _T_76[9] <= _T_75 @[el2_lib.scala 161:48] + _T_76[10] <= _T_75 @[el2_lib.scala 161:48] + _T_76[11] <= _T_75 @[el2_lib.scala 161:48] + _T_76[12] <= _T_75 @[el2_lib.scala 161:48] + _T_76[13] <= _T_75 @[el2_lib.scala 161:48] + _T_76[14] <= _T_75 @[el2_lib.scala 161:48] + _T_76[15] <= _T_75 @[el2_lib.scala 161:48] + _T_76[16] <= _T_75 @[el2_lib.scala 161:48] + _T_76[17] <= _T_75 @[el2_lib.scala 161:48] + _T_76[18] <= _T_75 @[el2_lib.scala 161:48] + _T_76[19] <= _T_75 @[el2_lib.scala 161:48] + _T_76[20] <= _T_75 @[el2_lib.scala 161:48] + _T_76[21] <= _T_75 @[el2_lib.scala 161:48] + _T_76[22] <= _T_75 @[el2_lib.scala 161:48] + _T_76[23] <= _T_75 @[el2_lib.scala 161:48] + _T_76[24] <= _T_75 @[el2_lib.scala 161:48] + _T_76[25] <= _T_75 @[el2_lib.scala 161:48] + _T_76[26] <= _T_75 @[el2_lib.scala 161:48] + _T_76[27] <= _T_75 @[el2_lib.scala 161:48] + _T_76[28] <= _T_75 @[el2_lib.scala 161:48] + _T_76[29] <= _T_75 @[el2_lib.scala 161:48] + _T_76[30] <= _T_75 @[el2_lib.scala 161:48] + _T_76[31] <= _T_75 @[el2_lib.scala 161:48] + node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58] + node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58] + node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58] + node _T_80 = cat(_T_79, _T_76[4]) @[Cat.scala 29:58] + node _T_81 = cat(_T_80, _T_76[5]) @[Cat.scala 29:58] + node _T_82 = cat(_T_81, _T_76[6]) @[Cat.scala 29:58] + node _T_83 = cat(_T_82, _T_76[7]) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76[8]) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_76[9]) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76[10]) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_76[11]) @[Cat.scala 29:58] + node _T_88 = cat(_T_87, _T_76[12]) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_76[13]) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_76[14]) @[Cat.scala 29:58] + node _T_91 = cat(_T_90, _T_76[15]) @[Cat.scala 29:58] + node _T_92 = cat(_T_91, _T_76[16]) @[Cat.scala 29:58] + node _T_93 = cat(_T_92, _T_76[17]) @[Cat.scala 29:58] + node _T_94 = cat(_T_93, _T_76[18]) @[Cat.scala 29:58] + node _T_95 = cat(_T_94, _T_76[19]) @[Cat.scala 29:58] + node _T_96 = cat(_T_95, _T_76[20]) @[Cat.scala 29:58] + node _T_97 = cat(_T_96, _T_76[21]) @[Cat.scala 29:58] + node _T_98 = cat(_T_97, _T_76[22]) @[Cat.scala 29:58] + node _T_99 = cat(_T_98, _T_76[23]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_76[24]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_76[25]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_76[26]) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_76[27]) @[Cat.scala 29:58] + node _T_104 = cat(_T_103, _T_76[28]) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58] + node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58] + node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58] + node _T_110 = and(_T_107, _T_109) @[el2_dec_trigger.scala 14:127] + node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] + node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[el2_dec_trigger.scala 14:93] + wire _T_113 : UInt<1>[32] @[el2_lib.scala 161:48] + _T_113[0] <= _T_112 @[el2_lib.scala 161:48] + _T_113[1] <= _T_112 @[el2_lib.scala 161:48] + _T_113[2] <= _T_112 @[el2_lib.scala 161:48] + _T_113[3] <= _T_112 @[el2_lib.scala 161:48] + _T_113[4] <= _T_112 @[el2_lib.scala 161:48] + _T_113[5] <= _T_112 @[el2_lib.scala 161:48] + _T_113[6] <= _T_112 @[el2_lib.scala 161:48] + _T_113[7] <= _T_112 @[el2_lib.scala 161:48] + _T_113[8] <= _T_112 @[el2_lib.scala 161:48] + _T_113[9] <= _T_112 @[el2_lib.scala 161:48] + _T_113[10] <= _T_112 @[el2_lib.scala 161:48] + _T_113[11] <= _T_112 @[el2_lib.scala 161:48] + _T_113[12] <= _T_112 @[el2_lib.scala 161:48] + _T_113[13] <= _T_112 @[el2_lib.scala 161:48] + _T_113[14] <= _T_112 @[el2_lib.scala 161:48] + _T_113[15] <= _T_112 @[el2_lib.scala 161:48] + _T_113[16] <= _T_112 @[el2_lib.scala 161:48] + _T_113[17] <= _T_112 @[el2_lib.scala 161:48] + _T_113[18] <= _T_112 @[el2_lib.scala 161:48] + _T_113[19] <= _T_112 @[el2_lib.scala 161:48] + _T_113[20] <= _T_112 @[el2_lib.scala 161:48] + _T_113[21] <= _T_112 @[el2_lib.scala 161:48] + _T_113[22] <= _T_112 @[el2_lib.scala 161:48] + _T_113[23] <= _T_112 @[el2_lib.scala 161:48] + _T_113[24] <= _T_112 @[el2_lib.scala 161:48] + _T_113[25] <= _T_112 @[el2_lib.scala 161:48] + _T_113[26] <= _T_112 @[el2_lib.scala 161:48] + _T_113[27] <= _T_112 @[el2_lib.scala 161:48] + _T_113[28] <= _T_112 @[el2_lib.scala 161:48] + _T_113[29] <= _T_112 @[el2_lib.scala 161:48] + _T_113[30] <= _T_112 @[el2_lib.scala 161:48] + _T_113[31] <= _T_112 @[el2_lib.scala 161:48] + node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_113[4]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_113[5]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_113[6]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_113[7]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_113[8]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_113[9]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_113[10]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_113[11]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_113[12]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_113[13]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_113[14]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113[15]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_113[16]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_113[17]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_113[18]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_113[19]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_113[20]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_113[21]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_113[22]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_113[23]) @[Cat.scala 29:58] + node _T_137 = cat(_T_136, _T_113[24]) @[Cat.scala 29:58] + node _T_138 = cat(_T_137, _T_113[25]) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_113[26]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_113[27]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_113[28]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58] + node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_dec_trigger.scala 14:177] + node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58] + node _T_147 = and(_T_144, _T_146) @[el2_dec_trigger.scala 14:127] + wire dec_i0_match_data : UInt<32>[4] @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[0] <= _T_36 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[1] <= _T_73 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] + dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] + node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] + node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_150 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 232:45] + node _T_152 = not(_T_151) @[el2_lib.scala 232:39] + node _T_153 = and(_T_149, _T_152) @[el2_lib.scala 232:37] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[el2_lib.scala 233:60] + node _T_156 = eq(_T_154, _T_155) @[el2_lib.scala 233:52] + node _T_157 = or(_T_153, _T_156) @[el2_lib.scala 233:41] + _T_150[0] <= _T_157 @[el2_lib.scala 233:18] + node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_159 = andr(_T_158) @[el2_lib.scala 235:36] + node _T_160 = and(_T_159, _T_153) @[el2_lib.scala 235:41] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[el2_lib.scala 235:86] + node _T_163 = eq(_T_161, _T_162) @[el2_lib.scala 235:78] + node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[el2_lib.scala 235:23] + _T_150[1] <= _T_164 @[el2_lib.scala 235:17] + node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_166 = andr(_T_165) @[el2_lib.scala 235:36] + node _T_167 = and(_T_166, _T_153) @[el2_lib.scala 235:41] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[el2_lib.scala 235:86] + node _T_170 = eq(_T_168, _T_169) @[el2_lib.scala 235:78] + node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[el2_lib.scala 235:23] + _T_150[2] <= _T_171 @[el2_lib.scala 235:17] + node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_173 = andr(_T_172) @[el2_lib.scala 235:36] + node _T_174 = and(_T_173, _T_153) @[el2_lib.scala 235:41] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[el2_lib.scala 235:86] + node _T_177 = eq(_T_175, _T_176) @[el2_lib.scala 235:78] + node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[el2_lib.scala 235:23] + _T_150[3] <= _T_178 @[el2_lib.scala 235:17] + node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_180 = andr(_T_179) @[el2_lib.scala 235:36] + node _T_181 = and(_T_180, _T_153) @[el2_lib.scala 235:41] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[el2_lib.scala 235:86] + node _T_184 = eq(_T_182, _T_183) @[el2_lib.scala 235:78] + node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[el2_lib.scala 235:23] + _T_150[4] <= _T_185 @[el2_lib.scala 235:17] + node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_187 = andr(_T_186) @[el2_lib.scala 235:36] + node _T_188 = and(_T_187, _T_153) @[el2_lib.scala 235:41] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[el2_lib.scala 235:86] + node _T_191 = eq(_T_189, _T_190) @[el2_lib.scala 235:78] + node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[el2_lib.scala 235:23] + _T_150[5] <= _T_192 @[el2_lib.scala 235:17] + node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_194 = andr(_T_193) @[el2_lib.scala 235:36] + node _T_195 = and(_T_194, _T_153) @[el2_lib.scala 235:41] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[el2_lib.scala 235:86] + node _T_198 = eq(_T_196, _T_197) @[el2_lib.scala 235:78] + node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[el2_lib.scala 235:23] + _T_150[6] <= _T_199 @[el2_lib.scala 235:17] + node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_201 = andr(_T_200) @[el2_lib.scala 235:36] + node _T_202 = and(_T_201, _T_153) @[el2_lib.scala 235:41] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[el2_lib.scala 235:86] + node _T_205 = eq(_T_203, _T_204) @[el2_lib.scala 235:78] + node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[el2_lib.scala 235:23] + _T_150[7] <= _T_206 @[el2_lib.scala 235:17] + node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_208 = andr(_T_207) @[el2_lib.scala 235:36] + node _T_209 = and(_T_208, _T_153) @[el2_lib.scala 235:41] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[el2_lib.scala 235:86] + node _T_212 = eq(_T_210, _T_211) @[el2_lib.scala 235:78] + node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[el2_lib.scala 235:23] + _T_150[8] <= _T_213 @[el2_lib.scala 235:17] + node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_215 = andr(_T_214) @[el2_lib.scala 235:36] + node _T_216 = and(_T_215, _T_153) @[el2_lib.scala 235:41] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[el2_lib.scala 235:86] + node _T_219 = eq(_T_217, _T_218) @[el2_lib.scala 235:78] + node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[el2_lib.scala 235:23] + _T_150[9] <= _T_220 @[el2_lib.scala 235:17] + node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_222 = andr(_T_221) @[el2_lib.scala 235:36] + node _T_223 = and(_T_222, _T_153) @[el2_lib.scala 235:41] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[el2_lib.scala 235:86] + node _T_226 = eq(_T_224, _T_225) @[el2_lib.scala 235:78] + node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[el2_lib.scala 235:23] + _T_150[10] <= _T_227 @[el2_lib.scala 235:17] + node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_229 = andr(_T_228) @[el2_lib.scala 235:36] + node _T_230 = and(_T_229, _T_153) @[el2_lib.scala 235:41] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[el2_lib.scala 235:86] + node _T_233 = eq(_T_231, _T_232) @[el2_lib.scala 235:78] + node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[el2_lib.scala 235:23] + _T_150[11] <= _T_234 @[el2_lib.scala 235:17] + node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_236 = andr(_T_235) @[el2_lib.scala 235:36] + node _T_237 = and(_T_236, _T_153) @[el2_lib.scala 235:41] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[el2_lib.scala 235:86] + node _T_240 = eq(_T_238, _T_239) @[el2_lib.scala 235:78] + node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[el2_lib.scala 235:23] + _T_150[12] <= _T_241 @[el2_lib.scala 235:17] + node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_243 = andr(_T_242) @[el2_lib.scala 235:36] + node _T_244 = and(_T_243, _T_153) @[el2_lib.scala 235:41] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[el2_lib.scala 235:86] + node _T_247 = eq(_T_245, _T_246) @[el2_lib.scala 235:78] + node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[el2_lib.scala 235:23] + _T_150[13] <= _T_248 @[el2_lib.scala 235:17] + node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_250 = andr(_T_249) @[el2_lib.scala 235:36] + node _T_251 = and(_T_250, _T_153) @[el2_lib.scala 235:41] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[el2_lib.scala 235:86] + node _T_254 = eq(_T_252, _T_253) @[el2_lib.scala 235:78] + node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[el2_lib.scala 235:23] + _T_150[14] <= _T_255 @[el2_lib.scala 235:17] + node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_257 = andr(_T_256) @[el2_lib.scala 235:36] + node _T_258 = and(_T_257, _T_153) @[el2_lib.scala 235:41] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[el2_lib.scala 235:86] + node _T_261 = eq(_T_259, _T_260) @[el2_lib.scala 235:78] + node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[el2_lib.scala 235:23] + _T_150[15] <= _T_262 @[el2_lib.scala 235:17] + node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_264 = andr(_T_263) @[el2_lib.scala 235:36] + node _T_265 = and(_T_264, _T_153) @[el2_lib.scala 235:41] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[el2_lib.scala 235:86] + node _T_268 = eq(_T_266, _T_267) @[el2_lib.scala 235:78] + node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[el2_lib.scala 235:23] + _T_150[16] <= _T_269 @[el2_lib.scala 235:17] + node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_271 = andr(_T_270) @[el2_lib.scala 235:36] + node _T_272 = and(_T_271, _T_153) @[el2_lib.scala 235:41] + node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[el2_lib.scala 235:86] + node _T_275 = eq(_T_273, _T_274) @[el2_lib.scala 235:78] + node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[el2_lib.scala 235:23] + _T_150[17] <= _T_276 @[el2_lib.scala 235:17] + node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_278 = andr(_T_277) @[el2_lib.scala 235:36] + node _T_279 = and(_T_278, _T_153) @[el2_lib.scala 235:41] + node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[el2_lib.scala 235:86] + node _T_282 = eq(_T_280, _T_281) @[el2_lib.scala 235:78] + node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[el2_lib.scala 235:23] + _T_150[18] <= _T_283 @[el2_lib.scala 235:17] + node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_285 = andr(_T_284) @[el2_lib.scala 235:36] + node _T_286 = and(_T_285, _T_153) @[el2_lib.scala 235:41] + node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[el2_lib.scala 235:86] + node _T_289 = eq(_T_287, _T_288) @[el2_lib.scala 235:78] + node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[el2_lib.scala 235:23] + _T_150[19] <= _T_290 @[el2_lib.scala 235:17] + node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_292 = andr(_T_291) @[el2_lib.scala 235:36] + node _T_293 = and(_T_292, _T_153) @[el2_lib.scala 235:41] + node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[el2_lib.scala 235:86] + node _T_296 = eq(_T_294, _T_295) @[el2_lib.scala 235:78] + node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[el2_lib.scala 235:23] + _T_150[20] <= _T_297 @[el2_lib.scala 235:17] + node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_299 = andr(_T_298) @[el2_lib.scala 235:36] + node _T_300 = and(_T_299, _T_153) @[el2_lib.scala 235:41] + node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[el2_lib.scala 235:86] + node _T_303 = eq(_T_301, _T_302) @[el2_lib.scala 235:78] + node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[el2_lib.scala 235:23] + _T_150[21] <= _T_304 @[el2_lib.scala 235:17] + node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_306 = andr(_T_305) @[el2_lib.scala 235:36] + node _T_307 = and(_T_306, _T_153) @[el2_lib.scala 235:41] + node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[el2_lib.scala 235:86] + node _T_310 = eq(_T_308, _T_309) @[el2_lib.scala 235:78] + node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[el2_lib.scala 235:23] + _T_150[22] <= _T_311 @[el2_lib.scala 235:17] + node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_313 = andr(_T_312) @[el2_lib.scala 235:36] + node _T_314 = and(_T_313, _T_153) @[el2_lib.scala 235:41] + node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[el2_lib.scala 235:86] + node _T_317 = eq(_T_315, _T_316) @[el2_lib.scala 235:78] + node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[el2_lib.scala 235:23] + _T_150[23] <= _T_318 @[el2_lib.scala 235:17] + node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_320 = andr(_T_319) @[el2_lib.scala 235:36] + node _T_321 = and(_T_320, _T_153) @[el2_lib.scala 235:41] + node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[el2_lib.scala 235:86] + node _T_324 = eq(_T_322, _T_323) @[el2_lib.scala 235:78] + node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[el2_lib.scala 235:23] + _T_150[24] <= _T_325 @[el2_lib.scala 235:17] + node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_327 = andr(_T_326) @[el2_lib.scala 235:36] + node _T_328 = and(_T_327, _T_153) @[el2_lib.scala 235:41] + node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[el2_lib.scala 235:86] + node _T_331 = eq(_T_329, _T_330) @[el2_lib.scala 235:78] + node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[el2_lib.scala 235:23] + _T_150[25] <= _T_332 @[el2_lib.scala 235:17] + node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_334 = andr(_T_333) @[el2_lib.scala 235:36] + node _T_335 = and(_T_334, _T_153) @[el2_lib.scala 235:41] + node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[el2_lib.scala 235:86] + node _T_338 = eq(_T_336, _T_337) @[el2_lib.scala 235:78] + node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[el2_lib.scala 235:23] + _T_150[26] <= _T_339 @[el2_lib.scala 235:17] + node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_341 = andr(_T_340) @[el2_lib.scala 235:36] + node _T_342 = and(_T_341, _T_153) @[el2_lib.scala 235:41] + node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[el2_lib.scala 235:86] + node _T_345 = eq(_T_343, _T_344) @[el2_lib.scala 235:78] + node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[el2_lib.scala 235:23] + _T_150[27] <= _T_346 @[el2_lib.scala 235:17] + node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_348 = andr(_T_347) @[el2_lib.scala 235:36] + node _T_349 = and(_T_348, _T_153) @[el2_lib.scala 235:41] + node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[el2_lib.scala 235:86] + node _T_352 = eq(_T_350, _T_351) @[el2_lib.scala 235:78] + node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[el2_lib.scala 235:23] + _T_150[28] <= _T_353 @[el2_lib.scala 235:17] + node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_355 = andr(_T_354) @[el2_lib.scala 235:36] + node _T_356 = and(_T_355, _T_153) @[el2_lib.scala 235:41] + node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[el2_lib.scala 235:86] + node _T_359 = eq(_T_357, _T_358) @[el2_lib.scala 235:78] + node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[el2_lib.scala 235:23] + _T_150[29] <= _T_360 @[el2_lib.scala 235:17] + node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_362 = andr(_T_361) @[el2_lib.scala 235:36] + node _T_363 = and(_T_362, _T_153) @[el2_lib.scala 235:41] + node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[el2_lib.scala 235:86] + node _T_366 = eq(_T_364, _T_365) @[el2_lib.scala 235:78] + node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[el2_lib.scala 235:23] + _T_150[30] <= _T_367 @[el2_lib.scala 235:17] + node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_369 = andr(_T_368) @[el2_lib.scala 235:36] + node _T_370 = and(_T_369, _T_153) @[el2_lib.scala 235:41] + node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[el2_lib.scala 235:86] + node _T_373 = eq(_T_371, _T_372) @[el2_lib.scala 235:78] + node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[el2_lib.scala 235:23] + _T_150[31] <= _T_374 @[el2_lib.scala 235:17] + node _T_375 = cat(_T_150[1], _T_150[0]) @[el2_lib.scala 236:14] + node _T_376 = cat(_T_150[3], _T_150[2]) @[el2_lib.scala 236:14] + node _T_377 = cat(_T_376, _T_375) @[el2_lib.scala 236:14] + node _T_378 = cat(_T_150[5], _T_150[4]) @[el2_lib.scala 236:14] + node _T_379 = cat(_T_150[7], _T_150[6]) @[el2_lib.scala 236:14] + node _T_380 = cat(_T_379, _T_378) @[el2_lib.scala 236:14] + node _T_381 = cat(_T_380, _T_377) @[el2_lib.scala 236:14] + node _T_382 = cat(_T_150[9], _T_150[8]) @[el2_lib.scala 236:14] + node _T_383 = cat(_T_150[11], _T_150[10]) @[el2_lib.scala 236:14] + node _T_384 = cat(_T_383, _T_382) @[el2_lib.scala 236:14] + node _T_385 = cat(_T_150[13], _T_150[12]) @[el2_lib.scala 236:14] + node _T_386 = cat(_T_150[15], _T_150[14]) @[el2_lib.scala 236:14] + node _T_387 = cat(_T_386, _T_385) @[el2_lib.scala 236:14] + node _T_388 = cat(_T_387, _T_384) @[el2_lib.scala 236:14] + node _T_389 = cat(_T_388, _T_381) @[el2_lib.scala 236:14] + node _T_390 = cat(_T_150[17], _T_150[16]) @[el2_lib.scala 236:14] + node _T_391 = cat(_T_150[19], _T_150[18]) @[el2_lib.scala 236:14] + node _T_392 = cat(_T_391, _T_390) @[el2_lib.scala 236:14] + node _T_393 = cat(_T_150[21], _T_150[20]) @[el2_lib.scala 236:14] + node _T_394 = cat(_T_150[23], _T_150[22]) @[el2_lib.scala 236:14] + node _T_395 = cat(_T_394, _T_393) @[el2_lib.scala 236:14] + node _T_396 = cat(_T_395, _T_392) @[el2_lib.scala 236:14] + node _T_397 = cat(_T_150[25], _T_150[24]) @[el2_lib.scala 236:14] + node _T_398 = cat(_T_150[27], _T_150[26]) @[el2_lib.scala 236:14] + node _T_399 = cat(_T_398, _T_397) @[el2_lib.scala 236:14] + node _T_400 = cat(_T_150[29], _T_150[28]) @[el2_lib.scala 236:14] + node _T_401 = cat(_T_150[31], _T_150[30]) @[el2_lib.scala 236:14] + node _T_402 = cat(_T_401, _T_400) @[el2_lib.scala 236:14] + node _T_403 = cat(_T_402, _T_399) @[el2_lib.scala 236:14] + node _T_404 = cat(_T_403, _T_396) @[el2_lib.scala 236:14] + node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 236:14] + node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] + node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] + node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_409 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 232:45] + node _T_411 = not(_T_410) @[el2_lib.scala 232:39] + node _T_412 = and(_T_408, _T_411) @[el2_lib.scala 232:37] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_414 = bits(dec_i0_match_data[1], 0, 0) @[el2_lib.scala 233:60] + node _T_415 = eq(_T_413, _T_414) @[el2_lib.scala 233:52] + node _T_416 = or(_T_412, _T_415) @[el2_lib.scala 233:41] + _T_409[0] <= _T_416 @[el2_lib.scala 233:18] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_418 = andr(_T_417) @[el2_lib.scala 235:36] + node _T_419 = and(_T_418, _T_412) @[el2_lib.scala 235:41] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_421 = bits(dec_i0_match_data[1], 1, 1) @[el2_lib.scala 235:86] + node _T_422 = eq(_T_420, _T_421) @[el2_lib.scala 235:78] + node _T_423 = mux(_T_419, UInt<1>("h01"), _T_422) @[el2_lib.scala 235:23] + _T_409[1] <= _T_423 @[el2_lib.scala 235:17] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_425 = andr(_T_424) @[el2_lib.scala 235:36] + node _T_426 = and(_T_425, _T_412) @[el2_lib.scala 235:41] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_428 = bits(dec_i0_match_data[1], 2, 2) @[el2_lib.scala 235:86] + node _T_429 = eq(_T_427, _T_428) @[el2_lib.scala 235:78] + node _T_430 = mux(_T_426, UInt<1>("h01"), _T_429) @[el2_lib.scala 235:23] + _T_409[2] <= _T_430 @[el2_lib.scala 235:17] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_432 = andr(_T_431) @[el2_lib.scala 235:36] + node _T_433 = and(_T_432, _T_412) @[el2_lib.scala 235:41] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_435 = bits(dec_i0_match_data[1], 3, 3) @[el2_lib.scala 235:86] + node _T_436 = eq(_T_434, _T_435) @[el2_lib.scala 235:78] + node _T_437 = mux(_T_433, UInt<1>("h01"), _T_436) @[el2_lib.scala 235:23] + _T_409[3] <= _T_437 @[el2_lib.scala 235:17] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_439 = andr(_T_438) @[el2_lib.scala 235:36] + node _T_440 = and(_T_439, _T_412) @[el2_lib.scala 235:41] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_442 = bits(dec_i0_match_data[1], 4, 4) @[el2_lib.scala 235:86] + node _T_443 = eq(_T_441, _T_442) @[el2_lib.scala 235:78] + node _T_444 = mux(_T_440, UInt<1>("h01"), _T_443) @[el2_lib.scala 235:23] + _T_409[4] <= _T_444 @[el2_lib.scala 235:17] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_446 = andr(_T_445) @[el2_lib.scala 235:36] + node _T_447 = and(_T_446, _T_412) @[el2_lib.scala 235:41] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_449 = bits(dec_i0_match_data[1], 5, 5) @[el2_lib.scala 235:86] + node _T_450 = eq(_T_448, _T_449) @[el2_lib.scala 235:78] + node _T_451 = mux(_T_447, UInt<1>("h01"), _T_450) @[el2_lib.scala 235:23] + _T_409[5] <= _T_451 @[el2_lib.scala 235:17] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_453 = andr(_T_452) @[el2_lib.scala 235:36] + node _T_454 = and(_T_453, _T_412) @[el2_lib.scala 235:41] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_456 = bits(dec_i0_match_data[1], 6, 6) @[el2_lib.scala 235:86] + node _T_457 = eq(_T_455, _T_456) @[el2_lib.scala 235:78] + node _T_458 = mux(_T_454, UInt<1>("h01"), _T_457) @[el2_lib.scala 235:23] + _T_409[6] <= _T_458 @[el2_lib.scala 235:17] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_460 = andr(_T_459) @[el2_lib.scala 235:36] + node _T_461 = and(_T_460, _T_412) @[el2_lib.scala 235:41] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_463 = bits(dec_i0_match_data[1], 7, 7) @[el2_lib.scala 235:86] + node _T_464 = eq(_T_462, _T_463) @[el2_lib.scala 235:78] + node _T_465 = mux(_T_461, UInt<1>("h01"), _T_464) @[el2_lib.scala 235:23] + _T_409[7] <= _T_465 @[el2_lib.scala 235:17] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_467 = andr(_T_466) @[el2_lib.scala 235:36] + node _T_468 = and(_T_467, _T_412) @[el2_lib.scala 235:41] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_470 = bits(dec_i0_match_data[1], 8, 8) @[el2_lib.scala 235:86] + node _T_471 = eq(_T_469, _T_470) @[el2_lib.scala 235:78] + node _T_472 = mux(_T_468, UInt<1>("h01"), _T_471) @[el2_lib.scala 235:23] + _T_409[8] <= _T_472 @[el2_lib.scala 235:17] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_474 = andr(_T_473) @[el2_lib.scala 235:36] + node _T_475 = and(_T_474, _T_412) @[el2_lib.scala 235:41] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_477 = bits(dec_i0_match_data[1], 9, 9) @[el2_lib.scala 235:86] + node _T_478 = eq(_T_476, _T_477) @[el2_lib.scala 235:78] + node _T_479 = mux(_T_475, UInt<1>("h01"), _T_478) @[el2_lib.scala 235:23] + _T_409[9] <= _T_479 @[el2_lib.scala 235:17] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_481 = andr(_T_480) @[el2_lib.scala 235:36] + node _T_482 = and(_T_481, _T_412) @[el2_lib.scala 235:41] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_484 = bits(dec_i0_match_data[1], 10, 10) @[el2_lib.scala 235:86] + node _T_485 = eq(_T_483, _T_484) @[el2_lib.scala 235:78] + node _T_486 = mux(_T_482, UInt<1>("h01"), _T_485) @[el2_lib.scala 235:23] + _T_409[10] <= _T_486 @[el2_lib.scala 235:17] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_488 = andr(_T_487) @[el2_lib.scala 235:36] + node _T_489 = and(_T_488, _T_412) @[el2_lib.scala 235:41] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_491 = bits(dec_i0_match_data[1], 11, 11) @[el2_lib.scala 235:86] + node _T_492 = eq(_T_490, _T_491) @[el2_lib.scala 235:78] + node _T_493 = mux(_T_489, UInt<1>("h01"), _T_492) @[el2_lib.scala 235:23] + _T_409[11] <= _T_493 @[el2_lib.scala 235:17] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_495 = andr(_T_494) @[el2_lib.scala 235:36] + node _T_496 = and(_T_495, _T_412) @[el2_lib.scala 235:41] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_498 = bits(dec_i0_match_data[1], 12, 12) @[el2_lib.scala 235:86] + node _T_499 = eq(_T_497, _T_498) @[el2_lib.scala 235:78] + node _T_500 = mux(_T_496, UInt<1>("h01"), _T_499) @[el2_lib.scala 235:23] + _T_409[12] <= _T_500 @[el2_lib.scala 235:17] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_502 = andr(_T_501) @[el2_lib.scala 235:36] + node _T_503 = and(_T_502, _T_412) @[el2_lib.scala 235:41] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_505 = bits(dec_i0_match_data[1], 13, 13) @[el2_lib.scala 235:86] + node _T_506 = eq(_T_504, _T_505) @[el2_lib.scala 235:78] + node _T_507 = mux(_T_503, UInt<1>("h01"), _T_506) @[el2_lib.scala 235:23] + _T_409[13] <= _T_507 @[el2_lib.scala 235:17] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_509 = andr(_T_508) @[el2_lib.scala 235:36] + node _T_510 = and(_T_509, _T_412) @[el2_lib.scala 235:41] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_512 = bits(dec_i0_match_data[1], 14, 14) @[el2_lib.scala 235:86] + node _T_513 = eq(_T_511, _T_512) @[el2_lib.scala 235:78] + node _T_514 = mux(_T_510, UInt<1>("h01"), _T_513) @[el2_lib.scala 235:23] + _T_409[14] <= _T_514 @[el2_lib.scala 235:17] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_516 = andr(_T_515) @[el2_lib.scala 235:36] + node _T_517 = and(_T_516, _T_412) @[el2_lib.scala 235:41] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_519 = bits(dec_i0_match_data[1], 15, 15) @[el2_lib.scala 235:86] + node _T_520 = eq(_T_518, _T_519) @[el2_lib.scala 235:78] + node _T_521 = mux(_T_517, UInt<1>("h01"), _T_520) @[el2_lib.scala 235:23] + _T_409[15] <= _T_521 @[el2_lib.scala 235:17] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_523 = andr(_T_522) @[el2_lib.scala 235:36] + node _T_524 = and(_T_523, _T_412) @[el2_lib.scala 235:41] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_526 = bits(dec_i0_match_data[1], 16, 16) @[el2_lib.scala 235:86] + node _T_527 = eq(_T_525, _T_526) @[el2_lib.scala 235:78] + node _T_528 = mux(_T_524, UInt<1>("h01"), _T_527) @[el2_lib.scala 235:23] + _T_409[16] <= _T_528 @[el2_lib.scala 235:17] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_530 = andr(_T_529) @[el2_lib.scala 235:36] + node _T_531 = and(_T_530, _T_412) @[el2_lib.scala 235:41] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_533 = bits(dec_i0_match_data[1], 17, 17) @[el2_lib.scala 235:86] + node _T_534 = eq(_T_532, _T_533) @[el2_lib.scala 235:78] + node _T_535 = mux(_T_531, UInt<1>("h01"), _T_534) @[el2_lib.scala 235:23] + _T_409[17] <= _T_535 @[el2_lib.scala 235:17] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_537 = andr(_T_536) @[el2_lib.scala 235:36] + node _T_538 = and(_T_537, _T_412) @[el2_lib.scala 235:41] + node _T_539 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_540 = bits(dec_i0_match_data[1], 18, 18) @[el2_lib.scala 235:86] + node _T_541 = eq(_T_539, _T_540) @[el2_lib.scala 235:78] + node _T_542 = mux(_T_538, UInt<1>("h01"), _T_541) @[el2_lib.scala 235:23] + _T_409[18] <= _T_542 @[el2_lib.scala 235:17] + node _T_543 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_544 = andr(_T_543) @[el2_lib.scala 235:36] + node _T_545 = and(_T_544, _T_412) @[el2_lib.scala 235:41] + node _T_546 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_547 = bits(dec_i0_match_data[1], 19, 19) @[el2_lib.scala 235:86] + node _T_548 = eq(_T_546, _T_547) @[el2_lib.scala 235:78] + node _T_549 = mux(_T_545, UInt<1>("h01"), _T_548) @[el2_lib.scala 235:23] + _T_409[19] <= _T_549 @[el2_lib.scala 235:17] + node _T_550 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_551 = andr(_T_550) @[el2_lib.scala 235:36] + node _T_552 = and(_T_551, _T_412) @[el2_lib.scala 235:41] + node _T_553 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_554 = bits(dec_i0_match_data[1], 20, 20) @[el2_lib.scala 235:86] + node _T_555 = eq(_T_553, _T_554) @[el2_lib.scala 235:78] + node _T_556 = mux(_T_552, UInt<1>("h01"), _T_555) @[el2_lib.scala 235:23] + _T_409[20] <= _T_556 @[el2_lib.scala 235:17] + node _T_557 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_558 = andr(_T_557) @[el2_lib.scala 235:36] + node _T_559 = and(_T_558, _T_412) @[el2_lib.scala 235:41] + node _T_560 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_561 = bits(dec_i0_match_data[1], 21, 21) @[el2_lib.scala 235:86] + node _T_562 = eq(_T_560, _T_561) @[el2_lib.scala 235:78] + node _T_563 = mux(_T_559, UInt<1>("h01"), _T_562) @[el2_lib.scala 235:23] + _T_409[21] <= _T_563 @[el2_lib.scala 235:17] + node _T_564 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_565 = andr(_T_564) @[el2_lib.scala 235:36] + node _T_566 = and(_T_565, _T_412) @[el2_lib.scala 235:41] + node _T_567 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_568 = bits(dec_i0_match_data[1], 22, 22) @[el2_lib.scala 235:86] + node _T_569 = eq(_T_567, _T_568) @[el2_lib.scala 235:78] + node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[el2_lib.scala 235:23] + _T_409[22] <= _T_570 @[el2_lib.scala 235:17] + node _T_571 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_572 = andr(_T_571) @[el2_lib.scala 235:36] + node _T_573 = and(_T_572, _T_412) @[el2_lib.scala 235:41] + node _T_574 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_575 = bits(dec_i0_match_data[1], 23, 23) @[el2_lib.scala 235:86] + node _T_576 = eq(_T_574, _T_575) @[el2_lib.scala 235:78] + node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[el2_lib.scala 235:23] + _T_409[23] <= _T_577 @[el2_lib.scala 235:17] + node _T_578 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_579 = andr(_T_578) @[el2_lib.scala 235:36] + node _T_580 = and(_T_579, _T_412) @[el2_lib.scala 235:41] + node _T_581 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_582 = bits(dec_i0_match_data[1], 24, 24) @[el2_lib.scala 235:86] + node _T_583 = eq(_T_581, _T_582) @[el2_lib.scala 235:78] + node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[el2_lib.scala 235:23] + _T_409[24] <= _T_584 @[el2_lib.scala 235:17] + node _T_585 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_586 = andr(_T_585) @[el2_lib.scala 235:36] + node _T_587 = and(_T_586, _T_412) @[el2_lib.scala 235:41] + node _T_588 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_589 = bits(dec_i0_match_data[1], 25, 25) @[el2_lib.scala 235:86] + node _T_590 = eq(_T_588, _T_589) @[el2_lib.scala 235:78] + node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[el2_lib.scala 235:23] + _T_409[25] <= _T_591 @[el2_lib.scala 235:17] + node _T_592 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_593 = andr(_T_592) @[el2_lib.scala 235:36] + node _T_594 = and(_T_593, _T_412) @[el2_lib.scala 235:41] + node _T_595 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_596 = bits(dec_i0_match_data[1], 26, 26) @[el2_lib.scala 235:86] + node _T_597 = eq(_T_595, _T_596) @[el2_lib.scala 235:78] + node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[el2_lib.scala 235:23] + _T_409[26] <= _T_598 @[el2_lib.scala 235:17] + node _T_599 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_600 = andr(_T_599) @[el2_lib.scala 235:36] + node _T_601 = and(_T_600, _T_412) @[el2_lib.scala 235:41] + node _T_602 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_603 = bits(dec_i0_match_data[1], 27, 27) @[el2_lib.scala 235:86] + node _T_604 = eq(_T_602, _T_603) @[el2_lib.scala 235:78] + node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[el2_lib.scala 235:23] + _T_409[27] <= _T_605 @[el2_lib.scala 235:17] + node _T_606 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_607 = andr(_T_606) @[el2_lib.scala 235:36] + node _T_608 = and(_T_607, _T_412) @[el2_lib.scala 235:41] + node _T_609 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_610 = bits(dec_i0_match_data[1], 28, 28) @[el2_lib.scala 235:86] + node _T_611 = eq(_T_609, _T_610) @[el2_lib.scala 235:78] + node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[el2_lib.scala 235:23] + _T_409[28] <= _T_612 @[el2_lib.scala 235:17] + node _T_613 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_614 = andr(_T_613) @[el2_lib.scala 235:36] + node _T_615 = and(_T_614, _T_412) @[el2_lib.scala 235:41] + node _T_616 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_617 = bits(dec_i0_match_data[1], 29, 29) @[el2_lib.scala 235:86] + node _T_618 = eq(_T_616, _T_617) @[el2_lib.scala 235:78] + node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[el2_lib.scala 235:23] + _T_409[29] <= _T_619 @[el2_lib.scala 235:17] + node _T_620 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_621 = andr(_T_620) @[el2_lib.scala 235:36] + node _T_622 = and(_T_621, _T_412) @[el2_lib.scala 235:41] + node _T_623 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_624 = bits(dec_i0_match_data[1], 30, 30) @[el2_lib.scala 235:86] + node _T_625 = eq(_T_623, _T_624) @[el2_lib.scala 235:78] + node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[el2_lib.scala 235:23] + _T_409[30] <= _T_626 @[el2_lib.scala 235:17] + node _T_627 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_628 = andr(_T_627) @[el2_lib.scala 235:36] + node _T_629 = and(_T_628, _T_412) @[el2_lib.scala 235:41] + node _T_630 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_631 = bits(dec_i0_match_data[1], 31, 31) @[el2_lib.scala 235:86] + node _T_632 = eq(_T_630, _T_631) @[el2_lib.scala 235:78] + node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[el2_lib.scala 235:23] + _T_409[31] <= _T_633 @[el2_lib.scala 235:17] + node _T_634 = cat(_T_409[1], _T_409[0]) @[el2_lib.scala 236:14] + node _T_635 = cat(_T_409[3], _T_409[2]) @[el2_lib.scala 236:14] + node _T_636 = cat(_T_635, _T_634) @[el2_lib.scala 236:14] + node _T_637 = cat(_T_409[5], _T_409[4]) @[el2_lib.scala 236:14] + node _T_638 = cat(_T_409[7], _T_409[6]) @[el2_lib.scala 236:14] + node _T_639 = cat(_T_638, _T_637) @[el2_lib.scala 236:14] + node _T_640 = cat(_T_639, _T_636) @[el2_lib.scala 236:14] + node _T_641 = cat(_T_409[9], _T_409[8]) @[el2_lib.scala 236:14] + node _T_642 = cat(_T_409[11], _T_409[10]) @[el2_lib.scala 236:14] + node _T_643 = cat(_T_642, _T_641) @[el2_lib.scala 236:14] + node _T_644 = cat(_T_409[13], _T_409[12]) @[el2_lib.scala 236:14] + node _T_645 = cat(_T_409[15], _T_409[14]) @[el2_lib.scala 236:14] + node _T_646 = cat(_T_645, _T_644) @[el2_lib.scala 236:14] + node _T_647 = cat(_T_646, _T_643) @[el2_lib.scala 236:14] + node _T_648 = cat(_T_647, _T_640) @[el2_lib.scala 236:14] + node _T_649 = cat(_T_409[17], _T_409[16]) @[el2_lib.scala 236:14] + node _T_650 = cat(_T_409[19], _T_409[18]) @[el2_lib.scala 236:14] + node _T_651 = cat(_T_650, _T_649) @[el2_lib.scala 236:14] + node _T_652 = cat(_T_409[21], _T_409[20]) @[el2_lib.scala 236:14] + node _T_653 = cat(_T_409[23], _T_409[22]) @[el2_lib.scala 236:14] + node _T_654 = cat(_T_653, _T_652) @[el2_lib.scala 236:14] + node _T_655 = cat(_T_654, _T_651) @[el2_lib.scala 236:14] + node _T_656 = cat(_T_409[25], _T_409[24]) @[el2_lib.scala 236:14] + node _T_657 = cat(_T_409[27], _T_409[26]) @[el2_lib.scala 236:14] + node _T_658 = cat(_T_657, _T_656) @[el2_lib.scala 236:14] + node _T_659 = cat(_T_409[29], _T_409[28]) @[el2_lib.scala 236:14] + node _T_660 = cat(_T_409[31], _T_409[30]) @[el2_lib.scala 236:14] + node _T_661 = cat(_T_660, _T_659) @[el2_lib.scala 236:14] + node _T_662 = cat(_T_661, _T_658) @[el2_lib.scala 236:14] + node _T_663 = cat(_T_662, _T_655) @[el2_lib.scala 236:14] + node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 236:14] + node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] + node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] + node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_668 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 232:45] + node _T_670 = not(_T_669) @[el2_lib.scala 232:39] + node _T_671 = and(_T_667, _T_670) @[el2_lib.scala 232:37] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_673 = bits(dec_i0_match_data[2], 0, 0) @[el2_lib.scala 233:60] + node _T_674 = eq(_T_672, _T_673) @[el2_lib.scala 233:52] + node _T_675 = or(_T_671, _T_674) @[el2_lib.scala 233:41] + _T_668[0] <= _T_675 @[el2_lib.scala 233:18] + node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_677 = andr(_T_676) @[el2_lib.scala 235:36] + node _T_678 = and(_T_677, _T_671) @[el2_lib.scala 235:41] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_680 = bits(dec_i0_match_data[2], 1, 1) @[el2_lib.scala 235:86] + node _T_681 = eq(_T_679, _T_680) @[el2_lib.scala 235:78] + node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[el2_lib.scala 235:23] + _T_668[1] <= _T_682 @[el2_lib.scala 235:17] + node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_684 = andr(_T_683) @[el2_lib.scala 235:36] + node _T_685 = and(_T_684, _T_671) @[el2_lib.scala 235:41] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_687 = bits(dec_i0_match_data[2], 2, 2) @[el2_lib.scala 235:86] + node _T_688 = eq(_T_686, _T_687) @[el2_lib.scala 235:78] + node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[el2_lib.scala 235:23] + _T_668[2] <= _T_689 @[el2_lib.scala 235:17] + node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_691 = andr(_T_690) @[el2_lib.scala 235:36] + node _T_692 = and(_T_691, _T_671) @[el2_lib.scala 235:41] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_694 = bits(dec_i0_match_data[2], 3, 3) @[el2_lib.scala 235:86] + node _T_695 = eq(_T_693, _T_694) @[el2_lib.scala 235:78] + node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[el2_lib.scala 235:23] + _T_668[3] <= _T_696 @[el2_lib.scala 235:17] + node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_698 = andr(_T_697) @[el2_lib.scala 235:36] + node _T_699 = and(_T_698, _T_671) @[el2_lib.scala 235:41] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_701 = bits(dec_i0_match_data[2], 4, 4) @[el2_lib.scala 235:86] + node _T_702 = eq(_T_700, _T_701) @[el2_lib.scala 235:78] + node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[el2_lib.scala 235:23] + _T_668[4] <= _T_703 @[el2_lib.scala 235:17] + node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_705 = andr(_T_704) @[el2_lib.scala 235:36] + node _T_706 = and(_T_705, _T_671) @[el2_lib.scala 235:41] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_708 = bits(dec_i0_match_data[2], 5, 5) @[el2_lib.scala 235:86] + node _T_709 = eq(_T_707, _T_708) @[el2_lib.scala 235:78] + node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[el2_lib.scala 235:23] + _T_668[5] <= _T_710 @[el2_lib.scala 235:17] + node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_712 = andr(_T_711) @[el2_lib.scala 235:36] + node _T_713 = and(_T_712, _T_671) @[el2_lib.scala 235:41] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_715 = bits(dec_i0_match_data[2], 6, 6) @[el2_lib.scala 235:86] + node _T_716 = eq(_T_714, _T_715) @[el2_lib.scala 235:78] + node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[el2_lib.scala 235:23] + _T_668[6] <= _T_717 @[el2_lib.scala 235:17] + node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_719 = andr(_T_718) @[el2_lib.scala 235:36] + node _T_720 = and(_T_719, _T_671) @[el2_lib.scala 235:41] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_722 = bits(dec_i0_match_data[2], 7, 7) @[el2_lib.scala 235:86] + node _T_723 = eq(_T_721, _T_722) @[el2_lib.scala 235:78] + node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[el2_lib.scala 235:23] + _T_668[7] <= _T_724 @[el2_lib.scala 235:17] + node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_726 = andr(_T_725) @[el2_lib.scala 235:36] + node _T_727 = and(_T_726, _T_671) @[el2_lib.scala 235:41] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_729 = bits(dec_i0_match_data[2], 8, 8) @[el2_lib.scala 235:86] + node _T_730 = eq(_T_728, _T_729) @[el2_lib.scala 235:78] + node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[el2_lib.scala 235:23] + _T_668[8] <= _T_731 @[el2_lib.scala 235:17] + node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_733 = andr(_T_732) @[el2_lib.scala 235:36] + node _T_734 = and(_T_733, _T_671) @[el2_lib.scala 235:41] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_736 = bits(dec_i0_match_data[2], 9, 9) @[el2_lib.scala 235:86] + node _T_737 = eq(_T_735, _T_736) @[el2_lib.scala 235:78] + node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[el2_lib.scala 235:23] + _T_668[9] <= _T_738 @[el2_lib.scala 235:17] + node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_740 = andr(_T_739) @[el2_lib.scala 235:36] + node _T_741 = and(_T_740, _T_671) @[el2_lib.scala 235:41] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_743 = bits(dec_i0_match_data[2], 10, 10) @[el2_lib.scala 235:86] + node _T_744 = eq(_T_742, _T_743) @[el2_lib.scala 235:78] + node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[el2_lib.scala 235:23] + _T_668[10] <= _T_745 @[el2_lib.scala 235:17] + node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_747 = andr(_T_746) @[el2_lib.scala 235:36] + node _T_748 = and(_T_747, _T_671) @[el2_lib.scala 235:41] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_750 = bits(dec_i0_match_data[2], 11, 11) @[el2_lib.scala 235:86] + node _T_751 = eq(_T_749, _T_750) @[el2_lib.scala 235:78] + node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[el2_lib.scala 235:23] + _T_668[11] <= _T_752 @[el2_lib.scala 235:17] + node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_754 = andr(_T_753) @[el2_lib.scala 235:36] + node _T_755 = and(_T_754, _T_671) @[el2_lib.scala 235:41] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_757 = bits(dec_i0_match_data[2], 12, 12) @[el2_lib.scala 235:86] + node _T_758 = eq(_T_756, _T_757) @[el2_lib.scala 235:78] + node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[el2_lib.scala 235:23] + _T_668[12] <= _T_759 @[el2_lib.scala 235:17] + node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_761 = andr(_T_760) @[el2_lib.scala 235:36] + node _T_762 = and(_T_761, _T_671) @[el2_lib.scala 235:41] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_764 = bits(dec_i0_match_data[2], 13, 13) @[el2_lib.scala 235:86] + node _T_765 = eq(_T_763, _T_764) @[el2_lib.scala 235:78] + node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[el2_lib.scala 235:23] + _T_668[13] <= _T_766 @[el2_lib.scala 235:17] + node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_768 = andr(_T_767) @[el2_lib.scala 235:36] + node _T_769 = and(_T_768, _T_671) @[el2_lib.scala 235:41] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_771 = bits(dec_i0_match_data[2], 14, 14) @[el2_lib.scala 235:86] + node _T_772 = eq(_T_770, _T_771) @[el2_lib.scala 235:78] + node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[el2_lib.scala 235:23] + _T_668[14] <= _T_773 @[el2_lib.scala 235:17] + node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_775 = andr(_T_774) @[el2_lib.scala 235:36] + node _T_776 = and(_T_775, _T_671) @[el2_lib.scala 235:41] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_778 = bits(dec_i0_match_data[2], 15, 15) @[el2_lib.scala 235:86] + node _T_779 = eq(_T_777, _T_778) @[el2_lib.scala 235:78] + node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[el2_lib.scala 235:23] + _T_668[15] <= _T_780 @[el2_lib.scala 235:17] + node _T_781 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_782 = andr(_T_781) @[el2_lib.scala 235:36] + node _T_783 = and(_T_782, _T_671) @[el2_lib.scala 235:41] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_785 = bits(dec_i0_match_data[2], 16, 16) @[el2_lib.scala 235:86] + node _T_786 = eq(_T_784, _T_785) @[el2_lib.scala 235:78] + node _T_787 = mux(_T_783, UInt<1>("h01"), _T_786) @[el2_lib.scala 235:23] + _T_668[16] <= _T_787 @[el2_lib.scala 235:17] + node _T_788 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_789 = andr(_T_788) @[el2_lib.scala 235:36] + node _T_790 = and(_T_789, _T_671) @[el2_lib.scala 235:41] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_792 = bits(dec_i0_match_data[2], 17, 17) @[el2_lib.scala 235:86] + node _T_793 = eq(_T_791, _T_792) @[el2_lib.scala 235:78] + node _T_794 = mux(_T_790, UInt<1>("h01"), _T_793) @[el2_lib.scala 235:23] + _T_668[17] <= _T_794 @[el2_lib.scala 235:17] + node _T_795 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_796 = andr(_T_795) @[el2_lib.scala 235:36] + node _T_797 = and(_T_796, _T_671) @[el2_lib.scala 235:41] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_799 = bits(dec_i0_match_data[2], 18, 18) @[el2_lib.scala 235:86] + node _T_800 = eq(_T_798, _T_799) @[el2_lib.scala 235:78] + node _T_801 = mux(_T_797, UInt<1>("h01"), _T_800) @[el2_lib.scala 235:23] + _T_668[18] <= _T_801 @[el2_lib.scala 235:17] + node _T_802 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_803 = andr(_T_802) @[el2_lib.scala 235:36] + node _T_804 = and(_T_803, _T_671) @[el2_lib.scala 235:41] + node _T_805 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_806 = bits(dec_i0_match_data[2], 19, 19) @[el2_lib.scala 235:86] + node _T_807 = eq(_T_805, _T_806) @[el2_lib.scala 235:78] + node _T_808 = mux(_T_804, UInt<1>("h01"), _T_807) @[el2_lib.scala 235:23] + _T_668[19] <= _T_808 @[el2_lib.scala 235:17] + node _T_809 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_810 = andr(_T_809) @[el2_lib.scala 235:36] + node _T_811 = and(_T_810, _T_671) @[el2_lib.scala 235:41] + node _T_812 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_813 = bits(dec_i0_match_data[2], 20, 20) @[el2_lib.scala 235:86] + node _T_814 = eq(_T_812, _T_813) @[el2_lib.scala 235:78] + node _T_815 = mux(_T_811, UInt<1>("h01"), _T_814) @[el2_lib.scala 235:23] + _T_668[20] <= _T_815 @[el2_lib.scala 235:17] + node _T_816 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_817 = andr(_T_816) @[el2_lib.scala 235:36] + node _T_818 = and(_T_817, _T_671) @[el2_lib.scala 235:41] + node _T_819 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_820 = bits(dec_i0_match_data[2], 21, 21) @[el2_lib.scala 235:86] + node _T_821 = eq(_T_819, _T_820) @[el2_lib.scala 235:78] + node _T_822 = mux(_T_818, UInt<1>("h01"), _T_821) @[el2_lib.scala 235:23] + _T_668[21] <= _T_822 @[el2_lib.scala 235:17] + node _T_823 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_824 = andr(_T_823) @[el2_lib.scala 235:36] + node _T_825 = and(_T_824, _T_671) @[el2_lib.scala 235:41] + node _T_826 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_827 = bits(dec_i0_match_data[2], 22, 22) @[el2_lib.scala 235:86] + node _T_828 = eq(_T_826, _T_827) @[el2_lib.scala 235:78] + node _T_829 = mux(_T_825, UInt<1>("h01"), _T_828) @[el2_lib.scala 235:23] + _T_668[22] <= _T_829 @[el2_lib.scala 235:17] + node _T_830 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_831 = andr(_T_830) @[el2_lib.scala 235:36] + node _T_832 = and(_T_831, _T_671) @[el2_lib.scala 235:41] + node _T_833 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_834 = bits(dec_i0_match_data[2], 23, 23) @[el2_lib.scala 235:86] + node _T_835 = eq(_T_833, _T_834) @[el2_lib.scala 235:78] + node _T_836 = mux(_T_832, UInt<1>("h01"), _T_835) @[el2_lib.scala 235:23] + _T_668[23] <= _T_836 @[el2_lib.scala 235:17] + node _T_837 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_838 = andr(_T_837) @[el2_lib.scala 235:36] + node _T_839 = and(_T_838, _T_671) @[el2_lib.scala 235:41] + node _T_840 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_841 = bits(dec_i0_match_data[2], 24, 24) @[el2_lib.scala 235:86] + node _T_842 = eq(_T_840, _T_841) @[el2_lib.scala 235:78] + node _T_843 = mux(_T_839, UInt<1>("h01"), _T_842) @[el2_lib.scala 235:23] + _T_668[24] <= _T_843 @[el2_lib.scala 235:17] + node _T_844 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_845 = andr(_T_844) @[el2_lib.scala 235:36] + node _T_846 = and(_T_845, _T_671) @[el2_lib.scala 235:41] + node _T_847 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_848 = bits(dec_i0_match_data[2], 25, 25) @[el2_lib.scala 235:86] + node _T_849 = eq(_T_847, _T_848) @[el2_lib.scala 235:78] + node _T_850 = mux(_T_846, UInt<1>("h01"), _T_849) @[el2_lib.scala 235:23] + _T_668[25] <= _T_850 @[el2_lib.scala 235:17] + node _T_851 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_852 = andr(_T_851) @[el2_lib.scala 235:36] + node _T_853 = and(_T_852, _T_671) @[el2_lib.scala 235:41] + node _T_854 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_855 = bits(dec_i0_match_data[2], 26, 26) @[el2_lib.scala 235:86] + node _T_856 = eq(_T_854, _T_855) @[el2_lib.scala 235:78] + node _T_857 = mux(_T_853, UInt<1>("h01"), _T_856) @[el2_lib.scala 235:23] + _T_668[26] <= _T_857 @[el2_lib.scala 235:17] + node _T_858 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_859 = andr(_T_858) @[el2_lib.scala 235:36] + node _T_860 = and(_T_859, _T_671) @[el2_lib.scala 235:41] + node _T_861 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_862 = bits(dec_i0_match_data[2], 27, 27) @[el2_lib.scala 235:86] + node _T_863 = eq(_T_861, _T_862) @[el2_lib.scala 235:78] + node _T_864 = mux(_T_860, UInt<1>("h01"), _T_863) @[el2_lib.scala 235:23] + _T_668[27] <= _T_864 @[el2_lib.scala 235:17] + node _T_865 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_866 = andr(_T_865) @[el2_lib.scala 235:36] + node _T_867 = and(_T_866, _T_671) @[el2_lib.scala 235:41] + node _T_868 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_869 = bits(dec_i0_match_data[2], 28, 28) @[el2_lib.scala 235:86] + node _T_870 = eq(_T_868, _T_869) @[el2_lib.scala 235:78] + node _T_871 = mux(_T_867, UInt<1>("h01"), _T_870) @[el2_lib.scala 235:23] + _T_668[28] <= _T_871 @[el2_lib.scala 235:17] + node _T_872 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_873 = andr(_T_872) @[el2_lib.scala 235:36] + node _T_874 = and(_T_873, _T_671) @[el2_lib.scala 235:41] + node _T_875 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_876 = bits(dec_i0_match_data[2], 29, 29) @[el2_lib.scala 235:86] + node _T_877 = eq(_T_875, _T_876) @[el2_lib.scala 235:78] + node _T_878 = mux(_T_874, UInt<1>("h01"), _T_877) @[el2_lib.scala 235:23] + _T_668[29] <= _T_878 @[el2_lib.scala 235:17] + node _T_879 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_880 = andr(_T_879) @[el2_lib.scala 235:36] + node _T_881 = and(_T_880, _T_671) @[el2_lib.scala 235:41] + node _T_882 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_883 = bits(dec_i0_match_data[2], 30, 30) @[el2_lib.scala 235:86] + node _T_884 = eq(_T_882, _T_883) @[el2_lib.scala 235:78] + node _T_885 = mux(_T_881, UInt<1>("h01"), _T_884) @[el2_lib.scala 235:23] + _T_668[30] <= _T_885 @[el2_lib.scala 235:17] + node _T_886 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_887 = andr(_T_886) @[el2_lib.scala 235:36] + node _T_888 = and(_T_887, _T_671) @[el2_lib.scala 235:41] + node _T_889 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_890 = bits(dec_i0_match_data[2], 31, 31) @[el2_lib.scala 235:86] + node _T_891 = eq(_T_889, _T_890) @[el2_lib.scala 235:78] + node _T_892 = mux(_T_888, UInt<1>("h01"), _T_891) @[el2_lib.scala 235:23] + _T_668[31] <= _T_892 @[el2_lib.scala 235:17] + node _T_893 = cat(_T_668[1], _T_668[0]) @[el2_lib.scala 236:14] + node _T_894 = cat(_T_668[3], _T_668[2]) @[el2_lib.scala 236:14] + node _T_895 = cat(_T_894, _T_893) @[el2_lib.scala 236:14] + node _T_896 = cat(_T_668[5], _T_668[4]) @[el2_lib.scala 236:14] + node _T_897 = cat(_T_668[7], _T_668[6]) @[el2_lib.scala 236:14] + node _T_898 = cat(_T_897, _T_896) @[el2_lib.scala 236:14] + node _T_899 = cat(_T_898, _T_895) @[el2_lib.scala 236:14] + node _T_900 = cat(_T_668[9], _T_668[8]) @[el2_lib.scala 236:14] + node _T_901 = cat(_T_668[11], _T_668[10]) @[el2_lib.scala 236:14] + node _T_902 = cat(_T_901, _T_900) @[el2_lib.scala 236:14] + node _T_903 = cat(_T_668[13], _T_668[12]) @[el2_lib.scala 236:14] + node _T_904 = cat(_T_668[15], _T_668[14]) @[el2_lib.scala 236:14] + node _T_905 = cat(_T_904, _T_903) @[el2_lib.scala 236:14] + node _T_906 = cat(_T_905, _T_902) @[el2_lib.scala 236:14] + node _T_907 = cat(_T_906, _T_899) @[el2_lib.scala 236:14] + node _T_908 = cat(_T_668[17], _T_668[16]) @[el2_lib.scala 236:14] + node _T_909 = cat(_T_668[19], _T_668[18]) @[el2_lib.scala 236:14] + node _T_910 = cat(_T_909, _T_908) @[el2_lib.scala 236:14] + node _T_911 = cat(_T_668[21], _T_668[20]) @[el2_lib.scala 236:14] + node _T_912 = cat(_T_668[23], _T_668[22]) @[el2_lib.scala 236:14] + node _T_913 = cat(_T_912, _T_911) @[el2_lib.scala 236:14] + node _T_914 = cat(_T_913, _T_910) @[el2_lib.scala 236:14] + node _T_915 = cat(_T_668[25], _T_668[24]) @[el2_lib.scala 236:14] + node _T_916 = cat(_T_668[27], _T_668[26]) @[el2_lib.scala 236:14] + node _T_917 = cat(_T_916, _T_915) @[el2_lib.scala 236:14] + node _T_918 = cat(_T_668[29], _T_668[28]) @[el2_lib.scala 236:14] + node _T_919 = cat(_T_668[31], _T_668[30]) @[el2_lib.scala 236:14] + node _T_920 = cat(_T_919, _T_918) @[el2_lib.scala 236:14] + node _T_921 = cat(_T_920, _T_917) @[el2_lib.scala 236:14] + node _T_922 = cat(_T_921, _T_914) @[el2_lib.scala 236:14] + node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 236:14] + node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] + node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] + node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + wire _T_927 : UInt<1>[32] @[el2_lib.scala 231:24] + node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 232:45] + node _T_929 = not(_T_928) @[el2_lib.scala 232:39] + node _T_930 = and(_T_926, _T_929) @[el2_lib.scala 232:37] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 233:48] + node _T_932 = bits(dec_i0_match_data[3], 0, 0) @[el2_lib.scala 233:60] + node _T_933 = eq(_T_931, _T_932) @[el2_lib.scala 233:52] + node _T_934 = or(_T_930, _T_933) @[el2_lib.scala 233:41] + _T_927[0] <= _T_934 @[el2_lib.scala 233:18] + node _T_935 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 235:28] + node _T_936 = andr(_T_935) @[el2_lib.scala 235:36] + node _T_937 = and(_T_936, _T_930) @[el2_lib.scala 235:41] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 235:74] + node _T_939 = bits(dec_i0_match_data[3], 1, 1) @[el2_lib.scala 235:86] + node _T_940 = eq(_T_938, _T_939) @[el2_lib.scala 235:78] + node _T_941 = mux(_T_937, UInt<1>("h01"), _T_940) @[el2_lib.scala 235:23] + _T_927[1] <= _T_941 @[el2_lib.scala 235:17] + node _T_942 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 235:28] + node _T_943 = andr(_T_942) @[el2_lib.scala 235:36] + node _T_944 = and(_T_943, _T_930) @[el2_lib.scala 235:41] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 235:74] + node _T_946 = bits(dec_i0_match_data[3], 2, 2) @[el2_lib.scala 235:86] + node _T_947 = eq(_T_945, _T_946) @[el2_lib.scala 235:78] + node _T_948 = mux(_T_944, UInt<1>("h01"), _T_947) @[el2_lib.scala 235:23] + _T_927[2] <= _T_948 @[el2_lib.scala 235:17] + node _T_949 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 235:28] + node _T_950 = andr(_T_949) @[el2_lib.scala 235:36] + node _T_951 = and(_T_950, _T_930) @[el2_lib.scala 235:41] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 235:74] + node _T_953 = bits(dec_i0_match_data[3], 3, 3) @[el2_lib.scala 235:86] + node _T_954 = eq(_T_952, _T_953) @[el2_lib.scala 235:78] + node _T_955 = mux(_T_951, UInt<1>("h01"), _T_954) @[el2_lib.scala 235:23] + _T_927[3] <= _T_955 @[el2_lib.scala 235:17] + node _T_956 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 235:28] + node _T_957 = andr(_T_956) @[el2_lib.scala 235:36] + node _T_958 = and(_T_957, _T_930) @[el2_lib.scala 235:41] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 235:74] + node _T_960 = bits(dec_i0_match_data[3], 4, 4) @[el2_lib.scala 235:86] + node _T_961 = eq(_T_959, _T_960) @[el2_lib.scala 235:78] + node _T_962 = mux(_T_958, UInt<1>("h01"), _T_961) @[el2_lib.scala 235:23] + _T_927[4] <= _T_962 @[el2_lib.scala 235:17] + node _T_963 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 235:28] + node _T_964 = andr(_T_963) @[el2_lib.scala 235:36] + node _T_965 = and(_T_964, _T_930) @[el2_lib.scala 235:41] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 235:74] + node _T_967 = bits(dec_i0_match_data[3], 5, 5) @[el2_lib.scala 235:86] + node _T_968 = eq(_T_966, _T_967) @[el2_lib.scala 235:78] + node _T_969 = mux(_T_965, UInt<1>("h01"), _T_968) @[el2_lib.scala 235:23] + _T_927[5] <= _T_969 @[el2_lib.scala 235:17] + node _T_970 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 235:28] + node _T_971 = andr(_T_970) @[el2_lib.scala 235:36] + node _T_972 = and(_T_971, _T_930) @[el2_lib.scala 235:41] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 235:74] + node _T_974 = bits(dec_i0_match_data[3], 6, 6) @[el2_lib.scala 235:86] + node _T_975 = eq(_T_973, _T_974) @[el2_lib.scala 235:78] + node _T_976 = mux(_T_972, UInt<1>("h01"), _T_975) @[el2_lib.scala 235:23] + _T_927[6] <= _T_976 @[el2_lib.scala 235:17] + node _T_977 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 235:28] + node _T_978 = andr(_T_977) @[el2_lib.scala 235:36] + node _T_979 = and(_T_978, _T_930) @[el2_lib.scala 235:41] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 235:74] + node _T_981 = bits(dec_i0_match_data[3], 7, 7) @[el2_lib.scala 235:86] + node _T_982 = eq(_T_980, _T_981) @[el2_lib.scala 235:78] + node _T_983 = mux(_T_979, UInt<1>("h01"), _T_982) @[el2_lib.scala 235:23] + _T_927[7] <= _T_983 @[el2_lib.scala 235:17] + node _T_984 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 235:28] + node _T_985 = andr(_T_984) @[el2_lib.scala 235:36] + node _T_986 = and(_T_985, _T_930) @[el2_lib.scala 235:41] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 235:74] + node _T_988 = bits(dec_i0_match_data[3], 8, 8) @[el2_lib.scala 235:86] + node _T_989 = eq(_T_987, _T_988) @[el2_lib.scala 235:78] + node _T_990 = mux(_T_986, UInt<1>("h01"), _T_989) @[el2_lib.scala 235:23] + _T_927[8] <= _T_990 @[el2_lib.scala 235:17] + node _T_991 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 235:28] + node _T_992 = andr(_T_991) @[el2_lib.scala 235:36] + node _T_993 = and(_T_992, _T_930) @[el2_lib.scala 235:41] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 235:74] + node _T_995 = bits(dec_i0_match_data[3], 9, 9) @[el2_lib.scala 235:86] + node _T_996 = eq(_T_994, _T_995) @[el2_lib.scala 235:78] + node _T_997 = mux(_T_993, UInt<1>("h01"), _T_996) @[el2_lib.scala 235:23] + _T_927[9] <= _T_997 @[el2_lib.scala 235:17] + node _T_998 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 235:28] + node _T_999 = andr(_T_998) @[el2_lib.scala 235:36] + node _T_1000 = and(_T_999, _T_930) @[el2_lib.scala 235:41] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 235:74] + node _T_1002 = bits(dec_i0_match_data[3], 10, 10) @[el2_lib.scala 235:86] + node _T_1003 = eq(_T_1001, _T_1002) @[el2_lib.scala 235:78] + node _T_1004 = mux(_T_1000, UInt<1>("h01"), _T_1003) @[el2_lib.scala 235:23] + _T_927[10] <= _T_1004 @[el2_lib.scala 235:17] + node _T_1005 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 235:28] + node _T_1006 = andr(_T_1005) @[el2_lib.scala 235:36] + node _T_1007 = and(_T_1006, _T_930) @[el2_lib.scala 235:41] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 235:74] + node _T_1009 = bits(dec_i0_match_data[3], 11, 11) @[el2_lib.scala 235:86] + node _T_1010 = eq(_T_1008, _T_1009) @[el2_lib.scala 235:78] + node _T_1011 = mux(_T_1007, UInt<1>("h01"), _T_1010) @[el2_lib.scala 235:23] + _T_927[11] <= _T_1011 @[el2_lib.scala 235:17] + node _T_1012 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 235:28] + node _T_1013 = andr(_T_1012) @[el2_lib.scala 235:36] + node _T_1014 = and(_T_1013, _T_930) @[el2_lib.scala 235:41] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 235:74] + node _T_1016 = bits(dec_i0_match_data[3], 12, 12) @[el2_lib.scala 235:86] + node _T_1017 = eq(_T_1015, _T_1016) @[el2_lib.scala 235:78] + node _T_1018 = mux(_T_1014, UInt<1>("h01"), _T_1017) @[el2_lib.scala 235:23] + _T_927[12] <= _T_1018 @[el2_lib.scala 235:17] + node _T_1019 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 235:28] + node _T_1020 = andr(_T_1019) @[el2_lib.scala 235:36] + node _T_1021 = and(_T_1020, _T_930) @[el2_lib.scala 235:41] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 235:74] + node _T_1023 = bits(dec_i0_match_data[3], 13, 13) @[el2_lib.scala 235:86] + node _T_1024 = eq(_T_1022, _T_1023) @[el2_lib.scala 235:78] + node _T_1025 = mux(_T_1021, UInt<1>("h01"), _T_1024) @[el2_lib.scala 235:23] + _T_927[13] <= _T_1025 @[el2_lib.scala 235:17] + node _T_1026 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 235:28] + node _T_1027 = andr(_T_1026) @[el2_lib.scala 235:36] + node _T_1028 = and(_T_1027, _T_930) @[el2_lib.scala 235:41] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 235:74] + node _T_1030 = bits(dec_i0_match_data[3], 14, 14) @[el2_lib.scala 235:86] + node _T_1031 = eq(_T_1029, _T_1030) @[el2_lib.scala 235:78] + node _T_1032 = mux(_T_1028, UInt<1>("h01"), _T_1031) @[el2_lib.scala 235:23] + _T_927[14] <= _T_1032 @[el2_lib.scala 235:17] + node _T_1033 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 235:28] + node _T_1034 = andr(_T_1033) @[el2_lib.scala 235:36] + node _T_1035 = and(_T_1034, _T_930) @[el2_lib.scala 235:41] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 235:74] + node _T_1037 = bits(dec_i0_match_data[3], 15, 15) @[el2_lib.scala 235:86] + node _T_1038 = eq(_T_1036, _T_1037) @[el2_lib.scala 235:78] + node _T_1039 = mux(_T_1035, UInt<1>("h01"), _T_1038) @[el2_lib.scala 235:23] + _T_927[15] <= _T_1039 @[el2_lib.scala 235:17] + node _T_1040 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 235:28] + node _T_1041 = andr(_T_1040) @[el2_lib.scala 235:36] + node _T_1042 = and(_T_1041, _T_930) @[el2_lib.scala 235:41] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 235:74] + node _T_1044 = bits(dec_i0_match_data[3], 16, 16) @[el2_lib.scala 235:86] + node _T_1045 = eq(_T_1043, _T_1044) @[el2_lib.scala 235:78] + node _T_1046 = mux(_T_1042, UInt<1>("h01"), _T_1045) @[el2_lib.scala 235:23] + _T_927[16] <= _T_1046 @[el2_lib.scala 235:17] + node _T_1047 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 235:28] + node _T_1048 = andr(_T_1047) @[el2_lib.scala 235:36] + node _T_1049 = and(_T_1048, _T_930) @[el2_lib.scala 235:41] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 235:74] + node _T_1051 = bits(dec_i0_match_data[3], 17, 17) @[el2_lib.scala 235:86] + node _T_1052 = eq(_T_1050, _T_1051) @[el2_lib.scala 235:78] + node _T_1053 = mux(_T_1049, UInt<1>("h01"), _T_1052) @[el2_lib.scala 235:23] + _T_927[17] <= _T_1053 @[el2_lib.scala 235:17] + node _T_1054 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 235:28] + node _T_1055 = andr(_T_1054) @[el2_lib.scala 235:36] + node _T_1056 = and(_T_1055, _T_930) @[el2_lib.scala 235:41] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 235:74] + node _T_1058 = bits(dec_i0_match_data[3], 18, 18) @[el2_lib.scala 235:86] + node _T_1059 = eq(_T_1057, _T_1058) @[el2_lib.scala 235:78] + node _T_1060 = mux(_T_1056, UInt<1>("h01"), _T_1059) @[el2_lib.scala 235:23] + _T_927[18] <= _T_1060 @[el2_lib.scala 235:17] + node _T_1061 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 235:28] + node _T_1062 = andr(_T_1061) @[el2_lib.scala 235:36] + node _T_1063 = and(_T_1062, _T_930) @[el2_lib.scala 235:41] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 235:74] + node _T_1065 = bits(dec_i0_match_data[3], 19, 19) @[el2_lib.scala 235:86] + node _T_1066 = eq(_T_1064, _T_1065) @[el2_lib.scala 235:78] + node _T_1067 = mux(_T_1063, UInt<1>("h01"), _T_1066) @[el2_lib.scala 235:23] + _T_927[19] <= _T_1067 @[el2_lib.scala 235:17] + node _T_1068 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 235:28] + node _T_1069 = andr(_T_1068) @[el2_lib.scala 235:36] + node _T_1070 = and(_T_1069, _T_930) @[el2_lib.scala 235:41] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 235:74] + node _T_1072 = bits(dec_i0_match_data[3], 20, 20) @[el2_lib.scala 235:86] + node _T_1073 = eq(_T_1071, _T_1072) @[el2_lib.scala 235:78] + node _T_1074 = mux(_T_1070, UInt<1>("h01"), _T_1073) @[el2_lib.scala 235:23] + _T_927[20] <= _T_1074 @[el2_lib.scala 235:17] + node _T_1075 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 235:28] + node _T_1076 = andr(_T_1075) @[el2_lib.scala 235:36] + node _T_1077 = and(_T_1076, _T_930) @[el2_lib.scala 235:41] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 235:74] + node _T_1079 = bits(dec_i0_match_data[3], 21, 21) @[el2_lib.scala 235:86] + node _T_1080 = eq(_T_1078, _T_1079) @[el2_lib.scala 235:78] + node _T_1081 = mux(_T_1077, UInt<1>("h01"), _T_1080) @[el2_lib.scala 235:23] + _T_927[21] <= _T_1081 @[el2_lib.scala 235:17] + node _T_1082 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 235:28] + node _T_1083 = andr(_T_1082) @[el2_lib.scala 235:36] + node _T_1084 = and(_T_1083, _T_930) @[el2_lib.scala 235:41] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 235:74] + node _T_1086 = bits(dec_i0_match_data[3], 22, 22) @[el2_lib.scala 235:86] + node _T_1087 = eq(_T_1085, _T_1086) @[el2_lib.scala 235:78] + node _T_1088 = mux(_T_1084, UInt<1>("h01"), _T_1087) @[el2_lib.scala 235:23] + _T_927[22] <= _T_1088 @[el2_lib.scala 235:17] + node _T_1089 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 235:28] + node _T_1090 = andr(_T_1089) @[el2_lib.scala 235:36] + node _T_1091 = and(_T_1090, _T_930) @[el2_lib.scala 235:41] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 235:74] + node _T_1093 = bits(dec_i0_match_data[3], 23, 23) @[el2_lib.scala 235:86] + node _T_1094 = eq(_T_1092, _T_1093) @[el2_lib.scala 235:78] + node _T_1095 = mux(_T_1091, UInt<1>("h01"), _T_1094) @[el2_lib.scala 235:23] + _T_927[23] <= _T_1095 @[el2_lib.scala 235:17] + node _T_1096 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 235:28] + node _T_1097 = andr(_T_1096) @[el2_lib.scala 235:36] + node _T_1098 = and(_T_1097, _T_930) @[el2_lib.scala 235:41] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 235:74] + node _T_1100 = bits(dec_i0_match_data[3], 24, 24) @[el2_lib.scala 235:86] + node _T_1101 = eq(_T_1099, _T_1100) @[el2_lib.scala 235:78] + node _T_1102 = mux(_T_1098, UInt<1>("h01"), _T_1101) @[el2_lib.scala 235:23] + _T_927[24] <= _T_1102 @[el2_lib.scala 235:17] + node _T_1103 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 235:28] + node _T_1104 = andr(_T_1103) @[el2_lib.scala 235:36] + node _T_1105 = and(_T_1104, _T_930) @[el2_lib.scala 235:41] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 235:74] + node _T_1107 = bits(dec_i0_match_data[3], 25, 25) @[el2_lib.scala 235:86] + node _T_1108 = eq(_T_1106, _T_1107) @[el2_lib.scala 235:78] + node _T_1109 = mux(_T_1105, UInt<1>("h01"), _T_1108) @[el2_lib.scala 235:23] + _T_927[25] <= _T_1109 @[el2_lib.scala 235:17] + node _T_1110 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 235:28] + node _T_1111 = andr(_T_1110) @[el2_lib.scala 235:36] + node _T_1112 = and(_T_1111, _T_930) @[el2_lib.scala 235:41] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 235:74] + node _T_1114 = bits(dec_i0_match_data[3], 26, 26) @[el2_lib.scala 235:86] + node _T_1115 = eq(_T_1113, _T_1114) @[el2_lib.scala 235:78] + node _T_1116 = mux(_T_1112, UInt<1>("h01"), _T_1115) @[el2_lib.scala 235:23] + _T_927[26] <= _T_1116 @[el2_lib.scala 235:17] + node _T_1117 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 235:28] + node _T_1118 = andr(_T_1117) @[el2_lib.scala 235:36] + node _T_1119 = and(_T_1118, _T_930) @[el2_lib.scala 235:41] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 235:74] + node _T_1121 = bits(dec_i0_match_data[3], 27, 27) @[el2_lib.scala 235:86] + node _T_1122 = eq(_T_1120, _T_1121) @[el2_lib.scala 235:78] + node _T_1123 = mux(_T_1119, UInt<1>("h01"), _T_1122) @[el2_lib.scala 235:23] + _T_927[27] <= _T_1123 @[el2_lib.scala 235:17] + node _T_1124 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 235:28] + node _T_1125 = andr(_T_1124) @[el2_lib.scala 235:36] + node _T_1126 = and(_T_1125, _T_930) @[el2_lib.scala 235:41] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 235:74] + node _T_1128 = bits(dec_i0_match_data[3], 28, 28) @[el2_lib.scala 235:86] + node _T_1129 = eq(_T_1127, _T_1128) @[el2_lib.scala 235:78] + node _T_1130 = mux(_T_1126, UInt<1>("h01"), _T_1129) @[el2_lib.scala 235:23] + _T_927[28] <= _T_1130 @[el2_lib.scala 235:17] + node _T_1131 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 235:28] + node _T_1132 = andr(_T_1131) @[el2_lib.scala 235:36] + node _T_1133 = and(_T_1132, _T_930) @[el2_lib.scala 235:41] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 235:74] + node _T_1135 = bits(dec_i0_match_data[3], 29, 29) @[el2_lib.scala 235:86] + node _T_1136 = eq(_T_1134, _T_1135) @[el2_lib.scala 235:78] + node _T_1137 = mux(_T_1133, UInt<1>("h01"), _T_1136) @[el2_lib.scala 235:23] + _T_927[29] <= _T_1137 @[el2_lib.scala 235:17] + node _T_1138 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 235:28] + node _T_1139 = andr(_T_1138) @[el2_lib.scala 235:36] + node _T_1140 = and(_T_1139, _T_930) @[el2_lib.scala 235:41] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 235:74] + node _T_1142 = bits(dec_i0_match_data[3], 30, 30) @[el2_lib.scala 235:86] + node _T_1143 = eq(_T_1141, _T_1142) @[el2_lib.scala 235:78] + node _T_1144 = mux(_T_1140, UInt<1>("h01"), _T_1143) @[el2_lib.scala 235:23] + _T_927[30] <= _T_1144 @[el2_lib.scala 235:17] + node _T_1145 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 235:28] + node _T_1146 = andr(_T_1145) @[el2_lib.scala 235:36] + node _T_1147 = and(_T_1146, _T_930) @[el2_lib.scala 235:41] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 235:74] + node _T_1149 = bits(dec_i0_match_data[3], 31, 31) @[el2_lib.scala 235:86] + node _T_1150 = eq(_T_1148, _T_1149) @[el2_lib.scala 235:78] + node _T_1151 = mux(_T_1147, UInt<1>("h01"), _T_1150) @[el2_lib.scala 235:23] + _T_927[31] <= _T_1151 @[el2_lib.scala 235:17] + node _T_1152 = cat(_T_927[1], _T_927[0]) @[el2_lib.scala 236:14] + node _T_1153 = cat(_T_927[3], _T_927[2]) @[el2_lib.scala 236:14] + node _T_1154 = cat(_T_1153, _T_1152) @[el2_lib.scala 236:14] + node _T_1155 = cat(_T_927[5], _T_927[4]) @[el2_lib.scala 236:14] + node _T_1156 = cat(_T_927[7], _T_927[6]) @[el2_lib.scala 236:14] + node _T_1157 = cat(_T_1156, _T_1155) @[el2_lib.scala 236:14] + node _T_1158 = cat(_T_1157, _T_1154) @[el2_lib.scala 236:14] + node _T_1159 = cat(_T_927[9], _T_927[8]) @[el2_lib.scala 236:14] + node _T_1160 = cat(_T_927[11], _T_927[10]) @[el2_lib.scala 236:14] + node _T_1161 = cat(_T_1160, _T_1159) @[el2_lib.scala 236:14] + node _T_1162 = cat(_T_927[13], _T_927[12]) @[el2_lib.scala 236:14] + node _T_1163 = cat(_T_927[15], _T_927[14]) @[el2_lib.scala 236:14] + node _T_1164 = cat(_T_1163, _T_1162) @[el2_lib.scala 236:14] + node _T_1165 = cat(_T_1164, _T_1161) @[el2_lib.scala 236:14] + node _T_1166 = cat(_T_1165, _T_1158) @[el2_lib.scala 236:14] + node _T_1167 = cat(_T_927[17], _T_927[16]) @[el2_lib.scala 236:14] + node _T_1168 = cat(_T_927[19], _T_927[18]) @[el2_lib.scala 236:14] + node _T_1169 = cat(_T_1168, _T_1167) @[el2_lib.scala 236:14] + node _T_1170 = cat(_T_927[21], _T_927[20]) @[el2_lib.scala 236:14] + node _T_1171 = cat(_T_927[23], _T_927[22]) @[el2_lib.scala 236:14] + node _T_1172 = cat(_T_1171, _T_1170) @[el2_lib.scala 236:14] + node _T_1173 = cat(_T_1172, _T_1169) @[el2_lib.scala 236:14] + node _T_1174 = cat(_T_927[25], _T_927[24]) @[el2_lib.scala 236:14] + node _T_1175 = cat(_T_927[27], _T_927[26]) @[el2_lib.scala 236:14] + node _T_1176 = cat(_T_1175, _T_1174) @[el2_lib.scala 236:14] + node _T_1177 = cat(_T_927[29], _T_927[28]) @[el2_lib.scala 236:14] + node _T_1178 = cat(_T_927[31], _T_927[30]) @[el2_lib.scala 236:14] + node _T_1179 = cat(_T_1178, _T_1177) @[el2_lib.scala 236:14] + node _T_1180 = cat(_T_1179, _T_1176) @[el2_lib.scala 236:14] + node _T_1181 = cat(_T_1180, _T_1173) @[el2_lib.scala 236:14] + node _T_1182 = cat(_T_1181, _T_1166) @[el2_lib.scala 236:14] + node _T_1183 = and(_T_925, _T_1182) @[el2_dec_trigger.scala 15:109] + node _T_1184 = cat(_T_1183, _T_924) @[Cat.scala 29:58] + node _T_1185 = cat(_T_1184, _T_665) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_406) @[Cat.scala 29:58] + io.dec_i0_trigger_match_d <= _T_1186 @[el2_dec_trigger.scala 15:29] + diff --git a/el2_dec_trigger.v b/el2_dec_trigger.v new file mode 100644 index 00000000..32c37bca --- /dev/null +++ b/el2_dec_trigger.v @@ -0,0 +1,613 @@ +module el2_dec_trigger( + input clock, + input reset, + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_store, + input io_trigger_pkt_any_0_load, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_store, + input io_trigger_pkt_any_1_load, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_store, + input io_trigger_pkt_any_2_load, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_store, + input io_trigger_pkt_any_3_load, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input [30:0] io_dec_i0_pc_d, + output [3:0] io_dec_i0_trigger_match_d +); + wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63] + wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127] + wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63] + wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127] + wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63] + wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127] + wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63] + wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93] + wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127] + wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] + wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 232:45] + wire _T_152 = ~_T_151; // @[el2_lib.scala 232:39] + wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 232:37] + wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 233:52] + wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 233:41] + wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 235:41] + wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 235:78] + wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 235:23] + wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 235:41] + wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 235:78] + wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 235:23] + wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 235:41] + wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 235:78] + wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 235:23] + wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 235:41] + wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 235:78] + wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 235:23] + wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 235:41] + wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 235:78] + wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 235:23] + wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 235:41] + wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 235:78] + wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 235:23] + wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 235:41] + wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 235:78] + wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 235:23] + wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 235:41] + wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 235:78] + wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 235:23] + wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 235:41] + wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 235:78] + wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 235:23] + wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 235:41] + wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 235:78] + wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 235:23] + wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 235:41] + wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 235:78] + wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 235:23] + wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 235:41] + wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 235:78] + wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 235:23] + wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 235:41] + wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 235:78] + wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 235:23] + wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 235:41] + wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 235:78] + wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 235:23] + wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 235:41] + wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 235:78] + wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 235:23] + wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 235:41] + wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 235:78] + wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 235:23] + wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 235:41] + wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 235:78] + wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 235:23] + wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 235:41] + wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 235:78] + wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 235:23] + wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 235:41] + wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 235:78] + wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 235:23] + wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 235:41] + wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 235:78] + wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 235:23] + wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 235:41] + wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 235:78] + wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 235:23] + wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 235:41] + wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 235:78] + wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 235:23] + wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 235:41] + wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 235:78] + wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 235:23] + wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 235:41] + wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 235:78] + wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 235:23] + wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 235:41] + wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 235:78] + wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 235:23] + wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 235:41] + wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 235:78] + wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 235:23] + wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 235:41] + wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 235:78] + wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 235:23] + wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 235:41] + wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 235:78] + wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 235:23] + wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 235:41] + wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 235:78] + wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 235:23] + wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 235:41] + wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 235:78] + wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 235:23] + wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 235:41] + wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 235:78] + wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 235:23] + wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 236:14] + wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 236:14] + wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 236:14] + wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109] + wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] + wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 232:45] + wire _T_411 = ~_T_410; // @[el2_lib.scala 232:39] + wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 232:37] + wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 233:52] + wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 233:41] + wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 235:41] + wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 235:78] + wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 235:23] + wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 235:41] + wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 235:78] + wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 235:23] + wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 235:41] + wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 235:78] + wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 235:23] + wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 235:41] + wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 235:78] + wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 235:23] + wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 235:41] + wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 235:78] + wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 235:23] + wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 235:41] + wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 235:78] + wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 235:23] + wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 235:41] + wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 235:78] + wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 235:23] + wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 235:41] + wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 235:78] + wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 235:23] + wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 235:41] + wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 235:78] + wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 235:23] + wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 235:41] + wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 235:78] + wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 235:23] + wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 235:41] + wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 235:78] + wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 235:23] + wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 235:41] + wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 235:78] + wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 235:23] + wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 235:41] + wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 235:78] + wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 235:23] + wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 235:41] + wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 235:78] + wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 235:23] + wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 235:41] + wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 235:78] + wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 235:23] + wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 235:41] + wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 235:78] + wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 235:23] + wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 235:41] + wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 235:78] + wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 235:23] + wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 235:41] + wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 235:78] + wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 235:23] + wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 235:41] + wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 235:78] + wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 235:23] + wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 235:41] + wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 235:78] + wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 235:23] + wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 235:41] + wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 235:78] + wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 235:23] + wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 235:41] + wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 235:78] + wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 235:23] + wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 235:41] + wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 235:78] + wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 235:23] + wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 235:41] + wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 235:78] + wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 235:23] + wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 235:41] + wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 235:78] + wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 235:23] + wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 235:41] + wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 235:78] + wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 235:23] + wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 235:41] + wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 235:78] + wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 235:23] + wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 235:41] + wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 235:78] + wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 235:23] + wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 235:41] + wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 235:78] + wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 235:23] + wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 235:41] + wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 235:78] + wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 235:23] + wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 235:41] + wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 235:78] + wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 235:23] + wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 236:14] + wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 236:14] + wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 236:14] + wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109] + wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] + wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 232:45] + wire _T_670 = ~_T_669; // @[el2_lib.scala 232:39] + wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 232:37] + wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 233:52] + wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 233:41] + wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 235:41] + wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 235:78] + wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 235:23] + wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 235:41] + wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 235:78] + wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 235:23] + wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 235:41] + wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 235:78] + wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 235:23] + wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 235:41] + wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 235:78] + wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 235:23] + wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 235:41] + wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 235:78] + wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 235:23] + wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 235:41] + wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 235:78] + wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 235:23] + wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 235:41] + wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 235:78] + wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 235:23] + wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 235:41] + wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 235:78] + wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 235:23] + wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 235:41] + wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 235:78] + wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 235:23] + wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 235:41] + wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 235:78] + wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 235:23] + wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 235:41] + wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 235:78] + wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 235:23] + wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 235:41] + wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 235:78] + wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 235:23] + wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 235:41] + wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 235:78] + wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 235:23] + wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 235:41] + wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 235:78] + wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 235:23] + wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 235:41] + wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 235:78] + wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 235:23] + wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 235:41] + wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 235:78] + wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 235:23] + wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 235:41] + wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 235:78] + wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 235:23] + wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 235:41] + wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 235:78] + wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 235:23] + wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 235:41] + wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 235:78] + wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 235:23] + wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 235:41] + wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 235:78] + wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 235:23] + wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 235:41] + wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 235:78] + wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 235:23] + wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 235:41] + wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 235:78] + wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 235:23] + wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 235:41] + wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 235:78] + wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 235:23] + wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 235:41] + wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 235:78] + wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 235:23] + wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 235:41] + wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 235:78] + wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 235:23] + wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 235:41] + wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 235:78] + wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 235:23] + wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 235:41] + wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 235:78] + wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 235:23] + wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 235:41] + wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 235:78] + wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 235:23] + wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 235:41] + wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 235:78] + wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 235:23] + wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 235:41] + wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 235:78] + wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 235:23] + wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 235:41] + wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 235:78] + wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 235:23] + wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 236:14] + wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 236:14] + wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 236:14] + wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109] + wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] + wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 232:45] + wire _T_929 = ~_T_928; // @[el2_lib.scala 232:39] + wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 232:37] + wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 233:52] + wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 233:41] + wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 235:36] + wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 235:41] + wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 235:78] + wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 235:23] + wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 235:36] + wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 235:41] + wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 235:78] + wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 235:23] + wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 235:36] + wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 235:41] + wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 235:78] + wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 235:23] + wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 235:36] + wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 235:41] + wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 235:78] + wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 235:23] + wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 235:36] + wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 235:41] + wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 235:78] + wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 235:23] + wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 235:36] + wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 235:41] + wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 235:78] + wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 235:23] + wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 235:36] + wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 235:41] + wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 235:78] + wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 235:23] + wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 235:36] + wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 235:41] + wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 235:78] + wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 235:23] + wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 235:36] + wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 235:41] + wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 235:78] + wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 235:23] + wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 235:36] + wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 235:78] + wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 235:23] + wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 235:36] + wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 235:78] + wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 235:23] + wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 235:36] + wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 235:78] + wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 235:23] + wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 235:36] + wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 235:78] + wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 235:23] + wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 235:36] + wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 235:78] + wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 235:23] + wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 235:36] + wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 235:78] + wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 235:23] + wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 235:36] + wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 235:78] + wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 235:23] + wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 235:36] + wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 235:78] + wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 235:23] + wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 235:36] + wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 235:78] + wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 235:23] + wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 235:36] + wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 235:78] + wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 235:23] + wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 235:36] + wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 235:78] + wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 235:23] + wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 235:36] + wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 235:78] + wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 235:23] + wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 235:36] + wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 235:78] + wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 235:23] + wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 235:36] + wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 235:78] + wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 235:23] + wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 235:36] + wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 235:78] + wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 235:23] + wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 235:36] + wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 235:78] + wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 235:23] + wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 235:36] + wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 235:78] + wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 235:23] + wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 235:36] + wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 235:78] + wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 235:23] + wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 235:36] + wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 235:78] + wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 235:23] + wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 235:36] + wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 235:78] + wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 235:23] + wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 235:36] + wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 235:78] + wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 235:23] + wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 235:36] + wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 235:41] + wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 235:78] + wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 235:23] + wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 236:14] + wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 236:14] + wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 236:14] + wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 236:14] + wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109] + wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109] + wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29] +endmodule diff --git a/src/main/scala/dec/el2_dec.scala b/src/main/scala/dec/el2_dec.scala new file mode 100644 index 00000000..af6d3ac8 --- /dev/null +++ b/src/main/scala/dec/el2_dec.scala @@ -0,0 +1,713 @@ +package dec +import chisel3._ +import include._ +import lib._ + +class el2_dec_IO extends Bundle with el2_lib { + //val clk = Input(Clock()) + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + + val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + val dec_extint_stall = Output(Bool()) + + val dec_i0_decode_d = Output(Bool()) + val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating + + // val rst_l = Input(Bool()) // reset, active low + val rst_vec = Input(UInt(32.W)) // [31:1] reset vector, from core pins + + val nmi_int = Input(Bool()) // NMI pin + val nmi_vec = Input(UInt(32.W)) // [31:1] NMI vector, from pins + + val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU + + val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw) + val o_cpu_halt_ack = Output(Bool()) // Halt request ack + val o_cpu_run_ack = Output(Bool()) // Run request ack + val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + val core_id = Input(UInt(32.W)) // [31:4] CORE ID + + // external MPC halt/run interface + val mpc_debug_halt_req = Input(Bool()) // Async halt request + val mpc_debug_run_req = Input(Bool()) // Async run request + val mpc_reset_run_req = Input(Bool()) // Run/halt after reset + val mpc_debug_halt_ack = Output(Bool()) // Halt ack + val mpc_debug_run_ack = Output(Bool()) // Run ack + val debug_brkpt_status = Output(Bool()) // debug breakpoint + + val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp + val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken + val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch + + + val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m + val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r + val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back + val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error + val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data + + val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction + val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned + val lsu_pmu_bus_error = Input(Bool()) // D side bus error + val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy + val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned + val lsu_pmu_load_external_m = Input(Bool()) // D side bus load + val lsu_pmu_store_external_m = Input(Bool()) // D side bus store + val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read + val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write + val dma_pmu_any_read = Input(Bool()) // DMA read + val dma_pmu_any_write = Input(Bool()) // DMA write + + val lsu_fir_addr = Input(UInt(32.W)) //[31:1] Fast int address + val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error + + val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions + val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled + val ifu_pmu_ic_miss = Input(Bool()) // icache miss + val ifu_pmu_ic_hit = Input(Bool()) // icache hit + val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error + val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy + val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction + + val ifu_ic_error_start = Input(Bool()) // IC single bit error + val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error + + val lsu_trigger_match_m = Input(UInt(4.W)) + val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid + val dbg_cmd_write = Input(Bool()) // command is a write + val dbg_cmd_type = Input(UInt(2.W)) // command type + val dbg_cmd_addr = Input(UInt(32.W)) // command address + val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i + + + val ifu_i0_icaf = Input(Bool()) // icache access fault + val ifu_i0_icaf_type = Input(UInt(2.W)) + + val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group + val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error + + val lsu_idle_any = Input(Bool()) // lsu idle for halting + + val i0_brp = Input(new el2_br_pkt_t) // branch packet + val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index + val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet + val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter + + val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error + val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address + + val exu_div_result = Input(UInt(32.W)) // final div result + val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR + val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data + + val lsu_load_stall_any = Input(Bool()) // This is for blocking loads + val lsu_store_stall_any = Input(Bool()) // This is for blocking stores + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event + val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event + + val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error + + val exu_flush_final = Input(Bool()) // slot0 flush + + val exu_npc_r = Input(UInt(32.W)) // next PC + + val exu_i0_result_x = Input(UInt(32.W)) // alu result x + + + val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer + val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer + val ifu_i0_pc = Input(UInt(32.W)) // pc's for instruction buffer + val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst + val exu_i0_pc_x = Input(UInt(32.W)) // pc's for e1 from the alu's + + val mexintpend = Input(Bool()) // External interrupt pending + val timer_int = Input(Bool()) // Timer interrupt pending (from pin) + val soft_int = Input(Bool()) // Software interrupt pending (from pin) + + val pic_claimid = Input(UInt(8.W)) // PIC claimid + val pic_pl = Input(UInt(4.W)) // PIC priv level + val mhwakeup = Input(Bool()) // High priority wakeup + + val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level + val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + + val ifu_ic_debug_rd_data = Input(UInt(70.W)) // diagnostic icache read data + val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + + + // Debug start + val dbg_halt_req = Input(Bool()) // DM requests a halt + val dbg_resume_req = Input(Bool()) // DM requests a resume + val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty + + val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command + val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode + val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge + val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush + val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC + val dec_tlu_flush_leak_one_r = Output(Bool()) // single step + val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc + val dec_tlu_meihap = Output(UInt(32.W)) // Fast ext int base + + val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode + + val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data + + val dec_dbg_cmd_done = Output(Bool()) // abstract command is done + val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address) + + val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks + + val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced + // Debug end + // branch info from pipe0 for errors or counter updates + val exu_i0_br_hist_r = Input(UInt(2.W)) // history + val exu_i0_br_error_r = Input(Bool()) // error + val exu_i0_br_start_error_r = Input(Bool()) // start error + val exu_i0_br_valid_r = Input(Bool()) // valid + val exu_i0_br_mp_r = Input(Bool()) // mispredict + val exu_i0_br_middle_r = Input(Bool()) // middle of bank + + val exu_i0_br_way_r = Input(Bool()) // way hit or repl + + val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data + val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data + val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data + val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data + + val dec_i0_immed_d = Output(UInt(32.W)) // immediate data + val dec_i0_br_immed_d = Output(UInt(13.W)) // br immediate data + + val i0_ap = Output(new el2_alu_pkt_t)// alu packet + + val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu + + val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's + + val dec_i0_pc_d = Output(UInt(32.W)) // pc's at decode + val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable + val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable + + val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data + val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data + + val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet + val mul_p = Output(new el2_mul_pkt_t) // mul packet + val div_p = Output(new el2_div_pkt_t) // div packet + val dec_div_cancel = Output(Bool()) // cancel divide operation + + val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses + + val dec_csr_ren_d = Output(Bool()) // csr read enable + + + val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int + val dec_tlu_flush_path_r = Output(UInt(32.W)) // tlu flush target + val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache + + val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage + + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet + + val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc + val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc + val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc + val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc + + val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus + val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr + val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index + val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag + + val dec_lsu_valid_raw_d = Output(Bool()) + + val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control + + val dec_data_en = Output(UInt(2.W)) // clock-gate control logic + val dec_ctl_en = Output(UInt(2.W)) + + val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction + + // val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet + + // feature disable from mfdc + val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding + val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address + val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC + val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction + val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating + val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating + val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating + val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating + val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating + val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating + val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating + + val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction + val scan_mode = Input(Bool()) + +} + +class el2_dec extends Module with param with RequireAsyncReset{ + val io = IO(new el2_dec_IO) + io.dec_i0_pc_d := 0.U + + + + // val dec_ib0_valid_d = WireInit(Bool(),0.B) + // + // val dec_pmu_instr_decoded = WireInit(Bool(),0.B) + // val dec_pmu_decode_stall = WireInit(Bool(),0.B) + // val dec_pmu_presync_stall = WireInit(Bool(),0.B) + // val dec_pmu_postsync_stall = WireInit(Bool(),0.B) + // + // val dec_tlu_wr_pause_r = WireInit(UInt(1.W),0.U) // CSR write to pause reg is at R. + // + // val dec_i0_rs1_d = WireInit(UInt(5.W),0.U) + // val dec_i0_rs2_d = WireInit(UInt(5.W),0.U) + // + // val dec_i0_instr_d = WireInit(UInt(32.W),0.U) + // + // val dec_tlu_pipelining_disable = WireInit(UInt(1.W),0.U) + // val dec_i0_waddr_r = WireInit(UInt(5.W),0.U) + // val dec_i0_wen_r = WireInit(UInt(5.W),0.U) + // val dec_i0_wdata_r = WireInit(UInt(32.W),0.U) + // val dec_csr_wen_r = WireInit(UInt(1.W),0.U) // csr write enable at wb + // val dec_csr_wraddr_r = WireInit(UInt(12.W),0.U) // write address for csryes + // val dec_csr_wrdata_r = WireInit(UInt(32.W),0.U) // csr write data at wb + // + // val dec_csr_rdaddr_d = WireInit(UInt(12.W),0.U) // read address for csr + // val dec_csr_rddata_d = WireInit(UInt(32.W),0.U) // csr read data at wb + // val dec_csr_legal_d = WireInit(Bool(),0.B) // csr indicates legal operation + // + // val dec_csr_wen_unq_d = WireInit(Bool(),0.B) // valid csr with write - for csr legal + // val dec_csr_any_unq_d = WireInit(Bool(),0.B) // valid csr - for csr legal + // val dec_csr_stall_int_ff = WireInit(Bool(),0.B) // csr is mie/mstatus + // + // val dec_tlu_packet_r = Wire(new el2_trap_pkt_t) + // + // val dec_i0_pc4_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_presync_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_postsync_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_debug_stall = WireInit(UInt(1.W),0.U) + // val dec_illegal_inst = WireInit(UInt(32.W),0.U) + // val dec_i0_icaf_d = WireInit(UInt(1.W),0.U) + // val dec_i0_dbecc_d = WireInit(UInt(1.W),0.U) + // val dec_i0_icaf_f1_d = WireInit(UInt(1.W),0.U) + // val dec_i0_trigger_match_d = WireInit(UInt(4.W),0.U) + // val dec_debug_fence_d = WireInit(UInt(1.W),0.U) + // val dec_nonblock_load_wen = WireInit(UInt(1.W),0.U) + // val dec_nonblock_load_waddr = WireInit(UInt(5.W),0.U) + // val dec_tlu_flush_pause_r = WireInit(UInt(1.W),0.U) + // val dec_i0_brp = Wire(new el2_br_pkt_t) + // val dec_i0_bp_index = WireInit(UInt(BTB_ADDR_HI.W),0.U) + // val dec_i0_bp_fghr = WireInit(UInt(BHT_GHR_SIZE.W),0.U) + // val dec_i0_bp_btag = WireInit(UInt(BTB_BTAG_SIZE.W),0.U) + // + // val dec_tlu_i0_pc_r = WireInit(UInt(32.W),0.U) + // val dec_tlu_i0_kill_writeb_wb = WireInit(Bool(),0.B) + // val dec_tlu_flush_lower_wb = WireInit(Bool(),0.B) + // val dec_tlu_i0_valid_r = WireInit(Bool(),0.B) + // + // val dec_pause_state = WireInit(Bool(),0.B) + // + // val dec_i0_icaf_type_d = WireInit(UInt(2.W),0.U) // i0 instruction access fault type + // + // val dec_tlu_flush_extint = WireInit(Bool(),0.B)// Fast ext int started + // + val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U) + val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U) + val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U) + + val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U) + val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B) + // + // val div_waddr_wb = WireInit(UInt(5.W),0.U) + // + // val dec_div_active = WireInit(Bool(),0.B) + + + //--------------------------------------------------------------------------// + val instbuff = Module(new el2_dec_ib_ctl) + val decode = Module(new el2_dec_decode_ctl) + val gpr = Module(new el2_dec_gpr_ctl) + val tlu = Module(new el2_dec_tlu_ctl) + val dec_trigger = Module(new el2_dec_trigger) + + //instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO(" + //--------------------------------------------------------------------------// + + //connections for el2_dec_Ib + //inputs + instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid + instbuff.io.dbg_cmd_write := io.dbg_cmd_write + instbuff.io.dbg_cmd_type := io.dbg_cmd_type + instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr + instbuff.io.i0_brp := io.i0_brp + instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index + instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr + instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag + instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4 + instbuff.io.ifu_i0_valid := io.ifu_i0_valid + instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf + instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type + instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1 + instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc + instbuff.io.ifu_i0_instr := io.ifu_i0_instr + instbuff.io.ifu_i0_pc := io.ifu_i0_pc + //outputs + decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d + decode.io.dec_i0_icaf_type_d :=instbuff.io.dec_i0_icaf_type_d + decode.io.dec_i0_instr_d :=instbuff.io.dec_i0_instr_d + decode.io.dec_i0_pc_d :=instbuff.io.dec_i0_pc_d + decode.io.dec_i0_pc4_d :=instbuff.io.dec_i0_pc4_d + decode.io.dec_i0_brp :=instbuff.io.dec_i0_brp + decode.io.dec_i0_bp_index :=instbuff.io.dec_i0_bp_index + decode.io.dec_i0_bp_fghr :=instbuff.io.dec_i0_bp_fghr + decode.io.dec_i0_bp_btag :=instbuff.io.dec_i0_bp_btag + decode.io.dec_i0_icaf_d :=instbuff.io.dec_i0_icaf_d + decode.io.dec_i0_icaf_f1_d :=instbuff.io.dec_i0_icaf_f1_d + decode.io.dec_i0_dbecc_d :=instbuff.io.dec_i0_dbecc_d + io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d + decode.io.dec_debug_fence_d :=instbuff.io.dec_debug_fence_d + //--------------------------------------------------------------------------// + + //connections for dec_trigger + //dec_trigger.io <> io + //inputs + dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d + dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any + //output + val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d + dontTouch(dec_i0_trigger_match_d) + //--------------------------------------------------------------------------// + + //connections for el2_dec_decode + // decode.io <> io + //inputs + decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint + decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt + decode.io.ifu_i0_cinst := io.ifu_i0_cinst + decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m + decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m + decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r + decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r + decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid + decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error + decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag + decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data + decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d + decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r + decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable + decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m + decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned + decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall + decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r + decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d + decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata + decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d + decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d + decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d + decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d + decode.io.dec_i0_brp := instbuff.io.dec_i0_brp + decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index + decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr + decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag + decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d + decode.io.lsu_idle_any := io.lsu_idle_any + decode.io.lsu_load_stall_any := io.lsu_load_stall_any + decode.io.lsu_store_stall_any := io.lsu_store_stall_any + decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any + decode.io.exu_div_wren := io.exu_div_wren + decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r + decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r + decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d + decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d + decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc_d + decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d + decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x + decode.io.lsu_result_m := io.lsu_result_m + decode.io.lsu_result_corr_r := io.lsu_result_corr_r + decode.io.exu_flush_final := io.exu_flush_final + decode.io.exu_i0_pc_x := io.exu_i0_pc_x + decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d + decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d + decode.io.exu_i0_result_x := io.exu_i0_result_x + //decode.io.clk := io.clk + decode.io.free_clk := io.free_clk + decode.io.active_clk := io.active_clk + decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override + // decode.io.rst_l := io.rst_l + decode.io.scan_mode := io.scan_mode + //outputs + io.dec_extint_stall := decode.io.dec_extint_stall + dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer + dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer + io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d + io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d + gpr.io.raddr0 := decode.io.dec_i0_rs1_d + gpr.io.raddr1 := decode.io.dec_i0_rs2_d + io.dec_i0_immed_d := decode.io.dec_i0_immed_d + io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d + io.i0_ap := decode.io.i0_ap + io.dec_i0_decode_d := decode.io.dec_i0_decode_d + io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d + io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d + io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d + gpr.io.waddr0 := decode.io.dec_i0_waddr_r + gpr.io.wen0 := decode.io.dec_i0_wen_r + gpr.io.wd0 := decode.io.dec_i0_wdata_r + io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d + io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d + io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d + io.lsu_p := decode.io.lsu_p + io.mul_p := decode.io.mul_p + io.div_p := decode.io.div_p + gpr.io.waddr2 := decode.io.div_waddr_wb + io.dec_div_cancel := decode.io.dec_div_cancel + io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d + io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d + io.dec_csr_ren_d := decode.io.dec_csr_ren_d + tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d + tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d + tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d + tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r + tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r + tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r + tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff + tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r + tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r + tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r + tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst + io.pred_correct_npc_x := decode.io.pred_correct_npc_x + io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d + io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d + io.i0_predict_index_d := decode.io.i0_predict_index_d + io.i0_predict_btag_d := decode.io.i0_predict_btag_d + io.dec_data_en := decode.io.dec_data_en + io.dec_ctl_en := decode.io.dec_ctl_en + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_instr_decoded + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_decode_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_presync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_wen + tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_waddr + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pause_state + io.dec_pause_state_cg := decode.io.dec_pause_state_cg + tlu.io.dec_div_active := decode.io.dec_div_active + //--------------------------------------------------------------------------// + + + //connections for gprfile + // gpr.io <> io + //inputs + gpr.io.raddr0 := decode.io.dec_i0_rs1_d + gpr.io.raddr1 := decode.io.dec_i0_rs2_d + gpr.io.wen0 := decode.io.dec_i0_wen_r + gpr.io.waddr0 := decode.io.dec_i0_waddr_r + gpr.io.wd0 := decode.io.dec_i0_wdata_r + gpr.io.wen1 := decode.io.dec_nonblock_load_wen + gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr + gpr.io.wd1 := io.lsu_nonblock_load_data + gpr.io.wen2 := io.exu_div_wren + gpr.io.waddr2 := decode.io.div_waddr_wb + gpr.io.wd2 := io.exu_div_result + //gpr.io.clk := io.clk + //gpr.io.rst_l := io.rst_l + gpr.io.scan_mode := io.scan_mode + // outputs + io.gpr_i0_rs1_d := gpr.io.rd0 + io.gpr_i0_rs2_d := gpr.io.rd1 + //--------------------------------------------------------------------------// + + + + //connection for dec_tlu + // tlu.io <> io + //inputs + //tlu.io.clk := io.clk + tlu.io.active_clk := io.active_clk + tlu.io.free_clk := io.free_clk + // tlu.io.rst_l := io.rst_l + tlu.io.scan_mode := io.scan_mode + tlu.io.rst_vec := io.rst_vec + tlu.io.nmi_int := io.nmi_int + tlu.io.nmi_vec := io.nmi_vec + tlu.io.i_cpu_halt_req := io.i_cpu_halt_req + tlu.io.i_cpu_run_req := io.i_cpu_run_req + tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any + tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned + tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall + tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss + tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit + tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error + tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy + tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn + tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded + tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall + tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall + tlu.io.lsu_store_stall_any := io.lsu_store_stall_any + tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any + tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any + tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp + tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken + tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4 + tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn + tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned + tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error + tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy + tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m + tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m + tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read + tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write + tlu.io.dma_pmu_any_read := io.dma_pmu_any_read + tlu.io.dma_pmu_any_write := io.dma_pmu_any_write + tlu.io.lsu_fir_addr := io.lsu_fir_addr + tlu.io.lsu_fir_error := io.lsu_fir_error + tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error + tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r + tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr + tlu.io.dec_pause_state := decode.io.dec_pause_state + tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any + tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any + tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any + tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d + tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d + tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d + tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r + tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r + tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r + tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff + tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r + tlu.io.exu_npc_r := io.exu_npc_r + tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r + tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r + tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst + tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d + tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r + tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r + tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r + tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r + tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r + tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r + tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r + tlu.io.dbg_halt_req := io.dbg_halt_req + tlu.io.dbg_resume_req := io.dbg_resume_req + tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle + tlu.io.lsu_idle_any := io.lsu_idle_any + tlu.io.dec_div_active := decode.io.dec_div_active + tlu.io.ifu_ic_error_start := io.ifu_ic_error_start + tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err + tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data + tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid + tlu.io.pic_claimid := io.pic_claimid + tlu.io.pic_pl := io.pic_pl + tlu.io.mhwakeup := io.mhwakeup + tlu.io.mexintpend := io.mexintpend + tlu.io.timer_int := io.timer_int + tlu.io.soft_int := io.soft_int + tlu.io.core_id := io.core_id + tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req + tlu.io.mpc_debug_run_req := io.mpc_debug_run_req + tlu.io.mpc_reset_run_req := io.mpc_reset_run_req + //outputs + io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done + io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail + io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted + io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode + io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack + decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall + io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r + io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only + io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r + io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r + decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint + io.dec_tlu_meihap := tlu.io.dec_tlu_meihap + io.trigger_pkt_any := tlu.io.trigger_pkt_any + io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt + io.o_cpu_halt_status := tlu.io.o_cpu_halt_status + io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack + io.o_cpu_run_ack := tlu.io.o_cpu_run_ack + io.o_debug_mode_status := tlu.io.o_debug_mode_status + io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack + io.debug_brkpt_status := tlu.io.debug_brkpt_status + io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl + io.dec_tlu_meipt := tlu.io.dec_tlu_meipt + decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d + io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt + decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt + io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r + io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r + io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r + decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r + decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r + decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d + decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d + io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff + io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt + io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3 + dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1 + dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1 + dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 + dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 + dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 + io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable + io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable + io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable + io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable + io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable + // := tlu.io.dec_tlu_pipelining_disable + io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty + io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override + //decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override + io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override + + //--------------------------------------------------------------------------// + + + + // debug command read data + io.dec_dbg_rddata := decode.io.dec_i0_wdata_r +} +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec())) +} diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala new file mode 100644 index 00000000..46932215 --- /dev/null +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -0,0 +1,827 @@ +package dec +import chisel3._ +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ + +class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ + val io = IO(new Bundle{ + + val dec_tlu_flush_extint = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event + val dec_extint_stall = Output(Bool()) + val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction + val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder + val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder + val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m + val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r + val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back + val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error + val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data + val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches + val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r + val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only + val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches + val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign + val dec_tlu_debug_stall = Input(Bool()) // debug stall decode + val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction + val dec_debug_fence_d = Input(Bool()) // debug fence instruction + val dbg_cmd_wrdata = Input(UInt(2.W)) // disambiguate fence, fence_i + val dec_i0_icaf_d = Input(Bool()) // icache access fault + val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type + val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error + val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet + val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_pc_d = Input(UInt(31.W)) // pc + val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode + val lsu_load_stall_any = Input(Bool()) // stall any load at decode + val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode + val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. + val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush + val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush + val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush + val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd + val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B + val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation + val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing + val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D + val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1 + val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode + val dec_ib0_valid_d = Input(Bool()) // inst valid at decode + val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) // clk except for halt / pause + val clk_override = Input(Bool()) // test stuff + + val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode + val dec_i0_rs2_en_d = Output(Bool()) + val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source + val dec_i0_rs2_d = Output(UInt(5.W)) + val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode + val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate + val i0_ap = Output(new el2_alu_pkt_t) // alu packets + val dec_i0_decode_d = Output(Bool()) // i0 decode + val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu + val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data + val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data + val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's + val dec_i0_wen_r = Output(Bool()) // i0 write enable + val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data + val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches + val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable + val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable + val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet + val mul_p = Output(new el2_mul_pkt_t) // multiply packet + val div_p = Output(new el2_div_pkt_t) // divide packet + val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR + val dec_div_cancel = Output(Bool()) // cancel the divide operation + val dec_lsu_valid_raw_d = Output(Bool()) + val dec_lsu_offset_d = Output(UInt(12.W)) + val dec_csr_ren_d = Output(Bool()) // valid csr decode + val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal + val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr + val dec_csr_wen_r = Output(Bool()) // csr write enable at r + val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r + val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus + val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c + val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet + val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc + val dec_illegal_inst = Output(UInt(32.W)) // illegal inst + val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct + val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode + val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr + val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index + val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag + val dec_data_en = Output(UInt(2.W)) // clock-gating logic + val dec_ctl_en = Output(UInt(2.W)) + val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded + val dec_pmu_decode_stall = Output(Bool()) // decode is stalled + val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall + val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall + val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load + val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load + val dec_pause_state = Output(Bool()) // core in pause state + val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating + val dec_div_active = Output(Bool()) // non-block divide is active + val scan_mode = Input(Bool()) + }) + ///////////////////////////////////////////////////////////////////////////////////////// + // //packets zero initialization + io.mul_p := 0.U.asTypeOf(io.mul_p) + // Vals defined + val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) + val i0r = Wire(new el2_reg_pkt_t) + val d_t = Wire(new el2_trap_pkt_t) + val x_t = Wire(new el2_trap_pkt_t) + val x_t_in = Wire(new el2_trap_pkt_t) + val r_t = Wire(new el2_trap_pkt_t) + val r_t_in = Wire(new el2_trap_pkt_t) + val d_d = Wire(new el2_dest_pkt_t) + val x_d = Wire(new el2_dest_pkt_t) + val r_d = Wire(new el2_dest_pkt_t) + val r_d_in = Wire(new el2_dest_pkt_t) + val wbd = Wire(new el2_dest_pkt_t) + val i0_d_c = Wire(new el2_class_pkt_t) + val i0_rs1_class_d = Wire(new el2_class_pkt_t) + val i0_rs2_class_d = Wire(new el2_class_pkt_t) + val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) + val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) + val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + val cam_write=WireInit(UInt(1.W), 0.U) + val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + //val i0_temp = Wire(new el2_inst_pkt_t) + val i0_dp= Wire(new el2_dec_pkt_t) + val i0_dp_raw= Wire(new el2_dec_pkt_t) + val i0_rs1bypass = WireInit(UInt(3.W), 0.U) + val i0_rs2bypass = WireInit(UInt(3.W), 0.U) + val illegal_lockout = WireInit(UInt(1.W), 0.U) + val postsync_stall = WireInit(UInt(1.W), 0.U) + val ps_stall_in = WireInit(UInt(1.W), 0.U) + val i0_pipe_en = WireInit(UInt(4.W), 0.U) + val i0_load_block_d = WireInit(UInt(1.W), 0.U) + val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_m = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) + val leak1_i1_stall = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall = WireInit(UInt(1.W), 0.U) + val pause_state = WireInit(Bool(), 0.B) + val flush_final_r = WireInit(UInt(1.W), 0.U) + val illegal_lockout_in = WireInit(UInt(1.W), 0.U) + val lsu_idle = WireInit(Bool(), 0.B) + val pause_state_in = WireInit(Bool(), 0.B) + val leak1_mode = WireInit(UInt(1.W), 0.U) + val i0_pcall = WireInit(UInt(1.W), 0.U) + val i0_pja = WireInit(UInt(1.W), 0.U) + val i0_pret = WireInit(UInt(1.W), 0.U) + val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) + val i0_pcall_raw = WireInit(UInt(1.W), 0.U) + val i0_pja_raw = WireInit(UInt(1.W), 0.U) + val i0_pret_raw = WireInit(UInt(1.W), 0.U) + val i0_br_offset = WireInit(UInt(12.W), 0.U) + val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) + val i0_jal = WireInit(UInt(1.W), 0.U) + val i0_wen_r = WireInit(UInt(1.W), 0.U) + val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_x_data_en = WireInit(UInt(1.W), 0.U) + val i0_r_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) + val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) + val csr_ren_qual_d = WireInit(Bool(), 0.B) + val lsu_decode_d = WireInit(UInt(1.W), 0.U) + val mul_decode_d = WireInit(UInt(1.W), 0.U) + val div_decode_d = WireInit(UInt(1.W), 0.U) + val write_csr_data = WireInit(UInt(32.W),0.U) + val i0_result_corr_r = WireInit(UInt(32.W),0.U) + val presync_stall = WireInit(UInt(1.W), 0.U) + val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) + val debug_fence = WireInit(Bool(), 0.B) + val i0_immed_d = WireInit(UInt(32.W), 0.U) + val i0_result_x = WireInit(UInt(32.W), 0.U) + val i0_result_r = WireInit(UInt(32.W), 0.U) + ////////////////////////////////////////////////////////////////////// + // Start - Data gating {{ + + val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk + (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk + (io.dec_tlu_flush_extint ^ io.dec_extint_stall) | + (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk + (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk + (pause_state_in ^ pause_state ) | // replaces free_clk + (ps_stall_in ^ postsync_stall ) | // replaces free_clk + (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk + (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk + + val data_gated_cgc= Module(new rvclkhdr) + data_gated_cgc.io.en := data_gate_en + data_gated_cgc.io.scan_mode :=io.scan_mode + data_gated_cgc.io.clk :=clock + val data_gate_clk =data_gated_cgc.io.l1clk + + // End - Data gating }} + + val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode + io.dec_i0_predict_p_d.misp :=0.U + io.dec_i0_predict_p_d.ataken :=0.U + io.dec_i0_predict_p_d.boffset :=0.U + io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error + io.dec_i0_predict_p_d.pja := i0_pja + io.dec_i0_predict_p_d.pret := i0_pret + io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett + io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d + io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist + io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d + val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) + + // no toffset error for a pret + val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw + val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw; + val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error + io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode + io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode + io.i0_predict_index_d := io.dec_i0_bp_index + io.i0_predict_btag_d := io.dec_i0_bp_btag + val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode + io.dec_i0_predict_p_d.toffset := i0_br_offset + io.i0_predict_fghr_d := io.dec_i0_bp_fghr + io.dec_i0_predict_p_d.way := io.dec_i0_brp.way + // end + + // on br error turn anything into a nop + // on i0 instruction fetch access fault turn anything into a nop + // nop => alu rs1 imm12 rd lor + val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d + + val i0_instr_error = i0_icaf_d; + i0_dp := i0_dp_raw + when((i0_br_error_all | i0_instr_error).asBool){ + i0_dp := 0.U.asTypeOf(i0_dp) + i0_dp.alu := 1.B + i0_dp.rs1 := 1.B + i0_dp.rs2 := 1.B + i0_dp.lor := 1.B + i0_dp.legal := 1.B + i0_dp.postsync := 1.B + } + + val i0 = io.dec_i0_instr_d + io.dec_i0_select_pc_d := i0_dp.pc; + + // branches that can be predicted + val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; + + val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br + val i0_ap_pc2 = !io.dec_i0_pc4_d + val i0_ap_pc4 = io.dec_i0_pc4_d + io.i0_ap.predict_nt := i0_predict_nt + io.i0_ap.predict_t := i0_predict_t + + io.i0_ap.add := i0_dp.add + io.i0_ap.sub := i0_dp.sub + io.i0_ap.land := i0_dp.land + io.i0_ap.lor := i0_dp.lor + io.i0_ap.lxor := i0_dp.lxor + io.i0_ap.sll := i0_dp.sll + io.i0_ap.srl := i0_dp.srl + io.i0_ap.sra := i0_dp.sra + io.i0_ap.slt := i0_dp.slt + io.i0_ap.unsign := i0_dp.unsign + io.i0_ap.beq := i0_dp.beq + io.i0_ap.bne := i0_dp.bne + io.i0_ap.blt := i0_dp.blt + io.i0_ap.bge := i0_dp.bge + io.i0_ap.csr_write := i0_csr_write_only_d + io.i0_ap.csr_imm := i0_dp.csr_imm + io.i0_ap.jal := i0_jal + + // non block load cam logic + // val found=Wire(UInt(1.W)) + cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i))) + + cam_write := io.lsu_nonblock_load_valid_m + val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0) + + val cam_inv_reset = io.lsu_nonblock_load_inv_r + val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r(LSU_NUM_NBLOAD_WIDTH-1,0) + + val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error + val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0) + + val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data + val load_data_tag = io.lsu_nonblock_load_data_tag + // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one + // don't writeback a nonblock load + val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} + val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load + for(i <- 0 until LSU_NUM_NBLOAD){ + cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid + cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid + cam_in(i):=0.U.asTypeOf(cam(0)) + cam(i):=cam_raw(i) + + when(cam_data_reset_val(i).asBool){ + cam(i).valid := 0.U(1.W) + } + when(cam_wen(i).asBool){ + cam_in(i).valid := 1.U(1.W) + cam_in(i).wb := 0.U(1.W) + cam_in(i).tag := cam_write_tag + cam_in(i).rd := nonblock_load_rd + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){ + cam_in(i).valid := 0.U + }.otherwise{ + cam_in(i) := cam(i) + } + when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){ + cam_in(i).wb := 1.U + } + // force debug halt forces cam valids to 0; highest priority + when(io.dec_tlu_force_halt){ + cam_in(i).valid := 0.U + } + + cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))} + nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid + } + + io.dec_nonblock_load_waddr:=0.U(5.W) + // cancel if any younger inst (including another nonblock) committing this cycle + val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) + io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) + val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) + + i0_nonblock_load_stall := i0_nonblock_boundary_stall + + val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2)) + val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) + io.dec_nonblock_load_waddr:=waddr + i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall + //i0_nonblock_load_stall:=ld_stall_2 + + // end non block load cam logic + + // pmu start + + val csr_read = csr_ren_qual_d + val csr_write = io.dec_csr_wen_unq_d + val i0_br_unpred = i0_dp.jal & !i0_predict_br + + // the classes must be mutually exclusive with one another + import el2_inst_pkt_t._ + d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array( + i0_dp.jal -> JAL, + i0_dp.condbr -> CONDBR, + i0_dp.mret -> MRET, + i0_dp.fence_i -> FENCEI, + i0_dp.fence -> FENCE, + i0_dp.ecall -> ECALL, + i0_dp.ebreak -> EBREAK, + ( csr_read & csr_write).asBool -> CSRRW, + (!csr_read & csr_write).asBool -> CSRWRITE, + ( csr_read & !csr_write).asBool -> CSRREAD, + i0_dp.pm_alu -> ALU, + i0_dp.store -> STORE, + i0_dp.load -> LOAD, + i0_dp.mul -> MUL)) + // end pmu + + val i0_dec =Module(new el2_dec_dec_ctl) + i0_dec.io.ins:= i0 + i0_dp_raw:=i0_dec.io.out + + lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)} + + // can't make this clock active_clock + leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r)) + leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)} + leak1_mode := leak1_i1_stall + leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r)) + leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)} + + // 12b jal's can be predicted - these are calls + + val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21),0.U(1.W)) + val i0_pcall_12b_offset = Mux(i0_pcall_imm(12).asBool, i0_pcall_imm(20,13) === 0xff.U , i0_pcall_imm(20,13) === 0.U(8.W)) + val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja + i0_pcall := i0_dp.jal & i0_pcall_case + i0_pja_raw := i0_dp_raw.jal & i0_pja_case + i0_pja := i0_dp.jal & i0_pja_case + i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(12,1) , Cat(i0(31),i0(7),i0(30,25),i0(11,8))) + // jalr with rd==0, rs1==1 or rs1==5 is a ret + val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W))) + i0_pret_raw := i0_dp_raw.jal & i0_pret_case + i0_pret := i0_dp.jal & i0_pret_case + i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + io.div_p.valid := div_decode_d + io.div_p.unsign := i0_dp.unsign + io.div_p.rem := i0_dp.rem + + io.mul_p.valid := mul_decode_d + io.mul_p.rs1_sign := i0_dp.rs1_sign + io.mul_p.rs2_sign := i0_dp.rs2_sign + io.mul_p.low := i0_dp.low + + io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)} + + io.lsu_p := 0.U.asTypeOf(io.lsu_p) + when (io.dec_extint_stall){ + io.lsu_p.load := 1.U(1.W) + io.lsu_p.word := 1.U(1.W) + io.lsu_p.fast_int := 1.U(1.W) + io.lsu_p.valid := 1.U(1.W) + }.otherwise { + io.lsu_p.valid := lsu_decode_d + io.lsu_p.load := i0_dp.load + io.lsu_p.store := i0_dp.store + io.lsu_p.by := i0_dp.by + io.lsu_p.half := i0_dp.half + io.lsu_p.word := i0_dp.word + io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d + io.lsu_p.store_data_bypass_d := store_data_bypass_d + io.lsu_p.store_data_bypass_m := store_data_bypass_m + io.lsu_p.unsign := i0_dp.unsign + } + + ////////////////////////////////////// + io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU + csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above + + val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d + val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool + val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool + val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool + + i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read + io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) // for csr legal, can't write read-only csr + //dec_csr_wen_unq_d assigned as csr_write above + + io.dec_csr_rdaddr_d := i0(31,20) + io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt + + // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb + // also use valid so it's flushable + io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r; + + // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. + io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb; + + val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} + val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} + val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)} + val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)} + val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)} + + // perform the update operation if any + val csrimm_x = rvdffe(i0(19,15),i0_x_data_en.asBool,clock,io.scan_mode) + val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en.asBool,clock,io.scan_mode) + + val csr_mask_x = Mux1H(Seq( + csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)), + !csr_imm_x.asBool -> io.exu_csr_rs1_x)) + + val write_csr_data_x = Mux1H(Seq( + csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt), + csr_set_x -> (csr_rddata_x | csr_mask_x), + csr_write_x -> ( csr_mask_x))) + // pause instruction + val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause + pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause + pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)} + io.dec_pause_state := pause_state + tlu_wr_pause_r1 := RegNext(io.dec_tlu_wr_pause_r, 0.U) + tlu_wr_pause_r2 := RegNext(tlu_wr_pause_r1, 0.U) + //pause for clock gating + io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2)) + // end pause + + val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)), + Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x)) + val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state + write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,clock,io.scan_mode) + + // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR + val pause_stall = pause_state + + // for csr write only data is produced by the alu + io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data) + + val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly; + + val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0) + val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1) + debug_fence := debug_fence_raw | debug_fence_i + + // some CSR reads need to be presync'd + val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync + + // some CSR writes need to be postsync'd + val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) + + val any_csr_d = i0_dp.csr_read | i0_csr_write + io.dec_csr_any_unq_d := any_csr_d + val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) + val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst)) + // illegal inst handling + + val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal + val illegal_inst_en = shift_illegal & !illegal_lockout + io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode) + illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r + illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)} + val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active + //stalls signals + val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall | + leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall | + ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | + i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall + + val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any) + val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any) + val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d + val i0_exublock_d = i0_block_raw_d + + //decode valid + io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exulegal_decode_d = i0_exudecode_d & i0_legal + + // performance monitor signals + io.dec_pmu_instr_decoded := io.dec_i0_decode_d + io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d + io.dec_pmu_postsync_stall := postsync_stall.asBool + io.dec_pmu_presync_stall := presync_stall.asBool + + val prior_inflight_x = x_d.i0valid + val prior_inflight_wb = r_d.i0valid + val prior_inflight = prior_inflight_x | prior_inflight_wb + val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) + + presync_stall := (i0_presync & prior_inflight_eff) + postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)} + // illegals will postsync + ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x) + + io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu + + lsu_decode_d := i0_legal_decode_d & i0_dp.lsu + mul_decode_d := i0_exulegal_decode_d & i0_dp.mul + div_decode_d := i0_exulegal_decode_d & i0_dp.div + + io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb + + //traps for TLU (tlu stuff) + d_t.legal := i0_legal_decode_d + d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception + d_t.icaf_f1 := io.dec_i0_icaf_f1_d & i0_legal_decode_d // this includes icaf and dbecc + d_t.icaf_type := io.dec_i0_icaf_type_d + + d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d + + // put pmu info into the trap packet + d_t.pmu_i0_br_unpred := i0_br_unpred + d_t.pmu_divide := 0.U(1.W) + d_t.pmu_lsu_misaligned := 0.U(1.W) + + d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d) + + + x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode) + + x_t_in := x_t + x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb)) + + r_t := rvdffe(x_t_in,i0_x_ctl_en.asBool,clock,io.scan_mode) + val lsu_trigger_match_r = RegNext(io.lsu_trigger_match_m, 0.U) + val lsu_pmu_misaligned_r = RegNext(io.lsu_pmu_misaligned_m, 0.U) + + r_t_in := r_t + + r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger + r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage + + when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } + + io.dec_tlu_packet_r := r_t_in + io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid + // end tlu stuff + + flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} + + io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + + i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits + i0r.rs2 := i0(24,20) + i0r.rd := i0(11,7) + + io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's + io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W)) + val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W)) + io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile + io.dec_i0_rs2_d := i0r.rs2 + + val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915) + val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20 + + io.dec_i0_immed_d := Mux1H(Seq( + i0_dp.csr_read -> io.dec_csr_rddata_d, + !i0_dp.csr_read -> i0_immed_d)) + + i0_immed_d := Mux1H(Seq( + i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr + i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)), + i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U), + i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)), + (i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write + + i0_legal_decode_d := io.dec_i0_decode_d & i0_legal + + i0_d_c.mul := i0_dp.mul & i0_legal_decode_d + i0_d_c.load := i0_dp.load & i0_legal_decode_d + i0_d_c.alu := i0_dp.alu & i0_legal_decode_d + + val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)} + val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)} + i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) + + i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) + i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override) + i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override) + i0_x_data_en := ( i0_pipe_en(3) | io.clk_override) + i0_r_data_en := ( i0_pipe_en(2) | io.clk_override) + i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override) + i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override) + + io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) + io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) + + d_d.i0rd := i0r.rd + d_d.i0v := i0_rd_en_d & i0_legal_decode_d + d_d.i0valid := io.dec_i0_decode_d // has flush_final_r + + d_d.i0load := i0_dp.load & i0_legal_decode_d + d_d.i0store := i0_dp.store & i0_legal_decode_d + d_d.i0div := i0_dp.div & i0_legal_decode_d + + d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d + d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d + d_d.csrwaddr := i0(31,20) + + x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) + val x_d_in = Wire(new el2_dest_pkt_t) + x_d_in := x_d + x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + + r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) + r_d_in := r_d + r_d_in.i0rd := r_d.i0rd + + r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb) + r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb) + r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb + r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb + + wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) + + io.dec_i0_waddr_r := r_d_in.i0rd + i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r + io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe + io.dec_i0_wdata_r := i0_result_corr_r + + val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) + if ( LOAD_TO_USE_PLUS1 == 1 ) { + i0_result_x := io.exu_i0_result_x + i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw) + } + else { + i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) + i0_result_r := i0_result_r_raw + } + + // correct lsu load data - don't use for bypass, do pass down the pipe + i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) + io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) + val last_br_immed_d = WireInit(UInt(12.W),0.U) + last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) + val last_br_immed_x = WireInit(UInt(12.W),0.U) + last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode) + + // divide stuff + + val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid) + + val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) | + (x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) | + (r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) + + // cancel if any younger inst committing this cycle to same dest as nonblock divide + + val nonblock_div_cancel = (io.dec_div_active & div_flush) | + (io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r) + + io.dec_div_cancel := nonblock_div_cancel.asBool + val i0_div_decode_d = i0_legal_decode_d & i0_dp.div + + val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel) + + io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)} + + // nonblocking div scheme + i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) | + (io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2)) + + io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool) + ///div end + + //for tracing instruction + val i0_wb_en = i0_wb_data_en + val i0_wb1_en = i0_wb1_data_en + + val div_inst = rvdffe(i0_inst_d(24,7),i0_div_decode_d.asBool,clock,io.scan_mode) + val i0_inst_x = rvdffe(i0_inst_d,i0_x_data_en.asBool,clock,io.scan_mode) + val i0_inst_r = rvdffe(i0_inst_x,i0_r_data_en.asBool,clock,io.scan_mode) + val i0_inst_wb_in = i0_inst_r + val i0_inst_wb = rvdffe(i0_inst_wb_in,i0_wb_en.asBool,clock,io.scan_mode) + io.dec_i0_inst_wb1 := rvdffe(i0_inst_wb,i0_wb1_en.asBool,clock,io.scan_mode) + val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode) + + io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode) + val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode) + + io.dec_tlu_i0_pc_r := dec_i0_pc_r + + //end tracing + + val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U)) + io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1) + + // scheduling logic for primary alu's + + val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1) + val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1) + + val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2) + val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2) + // order the producers as follows: , i0_x, i0_r, i0_wb + i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) + i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) + i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d))) + i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) + + // stores will bypass load data in the lsu pipe + if (LOAD_TO_USE_PLUS1 == 1) { + i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) + store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load) + } + else { + i0_load_block_d := 0.B + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load + store_data_bypass_m := 0.B + } + // add nonblock load rs1/rs2 bypass cases + + val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1) + + val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2) + + // bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r + i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load))) + + i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load))) + + io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d))) + io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d))) + + io.dec_i0_rs1_bypass_data_d := Mux1H(Seq( + i0_rs1bypass(1).asBool -> io.lsu_result_m, + i0_rs1bypass(0).asBool -> i0_result_r, + (!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, + )) + io.dec_i0_rs2_bypass_data_d := Mux1H(Seq( + i0_rs2bypass(1).asBool -> io.lsu_result_m, + i0_rs2bypass(0).asBool -> i0_result_r, + (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, + )) + io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall) + io.dec_lsu_offset_d := Mux1H(Seq( + (!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), + (!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) +} + +object dec_decode extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_decode_ctl))) +} diff --git a/src/main/scala/dec/el2_dec_gpr_ctl.scala b/src/main/scala/dec/el2_dec_gpr_ctl.scala new file mode 100644 index 00000000..b37f7f0e --- /dev/null +++ b/src/main/scala/dec/el2_dec_gpr_ctl.scala @@ -0,0 +1,58 @@ +package dec +import chisel3._ +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ + +class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { + val io =IO(new el2_dec_gpr_ctl_IO) + val w0v =Wire(Vec(32,UInt(1.W))) + val w1v =Wire(Vec(32,UInt(1.W))) + val w2v =Wire(Vec(32,UInt(1.W))) + val gpr_in =Wire(Vec(32,UInt(32.W))) + val gpr_out =Wire(Vec(32,UInt(32.W))) + val gpr_wr_en =Wire(UInt(32.W)) + w0v(0):=0.U + w1v(0):=0.U + w2v(0):=0.U + gpr_out(0):=0.U + gpr_in(0):=0.U + io.rd0:=0.U + io.rd1:=0.U + gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) + // GPR Write logic + for (j <-1 until 32){ + w0v(j) := io.wen0 & (io.waddr0===j.asUInt) + w1v(j) := io.wen1 & (io.waddr1===j.asUInt) + w2v(j) := io.wen2 & (io.waddr2===j.asUInt) + gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) + } + // GPR Write Enables for power savings + for (j <-1 until 32){ + gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) + } + // GPR Read logic + io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i))) + io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i))) +} + +class el2_dec_gpr_ctl_IO extends Bundle{ + val raddr0=Input(UInt(5.W)) // logical read addresses + val raddr1=Input(UInt(5.W)) + val wen0=Input(UInt(1.W)) // write enable + val waddr0=Input(UInt(5.W)) // write address + val wd0=Input(UInt(32.W)) // write data + val wen1=Input(UInt(1.W)) // write enable + val waddr1=Input(UInt(5.W)) // write address + val wd1=Input(UInt(32.W)) // write data + val wen2=Input(UInt(1.W)) // write enable + val waddr2=Input(UInt(5.W)) // write address + val wd2=Input(UInt(32.W)) // write data + val rd0=Output(UInt(32.W)) // read data + val rd1=Output(UInt(32.W)) + val scan_mode=Input(Bool()) +} +object gpr_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl))) +} diff --git a/src/main/scala/dec/el2_dec_ib_ctl.scala b/src/main/scala/dec/el2_dec_ib_ctl.scala new file mode 100644 index 00000000..9cdd876d --- /dev/null +++ b/src/main/scala/dec/el2_dec_ib_ctl.scala @@ -0,0 +1,99 @@ +package dec +import include._ +import chisel3._ +import chisel3.util._ +import lib._ + +class el2_dec_ib_ctl_IO extends Bundle with param{ + val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd + val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write + val dbg_cmd_type =Input(UInt(2.W)) // dbg type + val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0 + val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner + val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size) + val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR + val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag + val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B + val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu + val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault + val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type + val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group + val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error + val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner + val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner + + val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid + val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type + val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode + val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode + val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B + val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode + val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode + val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode + val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted + val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst +} + +class el2_dec_ib_ctl extends Module with param{ + val io=IO(new el2_dec_ib_ctl_IO) + io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1 + io.dec_i0_dbecc_d :=io.ifu_i0_dbecc + io.dec_i0_icaf_d :=io.ifu_i0_icaf + io.dec_i0_pc_d :=io.ifu_i0_pc + io.dec_i0_pc4_d :=io.ifu_i0_pc4 + io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type + io.dec_i0_brp :=io.i0_brp + io.dec_i0_bp_index :=io.ifu_i0_bp_index + io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr + io.dec_i0_bp_btag :=io.ifu_i0_bp_btag + + // GPR accesses + // put reg to read on rs1 + // read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011} + // put write date on rs1 + // write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011} + // CSR accesses + // csr is of form rd, csr, rs1 + // read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011} + // put write data on rs1 + // write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011} + + + val debug_valid =io.dbg_cmd_valid & (io.dbg_cmd_type =/= 2.U) + val debug_read =debug_valid & !io.dbg_cmd_write + val debug_write =debug_valid & io.dbg_cmd_write + + val debug_read_gpr = debug_read & (io.dbg_cmd_type===0.U) + val debug_write_gpr = debug_write & (io.dbg_cmd_type===0.U) + val debug_read_csr = debug_read & (io.dbg_cmd_type===1.U) + val debug_write_csr = debug_write & (io.dbg_cmd_type===1.U) + + val dreg = io.dbg_cmd_addr(4,0) + val dcsr = io.dbg_cmd_addr(11,0) + + val ib0_debug_in =Mux1H(Seq( + debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), + debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), + debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), + debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) + )) + + // machine is in halted state, pipe empty, write will always happen next cycle + io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr + + // special fence csr for use only in debug mode + io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U) + + io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid + io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr) + + +} + +object ib_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl))) +} diff --git a/src/main/scala/dec/el2_dec_tlu_ctl.scala b/src/main/scala/dec/el2_dec_tlu_ctl.scala new file mode 100644 index 00000000..6b64dc16 --- /dev/null +++ b/src/main/scala/dec/el2_dec_tlu_ctl.scala @@ -0,0 +1,2872 @@ +package dec +import chisel3._ +import chisel3.util._ +import lib._ +import include._ +import el2_inst_pkt_t._ +//import lib.beh_ib_func._ +trait CSR_VAL { + + val MSTATUS_MIE =0 + val MIP_MCEIP =5 + val MIP_MITIP0 =4 + val MIP_MITIP1 =3 + val MIP_MEIP =2 + val MIP_MTIP =1 + val MIP_MSIP =0 + + val MIE_MCEIE =5 + val MIE_MITIE0 =4 + val MIE_MITIE1 =3 + val MIE_MEIE =2 + val MIE_MTIE =1 + val MIE_MSIE =0 + + val DCSR_EBREAKM =15 + val DCSR_STEPIE =11 + val DCSR_STOPC =10 + val DCSR_STEP =2 + + val MTDATA1_DMODE =9 + val MTDATA1_SEL =7 + val MTDATA1_ACTION =6 + val MTDATA1_CHAIN =5 + val MTDATA1_MATCH =4 + val MTDATA1_M_ENABLED =3 + val MTDATA1_EXE =2 + val MTDATA1_ST =1 + val MTDATA1_LD =0 + + +} +class el2_dec_tlu_ctl_IO extends Bundle with el2_lib { + + val active_clk = Input(Clock()) + val free_clk = Input(Clock()) + //val rst_l = Input(Bool()) + val scan_mode = Input(Bool()) + + val rst_vec = Input(UInt(31.W)) // reset vector, from core pins + val nmi_int = Input(UInt(1.W)) // nmi pin + val nmi_vec = Input(UInt(31.W)) // nmi vector + val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU + + val lsu_fastint_stall_any = Input(UInt(1.W)) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + + // perf counter inputs + val ifu_pmu_instr_aligned = Input(UInt(1.W))// aligned instructions + val ifu_pmu_fetch_stall = Input(UInt(1.W))// fetch unit stalled + val ifu_pmu_ic_miss = Input(UInt(1.W))// icache miss + val ifu_pmu_ic_hit = Input(UInt(1.W))// icache hit + val ifu_pmu_bus_error = Input(UInt(1.W))// Instruction side bus error + val ifu_pmu_bus_busy = Input(UInt(1.W))// Instruction side bus busy + val ifu_pmu_bus_trxn = Input(UInt(1.W))// Instruction side bus transaction + val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions + val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall + val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst + val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst + val lsu_store_stall_any = Input(UInt(1.W))// SB or WB is full, stall decode + val dma_dccm_stall_any = Input(UInt(1.W))// DMA stall of lsu + val dma_iccm_stall_any = Input(UInt(1.W))// DMA stall of ifu + val exu_pmu_i0_br_misp = Input(UInt(1.W))// pipe 0 branch misp + val exu_pmu_i0_br_ataken = Input(UInt(1.W))// pipe 0 branch actual taken + val exu_pmu_i0_pc4 = Input(UInt(1.W))// pipe 0 4 byte branch + val lsu_pmu_bus_trxn = Input(UInt(1.W))// D side bus transaction + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) // D side bus misaligned + val lsu_pmu_bus_error = Input(UInt(1.W)) // D side bus error + val lsu_pmu_bus_busy = Input(UInt(1.W)) // D side bus busy + val lsu_pmu_load_external_m = Input(UInt(1.W)) // D side bus load + val lsu_pmu_store_external_m= Input(UInt(1.W)) // D side bus store + val dma_pmu_dccm_read = Input(UInt(1.W)) // DMA DCCM read + val dma_pmu_dccm_write = Input(UInt(1.W)) // DMA DCCM write + val dma_pmu_any_read = Input(UInt(1.W)) // DMA read + val dma_pmu_any_write = Input(UInt(1.W)) // DMA write + + val lsu_fir_addr = Input(UInt(31.W)) // Fast int address + val lsu_fir_error = Input(UInt(2.W)) // Fast int lookup error + + val iccm_dma_sb_error = Input(UInt(1.W)) // I side dma single bit error + + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t)// lsu precise exception/error packet + val lsu_single_ecc_error_incr = Input(UInt(1.W)) // LSU inc SB error counter + + val dec_pause_state = Input(UInt(1.W)) // Pause counter not zero + val lsu_imprecise_error_store_any = Input(UInt(1.W)) // store bus error + val lsu_imprecise_error_load_any = Input(UInt(1.W)) // store bus error + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // store bus error address + + val dec_csr_wen_unq_d = Input(UInt(1.W)) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Input(UInt(1.W)) // valid csr - for csr legal + val dec_csr_rdaddr_d = Input(UInt(12.W)) // read address for csr + + val dec_csr_wen_r = Input(UInt(1.W)) // csr write enable at wb + val dec_csr_wraddr_r = Input(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Input(UInt(32.W)) // csr write data at wb + + val dec_csr_stall_int_ff = Input(UInt(1.W)) // csr is mie/mstatus + + val dec_tlu_i0_valid_r = Input(UInt(1.W)) // pipe 0 op at e4 is valid + + val exu_npc_r = Input(UInt(31.W)) // for NPC tracking + + val dec_tlu_i0_pc_r = Input(UInt(31.W)) // for PC/NPC tracking + + val dec_tlu_packet_r = Input(new el2_trap_pkt_t) // exceptions known at decode + + val dec_illegal_inst = Input(UInt(32.W)) // For mtval + val dec_i0_decode_d = Input(UInt(1.W)) // decode valid, used for clean icache diagnostics + + // branch info from pipe0 for errors or counter updates + val exu_i0_br_hist_r = Input(UInt(2.W)) // history + val exu_i0_br_error_r = Input(UInt(1.W)) // error + val exu_i0_br_start_error_r = Input(UInt(1.W)) // start error + val exu_i0_br_valid_r = Input(UInt(1.W)) // valid + val exu_i0_br_mp_r = Input(UInt(1.W)) // mispredict + val exu_i0_br_middle_r = Input(UInt(1.W)) // middle of bank + + // branch info from pipe1 for errors or counter updates + + val exu_i0_br_way_r = Input(UInt(1.W))// way hit or repl + + // Debug start + val dec_dbg_cmd_done = Output(UInt(1.W)) // abstract command done + val dec_dbg_cmd_fail = Output(UInt(1.W)) // abstract command failed + val dec_tlu_dbg_halted = Output(UInt(1.W)) // Core is halted and ready for debug command + val dec_tlu_debug_mode = Output(UInt(1.W)) // Core is in debug mode + val dec_tlu_resume_ack = Output(UInt(1.W)) // Resume acknowledge + val dec_tlu_debug_stall = Output(UInt(1.W)) // stall decode while waiting on core to empty + + val dec_tlu_flush_noredir_r = Output(UInt(1.W)) // Tell fetch to idle on this flush + val dec_tlu_mpc_halted_only = Output(UInt(1.W)) // Core is halted only due to MPC + val dec_tlu_flush_leak_one_r = Output(UInt(1.W)) // single step + val dec_tlu_flush_err_r = Output(UInt(1.W)) // iside perr/ecc rfpc. This is the D stage of the error + + val dec_tlu_flush_extint = Output(UInt(1.W)) // fast ext int started + val dec_tlu_meihap = Output(UInt(30.W)) // meihap for fast int + + val dbg_halt_req = Input(UInt(1.W)) // DM requests a halt + val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume + val ifu_miss_state_idle = Input(UInt(1.W)) // I-side miss buffer empty + val lsu_idle_any = Input(UInt(1.W)) // lsu is idle + val dec_div_active = Input(UInt(1.W)) // oop div is active + val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t))// trigger info for trigger blocks + + val ifu_ic_error_start = Input(UInt(1.W)) // IC single bit error + val ifu_iccm_rd_ecc_single_err = Input(UInt(1.W)) // ICCM single bit error + + + val ifu_ic_debug_rd_data = Input(UInt(71.W)) // diagnostic icache read data + val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) // diagnostic icache read data valid + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + // Debug end + + val pic_claimid = Input(UInt(8.W)) // pic claimid for csr + val pic_pl = Input(UInt(4.W)) // pic priv level for csr + val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted + + val mexintpend= Input(UInt(1.W)) // external interrupt pending + val timer_int= Input(UInt(1.W)) // timer interrupt pending + val soft_int= Input(UInt(1.W)) // software interrupt pending + + val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted + val o_cpu_halt_ack = Output(UInt(1.W)) // halt req ack + val o_cpu_run_ack = Output(UInt(1.W)) // run req ack + val o_debug_mode_status = Output(UInt(1.W)) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + val core_id = Input(UInt(28.W)) // Core ID + + // external MPC halt/run interface + val mpc_debug_halt_req = Input(UInt(1.W)) // Async halt request + val mpc_debug_run_req = Input(UInt(1.W)) // Async run request + val mpc_reset_run_req = Input(UInt(1.W)) // Run/halt after reset + val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack + val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack + val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint + val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC + val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp + val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4) + val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction + val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Output(UInt(1.W)) // commit has a flush (exception, int) + val dec_tlu_flush_path_r = Output(UInt(31.W)) // flush pc + val dec_tlu_fence_i_r = Output(UInt(1.W)) // flush is a fence_i rfnpc, flush icache + val dec_tlu_wr_pause_r = Output(UInt(1.W)) // CSR write to pause reg is at R. + val dec_tlu_flush_pause_r = Output(UInt(1.W)) // Flush is due to pause + val dec_tlu_presync_d = Output(UInt(1.W)) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Output(UInt(1.W)) // CSR needs to be presync'd + val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control + val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced + val dec_tlu_perfcnt0 = Output(UInt(1.W)) // toggles when pipe0 perf counter 0 has an event inc + val dec_tlu_perfcnt1 = Output(UInt(1.W)) // toggles when pipe0 perf counter 1 has an event inc + val dec_tlu_perfcnt2 = Output(UInt(1.W)) // toggles when pipe0 perf counter 2 has an event inc + val dec_tlu_perfcnt3 = Output(UInt(1.W)) // toggles when pipe0 perf counter 3 has an event inc + val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) // pipe 0 exception valid + val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) // pipe 0 valid + val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) // pipe 2 int valid + val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) // exception or int cause + val dec_tlu_mtval_wb1 = Output(UInt(32.W)) // MTVAL value + + // feature disable from mfdc + val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) // disable external load forwarding + val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) // disable posted stores to side-effect address + val dec_tlu_core_ecc_disable = Output(UInt(1.W)) // disable core ECC + val dec_tlu_bpred_disable = Output(UInt(1.W)) // disable branch prediction + val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) // disable writebuffer coalescing + val dec_tlu_pipelining_disable = Output(UInt(1.W)) // disable pipelining + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + val dec_tlu_misc_clk_override = Output(UInt(1.W)) // override misc clock domain gating + val dec_tlu_dec_clk_override = Output(UInt(1.W)) // override decode clock domain gating + val dec_tlu_ifu_clk_override = Output(UInt(1.W)) // override fetch clock domain gating + val dec_tlu_lsu_clk_override = Output(UInt(1.W)) // override load/store clock domain gating + val dec_tlu_bus_clk_override = Output(UInt(1.W)) // override bus clock domain gating + val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating + val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating + val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating +} +class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CSR_VAL{ + val io = IO(new el2_dec_tlu_ctl_IO) + val mtdata1_t = Wire(Vec(4,UInt(10.W))) + val pause_expired_wb =Wire(UInt(1.W)) + val take_nmi_r_d1 =Wire(UInt(1.W)) + val exc_or_int_valid_r_d1 =Wire(UInt(1.W)) + val interrupt_valid_r_d1 =Wire(UInt(1.W)) + val tlu_flush_lower_r =Wire(UInt(1.W)) + val synchronous_flush_r =Wire(UInt(1.W)) + val interrupt_valid_r =Wire(UInt(1.W)) + val take_nmi =Wire(UInt(1.W)) + val take_reset =Wire(UInt(1.W)) + val take_int_timer1_int =Wire(UInt(1.W)) + val take_int_timer0_int =Wire(UInt(1.W)) + val take_timer_int =Wire(UInt(1.W)) + val take_soft_int =Wire(UInt(1.W)) + val take_ce_int =Wire(UInt(1.W)) + val take_ext_int_start =Wire(UInt(1.W)) + val ext_int_freeze =Wire(UInt(1.W)) + val ext_int_freeze_d1 =Wire(UInt(1.W)) + val take_ext_int_start_d1 =Wire(UInt(1.W)) + val take_ext_int_start_d2 =Wire(UInt(1.W)) + val take_ext_int_start_d3 =Wire(UInt(1.W)) + val fast_int_meicpct =Wire(UInt(1.W)) + val ignore_ext_int_due_to_lsu_stall =Wire(UInt(1.W)) + val take_ext_int =Wire(UInt(1.W)) + val internal_dbg_halt_timers =Wire(UInt(1.W)) + val int_timer1_int_hold =Wire(UInt(1.W)) + val int_timer0_int_hold =Wire(UInt(1.W)) + val mhwakeup_ready =Wire(UInt(1.W)) + val ext_int_ready =Wire(UInt(1.W)) + val ce_int_ready =Wire(UInt(1.W)) + val soft_int_ready =Wire(UInt(1.W)) + val timer_int_ready =Wire(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 =Wire(UInt(1.W)) + val ebreak_to_debug_mode_r =Wire(UInt(1.W)) + val inst_acc_r =Wire(UInt(1.W)) + val inst_acc_r_raw =Wire(UInt(1.W)) + val iccm_sbecc_r =Wire(UInt(1.W)) + val ic_perr_r =Wire(UInt(1.W)) + val fence_i_r =Wire(UInt(1.W)) + val ebreak_r =Wire(UInt(1.W)) + val ecall_r =Wire(UInt(1.W)) + val illegal_r =Wire(UInt(1.W)) + val mret_r =Wire(UInt(1.W)) + val iccm_repair_state_ns =Wire(UInt(1.W)) + val rfpc_i0_r =Wire(UInt(1.W)) + val tlu_i0_kill_writeb_r =Wire(UInt(1.W)) + val lsu_exc_valid_r_d1 =Wire(UInt(1.W)) + val lsu_i0_exc_r_raw =Wire(UInt(1.W)) + val mdseac_locked_f =Wire(UInt(1.W)) + val i_cpu_run_req_d1 =Wire(UInt(1.W)) + val cpu_run_ack =Wire(UInt(1.W)) + val cpu_halt_status =Wire(UInt(1.W)) + val cpu_halt_ack =Wire(UInt(1.W)) + val pmu_fw_tlu_halted =Wire(UInt(1.W)) + val internal_pmu_fw_halt_mode =Wire(UInt(1.W)) + val pmu_fw_halt_req_ns =Wire(UInt(1.W)) + val pmu_fw_halt_req_f =Wire(UInt(1.W)) + val pmu_fw_tlu_halted_f =Wire(UInt(1.W)) + val int_timer0_int_hold_f =Wire(UInt(1.W)) + val int_timer1_int_hold_f =Wire(UInt(1.W)) + val trigger_hit_dmode_r =Wire(UInt(1.W)) + val i0_trigger_hit_r =Wire(UInt(1.W)) + val pause_expired_r =Wire(UInt(1.W)) + val dec_tlu_pmu_fw_halted =Wire(UInt(1.W)) + val dec_tlu_flush_noredir_r_d1 =Wire(UInt(1.W)) + val halt_taken_f =Wire(UInt(1.W)) + val lsu_idle_any_f =Wire(UInt(1.W)) + val ifu_miss_state_idle_f =Wire(UInt(1.W)) + val dbg_tlu_halted_f =Wire(UInt(1.W)) + val debug_halt_req_f =Wire(UInt(1.W)) + val debug_resume_req_f =Wire(UInt(1.W)) + val trigger_hit_dmode_r_d1 =Wire(UInt(1.W)) + val dcsr_single_step_done_f =Wire(UInt(1.W)) + val debug_halt_req_d1 =Wire(UInt(1.W)) + val request_debug_mode_r_d1 =Wire(UInt(1.W)) + val request_debug_mode_done_f =Wire(UInt(1.W)) + val dcsr_single_step_running_f =Wire(UInt(1.W)) + val dec_tlu_flush_pause_r_d1 =Wire(UInt(1.W)) + val dbg_halt_req_held =Wire(UInt(1.W)) + val debug_halt_req_ns =Wire(UInt(1.W)) + val internal_dbg_halt_mode =Wire(UInt(1.W)) + val core_empty =Wire(UInt(1.W)) + val dbg_halt_req_final =Wire(UInt(1.W)) + val debug_brkpt_status_ns =Wire(UInt(1.W)) + val mpc_debug_halt_ack_ns =Wire(UInt(1.W)) + val mpc_debug_run_ack_ns =Wire(UInt(1.W)) + val mpc_halt_state_ns =Wire(UInt(1.W)) + val mpc_run_state_ns =Wire(UInt(1.W)) + val dbg_halt_state_ns =Wire(UInt(1.W)) + val dbg_run_state_ns =Wire(UInt(1.W)) + val dbg_halt_state_f =Wire(UInt(1.W)) + val mpc_halt_state_f =Wire(UInt(1.W)) + val nmi_int_detected =Wire(UInt(1.W)) + val nmi_lsu_load_type =Wire(UInt(1.W)) + val nmi_lsu_store_type =Wire(UInt(1.W)) + val reset_delayed =Wire(UInt(1.W)) + val internal_dbg_halt_mode_f =Wire(UInt(1.W)) + val e5_valid =Wire(UInt(1.W)) + val ic_perr_r_d1 =Wire(UInt(1.W)) + val iccm_sbecc_r_d1 =Wire(UInt(1.W)) + + val npc_r = Wire(UInt(31.W)) + val npc_r_d1 = Wire(UInt(31.W)) + val mie_ns = Wire(UInt(6.W)) + val mepc = Wire(UInt(31.W)) + val mdseac_locked_ns = Wire(UInt(1.W)) + val force_halt = Wire(UInt(1.W)) + val dpc = Wire(UInt(31.W)) + val mstatus_mie_ns = Wire(UInt(1.W)) + val dec_csr_wen_r_mod = Wire(UInt(1.W)) + val fw_halt_req = Wire(UInt(1.W)) + val mstatus = Wire(UInt(2.W)) + val dcsr = Wire(UInt(16.W)) + val mtvec = Wire(UInt(31.W)) + val mip = Wire(UInt(6.W)) + val csr_pkt = Wire(new el2_dec_tlu_csr_pkt) + val dec_tlu_mpc_halted_only_ns = Wire(UInt(1.W)) + // tell dbg we are only MPC halted + dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f + val int_timers=Module(new el2_dec_timer_ctl) + int_timers.io.free_clk :=io.free_clk + int_timers.io.scan_mode :=io.scan_mode + int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod + int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d + int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r + int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r + int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0 + int_timers.io.csr_mitctl1 :=csr_pkt.csr_mitctl1 + int_timers.io.csr_mitb0 :=csr_pkt.csr_mitb0 + int_timers.io.csr_mitb1 :=csr_pkt.csr_mitb1 + int_timers.io.csr_mitcnt0 :=csr_pkt.csr_mitcnt0 + int_timers.io.csr_mitcnt1 :=csr_pkt.csr_mitcnt1 + int_timers.io.dec_pause_state :=io.dec_pause_state + int_timers.io.dec_tlu_pmu_fw_halted :=dec_tlu_pmu_fw_halted + int_timers.io.internal_dbg_halt_timers:=internal_dbg_halt_timers + + val dec_timer_rddata_d =int_timers.io.dec_timer_rddata_d + val dec_timer_read_d =int_timers.io.dec_timer_read_d + val dec_timer_t0_pulse =int_timers.io.dec_timer_t0_pulse + val dec_timer_t1_pulse =int_timers.io.dec_timer_t1_pulse + + val clk_override = io.dec_tlu_dec_clk_override + + // Async inputs to the core have to be sync'd to the core clock. + + val syncro_ff=rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) + val nmi_int_sync =syncro_ff(6) + val timer_int_sync =syncro_ff(5) + val soft_int_sync =syncro_ff(4) + val i_cpu_halt_req_sync =syncro_ff(3) + val i_cpu_run_req_sync =syncro_ff(2) + val mpc_debug_halt_req_sync_raw =syncro_ff(1) + val mpc_debug_run_req_sync =syncro_ff(0) + + // for CSRs that have inpipe writes only + val csr_wr_clk=rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) + val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.exc_valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) + + val e4_valid = io.dec_tlu_i0_valid_r + val e4e5_valid = e4_valid | e5_valid + val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override + + val e4e5_clk=rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) + val e4e5_int_clk=rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) + + val iccm_repair_state_d1 =withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)} + ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)} + iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} + e5_valid :=withClock(io.free_clk){RegNext(e4_valid,0.U)} + internal_dbg_halt_mode_f :=withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)} + val lsu_pmu_load_external_r =withClock(io.free_clk){RegNext(io.lsu_pmu_load_external_m,0.U)} + val lsu_pmu_store_external_r =withClock(io.free_clk){RegNext(io.lsu_pmu_store_external_m,0.U)} + val tlu_flush_lower_r_d1 =withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)} + io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} + val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} + io.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} + + + + io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r + val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} + val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} + reset_delayed :=reset_detect ^ reset_detected + + val nmi_int_delayed =withClock(io.free_clk){RegNext(nmi_int_sync,0.U)} + val nmi_int_detected_f =withClock(io.free_clk){RegNext(nmi_int_detected,0.U)} + val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} + val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} + + + // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared + val nmi_lsu_detected = ~mdseac_locked_f & (io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any) + + nmi_int_detected := (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) |(take_ext_int_start_d3 & io.lsu_fir_error.orR) + // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore + nmi_lsu_load_type := (nmi_lsu_detected & io.lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1) + nmi_lsu_store_type := (nmi_lsu_detected & io.lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_store_type_f & ~take_nmi_r_d1) + + // ---------------------------------------------------------------------- + // MPC halt + // - can interact with debugger halt and v-v + + // fast ints in progress have priority + val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1 + val mpc_debug_halt_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} + val mpc_debug_run_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} + mpc_halt_state_f :=withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} + val mpc_run_state_f =withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} + val debug_brkpt_status_f =withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} + val mpc_debug_halt_ack_f =withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} + val mpc_debug_run_ack_f =withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} + dbg_halt_state_f :=withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} + val dbg_run_state_f =withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} + io.dec_tlu_mpc_halted_only :=withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} + + + // turn level sensitive requests into pulses + val mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f + val mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f + // states + mpc_halt_state_ns := (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~io.mpc_reset_run_req)) & ~mpc_debug_run_req_sync + mpc_run_state_ns := (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) + + dbg_halt_state_ns := (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~io.dbg_resume_req + dbg_run_state_ns := (dbg_run_state_f | io.dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) + + // tell dbg we are only MPC halted + dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f + + // this asserts from detection of bkpt until after we leave debug mode + val debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1 + debug_brkpt_status_ns := (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f) + + // acks back to interface + mpc_debug_halt_ack_ns := mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty + mpc_debug_run_ack_ns := (mpc_debug_run_req_sync & ~dbg_halt_state_ns & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) + + // Pins + io.mpc_debug_halt_ack := mpc_debug_halt_ack_f + io.mpc_debug_run_ack := mpc_debug_run_ack_f + io.debug_brkpt_status := debug_brkpt_status_f + + // DBG halt req is a pulse, fast ext int in progress has priority + val dbg_halt_req_held_ns = (io.dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1 + dbg_halt_req_final := (io.dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1 + + // combine MPC and DBG halt requests + val debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~io.mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1 + + val debug_resume_req = ~debug_resume_req_f & ((mpc_run_state_ns & ~dbg_halt_state_ns) | (dbg_run_state_ns & ~mpc_halt_state_ns)) + + + // HALT + // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts + val take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset + + // hold after we take a halt, so we don't keep taking halts + val halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1) + + // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode + // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle + core_empty := force_halt | (io.lsu_idle_any & lsu_idle_any_f & io.ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~io.dec_div_active) + + //-------------------------------------------------------------------------------- + // Debug start + // + + val enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1 + + // dbg halt state active from request until non-step resume + internal_dbg_halt_mode := debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr(DCSR_STEP))) + // dbg halt can access csrs as long as we are not stepping + val allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f + + + // hold debug_halt_req_ns high until we enter debug halt + + val dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f) + debug_halt_req_ns := enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted) + val resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns) + + val dcsr_single_step_done = io.dec_tlu_i0_valid_r & ~io.dec_tlu_dbg_halted & dcsr(DCSR_STEP) & ~rfpc_i0_r + + val dcsr_single_step_running = (debug_resume_req_f & dcsr(DCSR_STEP)) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f) + + val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted + + // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) + val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb) + + val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f + + + dec_tlu_flush_noredir_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_noredir_r,0.U)} + halt_taken_f :=withClock(io.free_clk){RegNext(halt_taken,0.U)} + lsu_idle_any_f :=withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} + ifu_miss_state_idle_f :=withClock(io.free_clk){RegNext(io.ifu_miss_state_idle,0.U)} + dbg_tlu_halted_f :=withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} + io.dec_tlu_resume_ack :=withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} + debug_halt_req_f :=withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} + debug_resume_req_f :=withClock(io.free_clk){RegNext(debug_resume_req,0.U)} + trigger_hit_dmode_r_d1 :=withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} + dcsr_single_step_done_f :=withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} + debug_halt_req_d1 :=withClock(io.free_clk){RegNext(debug_halt_req,0.U)} + val dec_tlu_wr_pause_r_d1 =withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} + val dec_pause_state_f =withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} + request_debug_mode_r_d1 :=withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} + request_debug_mode_done_f :=withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} + dcsr_single_step_running_f :=withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} + dec_tlu_flush_pause_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} + dbg_halt_req_held :=withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} + + + io.dec_tlu_debug_stall := debug_halt_req_f + io.dec_tlu_dbg_halted := dbg_tlu_halted_f + io.dec_tlu_debug_mode := internal_dbg_halt_mode_f + dec_tlu_pmu_fw_halted := pmu_fw_tlu_halted_f + + // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt + io.dec_tlu_flush_noredir_r := take_halt | (fence_i_r & internal_dbg_halt_mode) | io.dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start + + io.dec_tlu_flush_extint := take_ext_int_start + + // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D. + io.dec_tlu_flush_pause_r := dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start + // detect end of pause counter and rfpc + pause_expired_r := ~io.dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f + + io.dec_tlu_flush_leak_one_r := io.dec_tlu_flush_lower_r & dcsr(DCSR_STEP) & (io.dec_tlu_resume_ack | dcsr_single_step_running) & ~io.dec_tlu_flush_noredir_r + io.dec_tlu_flush_err_r := io.dec_tlu_flush_lower_r & (ic_perr_r_d1 | iccm_sbecc_r_d1) + + // If DM attempts to access an illegal CSR, send cmd_fail back + io.dec_dbg_cmd_done := dbg_cmd_done_ns + io.dec_dbg_cmd_fail := illegal_r & io.dec_dbg_cmd_done + + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + // Triggers + // + + // Prioritize trigger hits with other exceptions. + // + // Trigger should have highest priority except: + // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode) + // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc. + val trigger_execute = Cat(mtdata1_t(3)(MTDATA1_EXE), mtdata1_t(2)(MTDATA1_EXE), mtdata1_t(1)(MTDATA1_EXE), mtdata1_t(0)(MTDATA1_EXE)) + val trigger_data = Cat(mtdata1_t(3)(MTDATA1_SEL), mtdata1_t(2)(MTDATA1_SEL), mtdata1_t(1)(MTDATA1_SEL), mtdata1_t(0)(MTDATA1_SEL)) + val trigger_store = Cat(mtdata1_t(3)(MTDATA1_ST), mtdata1_t(2)(MTDATA1_ST), mtdata1_t(1)(MTDATA1_ST), mtdata1_t(0)(MTDATA1_ST)) + + // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode. + val trigger_enabled = Cat((mtdata1_t(3)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(3)(MTDATA1_M_ENABLED),(mtdata1_t(2)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(2)(MTDATA1_M_ENABLED), (mtdata1_t(1)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(1)(MTDATA1_M_ENABLED), (mtdata1_t(0)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(0)(MTDATA1_M_ENABLED)) + + // iside exceptions are always in i0 + val i0_iside_trigger_has_pri_r = ~((trigger_execute & trigger_data & Fill(4,inst_acc_r_raw)) | (Fill(4,io.exu_i0_br_error_r | io.exu_i0_br_start_error_r))) + + // lsu excs have to line up with their respective triggers since the lsu op can be i0 + val i0_lsu_trigger_has_pri_r = ~(trigger_store & trigger_data & Fill(4,lsu_i0_exc_r_raw)) + + // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen + val i0_trigger_eval_r = io.dec_tlu_i0_valid_r + + val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled + // Qual trigger hits + val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r + + // chaining can mask raw trigger info + val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) + + // This is the highest priority by this point. + val i0_trigger_hit_raw_r = i0_trigger_chain_masked_r.orR + + i0_trigger_hit_r := i0_trigger_hit_raw_r + + // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set. + // Otherwise, take a breakpoint. + val trigger_action = Cat(mtdata1_t(3)(MTDATA1_ACTION) & mtdata1_t(3)(MTDATA1_DMODE), mtdata1_t(2)(MTDATA1_ACTION) & mtdata1_t(2)(MTDATA1_DMODE), mtdata1_t(1)(MTDATA1_ACTION) & mtdata1_t(1)(MTDATA1_DMODE), mtdata1_t(0)(MTDATA1_ACTION) & mtdata1_t(0)(MTDATA1_DMODE)) + + // this is needed to set the HIT bit in the triggers + val update_hit_bit_r = (Fill(4,i0_trigger_hit_r) & i0_trigger_chain_masked_r) + + // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode. + val i0_trigger_action_r = (i0_trigger_chain_masked_r & trigger_action).orR + + trigger_hit_dmode_r := (i0_trigger_hit_r & i0_trigger_action_r) + + val mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r + + // + // Debug end + + + //---------------------------------------------------------------------- + // + // Commit + // + //---------------------------------------------------------------------- + + + + //-------------------------------------------------------------------------------- + // External halt (not debug halt) + // - Fully interlocked handshake + // i_cpu_halt_req ____|--------------|_______________ + // core_empty ---------------|___________ + // o_cpu_halt_ack _________________|----|__________ + // o_cpu_halt_status _______________|---------------------|_________ + // i_cpu_run_req ______|----------|____ + // o_cpu_run_ack ____________|------|________ + // + + + // debug mode has priority, ignore PMU/FW halt/run while in debug mode + val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1 + val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1 + + val i_cpu_halt_req_d1 =withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} + val i_cpu_run_req_d1_raw =withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)} + io.o_cpu_halt_status :=withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} + io.o_cpu_halt_ack :=withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} + io.o_cpu_run_ack :=withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} + val internal_pmu_fw_halt_mode_f=withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} + pmu_fw_halt_req_f :=withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} + pmu_fw_tlu_halted_f :=withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} + int_timer0_int_hold_f :=withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} + int_timer1_int_hold_f :=withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} + + + // only happens if we aren't in dgb_halt + val ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1 + val enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req + pmu_fw_halt_req_ns := (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f + internal_pmu_fw_halt_mode := pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f) + + // debug halt has priority + pmu_fw_tlu_halted := ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f + + cpu_halt_ack := i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f + cpu_halt_status := (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (io.o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f) + cpu_run_ack := (io.o_cpu_halt_status & i_cpu_run_req_sync_qual) | (io.o_cpu_run_ack & i_cpu_run_req_sync_qual) + val debug_mode_status = internal_dbg_halt_mode_f + io.o_debug_mode_status := debug_mode_status + + // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts + i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + + val lsu_single_ecc_error_r =io.lsu_single_ecc_error_incr + mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} + val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} + val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.addr + val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.exc_valid & ~io.dec_tlu_flush_lower_wb + lsu_i0_exc_r_raw := io.lsu_error_pkt_r.exc_valid + val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r + val lsu_exc_valid_r = lsu_i0_exc_r + lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} + val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} + val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.exc_type + val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.exc_type + val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.inst_type + + // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR. + // LSU turns the load into a store and patches the data in the DCCM + val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.inst_type & io.lsu_error_pkt_r.single_ecc_error) + + // Final commit valids + val tlu_i0_commit_cmt = io.dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & ~inst_acc_r & ~io.dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r + + // unified place to manage the killing of arch state writebacks + tlu_i0_kill_writeb_r := rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & io.dec_tlu_dbg_halted) | i0_trigger_hit_r + io.dec_tlu_i0_commit_cmt := tlu_i0_commit_cmt + + + // refetch PC, microarch flush + // ic errors only in pipe0 + rfpc_i0_r := ((io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (io.exu_i0_br_error_r | io.exu_i0_br_start_error_r)) | ((ic_perr_r_d1 | iccm_sbecc_r_d1) & ~ext_int_freeze_d1)) & ~i0_trigger_hit_r & ~lsu_i0_rfnpc_r + + // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits. + iccm_repair_state_ns := iccm_sbecc_r_d1 | (iccm_repair_state_d1 & ~io.dec_tlu_flush_lower_r) + + + val MCPC =0x7c2.U(12.W) + + // this is a flush of last resort, meaning only assert it if there is no other flush happening. + val iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 & ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (io.dec_csr_wraddr_r ===MCPC))) + + // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush + val dec_tlu_br0_error_r = io.exu_i0_br_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + val dec_tlu_br0_start_error_r = io.exu_i0_br_start_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken) + + + io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r + io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r + io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r + io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r + io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r + io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r + + + ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + // fence_i includes debug only fence_i's + fence_i_r := (io.dec_tlu_packet_r.fence_i & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r + ic_perr_r := io.ifu_ic_error_start & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + iccm_sbecc_r := io.ifu_iccm_rd_ecc_single_err & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + inst_acc_r_raw := io.dec_tlu_packet_r.icaf & io.dec_tlu_i0_valid_r + inst_acc_r := inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r + val inst_acc_second_r = io.dec_tlu_packet_r.icaf_f1 + + ebreak_to_debug_mode_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + + ebreak_to_debug_mode_r_d1:= withClock(e4e5_clk){RegNext(ebreak_to_debug_mode_r,0.U)} + io.dec_tlu_fence_i_r := fence_i_r + + // + // Exceptions + // + // - MEPC <- PC + // - PC <- MTVEC, assert flush_lower + // - MCAUSE <- cause + // - MSCAUSE <- secondary cause + // - MTVAL <- + // - MPIE <- MIE + // - MIE <- 0 + // + val i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~io.dec_tlu_dbg_halted + + // Cause: + // + // 0x2 : illegal + // 0x3 : breakpoint + // 0xb : Environment call M-mode + + val exc_cause_r = Mux1H(Seq( + (take_ext_int & ~take_nmi).asBool -> 0x0b.U(5.W), + (take_timer_int & ~take_nmi).asBool -> 0x07.U(5.W), + (take_soft_int & ~take_nmi).asBool -> 0x03.U(5.W), + (take_int_timer0_int & ~take_nmi).asBool -> 0x1d.U(5.W), + (take_int_timer1_int & ~take_nmi).asBool -> 0x1c.U(5.W), + (take_ce_int & ~take_nmi).asBool -> 0x1e.U(5.W), + (illegal_r & ~take_nmi).asBool -> 0x02.U(5.W), + (ecall_r & ~take_nmi).asBool -> 0x0b.U(5.W), + (inst_acc_r & ~take_nmi).asBool -> 0x01.U(5.W), + ((ebreak_r | i0_trigger_hit_r) & ~take_nmi).asBool -> 0x03.U(5.W), + (lsu_exc_ma_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x04.U(5.W), + (lsu_exc_acc_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x05.U(5.W), + (lsu_exc_ma_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x06.U(5.W), + (lsu_exc_acc_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x07.U(5.W) + )) + // + // Interrupts + // + // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle + // or more if MSTATUS[MIE] is cleared. + // + // -in priority order, highest to lowest + // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. + // Hold off externals for a cycle to make sure we are consistent with what was just written + mhwakeup_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) + ext_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) & ~ignore_ext_int_due_to_lsu_stall + ce_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MCEIP) & mie_ns(MIE_MCEIE) + soft_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MSIP) & mie_ns(MIE_MSIE) + timer_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MTIP) & mie_ns(MIE_MTIE) + + // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions. + val int_timer0_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE0) + val int_timer0_int_ready = mip(MIP_MITIP0) & int_timer0_int_possible + val int_timer1_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE1) + val int_timer1_int_ready = mip(MIP_MITIP1) & int_timer1_int_possible + + // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around + // Make it sticky, also for 1 cycle stall conditions. + val int_timer_stalled = io.dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r + + int_timer0_int_hold := (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) + int_timer1_int_hold := (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) + + internal_dbg_halt_timers := internal_dbg_halt_mode_f & ~dcsr_single_step_running; + + val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) + + + if(FAST_INTERRUPT_REDIRECT==1) { + take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} + take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} + take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} + ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} + take_ext_int_start := ext_int_ready & ~block_interrupts; + + ext_int_freeze := take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3 + take_ext_int := take_ext_int_start_d3 & ~io.lsu_fir_error.orR + fast_int_meicpct := csr_pkt.csr_meicpct & io.dec_csr_any_unq_d // MEICPCT becomes illegal if fast ints are enabled + ignore_ext_int_due_to_lsu_stall := io.lsu_fastint_stall_any + }else{ + take_ext_int_start := 0.U(1.W) + ext_int_freeze := 0.U(1.W) + ext_int_freeze_d1 := 0.U(1.W) + take_ext_int_start_d1 := 0.U(1.W) + take_ext_int_start_d2 := 0.U(1.W) + take_ext_int_start_d3 := 0.U(1.W) + fast_int_meicpct := 0.U(1.W) + ignore_ext_int_due_to_lsu_stall := 0.U(1.W) + take_ext_int := ext_int_ready & ~block_interrupts + } + + take_ce_int := ce_int_ready & ~ext_int_ready & ~block_interrupts + take_soft_int := soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_timer_int := timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_int_timer0_int := (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~io.dec_csr_stall_int_ff & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_int_timer1_int := (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~io.dec_csr_stall_int_ff & ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_reset := reset_delayed & io.mpc_reset_run_req + take_nmi := nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr(DCSR_STEPIE) & ~io.dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) & ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & io.lsu_fir_error.orR)) + + + interrupt_valid_r := take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int + + + // Compute interrupt path: + // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE); + val vectored_path = Cat(mtvec(30,1),0.U(1.W)) + Cat(0.U(25.W),exc_cause_r, 0.U(1.W)) ///After Combining Code revisit this + val interrupt_path = Mux(take_nmi.asBool, io.nmi_vec, Mux(mtvec(0) === 1.U, vectored_path, Cat(mtvec(30,1),0.U(1.W))))///After Combining Code revisit this + val sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~io.dec_tlu_i0_valid_r) + val sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r + val sel_fir_addr = take_ext_int_start_d3 & ~io.lsu_fir_error.orR + synchronous_flush_r := i0_exception_valid_r | rfpc_i0_r | lsu_exc_valid_r | fence_i_r | lsu_i0_rfnpc_r | iccm_repair_state_rfnpc | debug_resume_req_f | sel_npc_resume | dec_tlu_wr_pause_r_d1 | i0_trigger_hit_r + tlu_flush_lower_r := interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start + ///After Combining Code revisit this + val tlu_flush_path_r = Mux(take_reset.asBool, io.rst_vec,Mux1H(Seq( + (sel_fir_addr).asBool -> io.lsu_fir_addr, + (take_nmi===0.U & sel_npc_r===1.U) -> npc_r, + (take_nmi===0.U & rfpc_i0_r===1.U & io.dec_tlu_i0_valid_r===1.U & sel_npc_r===0.U) -> io.dec_tlu_i0_pc_r, + (interrupt_valid_r===1.U & sel_fir_addr===0.U) -> interrupt_path, + ((i0_exception_valid_r | lsu_exc_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr).asBool -> Cat(mtvec(30,1),0.U(1.W)), + (~take_nmi & mret_r).asBool -> mepc, + (~take_nmi & debug_resume_req_f).asBool -> dpc, + (~take_nmi & sel_npc_resume).asBool -> npc_r_d1 + ))) + + val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this + + io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 + io.dec_tlu_flush_lower_r := tlu_flush_lower_r + io.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this + + // this is used to capture mepc, etc. + val exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r) + + interrupt_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} + val i0_exception_valid_r_d1 =withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} + exc_or_int_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} + val exc_cause_wb =withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} + val i0_valid_wb =withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} + val trigger_hit_r_d1 =withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} + take_nmi_r_d1 :=withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} + pause_expired_wb :=withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} + + val csr=Module(new csr_tlu) + csr.io.free_clk := io.free_clk + csr.io.active_clk := io.active_clk + csr.io.scan_mode := io.scan_mode + csr.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r + csr.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r + csr.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d + csr.io.dec_csr_wen_unq_d := io.dec_csr_wen_unq_d + csr.io.dec_i0_decode_d := io.dec_i0_decode_d + csr.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid + csr.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn + csr.io.dma_iccm_stall_any :=io.dma_iccm_stall_any + csr.io.dma_dccm_stall_any :=io.dma_dccm_stall_any + csr.io.lsu_store_stall_any :=io.lsu_store_stall_any + csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall + csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall + csr.io.dec_pmu_decode_stall :=io.dec_pmu_decode_stall + csr.io.ifu_pmu_fetch_stall :=io.ifu_pmu_fetch_stall + csr.io.dec_tlu_packet_r :=io.dec_tlu_packet_r + csr.io.exu_pmu_i0_br_ataken :=io.exu_pmu_i0_br_ataken + csr.io.exu_pmu_i0_br_misp :=io.exu_pmu_i0_br_misp + csr.io.dec_pmu_instr_decoded :=io.dec_pmu_instr_decoded + csr.io.ifu_pmu_instr_aligned :=io.ifu_pmu_instr_aligned + csr.io.exu_pmu_i0_pc4 :=io.exu_pmu_i0_pc4 + csr.io.ifu_pmu_ic_miss :=io.ifu_pmu_ic_miss + csr.io.ifu_pmu_ic_hit :=io.ifu_pmu_ic_hit + csr.io.dec_csr_wen_r := io.dec_csr_wen_r + csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted + csr.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write + csr.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read + csr.io.dma_pmu_any_write := io.dma_pmu_any_write + csr.io.dma_pmu_any_read := io.dma_pmu_any_read + csr.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy + csr.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r + csr.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r + csr.io.dec_csr_stall_int_ff := io.dec_csr_stall_int_ff + csr.io.dec_csr_any_unq_d := io.dec_csr_any_unq_d + csr.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy + csr.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error + csr.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error + csr.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned + csr.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn + csr.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data + csr.io.pic_pl := io.pic_pl + csr.io.pic_claimid := io.pic_claimid + csr.io.iccm_dma_sb_error := io.iccm_dma_sb_error + csr.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any + csr.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any + csr.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.mexintpend + csr.io.exu_npc_r := io.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d + io.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl + io.dec_tlu_meihap := csr.io.dec_tlu_meihap + io.dec_tlu_meipt := csr.io.dec_tlu_meipt + io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 + io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 + io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 + io.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt + io.trigger_pkt_any := csr.io.trigger_pkt_any + io.dec_tlu_mtval_wb1 := csr.io.dec_tlu_mtval_wb1 + io.dec_tlu_exc_cause_wb1 := csr.io.dec_tlu_exc_cause_wb1 + io.dec_tlu_perfcnt0 := csr.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := csr.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := csr.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := csr.io.dec_tlu_perfcnt3 + io.dec_tlu_misc_clk_override := csr.io.dec_tlu_misc_clk_override + io.dec_tlu_dec_clk_override := csr.io.dec_tlu_dec_clk_override + io.dec_tlu_ifu_clk_override := csr.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := csr.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := csr.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := csr.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := csr.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := csr.io.dec_tlu_icm_clk_override + io.dec_csr_rddata_d := csr.io.dec_csr_rddata_d + io.dec_tlu_pipelining_disable := csr.io.dec_tlu_pipelining_disable + io.dec_tlu_wr_pause_r := csr.io.dec_tlu_wr_pause_r + io.dec_tlu_mrac_ff := csr.io.dec_tlu_mrac_ff + io.dec_tlu_wb_coalescing_disable := csr.io.dec_tlu_wb_coalescing_disable + io.dec_tlu_bpred_disable := csr.io.dec_tlu_bpred_disable + io.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable + io.dec_tlu_core_ecc_disable := csr.io.dec_tlu_core_ecc_disable + io.dec_tlu_external_ldfwd_disable := csr.io.dec_tlu_external_ldfwd_disable + io.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.mexintpend + csr.io.exu_npc_r := io.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d + + + csr.io.rfpc_i0_r := rfpc_i0_r + csr.io.i0_trigger_hit_r := i0_trigger_hit_r + csr.io.exc_or_int_valid_r := exc_or_int_valid_r + csr.io.mret_r := mret_r + csr.io.dcsr_single_step_running_f := dcsr_single_step_running_f + csr.io.dec_timer_t0_pulse := dec_timer_t0_pulse + csr.io.dec_timer_t1_pulse := dec_timer_t1_pulse + csr.io.timer_int_sync := timer_int_sync + csr.io.soft_int_sync := soft_int_sync + csr.io.csr_wr_clk := csr_wr_clk + csr.io.ebreak_to_debug_mode_r := ebreak_to_debug_mode_r + csr.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted + csr.io.lsu_fir_error := io.lsu_fir_error + csr.io.tlu_flush_lower_r_d1 := tlu_flush_lower_r_d1 + csr.io.dec_tlu_flush_noredir_r_d1 := dec_tlu_flush_noredir_r_d1 + csr.io.tlu_flush_path_r_d1 := tlu_flush_path_r_d1 + csr.io.reset_delayed := reset_delayed + csr.io.interrupt_valid_r := interrupt_valid_r + csr.io.i0_exception_valid_r := i0_exception_valid_r + csr.io.lsu_exc_valid_r := lsu_exc_valid_r + csr.io.mepc_trigger_hit_sel_pc_r := mepc_trigger_hit_sel_pc_r + csr.io.e4e5_int_clk := e4e5_int_clk + csr.io.lsu_i0_exc_r := lsu_i0_exc_r + csr.io.inst_acc_r := inst_acc_r + csr.io.inst_acc_second_r := inst_acc_second_r + csr.io.take_nmi := take_nmi + csr.io.lsu_error_pkt_addr_r := lsu_error_pkt_addr_r + csr.io.exc_cause_r := exc_cause_r + csr.io.i0_valid_wb := i0_valid_wb + csr.io.exc_or_int_valid_r_d1 := exc_or_int_valid_r_d1 + csr.io.interrupt_valid_r_d1 := interrupt_valid_r_d1 + csr.io.clk_override := clk_override + csr.io.i0_exception_valid_r_d1 := i0_exception_valid_r_d1 + csr.io.lsu_i0_exc_r_d1 := lsu_i0_exc_r_d1 + csr.io.exc_cause_wb := exc_cause_wb + csr.io.nmi_lsu_store_type := nmi_lsu_store_type + csr.io.nmi_lsu_load_type := nmi_lsu_load_type + csr.io.tlu_i0_commit_cmt := tlu_i0_commit_cmt + csr.io.ebreak_r := ebreak_r + csr.io.ecall_r := ecall_r + csr.io.illegal_r := illegal_r + csr.io.mdseac_locked_f := mdseac_locked_f + csr.io.nmi_int_detected_f := nmi_int_detected_f + csr.io.internal_dbg_halt_mode_f2 := internal_dbg_halt_mode_f2 + csr.io.ext_int_freeze_d1 := ext_int_freeze_d1 + csr.io.ic_perr_r_d1 := ic_perr_r_d1 + csr.io.iccm_sbecc_r_d1 := iccm_sbecc_r_d1 + csr.io.lsu_single_ecc_error_r_d1 := lsu_single_ecc_error_r_d1 + csr.io.ifu_miss_state_idle_f := ifu_miss_state_idle_f + csr.io.lsu_idle_any_f := lsu_idle_any_f + csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f + csr.io.dbg_tlu_halted := dbg_tlu_halted + csr.io.debug_halt_req_f := debug_halt_req_f + csr.io.take_ext_int_start := take_ext_int_start + csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 + csr.io.trigger_hit_r_d1 := trigger_hit_r_d1 + csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f + csr.io.ebreak_to_debug_mode_r_d1 := ebreak_to_debug_mode_r_d1 + csr.io.debug_halt_req := debug_halt_req + csr.io.allow_dbg_halt_csr_write := allow_dbg_halt_csr_write + csr.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f + csr.io.enter_debug_halt_req := enter_debug_halt_req + csr.io.internal_dbg_halt_mode := internal_dbg_halt_mode + csr.io.request_debug_mode_done := request_debug_mode_done + csr.io.request_debug_mode_r := request_debug_mode_r + csr.io.update_hit_bit_r := update_hit_bit_r + csr.io.take_timer_int := take_timer_int + csr.io.take_int_timer0_int := take_int_timer0_int + csr.io.take_int_timer1_int := take_int_timer1_int + csr.io.take_ext_int := take_ext_int + csr.io.tlu_flush_lower_r := tlu_flush_lower_r + csr.io.dec_tlu_br0_error_r := dec_tlu_br0_error_r + csr.io.dec_tlu_br0_start_error_r := dec_tlu_br0_start_error_r + csr.io.lsu_pmu_load_external_r := lsu_pmu_load_external_r + csr.io.lsu_pmu_store_external_r := lsu_pmu_store_external_r + csr.io.csr_pkt := csr_pkt + + npc_r := csr.io.npc_r + npc_r_d1 := csr.io.npc_r_d1 + mie_ns := csr.io.mie_ns + mepc := csr.io.mepc + mdseac_locked_ns := csr.io.mdseac_locked_ns + force_halt := csr.io.force_halt + dpc := csr.io.dpc + mstatus_mie_ns := csr.io.mstatus_mie_ns + dec_csr_wen_r_mod := csr.io.dec_csr_wen_r_mod + fw_halt_req := csr.io.fw_halt_req + mstatus := csr.io.mstatus + dcsr := csr.io.dcsr + mtvec := csr.io.mtvec + mip := csr.io.mip + mtdata1_t :=csr.io.mtdata1_t + val csr_read=Module(new el2_dec_decode_csr_read) + csr_read.io.dec_csr_rdaddr_d:=io.dec_csr_rdaddr_d + csr_pkt:=csr_read.io.csr_pkt + + io.dec_tlu_presync_d := csr_pkt.presync & io.dec_csr_any_unq_d & ~io.dec_csr_wen_unq_d + io.dec_tlu_postsync_d := csr_pkt.postsync & io.dec_csr_any_unq_d + + // allow individual configuration of these features + val conditionally_illegal = (csr_pkt.csr_mitcnt0 | csr_pkt.csr_mitcnt1 | csr_pkt.csr_mitb0 | csr_pkt.csr_mitb1 | csr_pkt.csr_mitctl0 | csr_pkt.csr_mitctl1) & ~TIMER_LEGAL_EN.asUInt + val valid_csr = ( csr_pkt.legal & (~(csr_pkt.csr_dcsr | csr_pkt.csr_dpc | csr_pkt.csr_dmst | csr_pkt.csr_dicawics | csr_pkt.csr_dicad0 | csr_pkt.csr_dicad0h | csr_pkt.csr_dicad1 | csr_pkt.csr_dicago) | dbg_tlu_halted_f) & ~fast_int_meicpct & ~conditionally_illegal) + + io.dec_csr_legal_d := ( io.dec_csr_any_unq_d &valid_csr & ~(io.dec_csr_wen_unq_d & (csr_pkt.csr_mvendorid | csr_pkt.csr_marchid | csr_pkt.csr_mimpid | csr_pkt.csr_mhartid | csr_pkt.csr_mdseac | csr_pkt.csr_meihap)) ) +} + +trait CSRs{ + val MISA = "h301".U(12.W) + val MVENDORID = "hf11".U(12.W) + val MARCHID = "hf12".U(12.W) + val MIMPID = "hf13".U(12.W) + val MHARTID = "hf14".U(12.W) + val MSTATUS = "h300".U(12.W) + val MTVEC = "h305".U(12.W) + val MIP = "h344".U(12.W) + val MIE = "h304".U(12.W) + val MCYCLEL = "hb00".U(12.W) + val MCYCLEH = "hb80".U(12.W) + val MINSTRETL = "hb02".U(12.W) + val MINSTRETH = "hb82".U(12.W) + val MSCRATCH = "h340".U(12.W) + val MEPC = "h341".U(12.W) + val MCAUSE = "h342".U(12.W) + val MSCAUSE = "h7ff".U(12.W) + val MTVAL = "h343".U(12.W) + val MCGC = "h7f8".U(12.W) + val MFDC = "h7f9".U(12.W) + val MCPC = "h7c2".U(12.W) + val MRAC = "h7c0".U(12.W) + val MDEAU = "hbc0".U(12.W) + val MDSEAC = "hfc0".U(12.W) + val MPMC = "h7c6".U(12.W) + val MICECT = "h7f0".U(12.W) + val MICCMECT = "h7f1".U(12.W) + val MDCCMECT = "h7f2".U(12.W) + val MFDHT = "h7ce".U(12.W) + val MFDHS = "h7cf".U(12.W) + val MEIVT = "hbc8".U(12.W) + val MEIHAP = "hfc8".U(12.W) + val MEICURPL = "hbcc".U(12.W) + val MEICIDPL = "hbcb".U(12.W) + val MEICPCT = "hbca".U(12.W) + val MEIPT = "hbc9".U(12.W) + val DCSR = "h7b0".U(12.W) + val DPC = "h7b1".U(12.W) + val DICAWICS = "h7c8".U(12.W) + val DICAD0 = "h7c9".U(12.W) + val DICAD0H = "h7cc".U(12.W) + val DICAD1 = "h7ca".U(12.W) + val DICAGO = "h7cb".U(12.W) + val MTSEL = "h7a0".U(12.W) + val MTDATA1 = "h7a1".U(12.W) + val MTDATA2 = "h7a2".U(12.W) + val MHPMC3 = "hB03".U(12.W) + val MHPMC3H = "hB83".U(12.W) + val MHPMC4 = "hB04".U(12.W) + val MHPMC4H = "hB84".U(12.W) + val MHPMC5 = "hB05".U(12.W) + val MHPMC5H = "hB85".U(12.W) + val MHPMC6 = "hB06".U(12.W) + val MHPMC6H = "hB86".U(12.W) + val MHPME3 = "h323".U(12.W) + val MHPME4 = "h324".U(12.W) + val MHPME5 = "h325".U(12.W) + val MHPME6 = "h326".U(12.W) + val MCOUNTINHIBIT = "h320".U(12.W) + val MSTATUS_MIE = 0.U + val MIP_MCEIP = 5.U + val MIP_MITIP0 = 4.U + val MIP_MITIP1 = 3.U + val MIP_MEIP = 2 + val MIP_MTIP = 1 + val MIP_MSIP = 0 + val MIE_MCEIE = 5 + val MIE_MITIE0 = 4 + val MIE_MITIE1 = 3 + val MIE_MEIE = 2 + val MIE_MTIE = 1 + val MIE_MSIE = 0 + val DCSR_EBREAKM = 15 + val DCSR_STEPIE = 11 + val DCSR_STOPC = 10 + val DCSR_STEP = 2 + val MTDATA1_DMODE = 9 + val MTDATA1_SEL = 7 + val MTDATA1_ACTION = 6 + val MTDATA1_CHAIN = 5 + val MTDATA1_MATCH = 4 + val MTDATA1_M_ENABLED = 3 + val MTDATA1_EXE = 2 + val MTDATA1_ST = 1 + val MTDATA1_LD = 0 + val MHPME_NOEVENT = 0.U + val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe + val MHPME_ICACHE_HIT = 2.U // OOP + val MHPME_ICACHE_MISS = 3.U // OOP + val MHPME_INST_COMMIT = 4.U + val MHPME_INST_COMMIT_16B = 5.U + val MHPME_INST_COMMIT_32B = 6.U + val MHPME_INST_ALIGNED = 7.U // OOP + val MHPME_INST_DECODED = 8.U // OOP + val MHPME_INST_MUL = 9.U + val MHPME_INST_DIV = 10.U + val MHPME_INST_LOAD = 11.U + val MHPME_INST_STORE = 12.U + val MHPME_INST_MALOAD = 13.U + val MHPME_INST_MASTORE = 14.U + val MHPME_INST_ALU = 15.U + val MHPME_INST_CSRREAD = 16.U + val MHPME_INST_CSRRW = 17.U + val MHPME_INST_CSRWRITE = 18.U + val MHPME_INST_EBREAK = 19.U + val MHPME_INST_ECALL = 20.U + val MHPME_INST_FENCE = 21.U + val MHPME_INST_FENCEI = 22.U + val MHPME_INST_MRET = 23.U + val MHPME_INST_BRANCH = 24.U + val MHPME_BRANCH_MP = 25.U + val MHPME_BRANCH_TAKEN = 26.U + val MHPME_BRANCH_NOTP = 27.U + val MHPME_FETCH_STALL = 28.U // OOP + val MHPME_ALGNR_STALL = 29.U // OOP + val MHPME_DECODE_STALL = 30.U // OOP + val MHPME_POSTSYNC_STALL = 31.U // OOP + val MHPME_PRESYNC_STALL = 32.U // OOP + val MHPME_LSU_SB_WB_STALL = 34.U // OOP + val MHPME_DMA_DCCM_STALL = 35.U // OOP + val MHPME_DMA_ICCM_STALL = 36.U // OOP + val MHPME_EXC_TAKEN = 37.U + val MHPME_TIMER_INT_TAKEN = 38.U + val MHPME_EXT_INT_TAKEN = 39.U + val MHPME_FLUSH_LOWER = 40.U + val MHPME_BR_ERROR = 41.U + val MHPME_IBUS_TRANS = 42.U // OOP + val MHPME_DBUS_TRANS = 43.U // OOP + val MHPME_DBUS_MA_TRANS = 44.U // OOP + val MHPME_IBUS_ERROR = 45.U // OOP + val MHPME_DBUS_ERROR = 46.U // OOP + val MHPME_IBUS_STALL = 47.U // OOP + val MHPME_DBUS_STALL = 48.U // OOP + val MHPME_INT_DISABLED = 49.U // OOP + val MHPME_INT_STALLED = 50.U // OOP + val MHPME_INST_BITMANIP = 54.U + val MHPME_DBUS_LOAD = 55.U + val MHPME_DBUS_STORE = 56.U + // Counts even during sleep state + val MHPME_SLEEP_CYC = 512.U // OOP + val MHPME_DMA_READ_ALL = 513.U // OOP + val MHPME_DMA_WRITE_ALL = 514.U // OOP + val MHPME_DMA_READ_DCCM = 515.U // OOP + val MHPME_DMA_WRITE_DCCM = 516.U // OOP + + +} +class el2_CSR_IO extends Bundle with el2_lib { + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val scan_mode = Input(Bool()) + val dec_csr_wrdata_r = Input(UInt(32.W)) + val dec_csr_wraddr_r = Input(UInt(12.W)) + val dec_csr_rdaddr_d = Input(UInt(12.W)) + val dec_csr_wen_unq_d = Input(UInt(1.W)) + val dec_i0_decode_d = Input(UInt(1.W)) + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) + val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) + val trigger_pkt_any = Output(Vec(4, new el2_trigger_pkt_t)) + val ifu_pmu_bus_trxn = Input(UInt(1.W)) + val dma_iccm_stall_any = Input(UInt(1.W)) + val dma_dccm_stall_any = Input(UInt(1.W)) + val lsu_store_stall_any = Input(UInt(1.W)) + val dec_pmu_presync_stall = Input(UInt(1.W)) + val dec_pmu_postsync_stall = Input(UInt(1.W)) + val dec_pmu_decode_stall = Input(UInt(1.W)) + val ifu_pmu_fetch_stall = Input(UInt(1.W)) + val dec_tlu_packet_r = Input(new el2_trap_pkt_t) + val exu_pmu_i0_br_ataken = Input(UInt(1.W)) + val exu_pmu_i0_br_misp = Input(UInt(1.W)) + val dec_pmu_instr_decoded = Input(UInt(1.W)) + val ifu_pmu_instr_aligned = Input(UInt(1.W)) + val exu_pmu_i0_pc4 = Input(UInt(1.W)) + val ifu_pmu_ic_miss = Input(UInt(1.W)) + val ifu_pmu_ic_hit = Input(UInt(1.W)) + val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) + val dec_csr_wen_r = Input(UInt(1.W)) + //val dec_tlu_force_halt = Output(UInt(1.W)) + //val dec_tlu_flush_extint = Output(UInt(1.W)) + val dec_tlu_mtval_wb1 = Output(UInt(32.W)) + val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) + val dec_tlu_perfcnt0 = Output(UInt(1.W)) + val dec_tlu_perfcnt1 = Output(UInt(1.W)) + val dec_tlu_perfcnt2 = Output(UInt(1.W)) + val dec_tlu_perfcnt3 = Output(UInt(1.W)) + val dec_tlu_dbg_halted = Input(UInt(1.W)) + val dma_pmu_dccm_write = Input(UInt(1.W)) + val dma_pmu_dccm_read = Input(UInt(1.W)) + val dma_pmu_any_write = Input(UInt(1.W)) + val dma_pmu_any_read = Input(UInt(1.W)) + val lsu_pmu_bus_busy = Input(UInt(1.W)) + val dec_tlu_i0_pc_r = Input(UInt(31.W)) + val dec_tlu_i0_valid_r = Input(UInt(1.W)) + val dec_csr_stall_int_ff = Input(UInt(1.W)) + val dec_csr_any_unq_d = Input(UInt(1.W)) + val dec_tlu_misc_clk_override = Output(UInt(1.W)) + val dec_tlu_dec_clk_override = Output(UInt(1.W)) + val dec_tlu_ifu_clk_override = Output(UInt(1.W)) + val dec_tlu_lsu_clk_override = Output(UInt(1.W)) + val dec_tlu_bus_clk_override = Output(UInt(1.W)) + val dec_tlu_pic_clk_override = Output(UInt(1.W)) + val dec_tlu_dccm_clk_override = Output(UInt(1.W)) + val dec_tlu_icm_clk_override = Output(UInt(1.W)) + //val dec_csr_legal_d = Output(UInt(1.W)) + val dec_csr_rddata_d = Output(UInt(32.W)) + //val dec_tlu_postsync_d = Output(UInt(1.W)) + //val dec_tlu_presync_d = Output(UInt(1.W)) + //val dec_tlu_flush_pause_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_r = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_wb = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) + // val dec_tlu_flush_leak_one_r = Output(UInt(1.W)) + //val dec_tlu_debug_stall = Output(UInt(1.W)) + val dec_tlu_pipelining_disable = Output(UInt(1.W)) + val dec_tlu_wr_pause_r = Output(UInt(1.W)) + val ifu_pmu_bus_busy = Input(UInt(1.W)) + val lsu_pmu_bus_error = Input(UInt(1.W)) + val ifu_pmu_bus_error = Input(UInt(1.W)) + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) + val lsu_pmu_bus_trxn = Input(UInt(1.W)) + val ifu_ic_debug_rd_data = Input(UInt(71.W)) + val dec_tlu_meipt = Output(UInt(4.W)) + val pic_pl = Input(UInt(4.W)) + val dec_tlu_meicurpl = Output(UInt(4.W)) + val dec_tlu_meihap = Output(UInt(30.W)) + val pic_claimid = Input(UInt(8.W)) + val iccm_dma_sb_error = Input(UInt(1.W)) + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) + val lsu_imprecise_error_load_any = Input(UInt(1.W)) + val lsu_imprecise_error_store_any = Input(UInt(1.W)) + val dec_tlu_mrac_ff = Output(UInt(32.W)) + val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) + val dec_tlu_bpred_disable = Output(UInt(1.W)) + val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) + val dec_tlu_core_ecc_disable = Output(UInt(1.W)) + val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) + val dec_illegal_inst = Input(UInt(32.W)) + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) + val mexintpend = Input(UInt(1.W)) + val exu_npc_r = Input(UInt(31.W)) + val mpc_reset_run_req = Input(UInt(1.W)) + val rst_vec = Input(UInt(31.W)) + val core_id = Input(UInt(28.W)) + val dec_timer_rddata_d = Input(UInt(32.W)) + val dec_timer_read_d = Input(UInt(1.W)) + + + ////////////////////////////////////////////////// + val dec_csr_wen_r_mod = Output(UInt(1.W)) + val rfpc_i0_r = Input(UInt(1.W)) + val i0_trigger_hit_r = Input(UInt(1.W)) + val fw_halt_req = Output(UInt(1.W)) + val mstatus = Output(UInt(2.W)) + val exc_or_int_valid_r = Input(UInt(1.W)) // remove this after + val mret_r = Input(UInt(1.W)) + val mstatus_mie_ns = Output(UInt(1.W)) + val dcsr_single_step_running_f = Input(UInt(1.W)) + val dcsr = Output(UInt(16.W)) + val mtvec = Output(UInt(31.W)) + val mip = Output(UInt(6.W)) + val dec_timer_t0_pulse = Input(UInt(1.W)) + val dec_timer_t1_pulse = Input(UInt(1.W)) + val timer_int_sync = Input(UInt(1.W)) + val soft_int_sync = Input(UInt(1.W)) + val mie_ns = Output(UInt(6.W)) + val csr_wr_clk: Clock = Input(Clock()) // remove after + val ebreak_to_debug_mode_r = Input(UInt(1.W)) + val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) + val lsu_fir_error = Input(UInt(2.W)) + val npc_r = Output(UInt(31.W)) + val tlu_flush_lower_r_d1 = Input(UInt(1.W)) + val dec_tlu_flush_noredir_r_d1 = Input(UInt(1.W)) + val tlu_flush_path_r_d1 = Input(UInt(31.W)) + val npc_r_d1 = Output(UInt(31.W)) + val reset_delayed = Input(UInt(1.W)) + val mepc = Output(UInt(31.W)) + val interrupt_valid_r = Input(UInt(1.W)) + val i0_exception_valid_r = Input(UInt(1.W)) //delete after + val lsu_exc_valid_r = Input(UInt(1.W)) + val mepc_trigger_hit_sel_pc_r = Input(UInt(1.W)) //delete after + val e4e5_int_clk = Input(Clock()) //delete after + val lsu_i0_exc_r = Input(UInt(1.W)) + val inst_acc_r = Input(UInt(1.W)) + val inst_acc_second_r = Input(UInt(1.W)) + val take_nmi = Input(UInt(1.W)) + val lsu_error_pkt_addr_r = Input(UInt(32.W)) + val exc_cause_r = Input(UInt(5.W)) + val i0_valid_wb = Input(UInt(1.W)) + val exc_or_int_valid_r_d1 = Input(UInt(1.W)) + val interrupt_valid_r_d1 = Input(UInt(1.W)) + val clk_override = Input(UInt(1.W)) + val i0_exception_valid_r_d1 = Input(UInt(1.W)) + val lsu_i0_exc_r_d1 = Input(UInt(1.W)) + val exc_cause_wb = Input(UInt(5.W)) + val nmi_lsu_store_type = Input(UInt(1.W)) + val nmi_lsu_load_type = Input(UInt(1.W)) + val tlu_i0_commit_cmt = Input(UInt(1.W)) + val ebreak_r = Input(UInt(1.W)) + val ecall_r = Input(UInt(1.W)) + val illegal_r = Input(UInt(1.W)) + val mdseac_locked_ns = Output(UInt(1.W)) + val mdseac_locked_f = Input(UInt(1.W)) + val nmi_int_detected_f = Input(UInt(1.W)) + val internal_dbg_halt_mode_f2 = Input(UInt(1.W)) + val ext_int_freeze_d1 = Input(UInt(1.W)) + val ic_perr_r_d1 = Input(UInt(1.W)) + val iccm_sbecc_r_d1 = Input(UInt(1.W)) + val lsu_single_ecc_error_r_d1 = Input(UInt(1.W)) + val ifu_miss_state_idle_f = Input(UInt(1.W)) + val lsu_idle_any_f = Input(UInt(1.W)) + val dbg_tlu_halted_f = Input(UInt(1.W)) + val dbg_tlu_halted = Input(UInt(1.W)) + val debug_halt_req_f = Input(UInt(1.W)) + val force_halt = Output(UInt(1.W)) + val take_ext_int_start = Input(UInt(1.W)) + val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) + val trigger_hit_r_d1 = Input(UInt(1.W)) + val dcsr_single_step_done_f = Input(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) + val debug_halt_req = Input(UInt(1.W)) + val allow_dbg_halt_csr_write = Input(UInt(1.W)) + val internal_dbg_halt_mode_f = Input(UInt(1.W)) + val enter_debug_halt_req = Input(UInt(1.W)) + val internal_dbg_halt_mode = Input(UInt(1.W)) + val request_debug_mode_done = Input(UInt(1.W)) + val request_debug_mode_r = Input(UInt(1.W)) + val dpc = Output(UInt(31.W)) + val update_hit_bit_r = Input(UInt(4.W)) + val take_timer_int = Input(UInt(1.W)) + val take_int_timer0_int = Input(UInt(1.W)) + val take_int_timer1_int = Input(UInt(1.W)) + val take_ext_int = Input(UInt(1.W)) + val tlu_flush_lower_r = Input(UInt(1.W)) + val dec_tlu_br0_error_r = Input(UInt(1.W)) + val dec_tlu_br0_start_error_r = Input(UInt(1.W)) + val lsu_pmu_load_external_r = Input(UInt(1.W)) + val lsu_pmu_store_external_r = Input(UInt(1.W)) + val csr_pkt = Input(new el2_dec_tlu_csr_pkt) + val mtdata1_t = Output(Vec(4,UInt(10.W))) +} + +class csr_tlu extends Module with el2_lib with CSRs { + val io = IO(new el2_CSR_IO) + + ////////////////////////////////wires/////////////////////////////// + val miccme_ce_req = Wire(UInt(1.W)) + val mice_ce_req = Wire(UInt(1.W)) + val mdccme_ce_req = Wire(UInt(1.W)) + val pc_r_d1 = Wire(UInt(31.W)) + val mpmc_b_ns = Wire(UInt(1.W)) + val mpmc_b = Wire(UInt(1.W)) + val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) + val mcycleh = WireInit(UInt(32.W),0.U) + val minstretl_inc = WireInit(UInt(33.W),0.U) + val wr_minstreth_r = WireInit(UInt(1.W),0.U) + val minstretl = WireInit(UInt(32.W),0.U) + val minstreth_inc = WireInit(UInt(32.W),0.U) + val minstreth = WireInit(UInt(32.W),0.U) + val mfdc_ns = WireInit(UInt(15.W),0.U) + val mfdc_int = WireInit(UInt(15.W),0.U) + val mhpmc6_incr = WireInit(UInt(64.W),0.U) + val mhpmc5_incr = WireInit(UInt(64.W),0.U) + val mhpmc4_incr = WireInit(UInt(64.W),0.U) + val perfcnt_halted = WireInit(UInt(1.W),0.U) + val mhpmc3_incr = WireInit(UInt(64.W),0.U) + val mhpme_vec = Wire(Vec(4,UInt(10.W))) + val mtdata2_t = Wire(Vec(4,UInt(32.W))) + val wr_meicpct_r = WireInit(UInt(1.W),0.U) + val force_halt_ctr_f = WireInit(UInt(32.W),0.U) + val mdccmect_inc = WireInit(UInt(27.W),0.U) + val miccmect_inc = WireInit(UInt(27.W),0.U) + val fw_halted = WireInit(UInt(1.W),0.U) + val micect_inc = WireInit(UInt(27.W),0.U) + val mdseac_en = WireInit(UInt(1.W),0.U) + val mie = WireInit(UInt(6.W),0.U) + val mcyclel = WireInit(UInt(32.W),0.U) + val mscratch = WireInit(UInt(32.W),0.U) + val mcause = WireInit(UInt(32.W),0.U) + val mscause = WireInit(UInt(4.W),0.U) + val mtval = WireInit(UInt(32.W),0.U) + val meicurpl = WireInit(UInt(4.W),0.U) + val meicidpl = WireInit(UInt(4.W),0.U) + val meipt = WireInit(UInt(4.W),0.U) + val mfdc = WireInit(UInt(19.W),0.U) + val mtsel = WireInit(UInt(2.W),0.U) + val micect = WireInit(UInt(32.W),0.U) + val miccmect = WireInit(UInt(32.W),0.U) + val mdccmect = WireInit(UInt(32.W),0.U) + val mhpmc3h = WireInit(UInt(32.W),0.U) + val mhpmc3 = WireInit(UInt(32.W),0.U) + val mhpmc4h = WireInit(UInt(32.W),0.U) + val mhpmc4 = WireInit(UInt(32.W),0.U) + val mhpmc5h = WireInit(UInt(32.W),0.U) + val mhpmc5 = WireInit(UInt(32.W),0.U) + val mhpmc6h = WireInit(UInt(32.W),0.U) + val mhpmc6 = WireInit(UInt(32.W),0.U) + val mhpme3 = WireInit(UInt(10.W),0.U) + val mhpme4 = WireInit(UInt(10.W),0.U) + val mhpme5 = WireInit(UInt(10.W),0.U) + val mhpme6 = WireInit(UInt(10.W),0.U) + val mfdht = WireInit(UInt(6.W),0.U) + val mfdhs = WireInit(UInt(2.W),0.U) + val mcountinhibit = WireInit(UInt(7.W),0.U) + val mpmc = WireInit(UInt(1.W),0.U) + val dicad1 = WireInit(UInt(32.W),0.U) + ///////////////////////////////////////////////////////////////////////// + //---------------------------------------------------------------------- + // + // CSRs + // + //---------------------------------------------------------------------- + + // ---------------------------------------------------------------------- + // MSTATUS (RW) + // [12:11] MPP : Prior priv level, always 2'b11, not flopped + // [7] MPIE : Int enable previous [1] + // [3] MIE : Int enable [0] + + //When executing a MRET instruction, supposing MPP holds the value 3, MIE + //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 + + io.dec_csr_wen_r_mod := io.dec_csr_wen_r & !io.i0_trigger_hit_r & !io.rfpc_i0_r + val wr_mstatus_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSTATUS) + + // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... + val set_mie_pmu_fw_halt = !mpmc_b_ns & io.fw_halt_req + + val mstatus_ns = Mux1H(Seq( + (!wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.mstatus(MSTATUS_MIE)), + (wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(3)), + (io.mret_r & !io.exc_or_int_valid_r).asBool -> Cat(1.U, io.mstatus(1)), + (set_mie_pmu_fw_halt).asBool -> Cat(io.mstatus(1), 1.U), + (wr_mstatus_r & !io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), + (!wr_mstatus_r & !io.exc_or_int_valid_r & !io.mret_r & !set_mie_pmu_fw_halt).asBool -> io.mstatus)) + + // gate MIE if we are single stepping and DCSR[STEPIE] is off + io.mstatus_mie_ns := io.mstatus(MSTATUS_MIE) & (~io.dcsr_single_step_running_f | io.dcsr(DCSR_STEPIE)) + io.mstatus := withClock(io.free_clk) { + RegNext(mstatus_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MTVEC (RW) + // [31:2] BASE : Trap vector base address + // [1] - Reserved, not implemented, reads zero + // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) + + val wr_mtvec_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVEC) + val mtvec_ns = Cat(io.dec_csr_wrdata_r(31, 2), io.dec_csr_wrdata_r(0)) + io.mtvec := rvdffe(mtvec_ns, wr_mtvec_r.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MIP (RW) + // + // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending + // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending + // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending + // [11] MEIP : (RO) M-Mode external interrupt pending + // [7] MTIP : (RO) M-Mode timer interrupt pending + // [3] MSIP : (RO) M-Mode software interrupt pending + + val ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req) + + val mip_ns = Cat(ce_int, io.dec_timer_t0_pulse, io.dec_timer_t1_pulse, io.mexintpend, io.timer_int_sync, io.soft_int_sync) + io.mip := withClock(io.free_clk) { + RegNext(mip_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MIE (RW) + // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable + // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable + // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable + // [11] MEIE : (RW) M-Mode external interrupt enable + // [7] MTIE : (RW) M-Mode timer interrupt enable + // [3] MSIE : (RW) M-Mode software interrupt enable + + val wr_mie_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MIE) + io.mie_ns := Mux(wr_mie_r.asBool, Cat(io.dec_csr_wrdata_r(30, 28), io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), mie) + mie := withClock(io.csr_wr_clk) { + RegNext(io.mie_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MCYCLEL (RW) + // [31:0] : Lower Cycle count + + val kill_ebreak_count_r = io.ebreak_to_debug_mode_r & io.dcsr(DCSR_STOPC) + + val wr_mcyclel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEL) + + val mcyclel_cout_in = ~(kill_ebreak_count_r | (io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted | mcountinhibit(0)) + + + val mcyclel_inc = WireInit(UInt(33.W),0.U) + mcyclel_inc := mcyclel + Cat(0.U(31.W), mcyclel_cout_in) + val mcyclel_ns = Mux(wr_mcyclel_r.asBool, io.dec_csr_wrdata_r, mcyclel_inc) + val mcyclel_cout = mcyclel_inc(32).asBool + mcyclel := rvdffe(mcyclel_ns, (wr_mcyclel_r | mcyclel_cout_in.asUInt).asBool, clock, io.scan_mode) + val mcyclel_cout_f = withClock(io.free_clk) {RegNext((mcyclel_cout & !wr_mcycleh_r),0.U)} + // ---------------------------------------------------------------------- + // MCYCLEH (RW) + // [63:32] : Higher Cycle count + // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + + wr_mcycleh_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEH) + + val mcycleh_inc = mcycleh + Cat(0.U(31.W), mcyclel_cout_f) + val mcycleh_ns = Mux(wr_mcycleh_r.asBool, io.dec_csr_wrdata_r, mcycleh_inc) + + mcycleh := rvdffe(mcycleh_ns, (wr_mcycleh_r | mcyclel_cout_f).asBool, clock, io.scan_mode) + + + // ---------------------------------------------------------------------- + // MINSTRETL (RW) + // [31:0] : Lower Instruction retired count + // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects + // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the + // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the + // update occurs after the execution of the instruction. In particular, a value written to instret by + // one instruction will be the value read by the following instruction (i.e., the increment of instret + // caused by the first instruction retiring happens before the write of the new value)." + + + val i0_valid_no_ebreak_ecall_r = io.tlu_i0_commit_cmt & ~(io.ebreak_r | io.ecall_r | io.ebreak_to_debug_mode_r | io.illegal_r | mcountinhibit(2)).asBool + + val wr_minstretl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETL) + + minstretl_inc := minstretl + Cat(0.U(31.W),i0_valid_no_ebreak_ecall_r) + val minstretl_cout = minstretl_inc(32) + val minstret_enable = (i0_valid_no_ebreak_ecall_r | wr_minstretl_r).asBool + + val minstretl_ns = Mux(wr_minstretl_r.asBool, io.dec_csr_wrdata_r , minstretl_inc) + minstretl := rvdffe(minstretl_ns,minstret_enable.asBool,clock,io.scan_mode) + val minstret_enable_f = withClock(io.free_clk){RegNext(minstret_enable,0.U)} + val minstretl_cout_f = withClock(io.free_clk){RegNext((minstretl_cout & ~wr_minstreth_r),0.U)} + + val minstretl_read = minstretl + // ---------------------------------------------------------------------- + // MINSTRETH (RW) + // [63:32] : Higher Instret count + // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. + + wr_minstreth_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETH)).asBool + + + minstreth_inc := minstreth + Cat(0.U(31.W), minstretl_cout_f) + val minstreth_ns = Mux(wr_minstreth_r.asBool, io.dec_csr_wrdata_r, minstreth_inc) + + minstreth := rvdffe(minstreth_ns, (minstret_enable_f | wr_minstreth_r).asBool, clock, io.scan_mode) + + val minstreth_read = minstreth_inc + + // ---------------------------------------------------------------------- + // mscratch (RW) + // [31:0] : Scratch register + + val wr_mscratch_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCRATCH) + + mscratch := rvdffe(io.dec_csr_wrdata_r,wr_mscratch_r.asBool,clock,io.scan_mode) + + + // ---------------------------------------------------------------------- + // MEPC (RW) + // [31:1] : Exception PC + + // NPC + + val sel_exu_npc_r = !io.dec_tlu_dbg_halted & !io.tlu_flush_lower_r_d1 & io.dec_tlu_i0_valid_r + val sel_flush_npc_r = !io.dec_tlu_dbg_halted & io.tlu_flush_lower_r_d1 & !io.dec_tlu_flush_noredir_r_d1 + val sel_hold_npc_r = !sel_exu_npc_r & !sel_flush_npc_r + + io.npc_r := Mux1H(Seq( + sel_exu_npc_r.asBool -> io.exu_npc_r, + (!io.mpc_reset_run_req & io.reset_delayed).asBool -> io.rst_vec, // init to reset vector for mpc halt on reset case + sel_flush_npc_r.asBool -> io.tlu_flush_path_r_d1, + sel_hold_npc_r.asBool -> io.npc_r_d1 )) + + io.npc_r_d1 := rvdffe(io.npc_r,(sel_exu_npc_r | sel_flush_npc_r | io.reset_delayed).asBool,clock,io.scan_mode) + // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an + // interrupt before the next instruction. + val pc0_valid_r = (!io.dec_tlu_dbg_halted & io.dec_tlu_i0_valid_r).asBool + + val pc_r = Mux1H( Seq( + pc0_valid_r -> io.dec_tlu_i0_pc_r, + ~pc0_valid_r -> pc_r_d1 )) + + pc_r_d1 := rvdffe(pc_r, pc0_valid_r, clock, io.scan_mode) + + val wr_mepc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEPC) + + val mepc_ns = Mux1H( Seq( + (io.i0_exception_valid_r | io.lsu_exc_valid_r | io.mepc_trigger_hit_sel_pc_r).asBool -> pc_r, + (io.interrupt_valid_r).asBool -> io.npc_r, + (wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(31,1), + (!wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.mepc) ) + + io.mepc := withClock(io.e4e5_int_clk){RegNext(mepc_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MCAUSE (RW) + // [31:0] : Exception Cause + + val wr_mcause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCAUSE) + val mcause_sel_nmi_store = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_store_type + val mcause_sel_nmi_load = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_load_type + val mcause_sel_nmi_ext = io.exc_or_int_valid_r & io.take_nmi & io.lsu_fir_error.orR + // FIR value decoder + // 0 –no error + // 1 –uncorrectable ecc => f000_1000 + // 2 –dccm region access error => f000_1001 + // 3 –non dccm region access error => f000_1002 + val mcause_fir_error_type = Cat(io.lsu_fir_error.andR, (io.lsu_fir_error(1) & ~io.lsu_fir_error(0))) + + val mcause_ns = Mux1H(Seq( + mcause_sel_nmi_store.asBool -> "hf000_0000".U(32.W), + mcause_sel_nmi_load.asBool -> "hf000_0001".U(32.W), + mcause_sel_nmi_ext.asBool -> Cat("hf000_100".U(28.W), 0.U(2.W), mcause_fir_error_type), + (io.exc_or_int_valid_r & ~io.take_nmi).asBool -> Cat(io.interrupt_valid_r, 0.U(26.W), io.exc_cause_r), + (wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r, + (~wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> mcause) ) + + mcause := withClock(io.e4e5_int_clk){RegNext(mcause_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MSCAUSE (RW) + // [2:0] : Secondary exception Cause + + val wr_mscause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCAUSE) + + val ifu_mscause = Mux((io.dec_tlu_packet_r.icaf_type === 0.U(2.W)), "b1001".U, Cat(0.U(2.W) , io.dec_tlu_packet_r.icaf_type)) + + val mscause_type = Mux1H( Seq( + io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.mscause, + io.i0_trigger_hit_r.asBool -> "b0001".U, + io.ebreak_r.asBool -> "b0010".U, + io.inst_acc_r.asBool -> ifu_mscause )) + + + val mscause_ns = Mux1H( Seq( + (io.exc_or_int_valid_r).asBool -> mscause_type, + (wr_mscause_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(3,0), + (!wr_mscause_r & !io.exc_or_int_valid_r).asBool -> mscause)) + + mscause := withClock(io.e4e5_int_clk){RegNext(mscause_ns,0.U)} + + // ---------------------------------------------------------------------- + // MTVAL (RW) + // [31:0] : Exception address if relevant + + + val wr_mtval_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVAL) + val mtval_capture_pc_r = io.exc_or_int_valid_r & (io.ebreak_r | (io.inst_acc_r & ~io.inst_acc_second_r) | io.mepc_trigger_hit_sel_pc_r) & ~io.take_nmi + val mtval_capture_pc_plus2_r = io.exc_or_int_valid_r & (io.inst_acc_r & io.inst_acc_second_r) & ~io.take_nmi + val mtval_capture_inst_r = io.exc_or_int_valid_r & io.illegal_r & ~io.take_nmi + val mtval_capture_lsu_r = io.exc_or_int_valid_r & io.lsu_exc_valid_r & ~io.take_nmi + val mtval_clear_r = io.exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~io.mepc_trigger_hit_sel_pc_r + + + val mtval_ns = Mux1H(Seq( + (mtval_capture_pc_r).asBool -> Cat(pc_r, 0.U(1.W)), + (mtval_capture_pc_plus2_r).asBool -> Cat(pc_r + 1.U(31.W), 0.U(1.W)), + (mtval_capture_inst_r).asBool -> io.dec_illegal_inst, + (mtval_capture_lsu_r).asBool -> io.lsu_error_pkt_addr_r, + (wr_mtval_r & ~io.interrupt_valid_r.asUInt).asBool -> io.dec_csr_wrdata_r, + (~io.take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r).asBool -> mtval )) + + mtval := withClock(io.e4e5_int_clk){RegNext(mtval_ns,0.U)} + + // ---------------------------------------------------------------------- + // MCGC (RW) Clock gating control + // [31:9] : Reserved, reads 0x0 + // [8] : misc_clk_override + // [7] : dec_clk_override + // [6] : unused + // [5] : ifu_clk_override + // [4] : lsu_clk_override + // [3] : bus_clk_override + // [2] : pic_clk_override + // [1] : dccm_clk_override + // [0] : icm_clk_override + // + val wr_mcgc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCGC) + + val mcgc = rvdffe(io.dec_csr_wrdata_r(8,0),wr_mcgc_r.asBool,clock,io.scan_mode) + + io.dec_tlu_misc_clk_override := mcgc(8) + io.dec_tlu_dec_clk_override := mcgc(7) + io.dec_tlu_ifu_clk_override := mcgc(5) + io.dec_tlu_lsu_clk_override := mcgc(4) + io.dec_tlu_bus_clk_override := mcgc(3) + io.dec_tlu_pic_clk_override := mcgc(2) + io.dec_tlu_dccm_clk_override := mcgc(1) + io.dec_tlu_icm_clk_override := mcgc(0) + + // ---------------------------------------------------------------------- + // MFDC (RW) Feature Disable Control + // [31:19] : Reserved, reads 0x0 + // [18:16] : DMA QoS Prty + // [15:12] : Reserved, reads 0x0 + // [11] : Disable external load forwarding + // [10] : Disable dual issue + // [9] : Disable pic multiple ints + // [8] : Disable core ecc + // [7] : Unused, 0x0 + // [6] : Disable Sideeffect lsu posting + // [5:4] : Unused, 0x0 + // [3] : Disable branch prediction and return stack + // [2] : Disable write buffer coalescing + // [1] : Unused, 0x0 + // [0] : Disable pipelining - Enable single instruction execution + // + val wr_mfdc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDC) + + + + mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) + // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); + + if(BUILD_AXI4 == true){ + // flip poweron value of bit 6 for AXI build + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) + mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) + } + else { + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,0)) + mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,0)) + } + + + io.dec_tlu_dma_qos_prty := mfdc(18,16) + io.dec_tlu_external_ldfwd_disable := mfdc(11) + io.dec_tlu_core_ecc_disable := mfdc(8) + io.dec_tlu_sideeffect_posted_disable := mfdc(6) + io.dec_tlu_bpred_disable := mfdc(3) + io.dec_tlu_wb_coalescing_disable := mfdc(2) + io.dec_tlu_pipelining_disable := mfdc(0) + + + // ---------------------------------------------------------------------- + // MCPC (RW) Pause counter + // [31:0] : Reads 0x0, decs in the wb register in decode_ctl + + + + io.dec_tlu_wr_pause_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCPC) & ~io.interrupt_valid_r & ~io.take_ext_int_start + + + // ---------------------------------------------------------------------- + // MRAC (RW) + // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs + + val wr_mrac_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MRAC) + + // prevent pairs of 0x11, side_effect and cacheable + val mrac_in = Cat(io.dec_csr_wrdata_r(31), io.dec_csr_wrdata_r(30) & ~io.dec_csr_wrdata_r(31), + io.dec_csr_wrdata_r(29), io.dec_csr_wrdata_r(28) & ~io.dec_csr_wrdata_r(29), + io.dec_csr_wrdata_r(27), io.dec_csr_wrdata_r(26) & ~io.dec_csr_wrdata_r(27), + io.dec_csr_wrdata_r(25), io.dec_csr_wrdata_r(24) & ~io.dec_csr_wrdata_r(25), + io.dec_csr_wrdata_r(23), io.dec_csr_wrdata_r(22) & ~io.dec_csr_wrdata_r(23), + io.dec_csr_wrdata_r(21), io.dec_csr_wrdata_r(20) & ~io.dec_csr_wrdata_r(21), + io.dec_csr_wrdata_r(19), io.dec_csr_wrdata_r(18) & ~io.dec_csr_wrdata_r(19), + io.dec_csr_wrdata_r(17), io.dec_csr_wrdata_r(16) & ~io.dec_csr_wrdata_r(17), + io.dec_csr_wrdata_r(15), io.dec_csr_wrdata_r(14) & ~io.dec_csr_wrdata_r(15), + io.dec_csr_wrdata_r(13), io.dec_csr_wrdata_r(12) & ~io.dec_csr_wrdata_r(13), + io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(10) & ~io.dec_csr_wrdata_r(11), + io.dec_csr_wrdata_r(9), io.dec_csr_wrdata_r(8) & ~io.dec_csr_wrdata_r(9), + io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(6) & ~io.dec_csr_wrdata_r(7), + io.dec_csr_wrdata_r(5), io.dec_csr_wrdata_r(4) & ~io.dec_csr_wrdata_r(5), + io.dec_csr_wrdata_r(3), io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(3), + io.dec_csr_wrdata_r(1), io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(1)) + + + val mrac = rvdffe(mrac_in,wr_mrac_r.asBool,clock,io.scan_mode) + // drive to LSU/IFU + io.dec_tlu_mrac_ff := mrac + + + // ---------------------------------------------------------------------- + // MDEAU (WAR0) + // [31:0] : Dbus Error Address Unlock register + // + + val wr_mdeau_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDEAU) + + + // ---------------------------------------------------------------------- + // MDSEAC (R) + // [31:0] : Dbus Store Error Address Capture register + // + + + // only capture error bus if the MDSEAC reg is not locked + io.mdseac_locked_ns := mdseac_en | (io.mdseac_locked_f & ~wr_mdeau_r) + + mdseac_en := (io.lsu_imprecise_error_store_any | io.lsu_imprecise_error_load_any) & ~io.nmi_int_detected_f & ~io.mdseac_locked_f + + val mdseac = rvdffe(io.lsu_imprecise_error_addr_any,mdseac_en.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MPMC (R0W1) + // [0] : FW halt + // [1] : Set MSTATUS[MIE] on halt + + + + val wr_mpmc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MPMC) + + // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to + // set the io.mstatus bit potentially, use delayed version of internal dbg halt. + io.fw_halt_req := wr_mpmc_r & io.dec_csr_wrdata_r(0) & ~io.internal_dbg_halt_mode_f2 & ~io.ext_int_freeze_d1 + + val fw_halted_ns = (io.fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt + mpmc_b_ns := Mux(wr_mpmc_r.asBool, ~io.dec_csr_wrdata_r(1), ~mpmc) + + mpmc_b := withClock(io.csr_wr_clk){RegNext(mpmc_b_ns,0.U)} + fw_halted := withClock(io.free_clk){RegNext(fw_halted_ns,0.U)} + + mpmc := ~mpmc_b + + // ---------------------------------------------------------------------- + // MICECT (I-Cache error counter/threshold) + // [31:27] : Icache parity error threshold + // [26:0] : Icache parity error count + + + + val csr_sat = Mux((io.dec_csr_wrdata_r(31,27) > 26.U(5.W)), 26.U(5.W), io.dec_csr_wrdata_r(31,27)) + + val wr_micect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICECT) + micect_inc := micect + Cat(0.U(26.W), io.ic_perr_r_d1) + val micect_ns = Mux(wr_micect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(micect(31,27), micect_inc)) + + micect := rvdffe(micect_ns,(wr_micect_r | io.ic_perr_r_d1).asBool,clock,io.scan_mode) + + mice_ce_req := ("hffffffff".U(32.W) << micect(31,27)).orR & Cat(0.U(5.W), micect(26,0)) + + // ---------------------------------------------------------------------- + // MICCMECT (ICCM error counter/threshold) + // [31:27] : ICCM parity error threshold + // [26:0] : ICCM parity error count + + + + val wr_miccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICCMECT) + miccmect_inc := miccmect(26,0) + Cat(0.U(26.W), (io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error)) + val miccmect_ns = Mux(wr_miccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(miccmect(31,27), miccmect_inc)) + + miccmect := rvdffe(miccmect_ns,(wr_miccmect_r | io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error).asBool,clock,io.scan_mode) + miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccmect(26,0))).orR + + // ---------------------------------------------------------------------- + // MDCCMECT (DCCM error counter/threshold) + // [31:27] : DCCM parity error threshold + // [26:0] : DCCM parity error count + + + + val wr_mdccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDCCMECT) + mdccmect_inc := mdccmect(26,0) + Cat(0.U(26.W), io.lsu_single_ecc_error_r_d1) + val mdccmect_ns = Mux(wr_mdccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(mdccmect(31,27), mdccmect_inc)) + + mdccmect := rvdffe(mdccmect_ns, (wr_mdccmect_r | io.lsu_single_ecc_error_r_d1).asBool, clock, io.scan_mode) + + mdccme_ce_req := (("hffffffff".U(32.W) << mdccmect(31,27)) & Cat(0.U(5.W), mdccmect(26,0))).orR + + + // ---------------------------------------------------------------------- + // MFDHT (Force Debug Halt Threshold) + // [5:1] : Halt timeout threshold (power of 2) + // [0] : Halt timeout enabled + + + + val wr_mfdht_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHT) + + val mfdht_ns = Mux(wr_mfdht_r.asBool, io.dec_csr_wrdata_r(5,0) , mfdht) + + mfdht := withClock(io.active_clk){RegNext(mfdht_ns,0.U)} + + // ---------------------------------------------------------------------- + // MFDHS(RW) + // [1] : LSU operation pending when debug halt threshold reached + // [0] : IFU operation pending when debug halt threshold reached + + + + val wr_mfdhs_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHS) + + val mfdhs_ns = Mux(wr_mfdhs_r.asBool, io.dec_csr_wrdata_r(1,0) , + Mux((io.dbg_tlu_halted & ~io.dbg_tlu_halted_f).asBool, Cat(~io.lsu_idle_any_f, ~io.ifu_miss_state_idle_f) , mfdhs)) + + mfdhs := withClock(io.active_clk){RegEnable(mfdhs_ns,0.U,(wr_mfdhs_r | io.dbg_tlu_halted).asBool)} + + val force_halt_ctr = Mux(io.debug_halt_req_f.asBool, (force_halt_ctr_f + 1.U(32.W)) , + Mux(io.dbg_tlu_halted_f.asBool, 0.U(32.W) , force_halt_ctr_f)) + + force_halt_ctr_f := withClock(io.active_clk){RegEnable(force_halt_ctr,0.U,mfdht(0))} + + io.force_halt := mfdht(0) & (force_halt_ctr_f & ("hffffffff".U(32.W) << mfdht(5,1))).orR + + + // ---------------------------------------------------------------------- + // MEIVT (External Interrupt Vector Table (R/W)) + // [31:10]: Base address (R/W) + // [9:0] : Reserved, reads 0x0 + + val wr_meivt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIVT) + + val meivt = rvdffe(io.dec_csr_wrdata_r(31,10),wr_meivt_r.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MEIHAP (External Interrupt Handler Access Pointer (R)) + // [31:10]: Base address (R/W) + // [9:2] : ClaimID (R) + // [1:0] : Reserved, 0x0 + + + + val wr_meihap_r = wr_meicpct_r + + val meihap = rvdffe(io.pic_claimid,wr_meihap_r.asBool,clock,io.scan_mode) + io.dec_tlu_meihap := Cat(meivt, meihap,0.U(2.W)) + + // ---------------------------------------------------------------------- + // MEICURPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) + + + + val wr_meicurpl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICURPL) + val meicurpl_ns = Mux(wr_meicurpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicurpl) + + meicurpl := withClock(io.csr_wr_clk){RegNext(meicurpl_ns,0.U)} + // PIC needs this reg + io.dec_tlu_meicurpl := meicurpl + + + // ---------------------------------------------------------------------- + // MEICIDPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : External Interrupt Claim ID's Priority Level Register + + + + val wr_meicidpl_r = (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICIDPL)) | io.take_ext_int_start + + val meicidpl_ns = Mux(wr_meicpct_r.asBool, io.pic_pl, + Mux(wr_meicidpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicidpl)) + + meicidpl := withClock(io.free_clk){RegNext(meicidpl_ns,0.U)} + + // ---------------------------------------------------------------------- + // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL + // [31:1] : Reserved (read 0x0) + // [0] : Capture (W1, Read 0) + + wr_meicpct_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICPCT)) | io.take_ext_int_start + + // ---------------------------------------------------------------------- + // MEIPT (External Interrupt Priority Threshold) + // [31:4] : Reserved (read 0x0) + // [3:0] : PRITHRESH + + + + val wr_meipt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIPT) + val meipt_ns = Mux(wr_meipt_r.asBool, io.dec_csr_wrdata_r(3,0), meipt) + + meipt := withClock(io.active_clk){RegNext(meipt_ns,0.U)} + // to PIC + io.dec_tlu_meipt := meipt + + // ---------------------------------------------------------------------- + // DCSR (R/W) (Only accessible in debug mode) + // [31:28] : xdebugver (hard coded to 0x4) RO + // [27:16] : 0x0, reserved + // [15] : ebreakm + // [14] : 0x0, reserved + // [13] : ebreaks (0x0 for this core) + // [12] : ebreaku (0x0 for this core) + // [11] : stepie + // [10] : stopcount + // [9] : 0x0 //stoptime + // [8:6] : cause (RO) + // [5:4] : 0x0, reserved + // [3] : nmip + // [2] : step + // [1:0] : prv (0x3 for this core) + // + + // RV has clarified that 'priority 4' in the spec means top priority. + // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. + + // RV debug spec indicates a cause priority change for trigger hits during single step. + + + val trigger_hit_for_dscr_cause_r_d1 = io.trigger_hit_dmode_r_d1 | (io.trigger_hit_r_d1 & io.dcsr_single_step_done_f); + + val dcsr_cause = Mux1H(Seq( + (io.dcsr_single_step_done_f & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~io.debug_halt_req).asBool -> "b100".U(3.W), + (io.debug_halt_req & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b011".U(3.W), + (io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b001".U(3.W), + (trigger_hit_for_dscr_cause_r_d1).asBool -> "b010".U(3.W) )) + + val wr_dcsr_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DCSR) + + + + // Multiple halt enter requests can happen before we are halted. + // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade. + val dcsr_cause_upgradeable = io.internal_dbg_halt_mode_f & (io.dcsr(8,6) === "b011".U(3.W)) + val enter_debug_halt_req_le = io.enter_debug_halt_req & (~io.dbg_tlu_halted | dcsr_cause_upgradeable) + + val nmi_in_debug_mode = io.nmi_int_detected_f & io.internal_dbg_halt_mode_f + val dcsr_ns = Mux(enter_debug_halt_req_le.asBool, Cat(io.dcsr(15,9), dcsr_cause, io.dcsr(5,2),"b11".U(2.W)) ,//prv 0x3 for this core + Mux(wr_dcsr_r.asBool, Cat(io.dec_csr_wrdata_r(15), 0.U(3.W), io.dec_csr_wrdata_r(11,10), 0.U(1.W), io.dcsr(8,6), 0.U(2.W), nmi_in_debug_mode | io.dcsr(3), io.dec_csr_wrdata_r(2), "b11".U(2.W)) , Cat(io.dcsr(15,4), nmi_in_debug_mode, io.dcsr(2),"b11".U(2.W)))) + + io.dcsr := rvdffe(dcsr_ns, (enter_debug_halt_req_le | wr_dcsr_r | io.internal_dbg_halt_mode | io.take_nmi).asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // DPC (R/W) (Only accessible in debug mode) + // [31:0] : Debug PC + + + + val wr_dpc_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DPC) + val dpc_capture_npc = io.dbg_tlu_halted & ~io.dbg_tlu_halted_f & ~io.request_debug_mode_done + val dpc_capture_pc = io.request_debug_mode_r + + val dpc_ns = Mux1H(Seq( + (~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r).asBool -> io.dec_csr_wrdata_r(31,1), + (dpc_capture_pc).asBool -> pc_r, + (~dpc_capture_pc & dpc_capture_npc).asBool -> io.npc_r )) + + io.dpc := rvdffe(dpc_ns,(wr_dpc_r | dpc_capture_pc | dpc_capture_npc).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAWICS (R/W) (Only accessible in debug mode) + // [31:25] : Reserved + // [24] : Array select, 0 is data, 1 is tag + // [23:22] : Reserved + // [21:20] : Way select + // [19:17] : Reserved + // [16:3] : Index + // [2:0] : Reserved + + + + val dicawics_ns = Cat(io.dec_csr_wrdata_r(24), io.dec_csr_wrdata_r(21,20), io.dec_csr_wrdata_r(16,3)) + val wr_dicawics_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAWICS) + + val dicawics = rvdffe(dicawics_ns,wr_dicawics_r.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAD0 (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [31:0] : inst data + // + // If io.dicawics[array] is 1 + // [31:16] : Tag + // [15:7] : Reserved + // [6:4] : LRU + // [3:1] : Reserved + // [0] : Valid + + + val wr_dicad0_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0) + val dicad0_ns = Mux(wr_dicad0_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) + + val dicad0 = rvdffe(dicad0_ns, (wr_dicad0_r | io.ifu_ic_debug_rd_data_valid).asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAD0H (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [63:32] : inst data + // + + + val wr_dicad0h_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0H) + + val dicad0h_ns = Mux(wr_dicad0h_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(63,32)) + + val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) + + if (ICACHE_ECC == true) { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [6:0] : ECC + + val dicad1_raw = WireInit(UInt(7.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) + + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) + + dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(25.W), dicad1_raw) + + } + else { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [3:0] : Parity + + + val dicad1_raw = WireInit(UInt(4.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) + + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(3,0), io.ifu_ic_debug_rd_data(67,64)) + + dicad1_raw :=withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(28.W), dicad1_raw) + } + + // ---------------------------------------------------------------------- + // DICAGO (R/W) (Only accessible in debug mode) + // [0] : Go + + if (ICACHE_ECC == true) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) + else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) + + io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics + + val icache_rd_valid = io.allow_dbg_halt_csr_write & io.dec_csr_any_unq_d & io.dec_i0_decode_d & ~io.dec_csr_wen_unq_d & (io.dec_csr_rdaddr_d(11,0) === DICAGO) + val icache_wr_valid = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAGO) + + val icache_rd_valid_f = withClock(io.active_clk){RegNext(icache_rd_valid,0.U)} + val icache_wr_valid_f = withClock(io.active_clk){RegNext(icache_wr_valid,0.U)} + + io.dec_tlu_ic_diag_pkt.icache_rd_valid := icache_rd_valid_f + io.dec_tlu_ic_diag_pkt.icache_wr_valid := icache_wr_valid_f + + // ---------------------------------------------------------------------- + // MTSEL (R/W) + // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count + + + + val wr_mtsel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTSEL) + val mtsel_ns = Mux(wr_mtsel_r.asBool, io.dec_csr_wrdata_r(1,0), mtsel) + + mtsel := withClock(io.csr_wr_clk){RegNext(mtsel_ns,0.U)} + // ---------------------------------------------------------------------- + // MTDATA1 (R/W) + // [31:0] : Trigger Data 1 + // for triggers 0, 1, 2 and 3 aka Match Control + // [31:28] : type, hard coded to 0x2 + // [27] : dmode + // [26:21] : hard coded to 0x1f + // [20] : hit + // [19] : select (0 - address, 1 - data) + // [18] : timing, always 'before', reads 0x0 + // [17:12] : action, bits [17:13] not implemented and reads 0x0 + // [11] : chain + // [10:7] : match, bits [10:8] not implemented and reads 0x0 + // [6] : M + // [5:3] : not implemented, reads 0x0 + // [2] : execute + // [1] : store + // [0] : load + // + // decoder ring + // [27] : => 9 + // [20] : => 8 + // [19] : => 7 + // [12] : => 6 + // [11] : => 5 + // [7] : => 4 + // [6] : => 3 + // [2] : => 2 + // [1] : => 1 + // [0] : => 0 + + + + // don't allow setting load-data. + val tdata_load = io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(19) + // don't allow setting execute-data. + val tdata_opcode = io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(19) + // don't allow clearing DMODE and action=1 + val tdata_action = (io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f) & io.dec_csr_wrdata_r(12) + + val tdata_wrdata_r = Cat(io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f, io.dec_csr_wrdata_r(20,19), tdata_action, io.dec_csr_wrdata_r(11), + io.dec_csr_wrdata_r(7,6), tdata_opcode, io.dec_csr_wrdata_r(1), tdata_load) + + // If the DMODE bit is set, tdata1 can only be updated in debug_mode + val wr_mtdata1_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA1) & (mtsel === 0.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) + val mtdata1_t_ns = VecInit.tabulate(4)(i => Mux(wr_mtdata1_t_r(i).asBool, tdata_wrdata_r, Cat(io.mtdata1_t(i)(9), io.update_hit_bit_r(i) | io.mtdata1_t(i)(8), io.mtdata1_t(i)(7,0)))) + + for(i <- 0 until 4) { io.mtdata1_t(i) := withClock(io.active_clk){RegNext(mtdata1_t_ns(i),0.U)}} + + + val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) + for(i <- 0 until 4 ){ + io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) + io.trigger_pkt_any(i).match_ := io.mtdata1_t(i)(MTDATA1_MATCH) + io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) + io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) + io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) + io.trigger_pkt_any(i).m := io.mtdata1_t(i)(MTDATA1_M_ENABLED) + } + + // ---------------------------------------------------------------------- + // MTDATA2 (R/W) + // [31:0] : Trigger Data 2 + // If the DMODE bit is set, tdata2 can only be updated in debug_mode + val wr_mtdata2_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA2) & (mtsel === i.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) + for(i <- 0 until 4) { mtdata2_t(i) := rvdffe(io.dec_csr_wrdata_r,wr_mtdata2_t_r(i).asBool,clock,io.scan_mode)} + + + + val mtdata2_tsel_out = Mux1H((0 until 4).map(i =>(mtsel === i.U(2.W)) -> mtdata2_t(i))) + for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} + + + //---------------------------------------------------------------------- + // Performance Monitor Counters section starts + //---------------------------------------------------------------------- + + + + // Pack the event selects into a vector for genvar + mhpme_vec(0) := mhpme3 + mhpme_vec(1) := mhpme4 + mhpme_vec(2) := mhpme5 + mhpme_vec(3) := mhpme6 + + import el2_inst_pkt_t._ + // only consider committed itypes + + + val pmu_i0_itype_qual = io.dec_tlu_packet_r.pmu_i0_itype & Fill(4,io.tlu_i0_commit_cmt) + val mhpmc_inc_r = Wire(Vec(4,UInt(1.W))) + val mhpmc_inc_r_d1 = Wire(Vec(4,UInt(1.W))) + + // Generate the muxed incs for all counters based on event type + for(i <- 0 until 4) { + mhpmc_inc_r(i) := (~mcountinhibit(i+3) & (Mux1H(Seq( + (mhpme_vec(i) === MHPME_CLK_ACTIVE ).asBool -> 1.U, + (mhpme_vec(i) === MHPME_ICACHE_HIT ).asBool -> io.ifu_pmu_ic_hit, + (mhpme_vec(i) === MHPME_ICACHE_MISS ).asBool -> io.ifu_pmu_ic_miss, + (mhpme_vec(i) === MHPME_INST_COMMIT ).asBool -> (io.tlu_i0_commit_cmt & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_COMMIT_16B ).asBool -> (io.tlu_i0_commit_cmt & ~io.exu_pmu_i0_pc4 & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_COMMIT_32B ).asBool -> (io.tlu_i0_commit_cmt & io.exu_pmu_i0_pc4 & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_ALIGNED ).asBool -> io.ifu_pmu_instr_aligned, + (mhpme_vec(i) === MHPME_INST_DECODED ).asBool -> io.dec_pmu_instr_decoded, + (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (mhpme_vec(i) === MHPME_INST_MUL ).asBool -> (pmu_i0_itype_qual === MUL), + (mhpme_vec(i) === MHPME_INST_DIV ).asBool -> (io.dec_tlu_packet_r.pmu_divide & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_INST_LOAD ).asBool -> (pmu_i0_itype_qual === LOAD), + (mhpme_vec(i) === MHPME_INST_STORE ).asBool -> (pmu_i0_itype_qual === STORE), + (mhpme_vec(i) === MHPME_INST_MALOAD ).asBool -> ((pmu_i0_itype_qual === LOAD) & io.dec_tlu_packet_r.pmu_lsu_misaligned + (mhpme_vec(i) === MHPME_INST_MASTORE) & (pmu_i0_itype_qual === STORE) & + io.dec_tlu_packet_r.pmu_lsu_misaligned.asBool), + (mhpme_vec(i) === MHPME_INST_ALU).asBool -> (pmu_i0_itype_qual === ALU), + (mhpme_vec(i) === MHPME_INST_CSRREAD ).asBool -> (pmu_i0_itype_qual === CSRREAD), + (mhpme_vec(i) === MHPME_INST_CSRWRITE).asBool -> (pmu_i0_itype_qual === CSRWRITE), + (mhpme_vec(i) === MHPME_INST_CSRRW ).asBool -> (pmu_i0_itype_qual === CSRRW), + (mhpme_vec(i) === MHPME_INST_EBREAK ).asBool -> (pmu_i0_itype_qual === EBREAK), + (mhpme_vec(i) === MHPME_INST_ECALL ).asBool -> (pmu_i0_itype_qual === ECALL), + (mhpme_vec(i) === MHPME_INST_FENCE ).asBool -> (pmu_i0_itype_qual === FENCE), + (mhpme_vec(i) === MHPME_INST_FENCEI ).asBool -> (pmu_i0_itype_qual === FENCEI), + (mhpme_vec(i) === MHPME_INST_MRET ).asBool -> (pmu_i0_itype_qual === MRET), + (mhpme_vec(i) === MHPME_INST_BRANCH ).asBool -> ((pmu_i0_itype_qual === CONDBR) | (pmu_i0_itype_qual === JAL)), + (mhpme_vec(i) === MHPME_BRANCH_MP ).asBool -> (io.exu_pmu_i0_br_misp & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_BRANCH_TAKEN ).asBool -> (io.exu_pmu_i0_br_ataken & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_BRANCH_NOTP ).asBool -> (io.dec_tlu_packet_r.pmu_i0_br_unpred & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_FETCH_STALL ).asBool -> io.ifu_pmu_fetch_stall, + (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (mhpme_vec(i) === MHPME_POSTSYNC_STALL ).asBool -> io.dec_pmu_postsync_stall, + (mhpme_vec(i) === MHPME_PRESYNC_STALL ).asBool -> io.dec_pmu_presync_stall, + (mhpme_vec(i) === MHPME_LSU_SB_WB_STALL ).asBool -> io.lsu_store_stall_any, + (mhpme_vec(i) === MHPME_DMA_DCCM_STALL ).asBool -> io.dma_dccm_stall_any, + (mhpme_vec(i) === MHPME_DMA_ICCM_STALL ).asBool -> io.dma_iccm_stall_any, + (mhpme_vec(i) === MHPME_EXC_TAKEN ).asBool -> (io.i0_exception_valid_r | io.i0_trigger_hit_r | io.lsu_exc_valid_r), + (mhpme_vec(i) === MHPME_TIMER_INT_TAKEN ).asBool -> (io.take_timer_int | io.take_int_timer0_int | io.take_int_timer1_int), + (mhpme_vec(i) === MHPME_EXT_INT_TAKEN ).asBool -> io.take_ext_int, + (mhpme_vec(i) === MHPME_FLUSH_LOWER ).asBool -> io.tlu_flush_lower_r, + (mhpme_vec(i) === MHPME_BR_ERROR ).asBool -> ((io.dec_tlu_br0_error_r | io.dec_tlu_br0_start_error_r) & io.rfpc_i0_r), + (mhpme_vec(i) === MHPME_IBUS_TRANS ).asBool -> io.ifu_pmu_bus_trxn, + (mhpme_vec(i) === MHPME_DBUS_TRANS ).asBool -> io.lsu_pmu_bus_trxn, + (mhpme_vec(i) === MHPME_DBUS_MA_TRANS ).asBool -> io.lsu_pmu_bus_misaligned, + (mhpme_vec(i) === MHPME_IBUS_ERROR ).asBool -> io.ifu_pmu_bus_error, + (mhpme_vec(i) === MHPME_DBUS_ERROR ).asBool -> io.lsu_pmu_bus_error, + (mhpme_vec(i) === MHPME_IBUS_STALL ).asBool -> io.ifu_pmu_bus_busy, + (mhpme_vec(i) === MHPME_DBUS_STALL ).asBool -> io.lsu_pmu_bus_busy, + (mhpme_vec(i) === MHPME_INT_DISABLED ).asBool -> (~io.mstatus(MSTATUS_MIE)), + (mhpme_vec(i) === MHPME_INT_STALLED ).asBool -> (~io.mstatus(MSTATUS_MIE) & (io.mip(5,0) & mie(5,0))), + (mhpme_vec(i) === MHPME_INST_BITMANIP ).asBool -> (pmu_i0_itype_qual === BITMANIPU), + (mhpme_vec(i) === MHPME_DBUS_LOAD ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_load_external_r), + (mhpme_vec(i) === MHPME_DBUS_STORE ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_store_external_r), + // These count even during sleep + (mhpme_vec(i) === MHPME_SLEEP_CYC ).asBool -> io.dec_tlu_pmu_fw_halted, + (mhpme_vec(i) === MHPME_DMA_READ_ALL ).asBool -> io.dma_pmu_any_read, + (mhpme_vec(i) === MHPME_DMA_WRITE_ALL ).asBool -> io.dma_pmu_any_write, + (mhpme_vec(i) === MHPME_DMA_READ_DCCM ).asBool -> io.dma_pmu_dccm_read, + (mhpme_vec(i) === MHPME_DMA_WRITE_DCCM ).asBool -> io.dma_pmu_dccm_write )))) + } + + mhpmc_inc_r_d1(0) := withClock(io.free_clk){RegNext(mhpmc_inc_r(0),0.U)} + mhpmc_inc_r_d1(1) := withClock(io.free_clk){RegNext(mhpmc_inc_r(1),0.U)} + mhpmc_inc_r_d1(2) := withClock(io.free_clk){RegNext(mhpmc_inc_r(2),0.U)} + mhpmc_inc_r_d1(3) := withClock(io.free_clk){RegNext(mhpmc_inc_r(3),0.U)} + val perfcnt_halted_d1 = withClock(io.free_clk){RegNext(perfcnt_halted,0.U)} + + + perfcnt_halted := ((io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted) + val perfcnt_during_sleep = (Fill(4,~(io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)))) & Cat(mhpme_vec(3)(9),mhpme_vec(2)(9),mhpme_vec(1)(9),mhpme_vec(0)(9)) + + io.dec_tlu_perfcnt0 := mhpmc_inc_r_d1(0) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(0)) + io.dec_tlu_perfcnt1 := mhpmc_inc_r_d1(1) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(1)) + io.dec_tlu_perfcnt2 := mhpmc_inc_r_d1(2) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(2)) + io.dec_tlu_perfcnt3 := mhpmc_inc_r_d1(3) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(3)) + + // ---------------------------------------------------------------------- + // MHPMC3H(RW), MHPMC3(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 3 + + val mhpmc3_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3) + val mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(0)) & ((mhpmc_inc_r(0)).orR) + val mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1 + + + mhpmc3_incr := Cat(mhpmc3h(31,0),mhpmc3(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(0)) + val mhpmc3_ns = Mux(mhpmc3_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(31,0)) + + mhpmc3 := rvdffe(mhpmc3_ns,mhpmc3_wr_en.asBool,clock,io.scan_mode) + + val mhpmc3h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3H) + val mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1 + val mhpmc3h_ns = Mux(mhpmc3h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(63,32)) + + mhpmc3h := rvdffe(mhpmc3h_ns, mhpmc3h_wr_en.asBool, clock, io.scan_mode) + // ---------------------------------------------------------------------- + // MHPMC4H(RW), MHPMC4(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 4 + + val mhpmc4_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4) + val mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(1)) & ((mhpmc_inc_r(1)).orR) + val mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1 + + + + mhpmc4_incr := Cat(mhpmc4h(31,0),mhpmc4(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(1)) + val mhpmc4_ns = Mux(mhpmc4_wr_en0.asBool, io.dec_csr_wrdata_r(31,0), mhpmc4_incr(31,0)) + mhpmc4 := rvdffe(mhpmc4_ns, mhpmc4_wr_en.asBool, clock, io.scan_mode) + + val mhpmc4h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4H) + val mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1 + val mhpmc4h_ns = Mux(mhpmc4h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc4_incr(63,32)) + mhpmc4h := rvdffe(mhpmc4h_ns, mhpmc4h_wr_en.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MHPMC5H(RW), MHPMC5(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 5 + + val mhpmc5_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5) + val mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(2)) & ((mhpmc_inc_r(2)).orR) + val mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1 + + mhpmc5_incr := Cat(mhpmc5h(31,0),mhpmc5(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(2)) + val mhpmc5_ns = Mux(mhpmc5_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(31,0)) + + mhpmc5 := rvdffe(mhpmc5_ns, mhpmc5_wr_en.asBool, clock, io.scan_mode) + + val mhpmc5h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5H) + val mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1 + val mhpmc5h_ns = Mux(mhpmc5h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(63,32)) + + mhpmc5h := rvdffe(mhpmc5h_ns, mhpmc5h_wr_en.asBool, clock, io.scan_mode) + // ---------------------------------------------------------------------- + // MHPMC6H(RW), MHPMC6(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 6 + + val mhpmc6_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6) + val mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(3)) & ((mhpmc_inc_r(3)).orR) + val mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1 + + mhpmc6_incr := Cat(mhpmc6h(31,0),mhpmc6(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(3)) + val mhpmc6_ns = Mux(mhpmc6_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(31,0)) + + mhpmc6 := rvdffe(mhpmc6_ns, mhpmc6_wr_en.asBool, clock, io.scan_mode) + + val mhpmc6h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6H) + val mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1 + val mhpmc6h_ns = Mux(mhpmc6h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(63,32)) + + mhpmc6h := rvdffe(mhpmc6h_ns, mhpmc6h_wr_en.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MHPME3(RW) + // [9:0] : Hardware Performance Monitor Event 3 + + // we only have events 0-56, 512-516, HPME* are WARL so saturate otherwise + val event_saturate_r = Mux(((io.dec_csr_wrdata_r(9,0) > 516.U(10.W)) | (io.dec_csr_wrdata_r(31,10)).orR), 516.U(10.W), io.dec_csr_wrdata_r(9,0)) + + val wr_mhpme3_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME3) + + mhpme3 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme3_r.asBool)} + // ---------------------------------------------------------------------- + // MHPME4(RW) + // [9:0] : Hardware Performance Monitor Event 4 + + val wr_mhpme4_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME4) + mhpme4 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme4_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME5(RW) + // [9:0] : Hardware Performance Monitor Event 5 + + val wr_mhpme5_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME5) + mhpme5 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme5_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME6(RW) + // [9:0] : Hardware Performance Monitor Event 6 + + val wr_mhpme6_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME6) + mhpme6 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme6_r.asBool)} + //---------------------------------------------------------------------- + // Performance Monitor Counters section ends + //---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + + // MCOUNTINHIBIT(RW) + // [31:7] : Reserved, read 0x0 + // [6] : HPM6 disable + // [5] : HPM5 disable + // [4] : HPM4 disable + // [3] : HPM3 disable + // [2] : MINSTRET disable + // [1] : reserved, read 0x0 + // [0] : MCYCLE disable + + val wr_mcountinhibit_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCOUNTINHIBIT) + + val temp_ncount0 = WireInit(UInt(1.W),mcountinhibit(0)) + val temp_ncount1 = WireInit(UInt(1.W),mcountinhibit(1)) + val temp_ncount6_2 = WireInit(UInt(5.W),mcountinhibit(6,2)) + temp_ncount6_2 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(6,2),0.U,wr_mcountinhibit_r.asBool)} + + temp_ncount0 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(0),0.U,wr_mcountinhibit_r.asBool)} + mcountinhibit := Cat(temp_ncount6_2, 0.U(1.W),temp_ncount0) + //-------------------------------------------------------------------------------- + // trace + //-------------------------------------------------------------------------------- + + + + val trace_tclk = rvclkhdr(clock, (io.i0_valid_wb | io.exc_or_int_valid_r_d1 | io.interrupt_valid_r_d1 | io.dec_tlu_i0_valid_wb1 | + io.dec_tlu_i0_exc_valid_wb1 | io.dec_tlu_int_valid_wb1 | io.clk_override).asBool, io.scan_mode) + + io.dec_tlu_i0_valid_wb1 := withClock(trace_tclk){RegNext(io.i0_valid_wb,0.U)} + io.dec_tlu_i0_exc_valid_wb1 := withClock(trace_tclk){RegNext((io.i0_exception_valid_r_d1 | io.lsu_i0_exc_r_d1 | (io.trigger_hit_r_d1 & ~io.trigger_hit_dmode_r_d1)),0.U)} + io.dec_tlu_exc_cause_wb1 := withClock(trace_tclk){RegNext(io.exc_cause_wb,0.U)} + io.dec_tlu_int_valid_wb1 := withClock(trace_tclk){RegNext(io.interrupt_valid_r_d1,0.U)} + + io.dec_tlu_mtval_wb1 := mtval + + // end trace + //-------------------------------------------------------------------------------- + // CSR read mux + io.dec_csr_rddata_d:=Mux1H(Seq( + io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), + io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), + io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), + io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), + io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), + io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), + io.csr_pkt.csr_mip.asBool -> Cat(0.U(1.W), io.mip(5,3), 0.U(16.W), io.mip(2), 0.U(3.W), io.mip(1), 0.U(3.W), io.mip(0), 0.U(3.W)), + io.csr_pkt.csr_mie.asBool -> Cat(0.U(1.W), mie(5,3), 0.U(16.W), mie(2), 0.U(3.W), mie(1), 0.U(3.W), mie(0), 0.U(3.W)), + io.csr_pkt.csr_mcyclel.asBool -> mcyclel(31,0), + io.csr_pkt.csr_mcycleh.asBool -> mcycleh_inc(31,0), + io.csr_pkt.csr_minstretl.asBool -> minstretl_read(31,0), + io.csr_pkt.csr_minstreth.asBool -> minstreth_read(31,0), + io.csr_pkt.csr_mscratch.asBool -> mscratch(31,0), + io.csr_pkt.csr_mepc.asBool -> Cat(io.mepc,0.U(1.W)), + io.csr_pkt.csr_mcause.asBool -> mcause(31,0), + io.csr_pkt.csr_mscause.asBool -> Cat(0.U(28.W), mscause(3,0)), + io.csr_pkt.csr_mtval.asBool -> mtval(31,0), + io.csr_pkt.csr_mrac.asBool -> mrac(31,0), + io.csr_pkt.csr_mdseac.asBool -> mdseac(31,0), + io.csr_pkt.csr_meivt.asBool -> Cat(meivt, 0.U(10.W)), + io.csr_pkt.csr_meihap.asBool -> Cat(meivt, meihap, 0.U(2.W)), + io.csr_pkt.csr_meicurpl.asBool -> Cat(0.U(28.W), meicurpl(3,0)), + io.csr_pkt.csr_meicidpl.asBool -> Cat(0.U(28.W), meicidpl(3,0)), + io.csr_pkt.csr_meipt.asBool -> Cat(0.U(28.W), meipt(3,0)), + io.csr_pkt.csr_mcgc.asBool -> Cat(0.U(23.W), mcgc(8,0)), + io.csr_pkt.csr_mfdc.asBool -> Cat(0.U(13.W), mfdc(18,0)), + io.csr_pkt.csr_dcsr.asBool -> Cat(0x4000.U(16.W), io.dcsr(15,2), 3.U(2.W)), + io.csr_pkt.csr_dpc.asBool -> Cat(io.dpc, 0.U(1.W)), + io.csr_pkt.csr_dicad0.asBool -> dicad0(31,0), + io.csr_pkt.csr_dicad0h.asBool -> dicad0h(31,0), + io.csr_pkt.csr_dicad1.asBool -> dicad1(31,0), + io.csr_pkt.csr_dicawics.asBool -> Cat(0.U(7.W), dicawics(16), 0.U(2.W), dicawics(15,14), 0.U(3.W), dicawics(13,0), 0.U(3.W)), + io.csr_pkt.csr_mtsel.asBool -> Cat(0.U(30.W), mtsel(1,0)), + io.csr_pkt.csr_mtdata1.asBool -> mtdata1_tsel_out(31,0), + io.csr_pkt.csr_mtdata2.asBool -> mtdata2_tsel_out(31,0), + io.csr_pkt.csr_micect.asBool -> micect(31,0), + io.csr_pkt.csr_miccmect.asBool -> miccmect(31,0), + io.csr_pkt.csr_mdccmect.asBool -> mdccmect(31,0), + io.csr_pkt.csr_mhpmc3.asBool -> mhpmc3(31,0), + io.csr_pkt.csr_mhpmc4.asBool -> mhpmc4(31,0), + io.csr_pkt.csr_mhpmc5.asBool -> mhpmc5(31,0), + io.csr_pkt.csr_mhpmc6.asBool -> mhpmc6(31,0), + io.csr_pkt.csr_mhpmc3h.asBool -> mhpmc3h(31,0), + io.csr_pkt.csr_mhpmc4h.asBool -> mhpmc4h(31,0), + io.csr_pkt.csr_mhpmc5h.asBool -> mhpmc5h(31,0), + io.csr_pkt.csr_mhpmc6h.asBool -> mhpmc6h(31,0), + io.csr_pkt.csr_mfdht.asBool -> Cat(0.U(26.W), mfdht(5,0)), + io.csr_pkt.csr_mfdhs.asBool -> Cat(0.U(30.W), mfdhs(1,0)), + io.csr_pkt.csr_mhpme3.asBool -> Cat(0.U(22.W), mhpme3(9,0)), + io.csr_pkt.csr_mhpme4.asBool -> Cat(0.U(22.W), mhpme4(9,0)), + io.csr_pkt.csr_mhpme5.asBool -> Cat(0.U(22.W),mhpme5(9,0)), + io.csr_pkt.csr_mhpme6.asBool -> Cat(0.U(22.W),mhpme6(9,0)), + io.csr_pkt.csr_mcountinhibit.asBool -> Cat(0.U(25.W), mcountinhibit(6,0)), + io.csr_pkt.csr_mpmc.asBool -> Cat(0.U(30.W), mpmc, 0.U(1.W)), + io.dec_timer_read_d.asBool -> io.dec_timer_rddata_d(31,0) + )) + + + +} + + +class el2_dec_decode_csr_read_IO extends Bundle with el2_lib { + val dec_csr_rdaddr_d=Input(UInt(12.W)) + val csr_pkt=Output(new el2_dec_tlu_csr_pkt) +} + +class el2_dec_decode_csr_read extends Module with el2_lib { + val io=IO(new el2_dec_decode_csr_read_IO) + + def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_) + // 'z' is used for !io.dec_csr_rdaddr_d(0) + io.csr_pkt.csr_misa :=pattern(List(-11,-6,-5,-2,0)) + io.csr_pkt.csr_mvendorid :=pattern(List(10,-7,-1,0)) + io.csr_pkt.csr_marchid :=pattern(List(10,-7,1,'z')) + io.csr_pkt.csr_mimpid :=pattern(List(10,-6,1,0)) + io.csr_pkt.csr_mhartid :=pattern(List(10,-7,2)) + io.csr_pkt.csr_mstatus :=pattern(List(-11,-6,-5,-2,'z')) + io.csr_pkt.csr_mtvec :=pattern(List(-11,-6,-5,2,0)) + io.csr_pkt.csr_mip :=pattern(List(-7,6,2)) + io.csr_pkt.csr_mie :=pattern(List(-11,-6,-5,2,'z')) + io.csr_pkt.csr_mcyclel :=pattern(List(11,-7,-4,-3,-2,-1)) + io.csr_pkt.csr_mcycleh :=pattern(List(7,-6,-5,-4,-3,-2,-1)) + io.csr_pkt.csr_minstretl :=pattern(List(-7,-6,-4,-3,-2,1,'z')) + io.csr_pkt.csr_minstreth :=pattern(List(-10,7,-4,-3,-2,1,'z')) + io.csr_pkt.csr_mscratch :=pattern(List(-7,6,-2,-1,'z')) + io.csr_pkt.csr_mepc :=pattern(List(-7,6,-1,0)) + io.csr_pkt.csr_mcause :=pattern(List(-7,6,1,'z')) + io.csr_pkt.csr_mscause :=pattern(List(6,5,2)) + io.csr_pkt.csr_mtval :=pattern(List(-7,6,1,0)) + io.csr_pkt.csr_mrac :=pattern(List(-11,7,-5,-3,-2,-1)) + io.csr_pkt.csr_dmst :=pattern(List(10,-4,-3,2,-1)) + io.csr_pkt.csr_mdseac :=pattern(List(11,10,-4,-3)) + io.csr_pkt.csr_meihap :=pattern(List(11,10,3)) + io.csr_pkt.csr_meivt :=pattern(List(-10,6,3,-2,-1,'z')) + io.csr_pkt.csr_meipt :=pattern(List(11,6,-1,0)) + io.csr_pkt.csr_meicurpl :=pattern(List(11,6,2)) + io.csr_pkt.csr_meicidpl :=pattern(List(11,6,1,0)) + io.csr_pkt.csr_dcsr :=pattern(List(10,-6,5,4,'z')) + io.csr_pkt.csr_mcgc :=pattern(List(10,4,3,'z')) + io.csr_pkt.csr_mfdc :=pattern(List(10,4,3,-1,0)) + io.csr_pkt.csr_dpc :=pattern(List(10,-6,5,4,0)) + io.csr_pkt.csr_mtsel :=pattern(List(10,5,-4,-1,'z')) + io.csr_pkt.csr_mtdata1 :=pattern(List(10,-4,-3,0)) + io.csr_pkt.csr_mtdata2 :=pattern(List(10,5,-4,1)) + io.csr_pkt.csr_mhpmc3 :=pattern(List(11,-7,-4,-3,-2,0)) + io.csr_pkt.csr_mhpmc4 :=pattern(List(11,-7,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpmc5 :=pattern(List(11,-7,-4,-3,-1,0)) + io.csr_pkt.csr_mhpmc6 :=pattern(List(-7,-5,-4,-3,2,1,'z')) + io.csr_pkt.csr_mhpmc3h :=pattern(List(7,-4,-3,-2,1,0)) + io.csr_pkt.csr_mhpmc4h :=pattern(List(7,-6,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpmc5h :=pattern(List(7,-4,-3,2,-1,0)) + io.csr_pkt.csr_mhpmc6h :=pattern(List(7,-6,-4,-3,2,1,'z')) + io.csr_pkt.csr_mhpme3 :=pattern(List(-7,5,-4,-3,-2,0)) + io.csr_pkt.csr_mhpme4 :=pattern(List(5,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpme5 :=pattern(List(5,-4,-3,2,-1,0)) + io.csr_pkt.csr_mhpme6 :=pattern(List(5,-4,-3,2,1,'z')) + io.csr_pkt.csr_mcountinhibit :=pattern(List(-7,5,-4,-3,-2,'z')) + io.csr_pkt.csr_mitctl0 :=pattern(List(6,-5,4,-1,'z')) + io.csr_pkt.csr_mitctl1 :=pattern(List(6,-3,2,1,0)) + io.csr_pkt.csr_mitb0 :=pattern(List(6,-5,4,-2,0)) + io.csr_pkt.csr_mitb1 :=pattern(List(6,4,2,1,'z')) + io.csr_pkt.csr_mitcnt0 :=pattern(List(6,-5,4,-2,'z')) + io.csr_pkt.csr_mitcnt1 :=pattern(List(6,2,-1,0)) + io.csr_pkt.csr_mpmc :=pattern(List(6,-4,-3,2,1)) + io.csr_pkt.csr_mcpc :=pattern(List(10,6,-4,-3,-2,1)) + io.csr_pkt.csr_meicpct :=pattern(List(11,6,1,'z')) + io.csr_pkt.csr_mdeau :=pattern(List(-10,7,6,-3)) + io.csr_pkt.csr_micect :=pattern(List(6,5,-3,-1,'z')) + io.csr_pkt.csr_miccmect :=pattern(List(6,5,-3,0)) + io.csr_pkt.csr_mdccmect :=pattern(List(6,5,1,'z')) + io.csr_pkt.csr_mfdht :=pattern(List(6,3,2,1,'z')) + io.csr_pkt.csr_mfdhs :=pattern(List(6,-4,2,0)) + io.csr_pkt.csr_dicawics :=pattern(List(-11,-5,3,-2,-1,'z')) + io.csr_pkt.csr_dicad0h :=pattern(List(10,3,2,-1)) + io.csr_pkt.csr_dicad0 :=pattern(List(10,-4,3,-1,0)) + io.csr_pkt.csr_dicad1 :=pattern(List(10,3,-2,1,'z')) + io.csr_pkt.csr_dicago :=pattern(List(10,3,-2,1,0)) + io.csr_pkt.presync := pattern(List(10,4,3,-1,0)) | pattern(List(-7,5,-4,-3,-2,'z')) | pattern(List(-6,-5,-4,-3,-2,1)) | + pattern(List(11,-4,-3,2,-1)) | pattern(List(11,-4,-3,1,'z')) | pattern(List(7,-5,-4,-3,-2,1)) + io.csr_pkt.postsync := pattern(List(10,4,3,-1,0)) | pattern(List(-11,-6,-5,2,0)) | pattern(List(-7,6,-1,0)) | + pattern(List(10,-4,-3,0)) | pattern(List(-11,-7,-6,-4,-3,-2,'z')) | pattern(List(-11,7,6,-4,-3,-1))| + pattern(List(10,-4,-3,-2,1)) + io.csr_pkt.legal := pattern(List(-11,10,9,8,7,6,4,-3,-2,1,'z')) | pattern(List(-11,-10,9,8,-7,-6,-5,-4,-3,-1)) | + pattern(List(-11,-10,9,8,-7,-6,5,-1,'z')) | pattern(List(11,9,8,7,6,-5,-4,-2,-1,'z')) | + pattern(List(11,-10,9,8,-6,-5,'z')) | pattern(List(-11,10,9,8,7,6,5,4,3,2,1,0)) | + pattern(List(-11,10,9,8,7,6,5,4,-2,-1)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,0)) | + pattern(List(-11,10,9,8,7,-6,5,-3,-2,-1)) | pattern(List(-11,-10,9,8,-7,-6,5,2)) | + pattern(List(11,9,8,-7,-6,-5,4,-3,2,-1,'z')) | pattern(List(-11,10,9,8,7,6,-5,-4,3,1)) | + pattern(List(-11,10,9,8,7,6,-5,4,-3,2)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,1)) | + pattern(List(-11,-10,9,8,-7,-6,5,1,0)) | pattern(List(11,-10,9,8,7,-5,-4,3,-2)) | + pattern(List(11,-10,9,8,7,-5,-4,3,-1,'z')) | pattern(List(11,-10,9,8,-6,-5,2)) | + pattern(List(-11,10,9,8,7,6,-5 ,4,-3,1)) | pattern(List(-11,10,9,8,7,6 ,-5,-4,'z')) | + pattern(List(-11,10,9,8,7,6 ,-5,-4,3,-2)) | pattern(List(-11,10,9,8,7,-6,5,-4,-3,-2,'z')) | + pattern(List(11,-10,9,8,-6,-5,1)) | pattern(List(-11,-10,9,8,-7,6,-5,-4,-3,-2)) | + pattern(List(-11,-10,9,8,-7,-5,-4,-3,-1,'z')) | pattern(List(-11,-10,9,8,-7,-6,5,3)) | + pattern(List(11,-10,9,8,-6,-5,3)) | pattern(List(-11,-10,9,8,-7,-6,5,4)) | + pattern(List(11,-10,9,8,-6,-5,4)) +} + + +class el2_dec_timer_ctl extends Module with el2_lib { + val io=IO(new el2_dec_timer_ctl_IO) + val MITCTL_ENABLE=0 + val MITCTL_ENABLE_HALTED=1 + val MITCTL_ENABLE_PAUSED=2 + + val mitctl1=Wire(UInt(4.W)) + val mitctl0=Wire(UInt(3.W)) + val mitb1 =Wire(UInt(32.W)) + val mitb0 =Wire(UInt(32.W)) + val mitcnt1=Wire(UInt(32.W)) + val mitcnt0=Wire(UInt(32.W)) + + val mit0_match_ns=(mitcnt0 >= mitb0).asUInt + val mit1_match_ns=(mitcnt1 >= mitb1).asUInt + + io.dec_timer_t0_pulse := mit0_match_ns + io.dec_timer_t1_pulse := mit1_match_ns + // ---------------------------------------------------------------------- + // MITCNT0 (RW) + // [31:0] : Internal Timer Counter 0 + + val MITCNT0 =0x7d2.U(12.W) + + val wr_mitcnt0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT0) + + val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers + val mitcnt0_inc = mitcnt0 + 1.U(32.W) + val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc)) + mitcnt0 := rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MITCNT1 (RW) + // [31:0] : Internal Timer Counter 0 + + val MITCNT1=0x7d5.U(12.W) + val wr_mitcnt1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT1).asUInt + + val mitcnt1_inc_ok = mitctl1(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl1(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl1(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers + + // only inc MITCNT1 if not cascaded with 0, or if 0 overflows + val mitcnt1_inc = mitcnt1 + Cat(Fill(31,0.U(1.W)),(~mitctl1(3) | mit0_match_ns)) + val mitcnt1_ns = Mux(mit1_match_ns.asBool, 0.U, Mux(wr_mitcnt1_r.asBool, io.dec_csr_wrdata_r,mitcnt1_inc)) + mitcnt1 := rvdffe(mitcnt1_ns,(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MITB0 (RW) + // [31:0] : Internal Timer Bound 0 + val MITB0 =0x7d3.U(12.W) + + val wr_mitb0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITB0) + val mitb0_b = rvdffe((~io.dec_csr_wrdata_r),wr_mitb0_r.asBool,clock,io.scan_mode) + mitb0 := ~mitb0_b + + // ---------------------------------------------------------------------- + // MITB1 (RW) + // [31:0] : Internal Timer Bound 1 + + val MITB1 =0x7d6.U(12.W) + val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1) + val mitb1_b = rvdffe(~io.dec_csr_wrdata_r,wr_mitb1_r.asBool,clock,io.scan_mode) + mitb1 := ~mitb1_b + + // ---------------------------------------------------------------------- + // MITCTL0 (RW) Internal Timer Ctl 0 + // [31:3] : Reserved, reads 0x0 + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + + val MITCTL0 =0x7d4.U(12.W) + + val wr_mitctl0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCTL0) + val mitctl0_ns = Mux(wr_mitctl0_r.asBool, io.dec_csr_wrdata_r(2,0), mitctl0(2,0)) + + val mitctl0_0_b_ns = ~mitctl0_ns(0) + val mitctl0_0_b = withClock(io.free_clk){RegNext(mitctl0_0_b_ns,0.U)} + mitctl0 :=Cat(withClock(io.free_clk){RegNext(mitctl0_ns(2,1),0.U)},~mitctl0_0_b) + + // ---------------------------------------------------------------------- + // MITCTL1 (RW) Internal Timer Ctl 1 + // [31:4] : Reserved, reads 0x0 + // [3] : Cascade + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + val MITCTL1 =0x7d7.U(12.W) + val wr_mitctl1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITCTL1) + val mitctl1_ns = Mux(wr_mitctl1_r.asBool,io.dec_csr_wrdata_r(3,0), mitctl1(3,0)) + val mitctl1_0_b_ns= ~mitctl1_ns(0) + val mitctl1_0_b=withClock(io.free_clk){RegNext(mitctl1_0_b_ns,0.U)} + mitctl1:=Cat(withClock(io.free_clk){RegNext(mitctl1_ns(3,1),0.U)},~mitctl1_0_b) + + io.dec_timer_read_d := io.csr_mitcnt1 | io.csr_mitcnt0 | io.csr_mitb1 | io.csr_mitb0 | io.csr_mitctl0 | io.csr_mitctl1 + io.dec_timer_rddata_d :=Mux1H(Seq( + io.csr_mitcnt0.asBool -> mitcnt0(31,0), + io.csr_mitcnt1.asBool -> mitcnt1, + io.csr_mitb0.asBool -> mitb0, + io.csr_mitb1.asBool -> mitb1, + io.csr_mitctl0.asBool -> Cat(Fill(29,0.U(1.W)),mitctl0), + io.csr_mitctl1.asBool -> Cat(Fill(28,0.U(1.W)),mitctl1) + )) +} + + +class el2_dec_timer_ctl_IO extends Bundle{ + val free_clk =Input(Clock()) + val scan_mode =Input(Bool()) + val dec_csr_wen_r_mod =Input(UInt(1.W)) // csr write enable at wb + val dec_csr_rdaddr_d =Input(UInt(12.W)) // read address for csr + val dec_csr_wraddr_r =Input(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r =Input(UInt(32.W)) // csr write data at wb + + val csr_mitctl0 =Input(UInt(1.W)) + val csr_mitctl1 =Input(UInt(1.W)) + val csr_mitb0 =Input(UInt(1.W)) + val csr_mitb1 =Input(UInt(1.W)) + val csr_mitcnt0 =Input(UInt(1.W)) + val csr_mitcnt1 =Input(UInt(1.W)) + + + val dec_pause_state =Input(UInt(1.W)) // Paused + val dec_tlu_pmu_fw_halted =Input(UInt(1.W)) // pmu/fw halted + val internal_dbg_halt_timers=Input(UInt(1.W)) // debug halted + + val dec_timer_rddata_d =Output(UInt(32.W)) // timer CSR read data + val dec_timer_read_d =Output(UInt(1.W)) // timer CSR address match + val dec_timer_t0_pulse =Output(UInt(1.W)) // timer0 int + val dec_timer_t1_pulse =Output(UInt(1.W)) // timer1 int +} + +object tlu_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_tlu_ctl()))) +} diff --git a/src/main/scala/dec/el2_dec_trigger.scala b/src/main/scala/dec/el2_dec_trigger.scala new file mode 100644 index 00000000..171579e8 --- /dev/null +++ b/src/main/scala/dec/el2_dec_trigger.scala @@ -0,0 +1,20 @@ +package dec + +import chisel3.util._ +import chisel3._ +import include.el2_trigger_pkt_t +import lib._ + +class el2_dec_trigger extends Module with el2_lib { + val io = IO(new Bundle { + val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t)) + val dec_i0_pc_d = Input(UInt(31.W)) + val dec_i0_trigger_match_d = Output(UInt(4.W)) + }) + val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0))) + io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_)) + +} +object dec_trig extends App { + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger()))) +} diff --git a/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module b/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module deleted file mode 100644 index a49347afef10a9b5f95305e1058ba36adec7d6dd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16 RcmZQzU|?ooU|@t|0RRA102TlM diff --git a/target/scala-2.12/classes/dec/CSR_VAL.class b/target/scala-2.12/classes/dec/CSR_VAL.class new file mode 100644 index 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