Predictor hash check

This commit is contained in:
waleed-lm 2020-10-06 09:37:22 +05:00
parent 1abfa096d5
commit 2448a3ce5c
7 changed files with 24262 additions and 24254 deletions

View File

@ -1,4 +1,19 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test1",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_btb_target_f", "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_btb_target_f",
@ -115,13 +130,6 @@
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r" "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test1",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test2", "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test2",

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -183,7 +183,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val mp_wrindex_dec = 1.U << exu_mp_addr val mp_wrindex_dec = 1.U << exu_mp_addr
val fetch_wrindex_dec = 1.U << btb_rd_addr_f val fetch_wrindex_dec = 1.U << btb_rd_addr_f
io.test1 := fetch_wrindex_dec //io.test1 := fetch_wrindex_dec
val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f
io.test2 := fetch_wrindex_p1_dec io.test2 := fetch_wrindex_p1_dec
val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid) val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
@ -192,10 +192,11 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f
val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f) val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(LRU_SIZE, lru_update_valid_f)
val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f) val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(LRU_SIZE, lru_update_valid_f)
val btb_lru_b0_hold = !mp_wrlru_b0 & !fetch_wrlru_b0 val btb_lru_b0_hold = ~mp_wrlru_b0 & ~fetch_wrlru_b0
io.test1 := btb_lru_b0_hold
val use_mp_way = fetch_mp_collision_f val use_mp_way = fetch_mp_collision_f
val use_mp_way_p1 = fetch_mp_collision_p1_f val use_mp_way_p1 = fetch_mp_collision_p1_f