Predictor hash check
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1abfa096d5
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2448a3ce5c
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@ -1,4 +1,19 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test1",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_btb_target_f",
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@ -115,13 +130,6 @@
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test1",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test2",
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41236
el2_ifu_bp_ctl.fir
41236
el2_ifu_bp_ctl.fir
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Load Diff
7249
el2_ifu_bp_ctl.v
7249
el2_ifu_bp_ctl.v
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Load Diff
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@ -183,7 +183,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
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val mp_wrindex_dec = 1.U << exu_mp_addr
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val fetch_wrindex_dec = 1.U << btb_rd_addr_f
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io.test1 := fetch_wrindex_dec
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//io.test1 := fetch_wrindex_dec
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val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f
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io.test2 := fetch_wrindex_p1_dec
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val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
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@ -192,10 +192,11 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
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val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f
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val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f)
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val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f)
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val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(LRU_SIZE, lru_update_valid_f)
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val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(LRU_SIZE, lru_update_valid_f)
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val btb_lru_b0_hold = !mp_wrlru_b0 & !fetch_wrlru_b0
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val btb_lru_b0_hold = ~mp_wrlru_b0 & ~fetch_wrlru_b0
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io.test1 := btb_lru_b0_hold
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val use_mp_way = fetch_mp_collision_f
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val use_mp_way_p1 = fetch_mp_collision_p1_f
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