From 25951d8fd8f08a274de4660981c06b38af29ab20 Mon Sep 17 00:00:00 2001 From: Laraib Khan <73219142+laraibkhan-lm@users.noreply.github.com> Date: Fri, 9 Apr 2021 09:58:01 +0500 Subject: [PATCH] Quasar 2.0 Final --- design/src/main/scala/lsu/lsu_lsc_ctl.scala | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/design/src/main/scala/lsu/lsu_lsc_ctl.scala b/design/src/main/scala/lsu/lsu_lsc_ctl.scala index 184dea39..dfdde499 100644 --- a/design/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/design/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -38,8 +38,6 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val picm_mask_data_m = Input(UInt(32.W)) val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface - - // val lsu_result_m = Output(UInt(32.W)) val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF // lsu address down the pipe @@ -117,7 +115,6 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val addrcheck = Module(new lsu_addrcheck()) addrcheck.io.lsu_c2_m_clk := io.lsu_c2_m_clk - //val rst_l = IO(Input(1.W)) //implicit addrcheck.io.start_addr_d := full_addr_d addrcheck.io.end_addr_d := full_end_addr_d addrcheck.io.lsu_pkt_d := io.lsu_pkt_d @@ -280,4 +277,4 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib } object lsc_ctl extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_lsc_ctl())) -} \ No newline at end of file +}