IMC DONE

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -338,14 +338,14 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
   val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
   val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
-  val ic_wr_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ifu_bus_rdata_ff)
-  val m1 = Module(new rvecc_encode_64())
-  val m2 = Module(new rvecc_encode_64())
-  m1.io.din := ifu_bus_rdata_ff
-  ic_wr_ecc := m1.io.ecc_out
-  val ic_miss_buff_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ic_miss_buff_half)
-  m2.io.din := ic_miss_buff_half
-  ic_miss_buff_ecc := m2.io.ecc_out
+  val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
+//  val m1 = Module(new rvecc_encode_64())
+//  val m2 = Module(new rvecc_encode_64())
+//  m1.io.din := ifu_bus_rdata_ff
+//  ic_wr_ecc := m1.io.ecc_out
+  val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
+//  m2.io.din := ic_miss_buff_half
+//  ic_miss_buff_ecc := m2.io.ecc_out
   val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
   io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
   io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata

src/main/scala/lib/el2_lib.scala

@@ -381,8 +381,7 @@ trait el2_lib extends param{
       if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
       if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
     }
-    val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
-    ecc_out
+    Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
   }
 
   def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = {