From 264b94b397da4334afe6ec89c4ea93022b5987c9 Mon Sep 17 00:00:00 2001 From: Jahanzaib-Rasheed Date: Wed, 23 Sep 2020 10:28:05 +0500 Subject: [PATCH] Clk domain ready for verification. --- src/main/scala/lsu/el2_lsu_clkdomain.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/lsu/el2_lsu_clkdomain.scala b/src/main/scala/lsu/el2_lsu_clkdomain.scala index 81ceb57a..3cc8ec75 100644 --- a/src/main/scala/lsu/el2_lsu_clkdomain.scala +++ b/src/main/scala/lsu/el2_lsu_clkdomain.scala @@ -77,7 +77,7 @@ class el2_lsu_clkdomain extends Module { val lsu_free_c1_clken_q = withClock(free_clk)RegNext(lsu_free_c1_clken,0.U) - val tuple3( lsu_c1_d_clken_q, lsu_c1_m_clken_q, lsu_c1_r_clken_q) = withClock(lsu_free_c2_clk) { + val ( lsu_c1_d_clken_q, lsu_c1_m_clken_q, lsu_c1_r_clken_q) = withClock(lsu_free_c2_clk) { RegNext(lsu_c1_d_clken, 0.U); RegNext(lsu_c1_m_clken, 0.U); RegNext(lsu_c1_r_clken, 0.U) }