From 26ff2b40092bcec29bd1216653dfc85c85ec47f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Wed, 23 Dec 2020 15:36:45 +0500 Subject: [PATCH] lsc_ctl added --- lsu_lsc_ctl.fir | 724 +++++++++--------- lsu_lsc_ctl.v | 387 +++++----- src/main/scala/lsu/lsu_lsc_ctl.scala | 3 + target/scala-2.12/classes/lsu/lsc_ctl$.class | Bin 0 -> 3864 bytes .../lsu/lsc_ctl$delayedInit$body.class | Bin 0 -> 732 bytes target/scala-2.12/classes/lsu/lsc_ctl.class | Bin 0 -> 776 bytes 6 files changed, 552 insertions(+), 562 deletions(-) create mode 100644 target/scala-2.12/classes/lsu/lsc_ctl$.class create mode 100644 target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/lsc_ctl.class diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir index 46ecf3e2..c087b0d2 100644 --- a/lsu_lsc_ctl.fir +++ b/lsu_lsc_ctl.fir @@ -5,37 +5,37 @@ circuit lsu_lsc_ctl : input reset : AsyncReset output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} - node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27] - node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49] - wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] - node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24] - node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39] - start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16] - node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27] - node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49] - wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] - node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24] - node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39] - end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16] + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16] wire addr_in_iccm : UInt<1> addr_in_iccm <= UInt<1>("h00") node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] - node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27] - node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49] - wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26] - node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24] - node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39] - start_addr_in_pic_d <= _T_11 @[lib.scala 361:16] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 370:16] node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] - node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27] - node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49] - wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26] - node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24] - node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39] - end_addr_in_pic_d <= _T_15 @[lib.scala 361:16] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 370:16] node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49] node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55] @@ -537,26 +537,26 @@ circuit lsu_lsc_ctl : node _T_105 = or(_T_104, io.clk_override) @[lsu_lsc_ctl.scala 185:113] node _T_106 = bits(_T_105, 0, 0) @[lib.scala 8:44] node _T_107 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr of rvclkhdr @[lib.scala 378:23] + inst rvclkhdr of rvclkhdr @[lib.scala 387:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 380:18] - rvclkhdr.io.en <= _T_106 @[lib.scala 381:17] - rvclkhdr.io.scan_mode <= _T_107 @[lib.scala 382:24] - wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 384:33] - _T_108.bits.addr <= UInt<32>("h00") @[lib.scala 384:33] - _T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 384:33] - _T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 384:33] - _T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 384:33] - _T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 384:33] - _T_108.valid <= UInt<1>("h00") @[lib.scala 384:33] - reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 384:16] - _T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 384:16] - _T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 384:16] - _T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 384:16] - _T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 384:16] - _T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 384:16] - _T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 384:16] + rvclkhdr.io.clk <= clock @[lib.scala 389:18] + rvclkhdr.io.en <= _T_106 @[lib.scala 390:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 391:24] + wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 393:33] + _T_108.bits.addr <= UInt<32>("h00") @[lib.scala 393:33] + _T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 393:33] + _T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 393:33] + _T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 393:33] + _T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 393:33] + _T_108.valid <= UInt<1>("h00") @[lib.scala 393:33] + reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 393:16] + _T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 393:16] + _T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 393:16] + _T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 393:16] + _T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 393:16] + _T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 393:16] + _T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 393:16] io.lsu_error_pkt_r.bits.addr <= _T_109.bits.addr @[lsu_lsc_ctl.scala 185:24] io.lsu_error_pkt_r.bits.mscause <= _T_109.bits.mscause @[lsu_lsc_ctl.scala 185:24] io.lsu_error_pkt_r.bits.exc_type <= _T_109.bits.exc_type @[lsu_lsc_ctl.scala 185:24] @@ -569,385 +569,385 @@ circuit lsu_lsc_ctl : reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67] _T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67] io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30] - reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 193:48] - _T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 193:48] - io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 193:38] - dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 195:27] - dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 196:27] - dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 197:22] - dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 198:27] - dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 199:27] - node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 200:30] - dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 200:27] - node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 201:56] - node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 201:62] - dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 201:27] - node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 202:56] - node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 202:62] - dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 202:27] - node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 203:56] - node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 203:62] - dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 203:27] - node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 204:56] - node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 204:62] - dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 204:27] - dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 205:39] - dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 206:39] - dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 207:39] + reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:48] + _T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:48] + io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 188:38] + dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27] + dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27] + dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22] + dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27] + dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27] + node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30] + dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 195:27] + node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56] + node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62] + dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 196:27] + node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56] + node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62] + dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 197:27] + node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56] + node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62] + dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 198:27] + node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56] + node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62] + dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 199:27] + dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39] + dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39] + dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39] wire lsu_ld_datafn_r : UInt<32> lsu_ld_datafn_r <= UInt<32>("h00") wire lsu_ld_datafn_corr_r : UInt<32> lsu_ld_datafn_corr_r <= UInt<32>("h00") wire lsu_ld_datafn_m : UInt<32> lsu_ld_datafn_m <= UInt<32>("h00") - node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 213:50] - node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 213:26] - io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 213:20] - io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 213:20] - lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 214:20] - lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 215:20] - lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 215:20] - node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:64] - node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 217:61] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 217:45] - node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 217:43] - node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 217:90] - io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 217:24] - node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:68] - node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 218:65] - node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 218:49] - node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 218:47] - lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 218:24] - node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:68] - node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 219:65] - node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 219:49] - node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 219:47] - lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 219:24] - wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - _T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 221:91] - reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 221:65] - _T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 221:65] - _T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 221:65] - io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 221:28] - io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 221:28] - wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - _T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 222:91] - reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 222:65] - _T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 222:65] - _T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 222:65] - io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 222:28] - io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 222:28] - reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 223:65] - _T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 223:65] - io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 223:28] - reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 224:65] - _T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 224:65] - io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 224:28] - node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 226:59] - node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 226:100] + node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50] + node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26] + io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 208:20] + io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20] + node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64] + node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 212:61] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45] + node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 212:43] + node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90] + io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 212:24] + node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68] + node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 213:65] + node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49] + node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 213:47] + lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 213:24] + node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68] + node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 214:65] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49] + node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 214:47] + lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 214:24] + wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + _T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91] + reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65] + _T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65] + _T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 216:28] + wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + _T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91] + reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65] + _T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65] + _T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 217:28] + io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 217:28] + reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65] + _T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 218:28] + reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65] + _T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65] + io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 219:28] + node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59] + node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100] node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58] - node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 226:66] - node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 227:63] - node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 227:91] - node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 227:122] - node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 227:34] - node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 228:73] - node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 228:95] - node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 228:114] - node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 228:34] - reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:72] - store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 230:72] - reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 231:62] - _T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 231:62] - io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 231:24] - reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62] - _T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 232:62] - io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 232:24] + node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 221:66] + node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63] + node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91] + node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122] + node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 222:34] + node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73] + node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:95] + node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:114] + node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 223:34] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72] + store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72] + reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62] + _T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62] + io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 226:24] + reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62] + _T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62] + io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24] node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44] - node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 234:71] - node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 234:27] - node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 234:128] - reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:114] - _T_158 <= _T_157 @[lsu_lsc_ctl.scala 234:114] + node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71] + node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27] + node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128] + reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114] + _T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114] node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58] - io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 234:17] + io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17] node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44] - node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 235:71] - node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 235:27] - node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 235:128] - reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:114] - _T_164 <= _T_163 @[lsu_lsc_ctl.scala 235:114] + node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71] + node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27] + node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128] + reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114] + _T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114] node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58] - io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 235:17] - node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 237:41] - node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 237:69] - node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 237:87] + io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17] + node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 232:41] + node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 232:69] + node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 232:87] node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44] node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_1.io.en <= _T_169 @[lib.scala 371:17] - rvclkhdr_1.io.scan_mode <= _T_170 @[lib.scala 372:24] - reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_171 <= _T_166 @[lib.scala 374:16] - end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 237:18] - node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 238:41] - node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 238:69] - node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 238:87] + rvclkhdr_1.io.clk <= clock @[lib.scala 379:18] + rvclkhdr_1.io.en <= _T_169 @[lib.scala 380:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] + reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] + _T_171 <= _T_166 @[lib.scala 383:16] + end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 232:18] + node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 233:41] + node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 233:69] + node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 233:87] node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44] node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_2.io.en <= _T_175 @[lib.scala 371:17] - rvclkhdr_2.io.scan_mode <= _T_176 @[lib.scala 372:24] - reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_177 <= _T_172 @[lib.scala 374:16] - end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 238:18] - reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62] - _T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 241:62] - io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 241:24] - reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62] - _T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 242:62] - io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 242:24] - reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:62] - _T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 243:62] - io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 243:24] - reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 244:62] - _T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 244:62] - io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 244:24] - reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 245:62] - _T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 245:62] - io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 245:24] - reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 246:62] - _T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 246:62] - io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 246:24] - reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 247:62] - _T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 247:62] - io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 247:24] - reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 248:66] - addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 248:66] - node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 249:77] + rvclkhdr_2.io.clk <= clock @[lib.scala 379:18] + rvclkhdr_2.io.en <= _T_175 @[lib.scala 380:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] + reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] + _T_177 <= _T_172 @[lib.scala 383:16] + end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 233:18] + reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62] + _T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 236:62] + io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 236:24] + reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62] + _T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 237:62] + io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 237:24] + reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62] + _T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 238:62] + io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 238:24] + reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62] + _T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 239:62] + io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 239:24] + reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62] + _T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 240:62] + io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 240:24] + reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62] + _T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 241:62] + io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 241:24] + reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62] + _T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 242:62] + io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 242:24] + reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:66] + addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 243:66] + node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 244:77] node _T_186 = bits(_T_185, 0, 0) @[lib.scala 8:44] node _T_187 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_3.io.en <= _T_186 @[lib.scala 371:17] - rvclkhdr_3.io.scan_mode <= _T_187 @[lib.scala 372:24] - reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - bus_read_data_r <= io.bus_read_data_m @[lib.scala 374:16] - node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 252:52] - io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 252:28] - io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 254:28] - node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 256:68] - node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 256:41] - node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:96] - node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 256:94] - node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:110] - node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 256:108] - io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 256:19] - node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 257:52] - node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:69] + rvclkhdr_3.io.clk <= clock @[lib.scala 379:18] + rvclkhdr_3.io.en <= _T_186 @[lib.scala 380:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24] + reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16] + bus_read_data_r <= io.bus_read_data_m @[lib.scala 383:16] + node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 247:52] + io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 247:28] + io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 249:28] + node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 251:68] + node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 251:41] + node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:96] + node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 251:94] + node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:110] + node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 251:108] + io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 251:19] + node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 252:52] + node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 252:69] node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15] node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 257:59] - node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 257:133] - node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 257:94] - node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 257:89] - io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 257:29] - node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 278:53] - node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 278:33] - lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 278:27] - node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 279:49] - node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 279:33] - lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 279:27] - node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 280:66] + node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 252:59] + node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 252:133] + node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 252:94] + node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 252:89] + io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 252:29] + node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 273:53] + node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 273:33] + lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 273:27] + node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 274:49] + node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 274:33] + lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 274:27] + node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:66] node _T_208 = bits(_T_207, 0, 0) @[Bitwise.scala 72:15] node _T_209 = mux(_T_208, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 280:125] + node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125] node _T_211 = cat(UInt<24>("h00"), _T_210) @[Cat.scala 29:58] - node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 280:94] - node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 281:43] + node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 275:94] + node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43] node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15] node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 281:102] + node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:102] node _T_217 = cat(UInt<16>("h00"), _T_216) @[Cat.scala 29:58] - node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 281:71] - node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 280:133] - node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17] - node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 282:43] + node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 276:71] + node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 275:133] + node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17] + node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 277:43] node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15] node _T_223 = mux(_T_222, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 282:102] + node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 277:102] node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15] node _T_226 = mux(_T_225, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 282:125] + node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 277:125] node _T_228 = cat(_T_226, _T_227) @[Cat.scala 29:58] - node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 282:71] - node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 281:114] - node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17] - node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 283:43] + node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 277:71] + node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 276:114] + node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17] + node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 278:43] node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15] node _T_234 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 283:101] + node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 278:101] node _T_236 = bits(_T_235, 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 283:125] + node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 278:125] node _T_239 = cat(_T_237, _T_238) @[Cat.scala 29:58] - node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 283:71] - node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 282:134] + node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 278:71] + node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 277:134] node _T_242 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_243 = mux(_T_242, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 284:60] - node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 284:43] - node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 283:134] - io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 280:27] - node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 285:66] + node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 279:60] + node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 279:43] + node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 278:134] + io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 275:27] + node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:66] node _T_248 = bits(_T_247, 0, 0) @[Bitwise.scala 72:15] node _T_249 = mux(_T_248, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 285:130] + node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:130] node _T_251 = cat(UInt<24>("h00"), _T_250) @[Cat.scala 29:58] - node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 285:94] - node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 286:43] + node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 280:94] + node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43] node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15] node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 286:107] + node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:107] node _T_257 = cat(UInt<16>("h00"), _T_256) @[Cat.scala 29:58] - node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 286:71] - node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 285:138] - node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 287:17] - node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 287:43] + node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 281:71] + node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 280:138] + node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17] + node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 282:43] node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15] node _T_263 = mux(_T_262, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 287:107] + node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 282:107] node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15] node _T_266 = mux(_T_265, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 287:135] + node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 282:135] node _T_268 = cat(_T_266, _T_267) @[Cat.scala 29:58] - node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 287:71] - node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 286:119] - node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 288:17] - node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 288:43] + node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 282:71] + node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 281:119] + node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17] + node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 283:43] node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15] node _T_274 = mux(_T_273, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 288:106] + node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 283:106] node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] node _T_277 = mux(_T_276, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 288:135] + node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 283:135] node _T_279 = cat(_T_277, _T_278) @[Cat.scala 29:58] - node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 288:71] - node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 287:144] + node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 283:71] + node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 282:144] node _T_282 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_283 = mux(_T_282, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 289:65] - node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 289:43] - node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 288:144] - io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 285:27] + node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 284:65] + node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 284:43] + node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 283:144] + io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 280:27] diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v index 60e9652c..ef2debf0 100644 --- a/lsu_lsc_ctl.v +++ b/lsu_lsc_ctl.v @@ -26,13 +26,13 @@ module lsu_addrcheck( `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; `endif // RANDOMIZE_REG_INIT - wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] - wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] - wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] - wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 365:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 365:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39] wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] - wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] - wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39] wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55] wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91] @@ -186,8 +186,7 @@ endmodule module rvclkhdr( output io_l1clk, input io_clk, - input io_en, - input io_scan_mode + input io_en ); wire clkhdr_Q; // @[lib.scala 334:26] wire clkhdr_CK; // @[lib.scala 334:26] @@ -202,7 +201,7 @@ module rvclkhdr( assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] assign clkhdr_CK = io_clk; // @[lib.scala 336:18] assign clkhdr_EN = io_en; // @[lib.scala 337:18] - assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] endmodule module lsu_lsc_ctl( input clock, @@ -394,22 +393,18 @@ module lsu_lsc_ctl( wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 118:25] wire addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25] wire addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25] - wire rvclkhdr_io_l1clk; // @[lib.scala 378:23] - wire rvclkhdr_io_clk; // @[lib.scala 378:23] - wire rvclkhdr_io_en; // @[lib.scala 378:23] - wire rvclkhdr_io_scan_mode; // @[lib.scala 378:23] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_1_io_en; // @[lib.scala 368:23] - wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_2_io_en; // @[lib.scala 368:23] - wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] - wire rvclkhdr_3_io_en; // @[lib.scala 368:23] - wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 387:23] + wire rvclkhdr_io_clk; // @[lib.scala 387:23] + wire rvclkhdr_io_en; // @[lib.scala 387:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 377:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 377:23] + wire rvclkhdr_1_io_en; // @[lib.scala 377:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 377:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 377:23] + wire rvclkhdr_2_io_en; // @[lib.scala 377:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 377:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 377:23] + wire rvclkhdr_3_io_en; // @[lib.scala 377:23] wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 100:28] wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[lsu_lsc_ctl.scala 101:51] @@ -473,128 +468,128 @@ module lsu_lsc_ctl( wire _T_92 = _T_90 & _T_91; // @[lsu_lsc_ctl.scala 182:100] wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 184:166] wire _T_104 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 185:73] - reg _T_109_bits_inst_type; // @[lib.scala 384:16] - reg _T_109_bits_exc_type; // @[lib.scala 384:16] - reg [3:0] _T_109_bits_mscause; // @[lib.scala 384:16] - reg [31:0] _T_109_bits_addr; // @[lib.scala 384:16] + reg _T_109_bits_inst_type; // @[lib.scala 393:16] + reg _T_109_bits_exc_type; // @[lib.scala 393:16] + reg [3:0] _T_109_bits_mscause; // @[lib.scala 393:16] + reg [31:0] _T_109_bits_addr; // @[lib.scala 393:16] reg _T_110; // @[lsu_lsc_ctl.scala 186:83] reg _T_111; // @[lsu_lsc_ctl.scala 187:67] - reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 193:48] - wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 200:30] - wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 201:62] - wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 202:62] - wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 203:62] - wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 204:62] - wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 217:64] - wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 217:61] - wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 217:45] - wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 217:43] - wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 218:68] - wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 218:65] - wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 218:49] - wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 219:65] - wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 219:49] - reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 221:65] - reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 221:65] - reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 222:65] - reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 222:65] - reg _T_141; // @[lsu_lsc_ctl.scala 223:65] - reg _T_142; // @[lsu_lsc_ctl.scala 224:65] + reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:48] + wire dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30] + wire dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62] + wire dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62] + wire dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62] + wire dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62] + wire _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64] + wire _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 212:61] + wire _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 212:45] + wire _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 212:43] + wire _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68] + wire _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 213:65] + wire _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 213:49] + wire _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 214:65] + wire _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 214:49] + reg _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:65] + reg _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65] + reg _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65] + reg _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65] + reg _T_141; // @[lsu_lsc_ctl.scala 218:65] + reg _T_142; // @[lsu_lsc_ctl.scala 219:65] wire [5:0] _T_145 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] - wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 226:66] - reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 230:72] - reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 231:62] - reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 232:62] - wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 237:69] - wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 238:69] - reg [31:0] _T_178; // @[lsu_lsc_ctl.scala 241:62] - reg [31:0] _T_179; // @[lsu_lsc_ctl.scala 242:62] - reg _T_180; // @[lsu_lsc_ctl.scala 243:62] - reg _T_181; // @[lsu_lsc_ctl.scala 244:62] - reg _T_182; // @[lsu_lsc_ctl.scala 245:62] - reg _T_183; // @[lsu_lsc_ctl.scala 246:62] - reg _T_184; // @[lsu_lsc_ctl.scala 247:62] - reg addr_external_r; // @[lsu_lsc_ctl.scala 248:66] - reg [31:0] bus_read_data_r; // @[lib.scala 374:16] - wire _T_189 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 256:68] - wire _T_190 = io_lsu_pkt_r_valid & _T_189; // @[lsu_lsc_ctl.scala 256:41] - wire _T_191 = ~io_flush_r; // @[lsu_lsc_ctl.scala 256:96] - wire _T_192 = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 256:94] - wire _T_193 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 256:110] - wire _T_196 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 257:69] + wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 221:66] + reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72] + reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62] + reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62] + wire _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 232:69] + wire _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 233:69] + reg [31:0] _T_178; // @[lsu_lsc_ctl.scala 236:62] + reg [31:0] _T_179; // @[lsu_lsc_ctl.scala 237:62] + reg _T_180; // @[lsu_lsc_ctl.scala 238:62] + reg _T_181; // @[lsu_lsc_ctl.scala 239:62] + reg _T_182; // @[lsu_lsc_ctl.scala 240:62] + reg _T_183; // @[lsu_lsc_ctl.scala 241:62] + reg _T_184; // @[lsu_lsc_ctl.scala 242:62] + reg addr_external_r; // @[lsu_lsc_ctl.scala 243:66] + reg [31:0] bus_read_data_r; // @[lib.scala 383:16] + wire _T_189 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 251:68] + wire _T_190 = io_lsu_pkt_r_valid & _T_189; // @[lsu_lsc_ctl.scala 251:41] + wire _T_191 = ~io_flush_r; // @[lsu_lsc_ctl.scala 251:96] + wire _T_192 = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 251:94] + wire _T_193 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 251:110] + wire _T_196 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 252:69] wire [31:0] _T_198 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_199 = io_picm_mask_data_m | _T_198; // @[lsu_lsc_ctl.scala 257:59] - wire [31:0] _T_201 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 257:94] - wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 278:33] - wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 279:33] - wire _T_207 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 280:66] + wire [31:0] _T_199 = io_picm_mask_data_m | _T_198; // @[lsu_lsc_ctl.scala 252:59] + wire [31:0] _T_201 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 252:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 273:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 274:33] + wire _T_207 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:66] wire [31:0] _T_209 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_211 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_212 = _T_209 & _T_211; // @[lsu_lsc_ctl.scala 280:94] - wire _T_213 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 281:43] + wire [31:0] _T_212 = _T_209 & _T_211; // @[lsu_lsc_ctl.scala 275:94] + wire _T_213 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43] wire [31:0] _T_215 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_217 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_218 = _T_215 & _T_217; // @[lsu_lsc_ctl.scala 281:71] - wire [31:0] _T_219 = _T_212 | _T_218; // @[lsu_lsc_ctl.scala 280:133] - wire _T_220 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 282:17] - wire _T_221 = _T_220 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 282:43] + wire [31:0] _T_218 = _T_215 & _T_217; // @[lsu_lsc_ctl.scala 276:71] + wire [31:0] _T_219 = _T_212 | _T_218; // @[lsu_lsc_ctl.scala 275:133] + wire _T_220 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 277:17] + wire _T_221 = _T_220 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 277:43] wire [31:0] _T_223 = _T_221 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_226 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_228 = {_T_226,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_229 = _T_223 & _T_228; // @[lsu_lsc_ctl.scala 282:71] - wire [31:0] _T_230 = _T_219 | _T_229; // @[lsu_lsc_ctl.scala 281:114] - wire _T_232 = _T_220 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 283:43] + wire [31:0] _T_229 = _T_223 & _T_228; // @[lsu_lsc_ctl.scala 277:71] + wire [31:0] _T_230 = _T_219 | _T_229; // @[lsu_lsc_ctl.scala 276:114] + wire _T_232 = _T_220 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 278:43] wire [31:0] _T_234 = _T_232 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_237 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_239 = {_T_237,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_240 = _T_234 & _T_239; // @[lsu_lsc_ctl.scala 283:71] - wire [31:0] _T_241 = _T_230 | _T_240; // @[lsu_lsc_ctl.scala 282:134] + wire [31:0] _T_240 = _T_234 & _T_239; // @[lsu_lsc_ctl.scala 278:71] + wire [31:0] _T_241 = _T_230 | _T_240; // @[lsu_lsc_ctl.scala 277:134] wire [31:0] _T_243 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_245 = _T_243 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 284:43] - wire _T_247 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 285:66] + wire [31:0] _T_245 = _T_243 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 279:43] + wire _T_247 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:66] wire [31:0] _T_249 = _T_247 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_251 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_252 = _T_249 & _T_251; // @[lsu_lsc_ctl.scala 285:94] - wire _T_253 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 286:43] + wire [31:0] _T_252 = _T_249 & _T_251; // @[lsu_lsc_ctl.scala 280:94] + wire _T_253 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43] wire [31:0] _T_255 = _T_253 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_257 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_258 = _T_255 & _T_257; // @[lsu_lsc_ctl.scala 286:71] - wire [31:0] _T_259 = _T_252 | _T_258; // @[lsu_lsc_ctl.scala 285:138] - wire _T_260 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 287:17] - wire _T_261 = _T_260 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 287:43] + wire [31:0] _T_258 = _T_255 & _T_257; // @[lsu_lsc_ctl.scala 281:71] + wire [31:0] _T_259 = _T_252 | _T_258; // @[lsu_lsc_ctl.scala 280:138] + wire _T_260 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 282:17] + wire _T_261 = _T_260 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 282:43] wire [31:0] _T_263 = _T_261 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [23:0] _T_266 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_268 = {_T_266,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_269 = _T_263 & _T_268; // @[lsu_lsc_ctl.scala 287:71] - wire [31:0] _T_270 = _T_259 | _T_269; // @[lsu_lsc_ctl.scala 286:119] - wire _T_272 = _T_260 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 288:43] + wire [31:0] _T_269 = _T_263 & _T_268; // @[lsu_lsc_ctl.scala 282:71] + wire [31:0] _T_270 = _T_259 | _T_269; // @[lsu_lsc_ctl.scala 281:119] + wire _T_272 = _T_260 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 283:43] wire [31:0] _T_274 = _T_272 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [15:0] _T_277 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_279 = {_T_277,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_280 = _T_274 & _T_279; // @[lsu_lsc_ctl.scala 288:71] - wire [31:0] _T_281 = _T_270 | _T_280; // @[lsu_lsc_ctl.scala 287:144] + wire [31:0] _T_280 = _T_274 & _T_279; // @[lsu_lsc_ctl.scala 283:71] + wire [31:0] _T_281 = _T_270 | _T_280; // @[lsu_lsc_ctl.scala 282:144] wire [31:0] _T_283 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_285 = _T_283 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 289:43] + wire [31:0] _T_285 = _T_283 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 284:43] lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25] .reset(addrcheck_reset), .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), @@ -620,42 +615,38 @@ module lsu_lsc_ctl( .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) ); - rvclkhdr rvclkhdr ( // @[lib.scala 378:23] + rvclkhdr rvclkhdr ( // @[lib.scala 387:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) + .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 377:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), - .io_en(rvclkhdr_1_io_en), - .io_scan_mode(rvclkhdr_1_io_scan_mode) + .io_en(rvclkhdr_1_io_en) ); - rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 377:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), - .io_en(rvclkhdr_2_io_en), - .io_scan_mode(rvclkhdr_2_io_scan_mode) + .io_en(rvclkhdr_2_io_en) ); - rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 377:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), - .io_en(rvclkhdr_3_io_en), - .io_scan_mode(rvclkhdr_3_io_scan_mode) + .io_en(rvclkhdr_3_io_en) ); - assign io_lsu_result_m = _T_241 | _T_245; // @[lsu_lsc_ctl.scala 280:27] - assign io_lsu_result_corr_r = _T_281 | _T_285; // @[lsu_lsc_ctl.scala 285:27] - assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 254:28] - assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 231:24] - assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 232:24] + assign io_lsu_result_m = _T_241 | _T_245; // @[lsu_lsc_ctl.scala 275:27] + assign io_lsu_result_corr_r = _T_281 | _T_285; // @[lsu_lsc_ctl.scala 280:27] + assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 249:28] + assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24] + assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24] assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24] - assign io_end_addr_m = _T_178; // @[lsu_lsc_ctl.scala 234:17 lsu_lsc_ctl.scala 241:24] - assign io_end_addr_r = _T_179; // @[lsu_lsc_ctl.scala 235:17 lsu_lsc_ctl.scala 242:24] - assign io_store_data_m = _T_199 & _T_201; // @[lsu_lsc_ctl.scala 257:29] + assign io_end_addr_m = _T_178; // @[lsu_lsc_ctl.scala 229:17 lsu_lsc_ctl.scala 236:24] + assign io_end_addr_r = _T_179; // @[lsu_lsc_ctl.scala 230:17 lsu_lsc_ctl.scala 237:24] + assign io_store_data_m = _T_199 & _T_201; // @[lsu_lsc_ctl.scala 252:29] assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16] assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42] - assign io_lsu_commit_r = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 256:19] + assign io_lsu_commit_r = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 251:19] assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32] assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30] assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46] @@ -663,54 +654,54 @@ module lsu_lsc_ctl( assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24] assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24] assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24] - assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 252:28] - assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 193:38] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 247:28] + assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38] assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42] - assign io_addr_in_dccm_m = _T_180; // @[lsu_lsc_ctl.scala 243:24] - assign io_addr_in_dccm_r = _T_181; // @[lsu_lsc_ctl.scala 244:24] + assign io_addr_in_dccm_m = _T_180; // @[lsu_lsc_ctl.scala 238:24] + assign io_addr_in_dccm_r = _T_181; // @[lsu_lsc_ctl.scala 239:24] assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42] - assign io_addr_in_pic_m = _T_182; // @[lsu_lsc_ctl.scala 245:24] - assign io_addr_in_pic_r = _T_183; // @[lsu_lsc_ctl.scala 246:24] - assign io_addr_external_m = _T_184; // @[lsu_lsc_ctl.scala 247:24] - assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 213:20 lsu_lsc_ctl.scala 217:24] - assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 213:20] - assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 221:28 lsu_lsc_ctl.scala 223:28] - assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 221:28] - assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 222:28 lsu_lsc_ctl.scala 224:28] - assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 222:28] - assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 222:28] + assign io_addr_in_pic_m = _T_182; // @[lsu_lsc_ctl.scala 240:24] + assign io_addr_in_pic_r = _T_183; // @[lsu_lsc_ctl.scala 241:24] + assign io_addr_external_m = _T_184; // @[lsu_lsc_ctl.scala 242:24] + assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24] + assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20] + assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28] + assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_138_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_138_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28] + assign io_lsu_pkt_r_bits_fast_int = _T_140_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_140_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_140_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_140_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28] assign addrcheck_reset = reset; assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 120:42] assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 122:42] @@ -725,18 +716,14 @@ module lsu_lsc_ctl( assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 124:42] assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 125:42] assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 126:42] - assign rvclkhdr_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_io_en = _T_104 | io_clk_override; // @[lib.scala 381:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_1_io_en = _T_167 | io_clk_override; // @[lib.scala 371:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_173 | io_clk_override; // @[lib.scala 371:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] - assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 371:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 389:18] + assign rvclkhdr_io_en = _T_104 | io_clk_override; // @[lib.scala 390:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 379:18] + assign rvclkhdr_1_io_en = _T_167 | io_clk_override; // @[lib.scala 380:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 379:18] + assign rvclkhdr_2_io_en = _T_173 | io_clk_override; // @[lib.scala 380:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 379:18] + assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 380:17] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala index 3a6900e9..a1780f17 100644 --- a/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -284,3 +284,6 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib ((Fill(32,io.lsu_pkt_r.bits.word)) & lsu_ld_datafn_corr_r(31,0)) } } +object lsc_ctl extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_lsc_ctl())) +} \ No newline at end of file diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$.class b/target/scala-2.12/classes/lsu/lsc_ctl$.class new file mode 100644 index 0000000000000000000000000000000000000000..190a28330274df35917aa8ba42a07991a7d2630e GIT binary patch literal 3864 zcmbtX30D(W7`+cdA~DJ)D2jp_YY1vov|3}W0$Q;_Z6mbSwsc5daCDf7lZjhfYd7t_ z*?sv5J*SJ?k#qV3`lEV!-^_#zkkXt}ax#;7^R4%N-~Aqc{r%`q0DJJWK+GtWQ${H_ znRASI1VW(of_7O;8JanrIyH4c=9~x`1)57a&CpUuip2<;1lp)J>8tH!M7JN$0$kKdza1Lzdzh%eq*m`Z9qHON&Mj6$pFs0+F#(BjcH)aeWf$5Y$cG8MgA0X=J=qbCzK+ zd)iLTlpSr#kg1Gba)!!Q;zwZF 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