Enable demo of jtag.
This commit is contained in:
colin
parent
400cf6450a
commit
2780c08c6a
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@ -0,0 +1,3 @@
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build/
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obj_dir/
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gen/
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@ -1,13 +1,14 @@
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export RV_ROOT = ${PWD}/../..
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export RV_ROOT = ${PWD}/..
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GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
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GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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ABI = -mabi=ilp32 -march=rv32imc
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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RV_SOC = ${RV_ROOT}/quasar
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DEFINE_DIR = ${DEMODIR}/../design/snapshots/default
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RV_SOC = ${RV_ROOT}/soc
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TEST = jtag
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@ -17,6 +18,7 @@ ifdef debug
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endif
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LINK = $(DEMODIR)/link.ld
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LINKPRO = $(DEMODIR)/link_pro.ld
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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@ -30,38 +32,45 @@ all: clean verilator
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clean:
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rm -rf build obj_dir
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swerv_define :
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BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
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##################### Verilog Builds #####################################
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verilator-build: swerv_define
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echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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verilator-build:
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echo '`undef RV_ASSERT_ON' >> ${DEFINE_DIR}/common_defines.vh
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verilator --cc -CFLAGS ${CFLAGS} \
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$(BUILD_DIR)/common_defines.vh \
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-I${BUILD_DIR} \
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-Wno-UNOPTFLAT \
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$(DEFINE_DIR)/common_defines.vh \
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-I${DEFINE_DIR} \
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-Wno-WIDTH \
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-Wno-UNOPTFLAT \
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-Wno-LATCH \
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-Wno-IMPLICIT \
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-F ${RV_SOC}/soc_top.mk \
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-F ${RV_SOC}/soc_sim.mk \
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$(RV_SOC)/soc_sim.sv \
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--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_sim.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
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$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
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##################### Simulation Runs #####################################
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verilator: program verilator-build
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verilator: program.hex verilator-build
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cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
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sim:
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cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
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##################### Test hex Build #####################################
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program:
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@mkdir build
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@cp program.hex build/program.hex
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@cp jtag.bin build/jtag.bin
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program.hex: $(TEST).o $(LINK)
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@echo Building $(TEST)
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$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINKPRO) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
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$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
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$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
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$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
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@echo Completed building $(TEST)
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%.o : %.s
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@mkdir -p $(BUILD_DIR)
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$(GCC_PREFIX)-cpp -g -I${DEFINE_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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##################### openocd #####################################
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@ -1,3 +1,3 @@
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# set debug remote 1
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target remote :3333
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target extended-remote :3333
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set remotetimeout 2000
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BIN
demo/jtag.bin
BIN
demo/jtag.bin
Binary file not shown.
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@ -0,0 +1,84 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// Assembly code for Hello World
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// Not using only ALU ops for creating the string
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#include "defines.h"
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#define STDOUT 0xd0580000
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// Code to execute
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.section .text
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.global _start
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_start:
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// Clear minstret
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csrw minstret, zero
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csrw minstreth, zero
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// Set up MTVEC - not expecting to use it though
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li x1, RV_ICCM_SADR
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csrw mtvec, x1
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// Enable Caches in MRAC
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li x1, 0x5f555555
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csrw 0x7c0, x1
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// Load string from hw_data
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// and write to stdout address
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li x3, STDOUT
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la x4, hw_data
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loop:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop
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li x3, STDOUT
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la x4, hw_data
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loop2:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop2
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loop3:
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beq x0, x0, loop3
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// Write 0xff to STDOUT for TB to terminate test.
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_finish:
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li x3, STDOUT
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addi x5, x0, 0xff
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sb x5, 0(x3)
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beq x0, x0, _finish
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.rept 100
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nop
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.endr
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.global hw_data
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.data
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hw_data:
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.ascii "----------------------------------\n"
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.ascii "Hello World Colin.liang EL2@WDC !!\n"
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.ascii "----------------------------------\n"
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.byte 0
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@ -0,0 +1,16 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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SECTIONS
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{
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. = 0x80000000;
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.text_init : { *(.text_init*) }
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.text : { *(.text*) }
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_end = .;
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. = 0x80004000;
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
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.bss : { *(.bss) }
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. = 0xd0580000;
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.data.io : { *(.data.io) }
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}
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@ -0,0 +1,16 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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SECTIONS
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{
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. = 0x0000;
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.text_init : { *(.text_init*) }
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.text : { *(.text*) }
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_end = .;
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. = 0x4000;
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
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.bss : { *(.bss) }
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. = 0xd0580000;
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.data.io : { *(.data.io) }
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}
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@ -1,28 +0,0 @@
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@00000000
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73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
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B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
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17 42 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
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05 02 E3 9B 02 FE B7 01 58 D0 17 42 00 00 13 02
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62 FC 83 02 02 00 23 80 51 00 05 02 E3 9B 02 FE
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63 00 00 00 B7 01 58 D0 93 02 F0 0F 23 80 51 00
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E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00
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@00004000
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 43
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6F 6C 69 6E 2E 6C 69 61 6E 67 20 45 4C 32 40 57
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44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 0A 00
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@ -0,0 +1,32 @@
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LOCATE COMP "clk" SITE "P3";
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IOBUF PORT "clk" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "clk" 25 MHZ;
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LOCATE COMP "dbg_rst" SITE "N2";
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IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "dbg_rst" 25 MHZ;
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LOCATE COMP "rst" SITE "N3";
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IOBUF PORT "rst" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "rst" 25 MHZ;
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LOCATE COMP "jtag_tck" SITE "T2";
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IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "jtag_tck" 25 MHZ;
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LOCATE COMP "jtag_tms" SITE "T3";
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IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "jtag_tms" 25 MHZ;
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LOCATE COMP "jtag_tdi" SITE "N4";
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IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "jtag_tdi" 25 MHZ;
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LOCATE COMP "jtag_trst_n" SITE "M3";
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IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "jtag_trst_n" 25 MHZ;
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LOCATE COMP "jtag_tdo" SITE "M4";
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IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;
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@ -0,0 +1,83 @@
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#!/bin/bash
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# if [ $# -ne 1 -o ! -d "$1" ]; then
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# echo "Usage: $0 <design>" >&2
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# exit 1
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# fi
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set -ex
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PWD=$(pwd)
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SOC=$PWD/../../soc
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design=${1%/}
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YOSYS_COARSE=true
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YOSYS_GLOBRST=false
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YOSYS_SPLITNETS=false
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TOP="soc_top"
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RTL=$(cat ../../soc/soc_top.mk)
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rtl_files=""
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
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for src in $RTL; do
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rtl_files="$rtl_files $SOC/$src"
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done
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mkdir -p gen
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rm -rf gen/*
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mkdir gen/design
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filelist=""
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for file in $rtl_files; do
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filelist="$filelist $file"
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done
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# sv2v $filelist > gen/soc_top.v
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sv2v -Ibuild $filelist > gen/soc_top.v
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{
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# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
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# for file in $rtl_files; do
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# echo "read_verilog -sv -I../../design/include $file"
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# done
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echo "read_verilog gen/soc_top.v"
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if test -n "$TOP"; then
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echo "hierarchy -check -top $TOP"
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else
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echo "hierarchy -check"
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fi
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if $YOSYS_GLOBRST; then
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# insertation of global reset (e.g. for FPGA cores)
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echo "add -global_input globrst 1"
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echo "proc -global_arst globrst"
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fi
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echo "synth -run coarse; opt -fine"
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# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
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if ! $YOSYS_COARSE; then
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echo "memory_map; techmap; opt; abc -dff; clean"
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fi
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if $YOSYS_SPLITNETS; then
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# icarus verilog has a performance problems when there are
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# dependencies between the bits of a long vector
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echo "splitnets; clean"
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fi
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if $YOSYS_COARSE; then
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echo "write_verilog -noexpr -noattr gen/synth.v"
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else
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echo "select -assert-none t:\$[!_]"
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echo "write_verilog -noattr gen/synth.v"
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fi
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echo "synth_ecp5 -top $TOP -json gen/soc.json"
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# echo "synth_xilinx -top $TOP"
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} > gen/synth.ys
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|
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yosys -v2 -l gen/synth.log gen/synth.ys
|
||||
|
||||
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json
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@ -17,16 +17,22 @@ module jtagdpi #(
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output logic jtag_srst_n
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);
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||||
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import "DPI-C"
|
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function chandle jtagdpi_create(input string name, input int listen_port);
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import "DPI-C" function chandle jtagdpi_create(
|
||||
input string name,
|
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input int listen_port
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||||
);
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||||
|
||||
import "DPI-C"
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function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,
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output bit tdi, output bit trst_n,
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output bit srst_n, input bit tdo);
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import "DPI-C" function void jtagdpi_tick(
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input chandle ctx,
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output bit tck,
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output bit tms,
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output bit tdi,
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output bit trst_n,
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output bit srst_n,
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input bit tdo
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);
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||||
|
||||
import "DPI-C"
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||||
function void jtagdpi_close(input chandle ctx);
|
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import "DPI-C" function void jtagdpi_close(input chandle ctx);
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|
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chandle ctx;
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@ -39,7 +45,10 @@ module jtagdpi #(
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ctx = 0;
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end
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always_ff @(posedge clk_i, negedge rst_ni) begin
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reg [1:0] plit;
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always_ff @(posedge clk_i) plit <= plit + 1'b1;
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|
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always_ff @(posedge plit[1], negedge rst_ni) begin
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jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
|
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jtag_tdo);
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end
|
||||
|
|
|
|||
84981
soc/quasar_wrapper.sv
84981
soc/quasar_wrapper.sv
File diff suppressed because it is too large
Load Diff
|
|
@ -1,19 +1,3 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
|
||||
module soc_sim (
|
||||
input bit core_clk
|
||||
);
|
||||
|
|
@ -343,6 +327,9 @@ module soc_sim (
|
|||
abi_reg[30] = "t5";
|
||||
abi_reg[31] = "t6";
|
||||
|
||||
$readmemh("program.hex", rvsoc.lmem.mem);
|
||||
$readmemh("program.hex", rvsoc.imem.mem);
|
||||
|
||||
tp = $fopen("trace_port.csv", "w");
|
||||
el = $fopen("exec.log", "w");
|
||||
//////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
./quasar_wrapper.sv
|
||||
../generated_rtl/quasar_wrapper.sv
|
||||
|
||||
vsrc/mem.sv
|
||||
vsrc/ifu_ic_mem.sv
|
||||
vsrc/ifu_iccm_mem.sv
|
||||
vsrc/lsu_dccm_mem.sv
|
||||
vsrc/dmi_wrapper.sv
|
||||
vsrc/dmi_jtag_to_core_sync.sv
|
||||
vsrc/rvjtag_tap.sv
|
||||
vsrc/gated_latch.sv
|
||||
vsrc/beh_lib.sv
|
||||
vsrc/mem_lib.sv
|
||||
../design/src/main/resources/vsrc/mem.sv
|
||||
../design/src/main/resources/vsrc/ifu_ic_mem.sv
|
||||
../design/src/main/resources/vsrc/ifu_iccm_mem.sv
|
||||
../design/src/main/resources/vsrc/lsu_dccm_mem.sv
|
||||
../design/src/main/resources/vsrc/dmi_wrapper.sv
|
||||
../design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv
|
||||
../design/src/main/resources/vsrc/rvjtag_tap.sv
|
||||
../design/src/main/resources/vsrc/gated_latch.sv
|
||||
../design/src/main/resources/vsrc/beh_lib.sv
|
||||
../design/src/main/resources/vsrc/mem_lib.sv
|
||||
|
||||
./ahb_sif.sv
|
||||
./axi_lsu_dma_bridge.sv
|
||||
|
|
|
|||
|
|
@ -1,19 +1,3 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
|
||||
module soc_top (
|
||||
input clk,
|
||||
input dbg_rst,
|
||||
|
|
@ -24,6 +8,7 @@ module soc_top (
|
|||
input jtag_tdi,
|
||||
input jtag_trst_n
|
||||
);
|
||||
|
||||
logic nmi_int;
|
||||
|
||||
logic [ 31:0] reset_vector;
|
||||
|
|
@ -104,6 +89,7 @@ module soc_top (
|
|||
logic [ 4:0] wb_dest;
|
||||
logic [ 31:0] wb_data;
|
||||
|
||||
|
||||
//-------------------------- LSU AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
wire lsu_axi_awvalid;
|
||||
|
|
@ -310,15 +296,15 @@ module soc_top (
|
|||
jtag_id[31:28] = 4'b1;
|
||||
jtag_id[27:12] = '0;
|
||||
jtag_id[11:1] = 11'h45;
|
||||
reset_vector = 32'h0;
|
||||
reset_vector = `RV_RESET_VEC;
|
||||
nmi_vector = 32'hee000000;
|
||||
nmi_int = 0;
|
||||
|
||||
$readmemh("program.hex", lmem.mem);
|
||||
$readmemh("program.hex", imem.mem);
|
||||
|
||||
end
|
||||
|
||||
//=========================================================================-
|
||||
// RTL instance
|
||||
//=========================================================================-
|
||||
/* verilator lint_off PINMISSING */
|
||||
quasar_wrapper rvtop (
|
||||
.reset (rst),
|
||||
.io_dbg_rst_l(dbg_rst),
|
||||
|
|
@ -812,6 +798,7 @@ module soc_top (
|
|||
|
||||
.s0_wvalid(lmem_axi_wvalid),
|
||||
.s0_wready(lmem_axi_wready),
|
||||
|
||||
.s0_bresp(lmem_axi_bresp),
|
||||
.s0_bvalid(lmem_axi_bvalid),
|
||||
.s0_bid(lmem_axi_bid),
|
||||
|
|
@ -836,8 +823,6 @@ module soc_top (
|
|||
.s1_bresp (dma_axi_bresp),
|
||||
.s1_bvalid(dma_axi_bvalid),
|
||||
.s1_bready(dma_axi_bready)
|
||||
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
2057
soc/swerv.config
2057
soc/swerv.config
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue