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Bug introduced

This commit is contained in:
waleed-lm 2020-10-01 18:09:57 +05:00
parent 9f854c59ec
commit 27fff4e140
21 changed files with 2362 additions and 698 deletions
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42
EL2_IC_DATA.anno.json
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@ -1,8 +1,11 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_1_1", "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_data",
"sources":[ "sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_sel_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override", "~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
@ -16,23 +19,9 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_0_0", "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_data",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_0_1",
"sources":[ "sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override", "~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
@ -46,14 +35,31 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_1_0", "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_eccerr",
"sources":[ "sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override", "~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_parerr",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en" "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"

2000
EL2_IC_DATA.fir
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File diff suppressed because it is too large Load Diff

608
EL2_IC_DATA.v
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@ -20,13 +20,7 @@ module EL2_IC_DATA(
input [63:0] io_ic_premux_data, input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data, input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit, input [1:0] io_ic_rd_hit,
input io_scan_mode, input io_scan_mode
input [70:0] io_test_in,
output io_test,
output [70:0] io_test_port_0_0,
output [70:0] io_test_port_0_1,
output [70:0] io_test_port_1_0,
output [70:0] io_test_port_1_1
); );
`ifdef RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_MEM_INIT
reg [95:0] _RAND_0; reg [95:0] _RAND_0;
@ -34,175 +28,368 @@ module EL2_IC_DATA(
reg [95:0] _RAND_2; reg [95:0] _RAND_2;
reg [95:0] _RAND_3; reg [95:0] _RAND_3;
`endif // RANDOMIZE_MEM_INIT `endif // RANDOMIZE_MEM_INIT
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21] `ifdef RANDOMIZE_REG_INIT
wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 243:21] reg [31:0] _RAND_4;
wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [31:0] _RAND_5;
wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 243:21] reg [31:0] _RAND_6;
wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [31:0] _RAND_7;
wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 243:21] `endif // RANDOMIZE_REG_INIT
wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21] reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21] wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21] wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 243:21] wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 200:70] wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 201:68] wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21]
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21]
wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21]
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 192:70]
wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 192:68]
wire [1:0] _T_3 = _T_1 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 192:94]
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 193:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58] wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 201:94] wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 193:94]
wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 206:45] wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 198:45]
wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58] wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58]
wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 206:25] wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 198:25]
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 208:79] wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 200:79]
wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 210:113] wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 202:113]
wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 210:38] wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 202:38]
wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 210:17] wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 202:17]
wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 210:38] wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 202:38]
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 210:17] wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 202:17]
wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 214:16] wire [1:0] ic_debug_sel_sb = {io_ic_debug_addr[0],_T_14}; // @[Cat.scala 29:58]
wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 215:91] wire _T_28 = ic_debug_sel_sb[0] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 204:80]
wire _T_31 = ic_debug_sel_sb[1] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 204:80]
wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 206:16]
wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 207:91]
wire _T_54 = ic_rw_addr_q[2] & _T_40; // @[Mux.scala 27:72] wire _T_54 = ic_rw_addr_q[2] & _T_40; // @[Mux.scala 27:72]
wire _T_57 = _T_35 | _T_54; // @[Mux.scala 27:72] wire _T_57 = _T_35 | _T_54; // @[Mux.scala 27:72]
wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 222:74] wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 214:74]
wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 222:61] wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 214:61]
wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 222:58] wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 214:58]
wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 222:38] wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 214:38]
wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117] wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 209:117]
wire _T_85 = _T_35 & _T_40; // @[Mux.scala 27:72] wire _T_85 = _T_35 & _T_40; // @[Mux.scala 27:72]
wire _T_88 = ic_rw_addr_q[2] | _T_85; // @[Mux.scala 27:72] wire _T_88 = ic_rw_addr_q[2] | _T_85; // @[Mux.scala 27:72]
wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117] wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 209:117]
wire [1:0] ic_b_rden = {_T_90,_T_61}; // @[Cat.scala 29:58] wire [1:0] ic_b_rden = {_T_90,_T_61}; // @[Cat.scala 29:58]
wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25] wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 220:43] wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 212:43]
wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25] wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 220:43] wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 212:43]
wire [1:0] ic_bank_way_clken_0 = {_T_98,_T_102}; // @[Cat.scala 29:58] wire [1:0] ic_bank_way_clken_0 = {_T_98,_T_102}; // @[Cat.scala 29:58]
wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25] wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 220:43] wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 212:43]
wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25] wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 212:25]
wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 220:43] wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 212:43]
wire [1:0] ic_bank_way_clken_1 = {_T_106,_T_110}; // @[Cat.scala 29:58] wire [1:0] ic_bank_way_clken_1 = {_T_106,_T_110}; // @[Cat.scala 29:58]
wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 224:86] wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 216:86]
wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 224:108] wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 216:108]
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40] wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 218:40]
wire [8:0] _T_127 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58] wire [8:0] _T_127 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:30] reg [1:0] ic_b_rden_ff; // @[el2_ifu_ic_mem.scala 225:29]
wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17] reg [4:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 226:30]
wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36] reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 227:38]
wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69] reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 228:34]
wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:30] wire ic_cacheline_wrap_ff = ic_rw_addr_ff[4:2] == 3'h7; // @[el2_ifu_ic_mem.scala 230:84]
wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17] wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36] wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 242:17]
wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69] wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 242:36]
wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:30] wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17] wire [70:0] wb_dout_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 240:64]
wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36] wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 240:30]
wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69] wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:30] wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 242:36]
wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17] wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36] wire [70:0] wb_dout_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 240:64]
wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69] wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 240:64]
wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 240:30]
wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 242:17]
wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 242:36]
wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69]
wire [70:0] wb_dout_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 240:64]
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 246:24]
wire _T_187 = ~ic_rw_addr_ff[2]; // @[el2_ifu_ic_mem.scala 250:95]
wire [70:0] _T_192 = _T_187 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_193 = ic_rw_addr_ff[2] ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_194 = _T_192 | _T_193; // @[Mux.scala 27:72]
wire _T_198 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 251:102]
wire _T_199 = ic_rw_addr_ff[2] == _T_198; // @[el2_ifu_ic_mem.scala 251:95]
wire [70:0] _T_206 = _T_199 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_207 = _T_187 ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_208 = _T_206 | _T_207; // @[Mux.scala 27:72]
wire [141:0] wb_dout_way_pre_0 = {_T_194,_T_208}; // @[Cat.scala 29:58]
wire [70:0] _T_216 = _T_187 ? wb_dout_1_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_217 = ic_rw_addr_ff[2] ? wb_dout_1_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_218 = _T_216 | _T_217; // @[Mux.scala 27:72]
wire [70:0] _T_230 = _T_199 ? wb_dout_1_0 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_231 = _T_187 ? wb_dout_1_1 : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_232 = _T_230 | _T_231; // @[Mux.scala 27:72]
wire [141:0] wb_dout_way_pre_1 = {_T_218,_T_232}; // @[Cat.scala 29:58]
wire _T_235 = ic_rw_addr_ff[1:0] == 2'h0; // @[el2_ifu_ic_mem.scala 253:83]
wire _T_239 = ic_rw_addr_ff[1:0] == 2'h1; // @[el2_ifu_ic_mem.scala 254:24]
wire [63:0] _T_243 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58]
wire _T_245 = ic_rw_addr_ff[1:0] == 2'h2; // @[el2_ifu_ic_mem.scala 255:24]
wire [63:0] _T_249 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58]
wire _T_251 = ic_rw_addr_ff[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 256:24]
wire [63:0] _T_255 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_256 = _T_235 ? wb_dout_way_pre_0[63:0] : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_257 = _T_239 ? _T_243 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_258 = _T_245 ? _T_249 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_259 = _T_251 ? _T_255 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_260 = _T_256 | _T_257; // @[Mux.scala 27:72]
wire [63:0] _T_261 = _T_260 | _T_258; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_0 = _T_261 | _T_259; // @[Mux.scala 27:72]
wire [63:0] _T_272 = {wb_dout_way_pre_1[86:71],wb_dout_way_pre_1[63:16]}; // @[Cat.scala 29:58]
wire [63:0] _T_278 = {wb_dout_way_pre_1[102:71],wb_dout_way_pre_1[63:32]}; // @[Cat.scala 29:58]
wire [63:0] _T_284 = {wb_dout_way_pre_1[118:71],wb_dout_way_pre_1[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_285 = _T_235 ? wb_dout_way_pre_1[63:0] : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_286 = _T_239 ? _T_272 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_287 = _T_245 ? _T_278 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_288 = _T_251 ? _T_284 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72]
wire [63:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_1 = _T_290 | _T_288; // @[Mux.scala 27:72]
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 258:69]
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 258:69]
wire _T_295 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75]
wire _T_298 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75]
wire [63:0] _T_300 = _T_295 ? wb_dout_way_with_premux_0 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_301 = _T_298 ? wb_dout_way_with_premux_1 : 64'h0; // @[Mux.scala 27:72]
wire [70:0] _T_310 = ic_rd_hit_q[0] ? wb_dout_way_pre_0[70:0] : 71'h0; // @[Mux.scala 27:72]
wire [70:0] _T_311 = ic_rd_hit_q[1] ? wb_dout_way_pre_1[70:0] : 71'h0; // @[Mux.scala 27:72]
wire [141:0] _T_318 = ic_rd_hit_q[0] ? wb_dout_way_pre_0 : 142'h0; // @[Mux.scala 27:72]
wire [141:0] _T_319 = ic_rd_hit_q[1] ? wb_dout_way_pre_1 : 142'h0; // @[Mux.scala 27:72]
wire [141:0] wb_dout_ecc = _T_318 | _T_319; // @[Mux.scala 27:72]
wire _T_321 = |io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 264:75]
wire _T_322 = ~ic_cacheline_wrap_ff; // @[el2_ifu_ic_mem.scala 264:103]
wire _T_325 = ic_b_rden_ff == 2'h3; // @[el2_ifu_ic_mem.scala 264:163]
wire _T_326 = _T_322 & _T_325; // @[el2_ifu_ic_mem.scala 264:125]
wire bank_check_en_0 = _T_321 & _T_326; // @[el2_ifu_ic_mem.scala 264:79]
wire [70:0] wb_dout_ecc_bank_0 = wb_dout_ecc[70:0]; // @[el2_ifu_ic_mem.scala 265:72]
wire [70:0] wb_dout_ecc_bank_1 = wb_dout_ecc[141:71]; // @[el2_ifu_ic_mem.scala 265:72]
wire [6:0] _T_555 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[60],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[58],wb_dout_ecc_bank_0[57]}; // @[el2_lib.scala 380:41]
wire _T_556 = ^_T_555; // @[el2_lib.scala 380:48]
wire _T_557 = wb_dout_ecc_bank_0[70] ^ _T_556; // @[el2_lib.scala 380:36]
wire [6:0] _T_564 = {wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31],wb_dout_ecc_bank_0[30],wb_dout_ecc_bank_0[29],wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[27],wb_dout_ecc_bank_0[26]}; // @[el2_lib.scala 380:69]
wire [7:0] _T_571 = {wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[33]}; // @[el2_lib.scala 380:69]
wire [14:0] _T_572 = {wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[33],_T_564}; // @[el2_lib.scala 380:69]
wire [7:0] _T_579 = {wb_dout_ecc_bank_0[48],wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[45],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[43],wb_dout_ecc_bank_0[42],wb_dout_ecc_bank_0[41]}; // @[el2_lib.scala 380:69]
wire [30:0] _T_588 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_579,_T_572}; // @[el2_lib.scala 380:69]
wire _T_589 = ^_T_588; // @[el2_lib.scala 380:76]
wire _T_590 = wb_dout_ecc_bank_0[69] ^ _T_589; // @[el2_lib.scala 380:64]
wire [6:0] _T_597 = {wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[15],wb_dout_ecc_bank_0[14],wb_dout_ecc_bank_0[13],wb_dout_ecc_bank_0[12],wb_dout_ecc_bank_0[11]}; // @[el2_lib.scala 380:96]
wire [14:0] _T_605 = {wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[18],_T_597}; // @[el2_lib.scala 380:96]
wire [30:0] _T_621 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_579,_T_605}; // @[el2_lib.scala 380:96]
wire _T_622 = ^_T_621; // @[el2_lib.scala 380:103]
wire _T_623 = wb_dout_ecc_bank_0[68] ^ _T_622; // @[el2_lib.scala 380:91]
wire [6:0] _T_630 = {wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[7],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[5],wb_dout_ecc_bank_0[4]}; // @[el2_lib.scala 380:123]
wire [14:0] _T_638 = {wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[18],_T_630}; // @[el2_lib.scala 380:123]
wire [30:0] _T_654 = {wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[49],_T_571,_T_638}; // @[el2_lib.scala 380:123]
wire _T_655 = ^_T_654; // @[el2_lib.scala 380:130]
wire _T_656 = wb_dout_ecc_bank_0[67] ^ _T_655; // @[el2_lib.scala 380:118]
wire [7:0] _T_664 = {wb_dout_ecc_bank_0[14],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[7],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[2],wb_dout_ecc_bank_0[1]}; // @[el2_lib.scala 380:150]
wire [16:0] _T_673 = {wb_dout_ecc_bank_0[30],wb_dout_ecc_bank_0[29],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[22],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[15],_T_664}; // @[el2_lib.scala 380:150]
wire [8:0] _T_681 = {wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[45],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[37],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31]}; // @[el2_lib.scala 380:150]
wire [17:0] _T_690 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[60],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[53],wb_dout_ecc_bank_0[48],_T_681}; // @[el2_lib.scala 380:150]
wire [34:0] _T_691 = {_T_690,_T_673}; // @[el2_lib.scala 380:150]
wire _T_692 = ^_T_691; // @[el2_lib.scala 380:157]
wire _T_693 = wb_dout_ecc_bank_0[66] ^ _T_692; // @[el2_lib.scala 380:145]
wire [7:0] _T_701 = {wb_dout_ecc_bank_0[12],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[9],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[5],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[2],wb_dout_ecc_bank_0[0]}; // @[el2_lib.scala 380:177]
wire [16:0] _T_710 = {wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[27],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[24],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[20],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[16],wb_dout_ecc_bank_0[13],_T_701}; // @[el2_lib.scala 380:177]
wire [8:0] _T_718 = {wb_dout_ecc_bank_0[47],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[43],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[39],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[35],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[31]}; // @[el2_lib.scala 380:177]
wire [17:0] _T_727 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[58],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[55],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[51],wb_dout_ecc_bank_0[48],_T_718}; // @[el2_lib.scala 380:177]
wire [34:0] _T_728 = {_T_727,_T_710}; // @[el2_lib.scala 380:177]
wire _T_729 = ^_T_728; // @[el2_lib.scala 380:184]
wire _T_730 = wb_dout_ecc_bank_0[65] ^ _T_729; // @[el2_lib.scala 380:172]
wire [7:0] _T_738 = {wb_dout_ecc_bank_0[11],wb_dout_ecc_bank_0[10],wb_dout_ecc_bank_0[8],wb_dout_ecc_bank_0[6],wb_dout_ecc_bank_0[4],wb_dout_ecc_bank_0[3],wb_dout_ecc_bank_0[1],wb_dout_ecc_bank_0[0]}; // @[el2_lib.scala 380:204]
wire [16:0] _T_747 = {wb_dout_ecc_bank_0[28],wb_dout_ecc_bank_0[26],wb_dout_ecc_bank_0[25],wb_dout_ecc_bank_0[23],wb_dout_ecc_bank_0[21],wb_dout_ecc_bank_0[19],wb_dout_ecc_bank_0[17],wb_dout_ecc_bank_0[15],wb_dout_ecc_bank_0[13],_T_738}; // @[el2_lib.scala 380:204]
wire [8:0] _T_755 = {wb_dout_ecc_bank_0[46],wb_dout_ecc_bank_0[44],wb_dout_ecc_bank_0[42],wb_dout_ecc_bank_0[40],wb_dout_ecc_bank_0[38],wb_dout_ecc_bank_0[36],wb_dout_ecc_bank_0[34],wb_dout_ecc_bank_0[32],wb_dout_ecc_bank_0[30]}; // @[el2_lib.scala 380:204]
wire [17:0] _T_764 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[57],wb_dout_ecc_bank_0[56],wb_dout_ecc_bank_0[54],wb_dout_ecc_bank_0[52],wb_dout_ecc_bank_0[50],wb_dout_ecc_bank_0[48],_T_755}; // @[el2_lib.scala 380:204]
wire [34:0] _T_765 = {_T_764,_T_747}; // @[el2_lib.scala 380:204]
wire _T_766 = ^_T_765; // @[el2_lib.scala 380:211]
wire _T_767 = wb_dout_ecc_bank_0[64] ^ _T_766; // @[el2_lib.scala 380:199]
wire [6:0] _T_773 = {_T_557,_T_590,_T_623,_T_656,_T_693,_T_730,_T_767}; // @[Cat.scala 29:58]
wire _T_775 = _T_773 != 7'h0; // @[el2_lib.scala 381:42]
wire _T_776 = bank_check_en_0 & _T_775; // @[el2_lib.scala 381:24]
wire [6:0] _T_997 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[60],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[58],wb_dout_ecc_bank_1[57]}; // @[el2_lib.scala 380:41]
wire _T_998 = ^_T_997; // @[el2_lib.scala 380:48]
wire _T_999 = wb_dout_ecc_bank_1[70] ^ _T_998; // @[el2_lib.scala 380:36]
wire [6:0] _T_1006 = {wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31],wb_dout_ecc_bank_1[30],wb_dout_ecc_bank_1[29],wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[27],wb_dout_ecc_bank_1[26]}; // @[el2_lib.scala 380:69]
wire [7:0] _T_1013 = {wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[33]}; // @[el2_lib.scala 380:69]
wire [14:0] _T_1014 = {wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[33],_T_1006}; // @[el2_lib.scala 380:69]
wire [7:0] _T_1021 = {wb_dout_ecc_bank_1[48],wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[45],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[43],wb_dout_ecc_bank_1[42],wb_dout_ecc_bank_1[41]}; // @[el2_lib.scala 380:69]
wire [30:0] _T_1030 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1021,_T_1014}; // @[el2_lib.scala 380:69]
wire _T_1031 = ^_T_1030; // @[el2_lib.scala 380:76]
wire _T_1032 = wb_dout_ecc_bank_1[69] ^ _T_1031; // @[el2_lib.scala 380:64]
wire [6:0] _T_1039 = {wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[15],wb_dout_ecc_bank_1[14],wb_dout_ecc_bank_1[13],wb_dout_ecc_bank_1[12],wb_dout_ecc_bank_1[11]}; // @[el2_lib.scala 380:96]
wire [14:0] _T_1047 = {wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[18],_T_1039}; // @[el2_lib.scala 380:96]
wire [30:0] _T_1063 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1021,_T_1047}; // @[el2_lib.scala 380:96]
wire _T_1064 = ^_T_1063; // @[el2_lib.scala 380:103]
wire _T_1065 = wb_dout_ecc_bank_1[68] ^ _T_1064; // @[el2_lib.scala 380:91]
wire [6:0] _T_1072 = {wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[7],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[5],wb_dout_ecc_bank_1[4]}; // @[el2_lib.scala 380:123]
wire [14:0] _T_1080 = {wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[18],_T_1072}; // @[el2_lib.scala 380:123]
wire [30:0] _T_1096 = {wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[49],_T_1013,_T_1080}; // @[el2_lib.scala 380:123]
wire _T_1097 = ^_T_1096; // @[el2_lib.scala 380:130]
wire _T_1098 = wb_dout_ecc_bank_1[67] ^ _T_1097; // @[el2_lib.scala 380:118]
wire [7:0] _T_1106 = {wb_dout_ecc_bank_1[14],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[7],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[2],wb_dout_ecc_bank_1[1]}; // @[el2_lib.scala 380:150]
wire [16:0] _T_1115 = {wb_dout_ecc_bank_1[30],wb_dout_ecc_bank_1[29],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[22],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[15],_T_1106}; // @[el2_lib.scala 380:150]
wire [8:0] _T_1123 = {wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[45],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[37],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31]}; // @[el2_lib.scala 380:150]
wire [17:0] _T_1132 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[60],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[53],wb_dout_ecc_bank_1[48],_T_1123}; // @[el2_lib.scala 380:150]
wire [34:0] _T_1133 = {_T_1132,_T_1115}; // @[el2_lib.scala 380:150]
wire _T_1134 = ^_T_1133; // @[el2_lib.scala 380:157]
wire _T_1135 = wb_dout_ecc_bank_1[66] ^ _T_1134; // @[el2_lib.scala 380:145]
wire [7:0] _T_1143 = {wb_dout_ecc_bank_1[12],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[9],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[5],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[2],wb_dout_ecc_bank_1[0]}; // @[el2_lib.scala 380:177]
wire [16:0] _T_1152 = {wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[27],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[24],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[20],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[16],wb_dout_ecc_bank_1[13],_T_1143}; // @[el2_lib.scala 380:177]
wire [8:0] _T_1160 = {wb_dout_ecc_bank_1[47],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[43],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[39],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[35],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[31]}; // @[el2_lib.scala 380:177]
wire [17:0] _T_1169 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[62],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[58],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[55],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[51],wb_dout_ecc_bank_1[48],_T_1160}; // @[el2_lib.scala 380:177]
wire [34:0] _T_1170 = {_T_1169,_T_1152}; // @[el2_lib.scala 380:177]
wire _T_1171 = ^_T_1170; // @[el2_lib.scala 380:184]
wire _T_1172 = wb_dout_ecc_bank_1[65] ^ _T_1171; // @[el2_lib.scala 380:172]
wire [7:0] _T_1180 = {wb_dout_ecc_bank_1[11],wb_dout_ecc_bank_1[10],wb_dout_ecc_bank_1[8],wb_dout_ecc_bank_1[6],wb_dout_ecc_bank_1[4],wb_dout_ecc_bank_1[3],wb_dout_ecc_bank_1[1],wb_dout_ecc_bank_1[0]}; // @[el2_lib.scala 380:204]
wire [16:0] _T_1189 = {wb_dout_ecc_bank_1[28],wb_dout_ecc_bank_1[26],wb_dout_ecc_bank_1[25],wb_dout_ecc_bank_1[23],wb_dout_ecc_bank_1[21],wb_dout_ecc_bank_1[19],wb_dout_ecc_bank_1[17],wb_dout_ecc_bank_1[15],wb_dout_ecc_bank_1[13],_T_1180}; // @[el2_lib.scala 380:204]
wire [8:0] _T_1197 = {wb_dout_ecc_bank_1[46],wb_dout_ecc_bank_1[44],wb_dout_ecc_bank_1[42],wb_dout_ecc_bank_1[40],wb_dout_ecc_bank_1[38],wb_dout_ecc_bank_1[36],wb_dout_ecc_bank_1[34],wb_dout_ecc_bank_1[32],wb_dout_ecc_bank_1[30]}; // @[el2_lib.scala 380:204]
wire [17:0] _T_1206 = {wb_dout_ecc_bank_1[63],wb_dout_ecc_bank_1[61],wb_dout_ecc_bank_1[59],wb_dout_ecc_bank_1[57],wb_dout_ecc_bank_1[56],wb_dout_ecc_bank_1[54],wb_dout_ecc_bank_1[52],wb_dout_ecc_bank_1[50],wb_dout_ecc_bank_1[48],_T_1197}; // @[el2_lib.scala 380:204]
wire [34:0] _T_1207 = {_T_1206,_T_1189}; // @[el2_lib.scala 380:204]
wire _T_1208 = ^_T_1207; // @[el2_lib.scala 380:211]
wire _T_1209 = wb_dout_ecc_bank_1[64] ^ _T_1208; // @[el2_lib.scala 380:199]
wire [6:0] _T_1215 = {_T_999,_T_1032,_T_1065,_T_1098,_T_1135,_T_1172,_T_1209}; // @[Cat.scala 29:58]
wire _T_1217 = _T_1215 != 7'h0; // @[el2_lib.scala 381:42]
wire _T_1218 = bank_check_en_0 & _T_1217; // @[el2_lib.scala 381:24]
wire _T_1222 = ^wb_dout_ecc_bank_0[15:0]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_0 = _T_1222 ^ wb_dout_ecc_bank_0[64]; // @[el2_lib.scala 190:27]
wire _T_1226 = ^wb_dout_ecc_bank_0[31:16]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_1 = _T_1226 ^ wb_dout_ecc_bank_0[65]; // @[el2_lib.scala 190:27]
wire _T_1230 = ^wb_dout_ecc_bank_0[47:32]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_2 = _T_1230 ^ wb_dout_ecc_bank_0[66]; // @[el2_lib.scala 190:27]
wire _T_1234 = ^wb_dout_ecc_bank_0[63:48]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_0_3 = _T_1234 ^ wb_dout_ecc_bank_0[67]; // @[el2_lib.scala 190:27]
wire _T_1238 = ^wb_dout_ecc_bank_1[15:0]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_0 = _T_1238 ^ wb_dout_ecc_bank_1[64]; // @[el2_lib.scala 190:27]
wire _T_1242 = ^wb_dout_ecc_bank_1[31:16]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_1 = _T_1242 ^ wb_dout_ecc_bank_1[65]; // @[el2_lib.scala 190:27]
wire _T_1246 = ^wb_dout_ecc_bank_1[47:32]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_2 = _T_1246 ^ wb_dout_ecc_bank_1[66]; // @[el2_lib.scala 190:27]
wire _T_1250 = ^wb_dout_ecc_bank_1[63:48]; // @[el2_lib.scala 190:14]
wire ic_parerr_bank_1_3 = _T_1250 ^ wb_dout_ecc_bank_1[67]; // @[el2_lib.scala 190:27]
wire _T_1252 = ic_parerr_bank_0_0 | ic_parerr_bank_0_1; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1253 = _T_1252 | ic_parerr_bank_0_2; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1254 = _T_1253 | ic_parerr_bank_0_3; // @[el2_ifu_ic_mem.scala 272:49]
wire _T_1255 = _T_1254 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:53]
wire _T_1256 = ic_parerr_bank_1_0 | ic_parerr_bank_1_1; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1257 = _T_1256 | ic_parerr_bank_1_2; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1258 = _T_1257 | ic_parerr_bank_1_3; // @[el2_ifu_ic_mem.scala 272:99]
wire _T_1259 = _T_1258 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:103]
assign data_mem_0_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_158_addr = ic_rw_addr_q[11:3]; assign data_mem_0_0__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_184_addr = ic_rw_addr_q[11:3]; assign data_mem_0_0__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_0__T_139_data = io_test_in; assign data_mem_0_0__T_139_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_0_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_0__T_139_mask = 1'h1; assign data_mem_0_0__T_139_mask = 1'h1;
assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
@ -219,13 +406,13 @@ module EL2_IC_DATA(
assign data_mem_0_0__T_178_mask = 1'h0; assign data_mem_0_0__T_178_mask = 1'h0;
assign data_mem_0_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_0_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_0_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_158_addr = ic_rw_addr_q[11:3]; assign data_mem_0_1__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_184_addr = ic_rw_addr_q[11:3]; assign data_mem_0_1__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_0_1__T_139_data = 71'h0; assign data_mem_0_1__T_139_data = 71'h0;
assign data_mem_0_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_139_mask = 1'h0; assign data_mem_0_1__T_139_mask = 1'h0;
@ -234,7 +421,7 @@ module EL2_IC_DATA(
assign data_mem_0_1__T_152_addr = ic_rw_addr_q[11:3]; assign data_mem_0_1__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_0_1__T_152_mask = 1'h0; assign data_mem_0_1__T_152_mask = 1'h0;
assign data_mem_0_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; assign data_mem_0_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
assign data_mem_0_1__T_165_data = io_test_in; assign data_mem_0_1__T_165_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_0_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_0_1__T_165_mask = 1'h1; assign data_mem_0_1__T_165_mask = 1'h1;
assign data_mem_0_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; assign data_mem_0_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
@ -243,18 +430,18 @@ module EL2_IC_DATA(
assign data_mem_0_1__T_178_mask = 1'h0; assign data_mem_0_1__T_178_mask = 1'h0;
assign data_mem_0_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_0_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_158_addr = ic_rw_addr_q[11:3]; assign data_mem_1_0__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_184_addr = ic_rw_addr_q[11:3]; assign data_mem_1_0__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_0__T_139_data = 71'h0; assign data_mem_1_0__T_139_data = 71'h0;
assign data_mem_1_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_0__T_139_mask = 1'h0; assign data_mem_1_0__T_139_mask = 1'h0;
assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
assign data_mem_1_0__T_152_data = io_test_in; assign data_mem_1_0__T_152_data = _T_31 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_1_0__T_152_addr = ic_rw_addr_q[11:3]; assign data_mem_1_0__T_152_addr = ic_rw_addr_q[11:3];
assign data_mem_1_0__T_152_mask = 1'h1; assign data_mem_1_0__T_152_mask = 1'h1;
assign data_mem_1_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; assign data_mem_1_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
@ -267,13 +454,13 @@ module EL2_IC_DATA(
assign data_mem_1_0__T_178_mask = 1'h0; assign data_mem_1_0__T_178_mask = 1'h0;
assign data_mem_1_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_1_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign data_mem_1_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_158_addr = ic_rw_addr_q[11:3]; assign data_mem_1_1__T_158_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_184_addr = ic_rw_addr_q[11:3]; assign data_mem_1_1__T_184_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21]
assign data_mem_1_1__T_139_data = 71'h0; assign data_mem_1_1__T_139_data = 71'h0;
assign data_mem_1_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_139_mask = 1'h0; assign data_mem_1_1__T_139_mask = 1'h0;
@ -286,19 +473,14 @@ module EL2_IC_DATA(
assign data_mem_1_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
assign data_mem_1_1__T_165_mask = 1'h0; assign data_mem_1_1__T_165_mask = 1'h0;
assign data_mem_1_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; assign data_mem_1_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
assign data_mem_1_1__T_178_data = io_test_in; assign data_mem_1_1__T_178_data = _T_31 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3]; assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3];
assign data_mem_1_1__T_178_mask = 1'h1; assign data_mem_1_1__T_178_mask = 1'h1;
assign data_mem_1_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_1_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17] assign io_ic_rd_data = _T_300 | _T_301; // @[el2_ifu_ic_mem.scala 260:17]
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23] assign io_ic_debug_rd_data = _T_310 | _T_311; // @[el2_ifu_ic_mem.scala 261:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16] assign io_ic_parerr = {_T_1255,_T_1259}; // @[el2_ifu_ic_mem.scala 272:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16] assign io_ic_eccerr = {_T_1218,_T_776}; // @[el2_ifu_ic_mem.scala 268:16]
assign io_test = 1'h0; // @[el2_ifu_ic_mem.scala 198:11]
assign io_test_port_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 254:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif
@ -347,6 +529,16 @@ initial begin
for (initvar = 0; initvar < 512; initvar = initvar+1) for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_1[initvar] = _RAND_3[70:0]; data_mem_1_1[initvar] = _RAND_3[70:0];
`endif // RANDOMIZE_MEM_INIT `endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
ic_b_rden_ff = _RAND_4[1:0];
_RAND_5 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_5[4:0];
_RAND_6 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_6[1:0];
_RAND_7 = {1{`RANDOM}};
ic_debug_rd_en_ff = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
`ifdef FIRRTL_AFTER_INITIAL `ifdef FIRRTL_AFTER_INITIAL
@ -355,52 +547,72 @@ end // initial
`endif // SYNTHESIS `endif // SYNTHESIS
always @(posedge clock) begin always @(posedge clock) begin
if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin
data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_0__T_152_en & data_mem_0_0__T_152_mask) begin if(data_mem_0_0__T_152_en & data_mem_0_0__T_152_mask) begin
data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_0__T_165_en & data_mem_0_0__T_165_mask) begin if(data_mem_0_0__T_165_en & data_mem_0_0__T_165_mask) begin
data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_0__T_178_en & data_mem_0_0__T_178_mask) begin if(data_mem_0_0__T_178_en & data_mem_0_0__T_178_mask) begin
data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin
data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_1__T_152_en & data_mem_0_1__T_152_mask) begin if(data_mem_0_1__T_152_en & data_mem_0_1__T_152_mask) begin
data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_1__T_165_en & data_mem_0_1__T_165_mask) begin if(data_mem_0_1__T_165_en & data_mem_0_1__T_165_mask) begin
data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_0_1__T_178_en & data_mem_0_1__T_178_mask) begin if(data_mem_0_1__T_178_en & data_mem_0_1__T_178_mask) begin
data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin
data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_0__T_152_en & data_mem_1_0__T_152_mask) begin if(data_mem_1_0__T_152_en & data_mem_1_0__T_152_mask) begin
data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_0__T_165_en & data_mem_1_0__T_165_mask) begin if(data_mem_1_0__T_165_en & data_mem_1_0__T_165_mask) begin
data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_0__T_178_en & data_mem_1_0__T_178_mask) begin if(data_mem_1_0__T_178_en & data_mem_1_0__T_178_mask) begin
data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin
data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_1__T_152_en & data_mem_1_1__T_152_mask) begin if(data_mem_1_1__T_152_en & data_mem_1_1__T_152_mask) begin
data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_1__T_165_en & data_mem_1_1__T_165_mask) begin if(data_mem_1_1__T_165_en & data_mem_1_1__T_165_mask) begin
data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21]
end end
if(data_mem_1_1__T_178_en & data_mem_1_1__T_178_mask) begin if(data_mem_1_1__T_178_en & data_mem_1_1__T_178_mask) begin
data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21] data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21]
end
if (reset) begin
ic_b_rden_ff <= 2'h0;
end else begin
ic_b_rden_ff <= ic_b_rden;
end
if (reset) begin
ic_rw_addr_ff <= 5'h0;
end else begin
ic_rw_addr_ff <= ic_rw_addr_q[4:0];
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
if (reset) begin
ic_debug_rd_en_ff <= 1'h0;
end else begin
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
end end
end end
endmodule endmodule

2
el2_ifu_ifc_ctl.fir
View File

@ -85,7 +85,7 @@ circuit el2_ifu_ifc_ctl :
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42] node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48] node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48] node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39] node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:39]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84] node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63] node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24] node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]

2
el2_ifu_ifc_ctl.v
View File

@ -55,7 +55,7 @@ module el2_ifu_ifc_ctl(
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48] wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63] wire _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24] wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109] wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58] wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]

70
src/main/scala/ifu/el2_ifu_aln_ctl.scala
View File

@ -7,41 +7,41 @@ import include._
class el2_ifu_aln_ctl extends Module with el2_lib { class el2_ifu_aln_ctl extends Module with el2_lib {
val io = IO(new Bundle{ val io = IO(new Bundle{
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val active_clk = Input(Clock()) val active_clk = Input(Clock())
val ifu_async_error_start = Input(Bool()) val ifu_async_error_start = Input(Bool())
val iccm_rd_ecc_double_err = Input(Bool()) val iccm_rd_ecc_double_err = Input(Bool())
val ic_access_fault_f = Input(Bool()) val ic_access_fault_f = Input(Bool())
val ic_access_fault_type_f = Input(UInt(2.W)) val ic_access_fault_type_f = Input(UInt(2.W))
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W))
val ifu_bp_btb_target_f = Input(UInt(32.W)) val ifu_bp_btb_target_f = Input(UInt(32.W))
val ifu_bp_poffset_f = Input(UInt(12.W)) val ifu_bp_poffset_f = Input(UInt(12.W))
val ifu_bp_hist0_f = Input(UInt(2.W)) val ifu_bp_hist0_f = Input(UInt(2.W))
val ifu_bp_hist1_f = Input(UInt(2.W)) val ifu_bp_hist1_f = Input(UInt(2.W))
val ifu_bp_pc4_f = Input(UInt(2.W)) val ifu_bp_pc4_f = Input(UInt(2.W))
val ifu_bp_way_f = Input(UInt(2.W)) val ifu_bp_way_f = Input(UInt(2.W))
val ifu_bp_valid_f = Input(UInt(2.W)) val ifu_bp_valid_f = Input(UInt(2.W))
val ifu_bp_ret_f = Input(UInt(2.W)) val ifu_bp_ret_f = Input(UInt(2.W))
val exu_flush_final = Input(Bool()) val exu_flush_final = Input(Bool())
val dec_i0_decode_d = Input(Bool()) val dec_i0_decode_d = Input(Bool())
val ifu_fetch_data_f = Input(UInt(32.W)) val ifu_fetch_data_f = Input(UInt(32.W))
val ifu_fetch_val = Input(UInt(2.W)) val ifu_fetch_val = Input(UInt(2.W))
val ifu_fetch_pc = Input(UInt(32.W)) val ifu_fetch_pc = Input(UInt(32.W))
val ifu_i0_valid = Output(Bool()) val ifu_i0_valid = Output(Bool())
val ifu_i0_icaf = Output(Bool()) val ifu_i0_icaf = Output(Bool())
val ifu_i0_icaf_type = Output(UInt(2.W)) val ifu_i0_icaf_type = Output(UInt(2.W))
val ifu_i0_icaf_f1 = Output(Bool()) val ifu_i0_icaf_f1 = Output(Bool())
val ifu_i0_dbecc = Output(Bool()) val ifu_i0_dbecc = Output(Bool())
val ifu_i0_instr = Output(UInt(32.W)) val ifu_i0_instr = Output(UInt(32.W))
val ifu_i0_pc = Output(UInt(32.W)) val ifu_i0_pc = Output(UInt(32.W))
val ifu_i0_pc4 = Output(Bool()) val ifu_i0_pc4 = Output(Bool())
val ifu_fb_consume1 = Output(Bool()) val ifu_fb_consume1 = Output(Bool())
val ifu_fb_consume2 = Output(Bool()) val ifu_fb_consume2 = Output(Bool())
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W))
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_pmu_instr_aligned = Output(Bool()) val ifu_pmu_instr_aligned = Output(Bool())
val ifu_i0_cinst = Output(UInt(16.W)) val ifu_i0_cinst = Output(UInt(16.W))
val i0_brp = Output(new el2_br_pkt_t) val i0_brp = Output(new el2_br_pkt_t)
}) })
val MHI = 46+BHT_GHR_SIZE // 54 val MHI = 46+BHT_GHR_SIZE // 54
val MSIZE = 47+BHT_GHR_SIZE // 55 val MSIZE = 47+BHT_GHR_SIZE // 55

262
src/main/scala/ifu/el2_ifu_ic_mem.scala
View File

@ -42,124 +42,123 @@ class el2_ifu_ic_mem extends Module with param{
/////////// ICACHE TAG /////////// ICACHE TAG
class EL2_IC_TAG extends Module with el2_lib with param { class EL2_IC_TAG extends Module with el2_lib with param {
val io = IO(new Bundle{ val io = IO(new Bundle{
val clk = Input(Bool()) val clk_override = Input(Bool())
val rst_l = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool())
val clk_override = Input(Bool()) val ic_rw_addr = Input(UInt(28.W))
val dec_tlu_core_ecc_disable = Input(Bool()) val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rw_addr = Input(UInt(32.W)) // TODO : In SV we have 31:3 what should we do here val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_rd_en = Input(Bool())
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W))
val ic_rd_en = Input(Bool()) val ic_debug_rd_en = Input(Bool())
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+1).W)) val ic_debug_wr_en = Input(Bool())
val ic_debug_rd_en = Input(Bool()) val ic_debug_tag_array = Input(Bool())
val ic_debug_wr_en = Input(Bool()) val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_debug_tag_array = Input(Bool()) // val ictag_debug_rd_data = Output(UInt(26.W))
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_debug_wr_data = Input(UInt(71.W))
val ictag_debug_rd_data = Output(UInt(26.W)) // val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_debug_wr_data = Input(UInt(71.W)) // val ic_tag_perr = Output(Bool())
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) val scan_mode = Input(Bool())
val ic_tag_perr = Output(Bool())
val scan_mode = Input(Bool())
}) })
val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)=== // val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
repl(ICACHE_NUM_WAYS-1, 1.U)) // val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en |
val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way // val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way // val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | // val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_wr_way_en | ic_debug_rd_way_en
ic_debug_rd_way_en // ic_debug_rd_way_en
val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U) // val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U)
val ic_rw_addr_ff = RegNext(io.ic_rw_addr, init=0.U) // val ic_rw_addr_ff = RegNext(io.ic_rw_addr, init=0.U)
val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) // val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en // val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
val ic_tag_ecc = Wire(UInt(7.W)) // val ic_tag_ecc = Wire(UInt(7.W))
val ic_tag_wr_data = Wire(UInt(26.W)) // val ic_tag_wr_data = Wire(UInt(26.W))
val ic_tag_parity = Wire(UInt(1.W)) // val ic_tag_parity = Wire(UInt(1.W))
ic_tag_ecc := 0.U // ic_tag_ecc := 0.U
ic_tag_wr_data := 0.U // ic_tag_wr_data := 0.U
ic_tag_parity := 0.U // ic_tag_parity := 0.U
when((ICACHE_TAG_LO == 11).B){ //
when(ICACHE_ECC.B){ // when((ICACHE_TAG_LO == 11).B){
ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO))) // when(ICACHE_ECC.B){
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, // ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) , // ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO))) // Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
} // Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
.otherwise{ // }
ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO)) // .otherwise{
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, // ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) , // ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO))) // Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
} // Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
} // }
// }
.otherwise{ //
when(ICACHE_ECC.B){ // .otherwise{
ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO))) // when(ICACHE_ECC.B){
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, // ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) , // ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO))) // Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
} // Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
.otherwise{ // }
ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO)) // .otherwise{
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, // ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) , // ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO))) // Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
} // Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
} // }
// }
val ic_rw_addr_q = Mux(io.ic_debug_rd_en | io.ic_debug_wr_en, //
io.ic_debug_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO), // val ic_rw_addr_q = Mux(io.ic_debug_rd_en | io.ic_debug_wr_en,
io.ic_rw_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO)) // io.ic_debug_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO),
// io.ic_rw_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO))
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U) //
// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
val ic_way_tag = if(ICACHE_ECC) SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))) //
else SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W))) // val ic_way_tag = if(ICACHE_ECC) SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W)))
//val ic_tag_data_raw = if(ICACHE_ECC) Vec(ICACHE_NUM_WAYS, UInt(26.W)) else Vec(ICACHE_NUM_WAYS, UInt(22.W)) // else SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
// //val ic_tag_data_raw = if(ICACHE_ECC) Vec(ICACHE_NUM_WAYS, UInt(26.W)) else Vec(ICACHE_NUM_WAYS, UInt(22.W))
val write_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wr_data) //
// val write_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wr_data)
val mem_mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wren_q(i) & ic_tag_clken(i)) //
// val mem_mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wren_q(i) & ic_tag_clken(i))
ic_way_tag.write(ic_rw_addr_q, write_data, mem_mask) //
// ic_way_tag.write(ic_rw_addr_q, write_data, mem_mask)
val ic_tag_data_raw = ic_way_tag.read(ic_rw_addr_q, 1.B) //
//val w_tout = Wire(UInt(32.W)) // val ic_tag_data_raw = ic_way_tag.read(ic_rw_addr_q, 1.B)
val w_tout = if(ICACHE_ECC)ic_tag_data_raw.map(x=>Cat(ic_tag_data_raw(x)(25,21),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W))) // //val w_tout = Wire(UInt(32.W))
else ic_tag_data_raw.map(x=>Cat(0.U(4.W),ic_tag_data_raw(x)(32),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W))) // val w_tout = if(ICACHE_ECC)ic_tag_data_raw.map(x=>Cat(ic_tag_data_raw(x)(25,21),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
// else ic_tag_data_raw.map(x=>Cat(0.U(4.W),ic_tag_data_raw(x)(32),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
val ecc_decode = new Array[rvecc_decode](ICACHE_NUM_WAYS) //
val parcheck = new Array[UInt](ICACHE_NUM_WAYS) // val ecc_decode = new Array[rvecc_decode](ICACHE_NUM_WAYS)
val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W))) // val parcheck = new Array[UInt](ICACHE_NUM_WAYS)
val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W))) // val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W)))
val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) // val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W)))
val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) // val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
// val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val ic_tag_way_perr = VecInit.tabulate(ICACHE_NUM_WAYS)(i => rveven_paritycheck(w_tout(i)(31,ICACHE_TAG_LO),w_tout(i)(31))) //
for(i <- 0 until ICACHE_NUM_WAYS) { // val ic_tag_way_perr = VecInit.tabulate(ICACHE_NUM_WAYS)(i => rveven_paritycheck(w_tout(i)(31,ICACHE_TAG_LO),w_tout(i)(31)))
ecc_decode(i) = Module(new rvecc_decode()) // for(i <- 0 until ICACHE_NUM_WAYS) {
ecc_decode(i).io.en := ~io.dec_tlu_core_ecc_disable & ic_rd_en_ff // ecc_decode(i) = Module(new rvecc_decode())
ecc_decode(i).io.sed_ded := 1.U // ecc_decode(i).io.en := ~io.dec_tlu_core_ecc_disable & ic_rd_en_ff
ecc_decode(i).io.din := Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)) // ecc_decode(i).io.sed_ded := 1.U
ecc_decode(i).io.ecc_in := Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)) // ecc_decode(i).io.din := Cat(0.U(11.W),ic_tag_data_raw(i)(20,0))
// ecc_decode(i).io.ecc_in := Cat(0.U(2.W),ic_tag_data_raw(i)(25,21))
//
ic_tag_way_perr(i) := ic_tag_single_ecc_error(i) | ic_tag_double_ecc_error(i) //
} // ic_tag_way_perr(i) := ic_tag_single_ecc_error(i) | ic_tag_double_ecc_error(i)
val temp = if(ICACHE_ECC) // }
VecInit.tabulate(ICACHE_NUM_WAYS)(i=>repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)).reduce(_|_) // val temp = if(ICACHE_ECC)
else // VecInit.tabulate(ICACHE_NUM_WAYS)(i=>repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)).reduce(_|_)
VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(0.U(4.W),repl(22,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i))).reduce(_|_) // else
// VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(0.U(4.W),repl(22,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i))).reduce(_|_)
for(i <- 0 until ICACHE_NUM_WAYS){ //
repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) // for(i <- 0 until ICACHE_NUM_WAYS){
} // repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)
io.ictag_debug_rd_data := temp // }
io.ic_tag_perr := (ic_tag_way_perr.reverse.reduce(Cat(_,_)) & io.ic_tag_valid).orR // io.ictag_debug_rd_data := temp
val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i)) // io.ic_tag_perr := (ic_tag_way_perr.reverse.reduce(Cat(_,_)) & io.ic_tag_valid).orR
io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reverse.reduce(Cat(_,_)) // val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i))
// io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reverse.reduce(Cat(_,_))
} }
@ -186,17 +185,8 @@ class EL2_IC_DATA extends Module with el2_lib {
val ic_sel_premux_data = Input(Bool()) val ic_sel_premux_data = Input(Bool())
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val scan_mode = Input(UInt(1.W)) val scan_mode = Input(UInt(1.W))
val test_in = Input(UInt(71.W))
val test = Output(UInt())
val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W))))
}) })
io.ic_rd_data := 0.U
io.ic_debug_rd_data := 0.U
io.ic_parerr := 0.U
io.ic_eccerr := 0.U
io.test := 0.U
val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
@ -246,12 +236,11 @@ class EL2_IC_DATA extends Module with el2_lib {
val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i) val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i) val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){ when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in data_mem(ic_rw_addr_bank_q(k))(k)(i) := ic_sb_wr_data(k)
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){ }.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i) wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
} }
} }
io.test_port := wb_dout
val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit) val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit)
ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_)) ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_))
@ -260,20 +249,27 @@ class EL2_IC_DATA extends Module with el2_lib {
Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j))))) Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j)))))
val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0), val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0),
(ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(86,71),wb_dout_way_pre(i)(63,16)), (ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+15,data_mem_word),wb_dout_way_pre(i)(63,16)),
(ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(102,71),wb_dout_way_pre(i)(63,32)), (ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+31,data_mem_word),wb_dout_way_pre(i)(63,32)),
(ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(119,71),wb_dout_way_pre(i)(63,48))))) (ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+47,data_mem_word),wb_dout_way_pre(i)(63,48)))))
val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i))) val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i)))
val ic_rd_data = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i))) io.ic_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i)))
val ic_debug_rd_data = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0))) io.ic_debug_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0)))
val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i))) val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)))
val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U)))) val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U))))
val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((71*i)+70,71*i)) val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((data_mem_word*i)+data_mem_word-1,data_mem_word*i))
// TODO: RVECC
io.ic_eccerr := (0 until ICACHE_NUM_WAYS).map(i=>rvecc_decode_64(bank_check_en(i),wb_dout_ecc_bank(i)(63,0),wb_dout_ecc_bank(i)(70,64)).asUInt).reverse.reduce(Cat(_,_))
val ic_parerr_bank = Wire(Vec(ICACHE_NUM_WAYS, Vec(4, UInt(1.W))))
for(i<-0 until ICACHE_NUM_WAYS; j<-0 until 4){ic_parerr_bank(i)(j):=rveven_paritycheck(wb_dout_ecc_bank(i)(16*(j+1)-1, 16*j), wb_dout_ecc_bank(i)(64+j))}
io.ic_parerr := Cat(ic_parerr_bank(0).reduce(_|_) & bank_check_en(0), ic_parerr_bank(1).reduce(_|_) & bank_check_en(1))
} }
object ifu_ic extends App { object ifu_ic extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA())) println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG()))
} }

2
src/main/scala/ifu/el2_ifu_ifc_ctl.scala
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@ -75,7 +75,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4 sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
fetch_addr_next := Cat(address_upper, fetch_addr_next_0) fetch_addr_next := Cat(address_upper, fetch_addr_next_0)

72
src/main/scala/lib/el2_lib.scala
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@ -309,4 +309,76 @@ trait el2_lib extends param{
io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
} }
def rvecc_encode_64(din:UInt):UInt = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 63 to 0)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
}
val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
ecc_out
}
def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = {
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := din(i); z = z +1 }
}
val ecc_check = Cat((ecc_in(6) ^ w6.asUInt.xorR) ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR))
val ecc_error = en & (ecc_check(6,0) =/= 0.U)
ecc_error
}
} }

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target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class
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target/scala-2.12/classes/ifu/EL2_IC_DATA.class
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target/scala-2.12/classes/ifu/EL2_IC_TAG$$anon$2.class
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target/scala-2.12/classes/ifu/EL2_IC_TAG.class
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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
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target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class
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target/scala-2.12/classes/ifu/ifu_ic$.class
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