diff --git a/.idea/misc.xml b/.idea/misc.xml
index ced87f49..4227b716 100644
--- a/.idea/misc.xml
+++ b/.idea/misc.xml
@@ -4,6 +4,71 @@
   <component name="SVCompilerDirectivesDefines">
     <option name="define">
       <map>
+        <entry key="EL2_LOCAL_RAM_TEST_IO">
+          <value>
+            <Define>
+              <option name="definitions">
+                <list>
+                  <Body>
+                    <option name="offset" value="668" />
+                    <option name="replacementList" value="input logic WE,              &#10;input logic ME,              &#10;input logic CLK" />
+                    <option name="source" value="mem_lib.sv" />
+                  </Body>
+                </list>
+              </option>
+            </Define>
+          </value>
+        </entry>
+        <entry key="EL2_RAM">
+          <value>
+            <Define>
+              <option name="definitions">
+                <list>
+                  <Body>
+                    <option name="offset" value="788" />
+                    <option name="parameters">
+                      <list>
+                        <Parameter>
+                          <option name="name" value="depth" />
+                        </Parameter>
+                        <Parameter>
+                          <option name="name" value="width" />
+                        </Parameter>
+                      </list>
+                    </option>
+                    <option name="replacementList" value="module ram_``depth``x``width(               &#10;   input logic [$clog2(depth)-1:0] ADR,     &#10;   input logic [(width-1):0] D,             &#10;   output logic [(width-1):0] Q,            &#10;    `EL2_LOCAL_RAM_TEST_IO                 &#10;);                                          &#10;reg [(width-1):0] ram_core [(depth-1):0];   &#10;                                            &#10;always @(posedge CLK) begin              &#10;   if (ME &amp;&amp; WE) ram_core[ADR] = D;        &#10;   if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR];       &#10;end                                         &#10;                                            &#10;endmodule" />
+                    <option name="source" value="mem_lib.sv" />
+                  </Body>
+                </list>
+              </option>
+            </Define>
+          </value>
+        </entry>
+        <entry key="EL2_RAM_BE">
+          <value>
+            <Define>
+              <option name="definitions">
+                <list>
+                  <Body>
+                    <option name="offset" value="1437" />
+                    <option name="parameters">
+                      <list>
+                        <Parameter>
+                          <option name="name" value="depth" />
+                        </Parameter>
+                        <Parameter>
+                          <option name="name" value="width" />
+                        </Parameter>
+                      </list>
+                    </option>
+                    <option name="replacementList" value="module ram_be_``depth``x``width(            &#10;   input logic [$clog2(depth)-1:0] ADR,     &#10;   input logic [(width-1):0] D, WEM,        &#10;   output logic [(width-1):0] Q,            &#10;    `EL2_LOCAL_RAM_TEST_IO                 &#10;);                                          &#10;reg [(width-1):0] ram_core [(depth-1):0];   &#10;                                            &#10;always @(posedge CLK) begin              &#10;   if (ME &amp;&amp; WE) ram_core[ADR] = D &amp; WEM | ~WEM &amp; ram_core[ADR];&#10;   if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR];       &#10;end                                         &#10;                                            &#10;                                            &#10;endmodule" />
+                    <option name="source" value="mem_lib.sv" />
+                  </Body>
+                </list>
+              </option>
+            </Define>
+          </value>
+        </entry>
         <entry key="RANDOM">
           <value>
             <Define>
@@ -84,6 +149,31 @@
                     <option name="replacementList" value="$random" />
                     <option name="source" value="el2_ifu_mem_ctl.v" />
                   </Body>
+                  <Body>
+                    <option name="offset" value="44499" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="dbg.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="9623" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="55649" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="dma_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="151383" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="198988" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="lsu_bus_buffer.v" />
+                  </Body>
                 </list>
               </option>
               <option name="dependencies">
@@ -98,6 +188,11 @@
                   <option value="el2_exu_alu_ctl.v" />
                   <option value="el2_lsu.v" />
                   <option value="el2_ifu_mem_ctl.v" />
+                  <option value="dbg.v" />
+                  <option value="lsu.v" />
+                  <option value="dma_ctrl.v" />
+                  <option value="pic_ctrl.v" />
+                  <option value="lsu_bus_buffer.v" />
                 </set>
               </option>
             </Define>
@@ -828,6 +923,246 @@
                     <option name="offset" value="411331" />
                     <option name="source" value="el2_ifu_mem_ctl.v" />
                   </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="44300" />
+                    <option name="source" value="dbg.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="44357" />
+                    <option name="source" value="dbg.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="44408" />
+                    <option name="source" value="dbg.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="44459" />
+                    <option name="source" value="dbg.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="9424" />
+                    <option name="source" value="lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="9481" />
+                    <option name="source" value="lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="9532" />
+                    <option name="source" value="lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="9583" />
+                    <option name="source" value="lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="55450" />
+                    <option name="source" value="dma_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="55507" />
+                    <option name="source" value="dma_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="55558" />
+                    <option name="source" value="dma_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="55609" />
+                    <option name="source" value="dma_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="151184" />
+                    <option name="source" value="pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="151241" />
+                    <option name="source" value="pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="151292" />
+                    <option name="source" value="pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="151343" />
+                    <option name="source" value="pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="198789" />
+                    <option name="source" value="lsu_bus_buffer.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="198846" />
+                    <option name="source" value="lsu_bus_buffer.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="198897" />
+                    <option name="source" value="lsu_bus_buffer.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="198948" />
+                    <option name="source" value="lsu_bus_buffer.v" />
+                  </Body>
                 </list>
               </option>
             </Define>
diff --git a/.idea/modules/chisel-module-template-build.iml b/.idea/modules/chisel-module-template-build.iml
index 0943f635..ef1baf81 100644
--- a/.idea/modules/chisel-module-template-build.iml
+++ b/.idea/modules/chisel-module-template-build.iml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
+<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, /home/abdulhameed.akram/.ivy2/cache|ivy|Local cache, https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, file:/home/abdulhameed.akram/.sbt/preloaded|maven|local-preloaded, https://repo1.maven.org/maven2/|maven|public" type="SBT_MODULE" version="4">
   <component name="NewModuleRootManager">
     <output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
     <output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />
diff --git a/.idea/modules/chisel-module-template.iml b/.idea/modules/chisel-module-template.iml
index 2a9bea34..003aa198 100644
--- a/.idea/modules/chisel-module-template.iml
+++ b/.idea/modules/chisel-module-template.iml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
+<module external.linked.project.id="quasar [file:/home/abdulhameed.akram/Music/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
   <component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
     <output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
     <output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f
index d4456bc6..40eae7ce 100644
--- a/firrtl_black_box_resource_files.f
+++ b/firrtl_black_box_resource_files.f
@@ -1 +1,3 @@
-/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
\ No newline at end of file
+/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
+/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
+/home/waleedbinehsan/Desktop/Quasar/mem.sv
\ No newline at end of file
diff --git a/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb$.class b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb$.class
new file mode 100644
index 00000000..a5b7fcc8
Binary files /dev/null and b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb$.class differ
diff --git a/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.cache b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.cache
@@ -0,0 +1 @@
+sbt.internal.DslEntry
\ No newline at end of file
diff --git a/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.class b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.class
new file mode 100644
index 00000000..24c8bdf6
Binary files /dev/null and b/project/project/target/config-classes/$4c86ca82ac1db5c0cbcb.class differ
diff --git a/project/target/config-classes/$2cafd43bf74a119abb04$.class b/project/target/config-classes/$2cafd43bf74a119abb04$.class
new file mode 100644
index 00000000..c498056c
Binary files /dev/null and b/project/target/config-classes/$2cafd43bf74a119abb04$.class differ
diff --git a/project/target/config-classes/$2cafd43bf74a119abb04.cache b/project/target/config-classes/$2cafd43bf74a119abb04.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/target/config-classes/$2cafd43bf74a119abb04.cache
@@ -0,0 +1 @@
+sbt.internal.DslEntry
\ No newline at end of file
diff --git a/project/target/config-classes/$2cafd43bf74a119abb04.class b/project/target/config-classes/$2cafd43bf74a119abb04.class
new file mode 100644
index 00000000..d06b169c
Binary files /dev/null and b/project/target/config-classes/$2cafd43bf74a119abb04.class differ
diff --git a/project/target/config-classes/$418b5ba19a4d2f79919d$.class b/project/target/config-classes/$418b5ba19a4d2f79919d$.class
new file mode 100644
index 00000000..2dd752ea
Binary files /dev/null and b/project/target/config-classes/$418b5ba19a4d2f79919d$.class differ
diff --git a/project/target/config-classes/$418b5ba19a4d2f79919d.cache b/project/target/config-classes/$418b5ba19a4d2f79919d.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/target/config-classes/$418b5ba19a4d2f79919d.cache
@@ -0,0 +1 @@
+sbt.internal.DslEntry
\ No newline at end of file
diff --git a/project/target/config-classes/$418b5ba19a4d2f79919d.class b/project/target/config-classes/$418b5ba19a4d2f79919d.class
new file mode 100644
index 00000000..37633caa
Binary files /dev/null and b/project/target/config-classes/$418b5ba19a4d2f79919d.class differ
diff --git a/project/target/config-classes/$6491f345f39de8f95c09$.class b/project/target/config-classes/$6491f345f39de8f95c09$.class
new file mode 100644
index 00000000..bb6cf9e6
Binary files /dev/null and b/project/target/config-classes/$6491f345f39de8f95c09$.class differ
diff --git a/project/target/config-classes/$6491f345f39de8f95c09.cache b/project/target/config-classes/$6491f345f39de8f95c09.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/target/config-classes/$6491f345f39de8f95c09.cache
@@ -0,0 +1 @@
+sbt.internal.DslEntry
\ No newline at end of file
diff --git a/project/target/config-classes/$6491f345f39de8f95c09.class b/project/target/config-classes/$6491f345f39de8f95c09.class
new file mode 100644
index 00000000..0003e8bb
Binary files /dev/null and b/project/target/config-classes/$6491f345f39de8f95c09.class differ
diff --git a/project/target/config-classes/$65f6b7c7a8627db9618c$.class b/project/target/config-classes/$65f6b7c7a8627db9618c$.class
new file mode 100644
index 00000000..131c91f3
Binary files /dev/null and b/project/target/config-classes/$65f6b7c7a8627db9618c$.class differ
diff --git a/project/target/config-classes/$65f6b7c7a8627db9618c.cache b/project/target/config-classes/$65f6b7c7a8627db9618c.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/target/config-classes/$65f6b7c7a8627db9618c.cache
@@ -0,0 +1 @@
+sbt.internal.DslEntry
\ No newline at end of file
diff --git a/project/target/config-classes/$65f6b7c7a8627db9618c.class b/project/target/config-classes/$65f6b7c7a8627db9618c.class
new file mode 100644
index 00000000..cb761a85
Binary files /dev/null and b/project/target/config-classes/$65f6b7c7a8627db9618c.class differ
diff --git a/project/target/config-classes/$6b90aa8a6aaf16c58492$.class b/project/target/config-classes/$6b90aa8a6aaf16c58492$.class
new file mode 100644
index 00000000..a6729b4a
Binary files /dev/null and b/project/target/config-classes/$6b90aa8a6aaf16c58492$.class differ
diff --git a/project/target/config-classes/$6b90aa8a6aaf16c58492.cache b/project/target/config-classes/$6b90aa8a6aaf16c58492.cache
new file mode 100644
index 00000000..050f36c6
--- /dev/null
+++ b/project/target/config-classes/$6b90aa8a6aaf16c58492.cache
@@ -0,0 +1 @@
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diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp
index 4d04d979..6cc9b2e0 100644
--- a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp
+++ b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp
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diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
index dba113a6..2d4cf3d8 100644
--- a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
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diff --git a/project/target/streams/_global/update/_global/streams/out b/project/target/streams/_global/update/_global/streams/out
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diff --git a/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous b/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous
index 2c776575..1b0853a2 100644
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\ No newline at end of file
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sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar",1586919578000],["/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar",1568150453000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar",1586919585000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar",1585597895000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar",1586919582000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar",1586919588000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar",1586919593000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar",1586919595000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar",1586919569000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar",1586919594000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar",1586919582000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar",1586919592000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar",1586919595000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar",1554476959000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar",1566946835000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar",1549415503000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar",1549415573000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar",1549415635000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar",1510153827000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar",1584360077000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar",1576119989000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar",1586906938000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar",1586906935000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar",1585527738000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar",1585527746000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar",1562617173000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar",1572453456000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar",1572453499000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar",1576119995000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar",1586919580000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar",1586919576000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar",1586919595000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.10/testing_2.12-1.3.10.jar",1586919585000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3.jar",1563056822000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3.jar",1576119981000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.5/zinc-classpath_2.12-1.3.5.jar",1585527746000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.5/zinc-apiinfo_2.12-1.3.5.jar",1585527734000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5.jar",1585527734000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.10/core-macros_2.12-1.3.10.jar",1586919602000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar",1576119990000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar",1576119992000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.10/protocol_2.12-1.3.10.jar",1586919599000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar",1563056819000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar",1471834035000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar",1576119996000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar",1576119985000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5.jar",1585527731000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar",1550531761000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar",1510153816000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar",1506124453000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar",1576119983000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar",1522055915000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar",1523227268000],["/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar",1568150359000],["/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar",1568150551000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar",1472895734000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar",1560903298000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar",1492307721000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5/ivy-2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5.jar",1582398156000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar",1551913597000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.10/test-agent-1.3.10.jar",1586919587000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar",1372459476000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar",1499894894000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar",1479009615000],["/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5.jar",1585527750000],["/home/abdulhameed.akra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\ No newline at end of file
diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous
index e2319964..67ff7765 100644
--- a/project/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/project/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/abdulhameed.akram/Music/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
\ No newline at end of file
diff --git a/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous
index cb0933f2..494eabf4 100644
--- a/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous
+++ b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous
@@ -1 +1 @@
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\ No newline at end of file
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\ No newline at end of file
diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out
index 6db8e09d..a24bed6f 100644
--- a/project/target/streams/compile/compileIncremental/_global/streams/out
+++ b/project/target/streams/compile/compileIncremental/_global/streams/out
@@ -1 +1 @@
-[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
+[debug] Full compilation, no sources in previous analysis.
diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out
index f25042f2..49995276 100644
--- a/project/target/streams/compile/copyResources/_global/streams/out
+++ b/project/target/streams/compile/copyResources/_global/streams/out
@@ -1,2 +1,2 @@
-[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
-[0m[[0m[0mdebug[0m] [0m[0m	[0m
+[debug] Copy resource mappings: 
+[debug] 	
diff --git a/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export
index 7a5c37b9..146a4675 100644
--- a/project/target/streams/compile/dependencyClasspath/_global/streams/export
+++ b/project/target/streams/compile/dependencyClasspath/_global/streams/export
@@ -1 +1 @@
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diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export
index 21b0f701..2bf29d14 100644
--- a/project/target/streams/compile/exportedProducts/_global/streams/export
+++ b/project/target/streams/compile/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
+/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export
index d4b92b6a..be6e24a8 100644
--- a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export
+++ b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
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diff --git a/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export
index d4b92b6a..be6e24a8 100644
--- a/project/target/streams/compile/managedClasspath/_global/streams/export
+++ b/project/target/streams/compile/managedClasspath/_global/streams/export
@@ -1 +1 @@
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1.3.5/zinc-apiinfo_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.10/core-macros_2.12-1.3.10.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.10/protocol_2.12-1.3.10.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5/ivy-2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.10/test-agent-1.3.10.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.5/zinc-classfile_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.5/zinc-core_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.5/zinc-persist_2.12-1.3.5.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.1/ipcsocket-1.0.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.5.0/gigahorse-core_2.12-0.5.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp/3.14.2/okhttp-3.14.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/scalapb/scalapb-runtime_2.12/0.6.0/scala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diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export
index bcc4f35b..d33aedff 100644
--- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export
+++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/abdulhameed.akram/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export
index 21b0f701..2bf29d14 100644
--- a/project/target/streams/runtime/exportedProducts/_global/streams/export
+++ b/project/target/streams/runtime/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
+/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export
index 94a89648..8b137891 100644
--- a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export
+++ b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+
diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export
index bcc4f35b..d33aedff 100644
--- a/project/target/streams/runtime/fullClasspath/_global/streams/export
+++ b/project/target/streams/runtime/fullClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/abdulhameed.akram/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
index 21b0f701..2bf29d14 100644
--- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
+++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes
+/home/abdulhameed.akram/Music/Quasar/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export
index 94a89648..8b137891 100644
--- a/project/target/streams/runtime/managedClasspath/_global/streams/export
+++ b/project/target/streams/runtime/managedClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+
diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir
index 622b991f..9ad3e7e0 100644
--- a/quasar_wrapper.fir
+++ b/quasar_wrapper.fir
@@ -64026,223 +64026,223 @@ circuit quasar_wrapper :
     input reset : AsyncReset
     output io : {flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip free_clk : Clock, flip active_clk : Clock, ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, exu_ifu : {flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, ifu : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, iccm_dma_sb_error : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst mem_ctl of ifu_mem_ctl @[ifu.scala 36:23]
+    inst mem_ctl of ifu_mem_ctl @[ifu.scala 34:23]
     mem_ctl.clock <= clock
     mem_ctl.reset <= reset
-    inst bp_ctl of ifu_bp_ctl @[ifu.scala 37:22]
+    inst bp_ctl of ifu_bp_ctl @[ifu.scala 35:22]
     bp_ctl.clock <= clock
     bp_ctl.reset <= reset
-    inst aln_ctl of ifu_aln_ctl @[ifu.scala 38:23]
+    inst aln_ctl of ifu_aln_ctl @[ifu.scala 36:23]
     aln_ctl.clock <= clock
     aln_ctl.reset <= reset
-    inst ifc_ctl of ifu_ifc_ctl @[ifu.scala 39:23]
+    inst ifc_ctl of ifu_ifc_ctl @[ifu.scala 37:23]
     ifc_ctl.clock <= clock
     ifc_ctl.reset <= reset
-    ifc_ctl.io.active_clk <= io.active_clk @[ifu.scala 42:25]
-    ifc_ctl.io.free_clk <= io.free_clk @[ifu.scala 43:23]
-    ifc_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 44:24]
-    ifc_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 45:23]
-    ifc_ctl.io.ifu_fb_consume1 <= aln_ctl.io.ifu_fb_consume1 @[ifu.scala 46:30]
-    ifc_ctl.io.ifu_fb_consume2 <= aln_ctl.io.ifu_fb_consume2 @[ifu.scala 47:30]
-    io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifc_ctl.io.dec_ifc.ifu_pmu_fetch_stall @[ifu.scala 48:22]
-    ifc_ctl.io.dec_ifc.dec_tlu_mrac_ff <= io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[ifu.scala 48:22]
-    ifc_ctl.io.dec_ifc.dec_tlu_flush_noredir_wb <= io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[ifu.scala 48:22]
-    ifc_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 49:30]
-    ifc_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 50:33]
-    ifc_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 51:34]
-    ifc_ctl.io.ic_dma_active <= mem_ctl.io.ic_dma_active @[ifu.scala 52:28]
-    ifc_ctl.io.ic_write_stall <= mem_ctl.io.ic_write_stall @[ifu.scala 53:29]
-    ifc_ctl.io.dma_ifc.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[ifu.scala 54:22]
-    ifc_ctl.io.ifu_ic_mb_empty <= mem_ctl.io.ifu_ic_mb_empty @[ifu.scala 55:30]
-    ifc_ctl.io.exu_flush_path_final <= io.exu_flush_path_final @[ifu.scala 56:35]
-    aln_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 59:24]
-    aln_ctl.io.active_clk <= io.active_clk @[ifu.scala 60:25]
-    aln_ctl.io.ifu_async_error_start <= mem_ctl.io.ifu_async_error_start @[ifu.scala 61:36]
-    aln_ctl.io.iccm_rd_ecc_double_err <= mem_ctl.io.iccm_rd_ecc_double_err @[ifu.scala 62:37]
-    aln_ctl.io.ic_access_fault_f <= mem_ctl.io.ic_access_fault_f @[ifu.scala 63:32]
-    aln_ctl.io.ic_access_fault_type_f <= mem_ctl.io.ic_access_fault_type_f @[ifu.scala 64:37]
-    aln_ctl.io.ifu_bp_fghr_f <= bp_ctl.io.ifu_bp_fghr_f @[ifu.scala 65:28]
-    aln_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 66:34]
-    aln_ctl.io.ifu_bp_poffset_f <= bp_ctl.io.ifu_bp_poffset_f @[ifu.scala 67:31]
-    aln_ctl.io.ifu_bp_hist0_f <= bp_ctl.io.ifu_bp_hist0_f @[ifu.scala 68:29]
-    aln_ctl.io.ifu_bp_hist1_f <= bp_ctl.io.ifu_bp_hist1_f @[ifu.scala 69:29]
-    aln_ctl.io.ifu_bp_pc4_f <= bp_ctl.io.ifu_bp_pc4_f @[ifu.scala 70:27]
-    aln_ctl.io.ifu_bp_way_f <= bp_ctl.io.ifu_bp_way_f @[ifu.scala 71:27]
-    aln_ctl.io.ifu_bp_valid_f <= bp_ctl.io.ifu_bp_valid_f @[ifu.scala 72:29]
-    aln_ctl.io.ifu_bp_ret_f <= bp_ctl.io.ifu_bp_ret_f @[ifu.scala 73:27]
-    aln_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 74:30]
-    io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= aln_ctl.io.dec_aln.ifu_pmu_instr_aligned @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.ret @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.way @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.prett @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.bank @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_start_error @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_error @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.hist @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.toffset @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= aln_ctl.io.dec_aln.aln_ib.i0_brp.valid @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc4 @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_instr @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_valid @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_btag @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_fghr @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_index @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_dbecc @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_f1 @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_type @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf @[ifu.scala 75:22]
-    io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= aln_ctl.io.dec_aln.aln_dec.ifu_i0_cinst @[ifu.scala 75:22]
-    aln_ctl.io.dec_aln.aln_dec.dec_i0_decode_d <= io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[ifu.scala 75:22]
-    aln_ctl.io.ifu_fetch_data_f <= mem_ctl.io.ic_data_f @[ifu.scala 76:31]
-    aln_ctl.io.ifu_fetch_val <= mem_ctl.io.ifu_fetch_val @[ifu.scala 77:28]
-    aln_ctl.io.ifu_fetch_pc <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 78:27]
-    bp_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 81:23]
-    bp_ctl.io.active_clk <= io.active_clk @[ifu.scala 82:24]
-    bp_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 83:22]
-    bp_ctl.io.ifc_fetch_addr_f <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 84:30]
-    bp_ctl.io.ifc_fetch_req_f <= ifc_ctl.io.ifc_fetch_req_f @[ifu.scala 85:29]
-    bp_ctl.io.dec_bp.dec_tlu_bpred_disable <= io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_flush_leak_one_wb <= io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.way <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[ifu.scala 86:20]
-    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.valid <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[ifu.scala 86:20]
-    bp_ctl.io.exu_bp.exu_mp_btag <= io.exu_ifu.exu_bp.exu_mp_btag @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_index <= io.exu_ifu.exu_bp.exu_mp_index @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_fghr <= io.exu_ifu.exu_bp.exu_mp_fghr @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_eghr <= io.exu_ifu.exu_bp.exu_mp_eghr @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.way <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.way @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pja <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pret <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pcall <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.prett <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_start_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.toffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.hist <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pc4 <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.boffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.ataken <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.bits.misp <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_mp_pkt.valid <= io.exu_ifu.exu_bp.exu_mp_pkt.valid @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_i0_br_way_r <= io.exu_ifu.exu_bp.exu_i0_br_way_r @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_i0_br_fghr_r <= io.exu_ifu.exu_bp.exu_i0_br_fghr_r @[ifu.scala 87:20]
-    bp_ctl.io.exu_bp.exu_i0_br_index_r <= io.exu_ifu.exu_bp.exu_i0_br_index_r @[ifu.scala 87:20]
-    bp_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 88:29]
-    bp_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 89:36]
-    mem_ctl.io.free_clk <= io.free_clk @[ifu.scala 91:23]
-    mem_ctl.io.active_clk <= io.active_clk @[ifu.scala 92:25]
-    mem_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 93:30]
-    io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= mem_ctl.io.dec_mem_ctrl.ifu_miss_state_idle @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= mem_ctl.io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= mem_ctl.io.dec_mem_ctrl.ifu_ic_error_start @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_trxn @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_busy @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_error @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_hit @[ifu.scala 94:27]
-    io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_miss @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_core_ecc_disable <= io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_fence_i_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_force_halt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[ifu.scala 94:27]
-    mem_ctl.io.dec_mem_ctrl.dec_tlu_flush_err_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[ifu.scala 94:27]
-    mem_ctl.io.ifc_fetch_addr_bf <= ifc_ctl.io.ifc_fetch_addr_bf @[ifu.scala 95:32]
-    mem_ctl.io.ifc_fetch_uncacheable_bf <= ifc_ctl.io.ifc_fetch_uncacheable_bf @[ifu.scala 96:39]
-    mem_ctl.io.ifc_fetch_req_bf <= ifc_ctl.io.ifc_fetch_req_bf @[ifu.scala 97:31]
-    mem_ctl.io.ifc_fetch_req_bf_raw <= ifc_ctl.io.ifc_fetch_req_bf_raw @[ifu.scala 98:35]
-    mem_ctl.io.ifc_iccm_access_bf <= ifc_ctl.io.ifc_iccm_access_bf @[ifu.scala 99:33]
-    mem_ctl.io.ifc_region_acc_fault_bf <= ifc_ctl.io.ifc_region_acc_fault_bf @[ifu.scala 100:38]
-    mem_ctl.io.ifc_dma_access_ok <= ifc_ctl.io.ifc_dma_access_ok @[ifu.scala 101:32]
-    mem_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 102:33]
-    mem_ctl.io.ifu_bp_inst_mask_f <= bp_ctl.io.ifu_bp_inst_mask_f @[ifu.scala 103:33]
-    mem_ctl.io.ifu_axi.r.bits.last <= io.ifu.r.bits.last @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.r.bits.resp <= io.ifu.r.bits.resp @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.r.bits.data <= io.ifu.r.bits.data @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.r.bits.id <= io.ifu.r.bits.id @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.r.valid <= io.ifu.r.valid @[ifu.scala 104:22]
-    io.ifu.r.ready <= mem_ctl.io.ifu_axi.r.ready @[ifu.scala 104:22]
-    io.ifu.ar.bits.qos <= mem_ctl.io.ifu_axi.ar.bits.qos @[ifu.scala 104:22]
-    io.ifu.ar.bits.prot <= mem_ctl.io.ifu_axi.ar.bits.prot @[ifu.scala 104:22]
-    io.ifu.ar.bits.cache <= mem_ctl.io.ifu_axi.ar.bits.cache @[ifu.scala 104:22]
-    io.ifu.ar.bits.lock <= mem_ctl.io.ifu_axi.ar.bits.lock @[ifu.scala 104:22]
-    io.ifu.ar.bits.burst <= mem_ctl.io.ifu_axi.ar.bits.burst @[ifu.scala 104:22]
-    io.ifu.ar.bits.size <= mem_ctl.io.ifu_axi.ar.bits.size @[ifu.scala 104:22]
-    io.ifu.ar.bits.len <= mem_ctl.io.ifu_axi.ar.bits.len @[ifu.scala 104:22]
-    io.ifu.ar.bits.region <= mem_ctl.io.ifu_axi.ar.bits.region @[ifu.scala 104:22]
-    io.ifu.ar.bits.addr <= mem_ctl.io.ifu_axi.ar.bits.addr @[ifu.scala 104:22]
-    io.ifu.ar.bits.id <= mem_ctl.io.ifu_axi.ar.bits.id @[ifu.scala 104:22]
-    io.ifu.ar.valid <= mem_ctl.io.ifu_axi.ar.valid @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.ar.ready <= io.ifu.ar.ready @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.b.bits.id <= io.ifu.b.bits.id @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.b.bits.resp <= io.ifu.b.bits.resp @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.b.valid <= io.ifu.b.valid @[ifu.scala 104:22]
-    io.ifu.b.ready <= mem_ctl.io.ifu_axi.b.ready @[ifu.scala 104:22]
-    io.ifu.w.bits.last <= mem_ctl.io.ifu_axi.w.bits.last @[ifu.scala 104:22]
-    io.ifu.w.bits.strb <= mem_ctl.io.ifu_axi.w.bits.strb @[ifu.scala 104:22]
-    io.ifu.w.bits.data <= mem_ctl.io.ifu_axi.w.bits.data @[ifu.scala 104:22]
-    io.ifu.w.valid <= mem_ctl.io.ifu_axi.w.valid @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.w.ready <= io.ifu.w.ready @[ifu.scala 104:22]
-    io.ifu.aw.bits.qos <= mem_ctl.io.ifu_axi.aw.bits.qos @[ifu.scala 104:22]
-    io.ifu.aw.bits.prot <= mem_ctl.io.ifu_axi.aw.bits.prot @[ifu.scala 104:22]
-    io.ifu.aw.bits.cache <= mem_ctl.io.ifu_axi.aw.bits.cache @[ifu.scala 104:22]
-    io.ifu.aw.bits.lock <= mem_ctl.io.ifu_axi.aw.bits.lock @[ifu.scala 104:22]
-    io.ifu.aw.bits.burst <= mem_ctl.io.ifu_axi.aw.bits.burst @[ifu.scala 104:22]
-    io.ifu.aw.bits.size <= mem_ctl.io.ifu_axi.aw.bits.size @[ifu.scala 104:22]
-    io.ifu.aw.bits.len <= mem_ctl.io.ifu_axi.aw.bits.len @[ifu.scala 104:22]
-    io.ifu.aw.bits.region <= mem_ctl.io.ifu_axi.aw.bits.region @[ifu.scala 104:22]
-    io.ifu.aw.bits.addr <= mem_ctl.io.ifu_axi.aw.bits.addr @[ifu.scala 104:22]
-    io.ifu.aw.bits.id <= mem_ctl.io.ifu_axi.aw.bits.id @[ifu.scala 104:22]
-    io.ifu.aw.valid <= mem_ctl.io.ifu_axi.aw.valid @[ifu.scala 104:22]
-    mem_ctl.io.ifu_axi.aw.ready <= io.ifu.aw.ready @[ifu.scala 104:22]
-    mem_ctl.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu.scala 105:29]
-    mem_ctl.io.dma_mem_ctl.dma_mem_tag <= io.ifu_dma.dma_mem_ctl.dma_mem_tag @[ifu.scala 106:26]
-    mem_ctl.io.dma_mem_ctl.dma_mem_wdata <= io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[ifu.scala 106:26]
-    mem_ctl.io.dma_mem_ctl.dma_mem_write <= io.ifu_dma.dma_mem_ctl.dma_mem_write @[ifu.scala 106:26]
-    mem_ctl.io.dma_mem_ctl.dma_mem_sz <= io.ifu_dma.dma_mem_ctl.dma_mem_sz @[ifu.scala 106:26]
-    mem_ctl.io.dma_mem_ctl.dma_mem_addr <= io.ifu_dma.dma_mem_ctl.dma_mem_addr @[ifu.scala 106:26]
-    mem_ctl.io.dma_mem_ctl.dma_iccm_req <= io.ifu_dma.dma_mem_ctl.dma_iccm_req @[ifu.scala 106:26]
-    io.ic.sel_premux_data <= mem_ctl.io.ic.sel_premux_data @[ifu.scala 107:17]
-    io.ic.premux_data <= mem_ctl.io.ic.premux_data @[ifu.scala 107:17]
-    io.ic.debug_way <= mem_ctl.io.ic.debug_way @[ifu.scala 107:17]
-    io.ic.debug_tag_array <= mem_ctl.io.ic.debug_tag_array @[ifu.scala 107:17]
-    io.ic.debug_wr_en <= mem_ctl.io.ic.debug_wr_en @[ifu.scala 107:17]
-    io.ic.debug_rd_en <= mem_ctl.io.ic.debug_rd_en @[ifu.scala 107:17]
-    mem_ctl.io.ic.tag_perr <= io.ic.tag_perr @[ifu.scala 107:17]
-    mem_ctl.io.ic.rd_hit <= io.ic.rd_hit @[ifu.scala 107:17]
-    mem_ctl.io.ic.parerr <= io.ic.parerr @[ifu.scala 107:17]
-    mem_ctl.io.ic.eccerr <= io.ic.eccerr @[ifu.scala 107:17]
-    mem_ctl.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[ifu.scala 107:17]
-    mem_ctl.io.ic.debug_rd_data <= io.ic.debug_rd_data @[ifu.scala 107:17]
-    mem_ctl.io.ic.rd_data <= io.ic.rd_data @[ifu.scala 107:17]
-    io.ic.debug_addr <= mem_ctl.io.ic.debug_addr @[ifu.scala 107:17]
-    io.ic.debug_wr_data <= mem_ctl.io.ic.debug_wr_data @[ifu.scala 107:17]
-    io.ic.wr_data[0] <= mem_ctl.io.ic.wr_data[0] @[ifu.scala 107:17]
-    io.ic.wr_data[1] <= mem_ctl.io.ic.wr_data[1] @[ifu.scala 107:17]
-    io.ic.rd_en <= mem_ctl.io.ic.rd_en @[ifu.scala 107:17]
-    io.ic.wr_en <= mem_ctl.io.ic.wr_en @[ifu.scala 107:17]
-    io.ic.tag_valid <= mem_ctl.io.ic.tag_valid @[ifu.scala 107:17]
-    io.ic.rw_addr <= mem_ctl.io.ic.rw_addr @[ifu.scala 107:17]
-    mem_ctl.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[ifu.scala 108:19]
-    mem_ctl.io.iccm.rd_data <= io.iccm.rd_data @[ifu.scala 108:19]
-    io.iccm.wr_data <= mem_ctl.io.iccm.wr_data @[ifu.scala 108:19]
-    io.iccm.wr_size <= mem_ctl.io.iccm.wr_size @[ifu.scala 108:19]
-    io.iccm.rden <= mem_ctl.io.iccm.rden @[ifu.scala 108:19]
-    io.iccm.wren <= mem_ctl.io.iccm.wren @[ifu.scala 108:19]
-    io.iccm.correction_state <= mem_ctl.io.iccm.correction_state @[ifu.scala 108:19]
-    io.iccm.buf_correct_ecc <= mem_ctl.io.iccm.buf_correct_ecc @[ifu.scala 108:19]
-    io.iccm.rw_addr <= mem_ctl.io.iccm.rw_addr @[ifu.scala 108:19]
-    mem_ctl.io.ifu_fetch_val <= mem_ctl.io.ic_fetch_val_f @[ifu.scala 109:28]
-    mem_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 110:37]
-    mem_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 111:24]
+    ifc_ctl.io.active_clk <= io.active_clk @[ifu.scala 40:25]
+    ifc_ctl.io.free_clk <= io.free_clk @[ifu.scala 41:23]
+    ifc_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 42:24]
+    ifc_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 43:23]
+    ifc_ctl.io.ifu_fb_consume1 <= aln_ctl.io.ifu_fb_consume1 @[ifu.scala 44:30]
+    ifc_ctl.io.ifu_fb_consume2 <= aln_ctl.io.ifu_fb_consume2 @[ifu.scala 45:30]
+    io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifc_ctl.io.dec_ifc.ifu_pmu_fetch_stall @[ifu.scala 46:22]
+    ifc_ctl.io.dec_ifc.dec_tlu_mrac_ff <= io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[ifu.scala 46:22]
+    ifc_ctl.io.dec_ifc.dec_tlu_flush_noredir_wb <= io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[ifu.scala 46:22]
+    ifc_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 47:30]
+    ifc_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 48:33]
+    ifc_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 49:34]
+    ifc_ctl.io.ic_dma_active <= mem_ctl.io.ic_dma_active @[ifu.scala 50:28]
+    ifc_ctl.io.ic_write_stall <= mem_ctl.io.ic_write_stall @[ifu.scala 51:29]
+    ifc_ctl.io.dma_ifc.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[ifu.scala 52:22]
+    ifc_ctl.io.ifu_ic_mb_empty <= mem_ctl.io.ifu_ic_mb_empty @[ifu.scala 53:30]
+    ifc_ctl.io.exu_flush_path_final <= io.exu_flush_path_final @[ifu.scala 54:35]
+    aln_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 57:24]
+    aln_ctl.io.active_clk <= io.active_clk @[ifu.scala 58:25]
+    aln_ctl.io.ifu_async_error_start <= mem_ctl.io.ifu_async_error_start @[ifu.scala 59:36]
+    aln_ctl.io.iccm_rd_ecc_double_err <= mem_ctl.io.iccm_rd_ecc_double_err @[ifu.scala 60:37]
+    aln_ctl.io.ic_access_fault_f <= mem_ctl.io.ic_access_fault_f @[ifu.scala 61:32]
+    aln_ctl.io.ic_access_fault_type_f <= mem_ctl.io.ic_access_fault_type_f @[ifu.scala 62:37]
+    aln_ctl.io.ifu_bp_fghr_f <= bp_ctl.io.ifu_bp_fghr_f @[ifu.scala 63:28]
+    aln_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 64:34]
+    aln_ctl.io.ifu_bp_poffset_f <= bp_ctl.io.ifu_bp_poffset_f @[ifu.scala 65:31]
+    aln_ctl.io.ifu_bp_hist0_f <= bp_ctl.io.ifu_bp_hist0_f @[ifu.scala 66:29]
+    aln_ctl.io.ifu_bp_hist1_f <= bp_ctl.io.ifu_bp_hist1_f @[ifu.scala 67:29]
+    aln_ctl.io.ifu_bp_pc4_f <= bp_ctl.io.ifu_bp_pc4_f @[ifu.scala 68:27]
+    aln_ctl.io.ifu_bp_way_f <= bp_ctl.io.ifu_bp_way_f @[ifu.scala 69:27]
+    aln_ctl.io.ifu_bp_valid_f <= bp_ctl.io.ifu_bp_valid_f @[ifu.scala 70:29]
+    aln_ctl.io.ifu_bp_ret_f <= bp_ctl.io.ifu_bp_ret_f @[ifu.scala 71:27]
+    aln_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 72:30]
+    io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= aln_ctl.io.dec_aln.ifu_pmu_instr_aligned @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.ret @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.way @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.prett @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.bank @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_start_error @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_error @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.hist @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.toffset @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= aln_ctl.io.dec_aln.aln_ib.i0_brp.valid @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc4 @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_instr @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_valid @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_btag @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_fghr @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_index @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_dbecc @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_f1 @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_type @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf @[ifu.scala 73:22]
+    io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= aln_ctl.io.dec_aln.aln_dec.ifu_i0_cinst @[ifu.scala 73:22]
+    aln_ctl.io.dec_aln.aln_dec.dec_i0_decode_d <= io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[ifu.scala 73:22]
+    aln_ctl.io.ifu_fetch_data_f <= mem_ctl.io.ic_data_f @[ifu.scala 74:31]
+    aln_ctl.io.ifu_fetch_val <= mem_ctl.io.ifu_fetch_val @[ifu.scala 75:28]
+    aln_ctl.io.ifu_fetch_pc <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 76:27]
+    bp_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 79:23]
+    bp_ctl.io.active_clk <= io.active_clk @[ifu.scala 80:24]
+    bp_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 81:22]
+    bp_ctl.io.ifc_fetch_addr_f <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 82:30]
+    bp_ctl.io.ifc_fetch_req_f <= ifc_ctl.io.ifc_fetch_req_f @[ifu.scala 83:29]
+    bp_ctl.io.dec_bp.dec_tlu_bpred_disable <= io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_flush_leak_one_wb <= io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.way <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[ifu.scala 84:20]
+    bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.valid <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[ifu.scala 84:20]
+    bp_ctl.io.exu_bp.exu_mp_btag <= io.exu_ifu.exu_bp.exu_mp_btag @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_index <= io.exu_ifu.exu_bp.exu_mp_index @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_fghr <= io.exu_ifu.exu_bp.exu_mp_fghr @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_eghr <= io.exu_ifu.exu_bp.exu_mp_eghr @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.way <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.way @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pja <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pret <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pcall <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.prett <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_start_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.toffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.hist <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.pc4 <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.boffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.ataken <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.bits.misp <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_mp_pkt.valid <= io.exu_ifu.exu_bp.exu_mp_pkt.valid @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_i0_br_way_r <= io.exu_ifu.exu_bp.exu_i0_br_way_r @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_i0_br_fghr_r <= io.exu_ifu.exu_bp.exu_i0_br_fghr_r @[ifu.scala 85:20]
+    bp_ctl.io.exu_bp.exu_i0_br_index_r <= io.exu_ifu.exu_bp.exu_i0_br_index_r @[ifu.scala 85:20]
+    bp_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 86:29]
+    bp_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 87:36]
+    mem_ctl.io.free_clk <= io.free_clk @[ifu.scala 90:23]
+    mem_ctl.io.active_clk <= io.active_clk @[ifu.scala 91:25]
+    mem_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 92:30]
+    io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= mem_ctl.io.dec_mem_ctrl.ifu_miss_state_idle @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= mem_ctl.io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= mem_ctl.io.dec_mem_ctrl.ifu_ic_error_start @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_trxn @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_busy @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_error @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_hit @[ifu.scala 93:27]
+    io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_miss @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_core_ecc_disable <= io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_fence_i_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_force_halt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[ifu.scala 93:27]
+    mem_ctl.io.dec_mem_ctrl.dec_tlu_flush_err_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[ifu.scala 93:27]
+    mem_ctl.io.ifc_fetch_addr_bf <= ifc_ctl.io.ifc_fetch_addr_bf @[ifu.scala 94:32]
+    mem_ctl.io.ifc_fetch_uncacheable_bf <= ifc_ctl.io.ifc_fetch_uncacheable_bf @[ifu.scala 95:39]
+    mem_ctl.io.ifc_fetch_req_bf <= ifc_ctl.io.ifc_fetch_req_bf @[ifu.scala 96:31]
+    mem_ctl.io.ifc_fetch_req_bf_raw <= ifc_ctl.io.ifc_fetch_req_bf_raw @[ifu.scala 97:35]
+    mem_ctl.io.ifc_iccm_access_bf <= ifc_ctl.io.ifc_iccm_access_bf @[ifu.scala 98:33]
+    mem_ctl.io.ifc_region_acc_fault_bf <= ifc_ctl.io.ifc_region_acc_fault_bf @[ifu.scala 99:38]
+    mem_ctl.io.ifc_dma_access_ok <= ifc_ctl.io.ifc_dma_access_ok @[ifu.scala 100:32]
+    mem_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 101:33]
+    mem_ctl.io.ifu_bp_inst_mask_f <= bp_ctl.io.ifu_bp_inst_mask_f @[ifu.scala 102:33]
+    mem_ctl.io.ifu_axi.r.bits.last <= io.ifu.r.bits.last @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.r.bits.resp <= io.ifu.r.bits.resp @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.r.bits.data <= io.ifu.r.bits.data @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.r.bits.id <= io.ifu.r.bits.id @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.r.valid <= io.ifu.r.valid @[ifu.scala 103:22]
+    io.ifu.r.ready <= mem_ctl.io.ifu_axi.r.ready @[ifu.scala 103:22]
+    io.ifu.ar.bits.qos <= mem_ctl.io.ifu_axi.ar.bits.qos @[ifu.scala 103:22]
+    io.ifu.ar.bits.prot <= mem_ctl.io.ifu_axi.ar.bits.prot @[ifu.scala 103:22]
+    io.ifu.ar.bits.cache <= mem_ctl.io.ifu_axi.ar.bits.cache @[ifu.scala 103:22]
+    io.ifu.ar.bits.lock <= mem_ctl.io.ifu_axi.ar.bits.lock @[ifu.scala 103:22]
+    io.ifu.ar.bits.burst <= mem_ctl.io.ifu_axi.ar.bits.burst @[ifu.scala 103:22]
+    io.ifu.ar.bits.size <= mem_ctl.io.ifu_axi.ar.bits.size @[ifu.scala 103:22]
+    io.ifu.ar.bits.len <= mem_ctl.io.ifu_axi.ar.bits.len @[ifu.scala 103:22]
+    io.ifu.ar.bits.region <= mem_ctl.io.ifu_axi.ar.bits.region @[ifu.scala 103:22]
+    io.ifu.ar.bits.addr <= mem_ctl.io.ifu_axi.ar.bits.addr @[ifu.scala 103:22]
+    io.ifu.ar.bits.id <= mem_ctl.io.ifu_axi.ar.bits.id @[ifu.scala 103:22]
+    io.ifu.ar.valid <= mem_ctl.io.ifu_axi.ar.valid @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.ar.ready <= io.ifu.ar.ready @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.b.bits.id <= io.ifu.b.bits.id @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.b.bits.resp <= io.ifu.b.bits.resp @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.b.valid <= io.ifu.b.valid @[ifu.scala 103:22]
+    io.ifu.b.ready <= mem_ctl.io.ifu_axi.b.ready @[ifu.scala 103:22]
+    io.ifu.w.bits.last <= mem_ctl.io.ifu_axi.w.bits.last @[ifu.scala 103:22]
+    io.ifu.w.bits.strb <= mem_ctl.io.ifu_axi.w.bits.strb @[ifu.scala 103:22]
+    io.ifu.w.bits.data <= mem_ctl.io.ifu_axi.w.bits.data @[ifu.scala 103:22]
+    io.ifu.w.valid <= mem_ctl.io.ifu_axi.w.valid @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.w.ready <= io.ifu.w.ready @[ifu.scala 103:22]
+    io.ifu.aw.bits.qos <= mem_ctl.io.ifu_axi.aw.bits.qos @[ifu.scala 103:22]
+    io.ifu.aw.bits.prot <= mem_ctl.io.ifu_axi.aw.bits.prot @[ifu.scala 103:22]
+    io.ifu.aw.bits.cache <= mem_ctl.io.ifu_axi.aw.bits.cache @[ifu.scala 103:22]
+    io.ifu.aw.bits.lock <= mem_ctl.io.ifu_axi.aw.bits.lock @[ifu.scala 103:22]
+    io.ifu.aw.bits.burst <= mem_ctl.io.ifu_axi.aw.bits.burst @[ifu.scala 103:22]
+    io.ifu.aw.bits.size <= mem_ctl.io.ifu_axi.aw.bits.size @[ifu.scala 103:22]
+    io.ifu.aw.bits.len <= mem_ctl.io.ifu_axi.aw.bits.len @[ifu.scala 103:22]
+    io.ifu.aw.bits.region <= mem_ctl.io.ifu_axi.aw.bits.region @[ifu.scala 103:22]
+    io.ifu.aw.bits.addr <= mem_ctl.io.ifu_axi.aw.bits.addr @[ifu.scala 103:22]
+    io.ifu.aw.bits.id <= mem_ctl.io.ifu_axi.aw.bits.id @[ifu.scala 103:22]
+    io.ifu.aw.valid <= mem_ctl.io.ifu_axi.aw.valid @[ifu.scala 103:22]
+    mem_ctl.io.ifu_axi.aw.ready <= io.ifu.aw.ready @[ifu.scala 103:22]
+    mem_ctl.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu.scala 104:29]
+    mem_ctl.io.dma_mem_ctl.dma_mem_tag <= io.ifu_dma.dma_mem_ctl.dma_mem_tag @[ifu.scala 105:26]
+    mem_ctl.io.dma_mem_ctl.dma_mem_wdata <= io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[ifu.scala 105:26]
+    mem_ctl.io.dma_mem_ctl.dma_mem_write <= io.ifu_dma.dma_mem_ctl.dma_mem_write @[ifu.scala 105:26]
+    mem_ctl.io.dma_mem_ctl.dma_mem_sz <= io.ifu_dma.dma_mem_ctl.dma_mem_sz @[ifu.scala 105:26]
+    mem_ctl.io.dma_mem_ctl.dma_mem_addr <= io.ifu_dma.dma_mem_ctl.dma_mem_addr @[ifu.scala 105:26]
+    mem_ctl.io.dma_mem_ctl.dma_iccm_req <= io.ifu_dma.dma_mem_ctl.dma_iccm_req @[ifu.scala 105:26]
+    io.ic.sel_premux_data <= mem_ctl.io.ic.sel_premux_data @[ifu.scala 106:17]
+    io.ic.premux_data <= mem_ctl.io.ic.premux_data @[ifu.scala 106:17]
+    io.ic.debug_way <= mem_ctl.io.ic.debug_way @[ifu.scala 106:17]
+    io.ic.debug_tag_array <= mem_ctl.io.ic.debug_tag_array @[ifu.scala 106:17]
+    io.ic.debug_wr_en <= mem_ctl.io.ic.debug_wr_en @[ifu.scala 106:17]
+    io.ic.debug_rd_en <= mem_ctl.io.ic.debug_rd_en @[ifu.scala 106:17]
+    mem_ctl.io.ic.tag_perr <= io.ic.tag_perr @[ifu.scala 106:17]
+    mem_ctl.io.ic.rd_hit <= io.ic.rd_hit @[ifu.scala 106:17]
+    mem_ctl.io.ic.parerr <= io.ic.parerr @[ifu.scala 106:17]
+    mem_ctl.io.ic.eccerr <= io.ic.eccerr @[ifu.scala 106:17]
+    mem_ctl.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[ifu.scala 106:17]
+    mem_ctl.io.ic.debug_rd_data <= io.ic.debug_rd_data @[ifu.scala 106:17]
+    mem_ctl.io.ic.rd_data <= io.ic.rd_data @[ifu.scala 106:17]
+    io.ic.debug_addr <= mem_ctl.io.ic.debug_addr @[ifu.scala 106:17]
+    io.ic.debug_wr_data <= mem_ctl.io.ic.debug_wr_data @[ifu.scala 106:17]
+    io.ic.wr_data[0] <= mem_ctl.io.ic.wr_data[0] @[ifu.scala 106:17]
+    io.ic.wr_data[1] <= mem_ctl.io.ic.wr_data[1] @[ifu.scala 106:17]
+    io.ic.rd_en <= mem_ctl.io.ic.rd_en @[ifu.scala 106:17]
+    io.ic.wr_en <= mem_ctl.io.ic.wr_en @[ifu.scala 106:17]
+    io.ic.tag_valid <= mem_ctl.io.ic.tag_valid @[ifu.scala 106:17]
+    io.ic.rw_addr <= mem_ctl.io.ic.rw_addr @[ifu.scala 106:17]
+    mem_ctl.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[ifu.scala 107:19]
+    mem_ctl.io.iccm.rd_data <= io.iccm.rd_data @[ifu.scala 107:19]
+    io.iccm.wr_data <= mem_ctl.io.iccm.wr_data @[ifu.scala 107:19]
+    io.iccm.wr_size <= mem_ctl.io.iccm.wr_size @[ifu.scala 107:19]
+    io.iccm.rden <= mem_ctl.io.iccm.rden @[ifu.scala 107:19]
+    io.iccm.wren <= mem_ctl.io.iccm.wren @[ifu.scala 107:19]
+    io.iccm.correction_state <= mem_ctl.io.iccm.correction_state @[ifu.scala 107:19]
+    io.iccm.buf_correct_ecc <= mem_ctl.io.iccm.buf_correct_ecc @[ifu.scala 107:19]
+    io.iccm.rw_addr <= mem_ctl.io.iccm.rw_addr @[ifu.scala 107:19]
+    mem_ctl.io.ifu_fetch_val <= mem_ctl.io.ic_fetch_val_f @[ifu.scala 108:28]
+    mem_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 109:37]
+    mem_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 110:24]
     io.iccm_dma_ecc_error <= mem_ctl.io.iccm_dma_ecc_error @[ifu.scala 113:25]
     io.iccm_dma_rvalid <= mem_ctl.io.iccm_dma_rvalid @[ifu.scala 114:22]
     io.iccm_dma_rdata <= mem_ctl.io.iccm_dma_rdata @[ifu.scala 115:21]
@@ -66826,81 +66826,81 @@ circuit quasar_wrapper :
   module dec_decode_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}
+    output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
     
-    wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38]
-    _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38]
-    io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 97:23]
-    io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 97:23]
+    wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 95:40]
+    _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40]
+    io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 95:25]
+    io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 95:25]
     wire leak1_i1_stall_in : UInt<1>
     leak1_i1_stall_in <= UInt<1>("h00")
     wire leak1_i0_stall_in : UInt<1>
     leak1_i0_stall_in <= UInt<1>("h00")
-    wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 101:17]
-    wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:17]
-    wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:17]
-    wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:20]
-    wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 105:17]
-    wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 106:23]
-    wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:17]
-    wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:17]
-    wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:17]
-    wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 110:20]
-    wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 111:17]
-    wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:20]
-    wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 113:28]
-    wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 114:28]
+    wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 99:37]
+    wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 100:37]
+    wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 101:37]
+    wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:37]
+    wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:37]
+    wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:37]
+    wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 105:37]
+    wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 106:37]
+    wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:37]
+    wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:37]
+    wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:37]
+    wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 110:37]
+    wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 111:37]
+    wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:37]
     wire i0_rs1_depth_d : UInt<2>
     i0_rs1_depth_d <= UInt<1>("h00")
     wire i0_rs2_depth_d : UInt<2>
     i0_rs2_depth_d <= UInt<1>("h00")
     wire cam_wen : UInt<4>
     cam_wen <= UInt<1>("h00")
-    wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 118:17]
+    wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 116:37]
     wire cam_write : UInt<1>
     cam_write <= UInt<1>("h00")
-    wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 120:29]
-    wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 121:30]
-    wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 122:31]
-    wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 123:20]
-    wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 124:20]
-    wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 126:18]
-    wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 127:22]
+    wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 118:37]
+    wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 119:37]
+    wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 120:37]
+    wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 121:37]
+    wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 122:37]
+    wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 123:37]
+    wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 124:37]
     wire i0_rs1bypass : UInt<3>
     i0_rs1bypass <= UInt<1>("h00")
     wire i0_rs2bypass : UInt<3>
@@ -67003,299 +67003,299 @@ circuit quasar_wrapper :
     i0_result_x <= UInt<1>("h00")
     wire i0_result_r : UInt<32>
     i0_result_r <= UInt<1>("h00")
-    node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 181:51]
-    node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 182:32]
-    node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 181:73]
-    node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 183:32]
-    node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 182:56]
-    node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 184:32]
-    node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 183:67]
-    node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 185:32]
-    node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 184:56]
-    node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 186:32]
-    node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 185:56]
-    node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 187:32]
-    node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 186:56]
-    node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 188:32]
-    node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 187:56]
-    node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 189:32]
-    node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 188:56]
-    node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 192:56]
+    node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 178:54]
+    node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 179:54]
+    node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 178:89]
+    node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 180:54]
+    node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 179:89]
+    node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 181:54]
+    node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 180:89]
+    node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 182:54]
+    node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 181:89]
+    node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 183:54]
+    node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 182:89]
+    node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 184:54]
+    node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 183:89]
+    node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 185:54]
+    node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 184:89]
+    node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 186:54]
+    node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 185:89]
+    node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 189:57]
     inst rvclkhdr of rvclkhdr_661 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr.io.en <= _T_17 @[lib.scala 329:16]
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 196:62]
-    node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 196:60]
-    io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 197:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 198:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 199:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 200:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 201:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 202:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 203:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 204:54]
-    io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 205:54]
-    node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 206:66]
-    io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 206:49]
-    node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 207:75]
-    node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 207:90]
-    node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 207:103]
-    node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 207:56]
-    node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 207:54]
-    node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 210:72]
-    node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 210:47]
-    node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 210:106]
-    node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 210:76]
-    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 210:126]
-    node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 210:124]
-    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 211:47]
-    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 211:74]
-    node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 211:72]
-    node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 212:62]
-    node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 212:79]
-    node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 212:101]
-    node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 213:83]
-    node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:105]
-    node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 213:103]
-    io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 213:67]
-    node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 214:105]
-    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 214:127]
-    node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 214:125]
-    io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 214:67]
-    io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 215:43]
-    io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 216:43]
-    node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 217:47]
-    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 217:86]
-    node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 217:84]
-    io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 218:60]
-    io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 219:43]
-    io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 220:67]
-    node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 226:36]
-    i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 229:9]
-    i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 229:9]
-    i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 229:9]
-    i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 229:9]
-    i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 229:9]
-    i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 229:9]
-    i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 229:9]
-    i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 229:9]
-    i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 229:9]
-    i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 229:9]
-    i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 229:9]
-    i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 229:9]
-    i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 229:9]
-    i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 229:9]
-    i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 229:9]
-    i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 229:9]
-    i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 229:9]
-    i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 229:9]
-    i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 229:9]
-    i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 229:9]
-    i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 229:9]
-    i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 229:9]
-    i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 229:9]
-    i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 229:9]
-    i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 229:9]
-    i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 229:9]
-    i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 229:9]
-    i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 229:9]
-    i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 229:9]
-    i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 229:9]
-    i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 229:9]
-    i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 229:9]
-    i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 229:9]
-    i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 229:9]
-    i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 229:9]
-    i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 229:9]
-    i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 229:9]
-    i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 229:9]
-    i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 229:9]
-    i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 229:9]
-    i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 229:9]
-    i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 229:9]
-    i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 229:9]
-    i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 229:9]
-    i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 229:9]
-    i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 229:9]
-    i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 229:9]
-    i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 229:9]
-    i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 229:9]
-    i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 229:9]
-    node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 230:25]
-    node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 230:43]
-    when _T_42 : @[dec_decode_ctl.scala 230:50]
-      wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 231:35]
-      _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35]
-      i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 231:20]
-      i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 231:20]
-      i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 231:20]
-      i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 231:20]
-      i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 231:20]
-      i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 231:20]
-      i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 231:20]
-      i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 231:20]
-      i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 231:20]
-      i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 231:20]
-      i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 231:20]
-      i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 231:20]
-      i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 231:20]
-      i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 231:20]
-      i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 231:20]
-      i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 231:20]
-      i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 231:20]
-      i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 231:20]
-      i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 231:20]
-      i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 231:20]
-      i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 231:20]
-      i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 231:20]
-      i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 231:20]
-      i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 231:20]
-      i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 231:20]
-      i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 231:20]
-      i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 231:20]
-      i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 231:20]
-      i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 231:20]
-      i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 231:20]
-      i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 231:20]
-      i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 231:20]
-      i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 231:20]
-      i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 231:20]
-      i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 231:20]
-      i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 231:20]
-      i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 231:20]
-      i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 231:20]
-      i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 231:20]
-      i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 231:20]
-      i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 231:20]
-      i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 231:20]
-      i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 231:20]
-      i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 231:20]
-      i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 231:20]
-      i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 231:20]
-      i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 231:20]
-      i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 231:20]
-      i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 231:20]
-      i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 231:20]
-      i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 232:20]
-      i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 233:20]
-      i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 234:20]
-      i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 235:20]
-      i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 236:20]
-      i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 237:20]
-      skip @[dec_decode_ctl.scala 230:50]
-    io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 241:36]
-    node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 244:40]
-    node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 244:51]
-    node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 244:60]
-    node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 246:51]
-    node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 246:55]
-    node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 246:26]
-    node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 246:71]
-    node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 247:51]
-    node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 247:55]
-    node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 247:71]
-    node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 248:20]
-    io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 250:37]
-    io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 251:37]
-    io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 253:31]
-    io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 254:31]
-    io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 255:31]
-    io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 256:31]
-    io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 257:31]
-    io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 258:31]
-    io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 259:31]
-    io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 260:31]
-    io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 261:31]
-    io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 262:31]
-    io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 263:31]
-    io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 264:31]
-    io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 265:31]
-    io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 266:31]
-    io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 267:33]
-    io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 268:33]
-    io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 269:33]
-    node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78]
-    node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 273:137]
-    node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 273:158]
-    node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78]
-    node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 273:126]
-    node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 273:137]
-    node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 273:158]
-    node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78]
-    node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 273:126]
-    node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 273:126]
-    node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 273:137]
-    node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 273:158]
-    node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78]
-    node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 273:126]
-    node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 273:126]
-    node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 273:120]
-    node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 273:129]
-    node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 273:126]
-    node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 273:137]
-    node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 273:158]
+    node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 192:80]
+    node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 192:78]
+    io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 193:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 194:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 195:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 196:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 197:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 198:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 199:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 200:55]
+    io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 201:55]
+    node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 202:71]
+    io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 202:55]
+    node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 203:92]
+    node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 203:107]
+    node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 203:120]
+    node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 203:73]
+    node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 203:71]
+    node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 206:97]
+    node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 206:72]
+    node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 206:131]
+    node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 206:101]
+    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 206:151]
+    node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 206:149]
+    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 207:72]
+    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 207:99]
+    node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 207:97]
+    node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 208:87]
+    node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 208:104]
+    node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 208:126]
+    node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 209:72]
+    node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 209:94]
+    node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 209:92]
+    io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 209:56]
+    node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 210:94]
+    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 210:116]
+    node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 210:114]
+    io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 210:56]
+    io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 211:56]
+    io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 212:56]
+    node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 213:72]
+    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:111]
+    node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 213:109]
+    io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 214:56]
+    io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 215:56]
+    io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 216:56]
+    node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43]
+    i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 224:23]
+    i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 224:23]
+    i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 224:23]
+    i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 224:23]
+    i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 224:23]
+    i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 224:23]
+    i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 224:23]
+    i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 224:23]
+    i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 224:23]
+    i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 224:23]
+    i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 224:23]
+    i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 224:23]
+    i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 224:23]
+    i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 224:23]
+    i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 224:23]
+    i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 224:23]
+    i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 224:23]
+    i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 224:23]
+    i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 224:23]
+    i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 224:23]
+    i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 224:23]
+    i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 224:23]
+    i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 224:23]
+    i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 224:23]
+    i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 224:23]
+    i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 224:23]
+    i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 224:23]
+    i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 224:23]
+    i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 224:23]
+    i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 224:23]
+    i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 224:23]
+    i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 224:23]
+    i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 224:23]
+    i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 224:23]
+    i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 224:23]
+    i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 224:23]
+    i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 224:23]
+    i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 224:23]
+    i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 224:23]
+    i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 224:23]
+    i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 224:23]
+    i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 224:23]
+    i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 224:23]
+    i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 224:23]
+    i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 224:23]
+    i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 224:23]
+    i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 224:23]
+    i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 224:23]
+    i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 224:23]
+    i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 224:23]
+    node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 225:25]
+    node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 225:43]
+    when _T_42 : @[dec_decode_ctl.scala 225:50]
+      wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 226:38]
+      _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38]
+      i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 226:23]
+      i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 226:23]
+      i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 226:23]
+      i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 226:23]
+      i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 226:23]
+      i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 226:23]
+      i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 226:23]
+      i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 226:23]
+      i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 226:23]
+      i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 226:23]
+      i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 226:23]
+      i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 226:23]
+      i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 226:23]
+      i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 226:23]
+      i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 226:23]
+      i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 226:23]
+      i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 226:23]
+      i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 226:23]
+      i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 226:23]
+      i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 226:23]
+      i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 226:23]
+      i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 226:23]
+      i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 226:23]
+      i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 226:23]
+      i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 226:23]
+      i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 226:23]
+      i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 226:23]
+      i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 226:23]
+      i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 226:23]
+      i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 226:23]
+      i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 226:23]
+      i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 226:23]
+      i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 226:23]
+      i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 226:23]
+      i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 226:23]
+      i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 226:23]
+      i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 226:23]
+      i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 226:23]
+      i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 226:23]
+      i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 226:23]
+      i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 226:23]
+      i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 226:23]
+      i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 226:23]
+      i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 226:23]
+      i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 226:23]
+      i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 226:23]
+      i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 226:23]
+      i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 226:23]
+      i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 226:23]
+      i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 226:23]
+      i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 227:23]
+      i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 228:23]
+      i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 229:23]
+      i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 230:23]
+      i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 231:23]
+      i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 232:23]
+      skip @[dec_decode_ctl.scala 225:50]
+    io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 236:36]
+    node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 239:54]
+    node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 239:65]
+    node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 239:74]
+    node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 240:65]
+    node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 240:69]
+    node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 240:40]
+    node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 240:85]
+    node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 241:65]
+    node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 241:69]
+    node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 241:85]
+    node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 242:40]
+    io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 244:37]
+    io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 245:37]
+    io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 247:37]
+    io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 248:37]
+    io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 249:37]
+    io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 250:37]
+    io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 251:37]
+    io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 252:37]
+    io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 253:37]
+    io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 254:37]
+    io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 255:37]
+    io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 256:37]
+    io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 257:37]
+    io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 258:37]
+    io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 259:37]
+    io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 260:37]
+    io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 261:37]
+    io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 262:37]
+    io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 263:37]
+    node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
+    node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 267:137]
+    node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 267:158]
+    node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
+    node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 267:126]
+    node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 267:137]
+    node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 267:158]
+    node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
+    node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 267:126]
+    node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 267:126]
+    node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 267:137]
+    node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 267:158]
+    node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78]
+    node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 267:126]
+    node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 267:126]
+    node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 267:120]
+    node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 267:129]
+    node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 267:126]
+    node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 267:137]
+    node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 267:158]
     node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -67305,410 +67305,410 @@ circuit quasar_wrapper :
     node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72]
     wire _T_88 : UInt<4> @[Mux.scala 27:72]
     _T_88 <= _T_87 @[Mux.scala 27:72]
-    cam_wen <= _T_88 @[dec_decode_ctl.scala 273:11]
-    cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 275:25]
-    node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 276:67]
-    node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 281:76]
-    node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 284:48]
-    node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 284:31]
-    node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 288:129]
+    cam_wen <= _T_88 @[dec_decode_ctl.scala 267:11]
+    cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 269:25]
+    node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 270:67]
+    node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 275:76]
+    node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 278:48]
+    node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 278:31]
+    node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 282:129]
     reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_90 : @[Reg.scala 28:19]
       nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 289:56]
-    node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 291:66]
-    node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 291:45]
-    node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 291:87]
-    cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 291:26]
-    node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 292:67]
-    node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 292:45]
-    node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 292:88]
-    cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 292:27]
-    wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28]
-    _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 293:14]
-    cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 293:14]
-    cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 293:14]
-    cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 293:14]
-    cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 294:11]
-    cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 294:11]
-    cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 294:11]
-    cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 294:11]
-    node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 296:32]
-    when _T_98 : @[dec_decode_ctl.scala 296:39]
-      cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20]
-      skip @[dec_decode_ctl.scala 296:39]
-    node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 299:17]
-    node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 299:21]
-    when _T_100 : @[dec_decode_ctl.scala 299:28]
-      cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27]
-      cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32]
-      cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32]
-      cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32]
-      skip @[dec_decode_ctl.scala 299:28]
-    else : @[dec_decode_ctl.scala 304:131]
-      node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 304:37]
-      node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57]
-      node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 304:85]
-      node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 304:64]
-      node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123]
-      node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 304:105]
-      node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 304:44]
-      when _T_107 : @[dec_decode_ctl.scala 304:131]
-        cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23]
-        skip @[dec_decode_ctl.scala 304:131]
-      else : @[dec_decode_ctl.scala 306:16]
-        cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 307:22]
-        cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 307:22]
-        cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 307:22]
-        cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 307:22]
-        skip @[dec_decode_ctl.scala 306:16]
-    node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37]
-    node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 309:92]
-    node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 309:44]
-    node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128]
-    node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 309:113]
-    when _T_112 : @[dec_decode_ctl.scala 309:135]
-      cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25]
-      skip @[dec_decode_ctl.scala 309:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32]
-      cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23]
-      skip @[dec_decode_ctl.scala 313:32]
-    wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70]
-    _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 317:47]
-    _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 317:47]
-    _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 317:47]
-    _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 317:47]
-    _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 317:47]
-    cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 317:15]
-    cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 317:15]
-    cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 317:15]
-    cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 317:15]
-    node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 318:46]
-    node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 318:71]
-    nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 318:28]
-    node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 291:66]
-    node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 291:45]
-    node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 291:87]
-    cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 291:26]
-    node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 292:67]
-    node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 292:45]
-    node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 292:88]
-    cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 292:27]
-    wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28]
-    _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 293:14]
-    cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 293:14]
-    cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 293:14]
-    cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 293:14]
-    cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 294:11]
-    cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 294:11]
-    cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 294:11]
-    cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 294:11]
-    node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 296:32]
-    when _T_124 : @[dec_decode_ctl.scala 296:39]
-      cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20]
-      skip @[dec_decode_ctl.scala 296:39]
-    node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 299:17]
-    node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 299:21]
-    when _T_126 : @[dec_decode_ctl.scala 299:28]
-      cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27]
-      cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32]
-      cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32]
-      cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32]
-      skip @[dec_decode_ctl.scala 299:28]
-    else : @[dec_decode_ctl.scala 304:131]
-      node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 304:37]
-      node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57]
-      node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 304:85]
-      node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 304:64]
-      node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123]
-      node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 304:105]
-      node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 304:44]
-      when _T_133 : @[dec_decode_ctl.scala 304:131]
-        cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23]
-        skip @[dec_decode_ctl.scala 304:131]
-      else : @[dec_decode_ctl.scala 306:16]
-        cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 307:22]
-        cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 307:22]
-        cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 307:22]
-        cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 307:22]
-        skip @[dec_decode_ctl.scala 306:16]
-    node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37]
-    node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 309:92]
-    node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 309:44]
-    node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128]
-    node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 309:113]
-    when _T_138 : @[dec_decode_ctl.scala 309:135]
-      cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25]
-      skip @[dec_decode_ctl.scala 309:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32]
-      cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23]
-      skip @[dec_decode_ctl.scala 313:32]
-    wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70]
-    _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 317:47]
-    _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 317:47]
-    _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 317:47]
-    _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 317:47]
-    _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 317:47]
-    cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 317:15]
-    cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 317:15]
-    cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 317:15]
-    cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 317:15]
-    node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 318:46]
-    node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 318:71]
-    nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 318:28]
-    node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 291:66]
-    node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 291:45]
-    node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 291:87]
-    cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 291:26]
-    node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 292:67]
-    node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 292:45]
-    node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 292:88]
-    cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 292:27]
-    wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28]
-    _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 293:14]
-    cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 293:14]
-    cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 293:14]
-    cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 293:14]
-    cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 294:11]
-    cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 294:11]
-    cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 294:11]
-    cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 294:11]
-    node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 296:32]
-    when _T_150 : @[dec_decode_ctl.scala 296:39]
-      cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20]
-      skip @[dec_decode_ctl.scala 296:39]
-    node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 299:17]
-    node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 299:21]
-    when _T_152 : @[dec_decode_ctl.scala 299:28]
-      cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27]
-      cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32]
-      cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32]
-      cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32]
-      skip @[dec_decode_ctl.scala 299:28]
-    else : @[dec_decode_ctl.scala 304:131]
-      node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 304:37]
-      node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57]
-      node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 304:85]
-      node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 304:64]
-      node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123]
-      node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 304:105]
-      node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 304:44]
-      when _T_159 : @[dec_decode_ctl.scala 304:131]
-        cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23]
-        skip @[dec_decode_ctl.scala 304:131]
-      else : @[dec_decode_ctl.scala 306:16]
-        cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 307:22]
-        cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 307:22]
-        cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 307:22]
-        cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 307:22]
-        skip @[dec_decode_ctl.scala 306:16]
-    node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37]
-    node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 309:92]
-    node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 309:44]
-    node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128]
-    node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 309:113]
-    when _T_164 : @[dec_decode_ctl.scala 309:135]
-      cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25]
-      skip @[dec_decode_ctl.scala 309:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32]
-      cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23]
-      skip @[dec_decode_ctl.scala 313:32]
-    wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70]
-    _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 317:47]
-    _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 317:47]
-    _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 317:47]
-    _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 317:47]
-    _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 317:47]
-    cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 317:15]
-    cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 317:15]
-    cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 317:15]
-    cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 317:15]
-    node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 318:46]
-    node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 318:71]
-    nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 318:28]
-    node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 291:66]
-    node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 291:45]
-    node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 291:87]
-    cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 291:26]
-    node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 292:67]
-    node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 292:45]
-    node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 292:88]
-    cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 292:27]
-    wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28]
-    _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28]
-    cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 293:14]
-    cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 293:14]
-    cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 293:14]
-    cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 293:14]
-    cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 294:11]
-    cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 294:11]
-    cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 294:11]
-    cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 294:11]
-    node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 296:32]
-    when _T_176 : @[dec_decode_ctl.scala 296:39]
-      cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20]
-      skip @[dec_decode_ctl.scala 296:39]
-    node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 299:17]
-    node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 299:21]
-    when _T_178 : @[dec_decode_ctl.scala 299:28]
-      cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27]
-      cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32]
-      cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32]
-      cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32]
-      skip @[dec_decode_ctl.scala 299:28]
-    else : @[dec_decode_ctl.scala 304:131]
-      node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 304:37]
-      node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57]
-      node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 304:85]
-      node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 304:64]
-      node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123]
-      node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 304:105]
-      node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 304:44]
-      when _T_185 : @[dec_decode_ctl.scala 304:131]
-        cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23]
-        skip @[dec_decode_ctl.scala 304:131]
-      else : @[dec_decode_ctl.scala 306:16]
-        cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 307:22]
-        cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 307:22]
-        cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 307:22]
-        cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 307:22]
-        skip @[dec_decode_ctl.scala 306:16]
-    node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37]
-    node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 309:92]
-    node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 309:44]
-    node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128]
-    node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 309:113]
-    when _T_190 : @[dec_decode_ctl.scala 309:135]
-      cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25]
-      skip @[dec_decode_ctl.scala 309:135]
-    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32]
-      cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23]
-      skip @[dec_decode_ctl.scala 313:32]
-    wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70]
-    _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70]
-    reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 317:47]
-    _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 317:47]
-    _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 317:47]
-    _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 317:47]
-    _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 317:47]
-    cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 317:15]
-    cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 317:15]
-    cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 317:15]
-    cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 317:15]
-    node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 318:46]
-    node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 318:71]
-    nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 318:28]
-    io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 321:29]
-    node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 323:49]
-    node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 323:81]
-    node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 324:108]
-    node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 324:108]
-    node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 324:108]
-    node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 324:112]
-    node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 324:77]
-    node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 324:122]
-    node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 324:119]
-    io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 324:28]
-    node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 325:54]
-    node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:66]
-    node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 325:110]
-    node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 325:161]
-    node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:173]
-    node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 325:217]
-    node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 325:142]
-    i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 327:26]
+    node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 283:56]
+    node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 285:66]
+    node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 285:45]
+    node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 285:87]
+    cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 285:26]
+    node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 286:67]
+    node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 286:45]
+    node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 286:88]
+    cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 286:27]
+    wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
+    _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 287:14]
+    cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 287:14]
+    cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 287:14]
+    cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 287:14]
+    cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 288:11]
+    cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 288:11]
+    cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 288:11]
+    cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 288:11]
+    node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 290:32]
+    when _T_98 : @[dec_decode_ctl.scala 290:39]
+      cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
+      skip @[dec_decode_ctl.scala 290:39]
+    node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 293:17]
+    node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 293:21]
+    when _T_100 : @[dec_decode_ctl.scala 293:28]
+      cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
+      cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
+      cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
+      cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
+      skip @[dec_decode_ctl.scala 293:28]
+    else : @[dec_decode_ctl.scala 298:131]
+      node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 298:37]
+      node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
+      node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 298:85]
+      node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 298:64]
+      node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
+      node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 298:105]
+      node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 298:44]
+      when _T_107 : @[dec_decode_ctl.scala 298:131]
+        cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
+        skip @[dec_decode_ctl.scala 298:131]
+      else : @[dec_decode_ctl.scala 300:16]
+        cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 301:22]
+        cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 301:22]
+        cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 301:22]
+        cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 301:22]
+        skip @[dec_decode_ctl.scala 300:16]
+    node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
+    node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 303:92]
+    node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 303:44]
+    node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
+    node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 303:113]
+    when _T_112 : @[dec_decode_ctl.scala 303:135]
+      cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
+      skip @[dec_decode_ctl.scala 303:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
+      cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
+      skip @[dec_decode_ctl.scala 307:32]
+    wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
+    _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 311:47]
+    _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 311:47]
+    _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 311:47]
+    _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 311:47]
+    _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 311:47]
+    cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 311:15]
+    cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 311:15]
+    cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 311:15]
+    cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 311:15]
+    node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 312:46]
+    node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 312:71]
+    nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 312:28]
+    node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 285:66]
+    node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 285:45]
+    node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 285:87]
+    cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 285:26]
+    node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 286:67]
+    node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 286:45]
+    node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 286:88]
+    cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 286:27]
+    wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
+    _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 287:14]
+    cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 287:14]
+    cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 287:14]
+    cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 287:14]
+    cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 288:11]
+    cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 288:11]
+    cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 288:11]
+    cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 288:11]
+    node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 290:32]
+    when _T_124 : @[dec_decode_ctl.scala 290:39]
+      cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
+      skip @[dec_decode_ctl.scala 290:39]
+    node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 293:17]
+    node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 293:21]
+    when _T_126 : @[dec_decode_ctl.scala 293:28]
+      cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
+      cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
+      cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
+      cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
+      skip @[dec_decode_ctl.scala 293:28]
+    else : @[dec_decode_ctl.scala 298:131]
+      node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 298:37]
+      node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
+      node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 298:85]
+      node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 298:64]
+      node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
+      node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 298:105]
+      node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 298:44]
+      when _T_133 : @[dec_decode_ctl.scala 298:131]
+        cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
+        skip @[dec_decode_ctl.scala 298:131]
+      else : @[dec_decode_ctl.scala 300:16]
+        cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 301:22]
+        cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 301:22]
+        cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 301:22]
+        cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 301:22]
+        skip @[dec_decode_ctl.scala 300:16]
+    node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
+    node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 303:92]
+    node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 303:44]
+    node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
+    node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 303:113]
+    when _T_138 : @[dec_decode_ctl.scala 303:135]
+      cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
+      skip @[dec_decode_ctl.scala 303:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
+      cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
+      skip @[dec_decode_ctl.scala 307:32]
+    wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
+    _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 311:47]
+    _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 311:47]
+    _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 311:47]
+    _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 311:47]
+    _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 311:47]
+    cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 311:15]
+    cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 311:15]
+    cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 311:15]
+    cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 311:15]
+    node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 312:46]
+    node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 312:71]
+    nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 312:28]
+    node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 285:66]
+    node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 285:45]
+    node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 285:87]
+    cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 285:26]
+    node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 286:67]
+    node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 286:45]
+    node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 286:88]
+    cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 286:27]
+    wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
+    _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 287:14]
+    cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 287:14]
+    cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 287:14]
+    cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 287:14]
+    cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 288:11]
+    cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 288:11]
+    cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 288:11]
+    cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 288:11]
+    node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 290:32]
+    when _T_150 : @[dec_decode_ctl.scala 290:39]
+      cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
+      skip @[dec_decode_ctl.scala 290:39]
+    node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 293:17]
+    node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 293:21]
+    when _T_152 : @[dec_decode_ctl.scala 293:28]
+      cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
+      cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
+      cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
+      cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
+      skip @[dec_decode_ctl.scala 293:28]
+    else : @[dec_decode_ctl.scala 298:131]
+      node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 298:37]
+      node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
+      node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 298:85]
+      node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 298:64]
+      node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
+      node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 298:105]
+      node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 298:44]
+      when _T_159 : @[dec_decode_ctl.scala 298:131]
+        cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
+        skip @[dec_decode_ctl.scala 298:131]
+      else : @[dec_decode_ctl.scala 300:16]
+        cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 301:22]
+        cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 301:22]
+        cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 301:22]
+        cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 301:22]
+        skip @[dec_decode_ctl.scala 300:16]
+    node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
+    node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 303:92]
+    node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 303:44]
+    node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
+    node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 303:113]
+    when _T_164 : @[dec_decode_ctl.scala 303:135]
+      cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
+      skip @[dec_decode_ctl.scala 303:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
+      cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
+      skip @[dec_decode_ctl.scala 307:32]
+    wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
+    _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 311:47]
+    _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 311:47]
+    _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 311:47]
+    _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 311:47]
+    _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 311:47]
+    cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 311:15]
+    cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 311:15]
+    cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 311:15]
+    cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 311:15]
+    node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 312:46]
+    node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 312:71]
+    nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 312:28]
+    node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 285:66]
+    node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 285:45]
+    node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 285:87]
+    cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 285:26]
+    node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 286:67]
+    node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 286:45]
+    node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 286:88]
+    cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 286:27]
+    wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28]
+    _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28]
+    cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 287:14]
+    cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 287:14]
+    cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 287:14]
+    cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 287:14]
+    cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 288:11]
+    cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 288:11]
+    cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 288:11]
+    cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 288:11]
+    node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 290:32]
+    when _T_176 : @[dec_decode_ctl.scala 290:39]
+      cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20]
+      skip @[dec_decode_ctl.scala 290:39]
+    node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 293:17]
+    node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 293:21]
+    when _T_178 : @[dec_decode_ctl.scala 293:28]
+      cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27]
+      cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32]
+      cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32]
+      cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32]
+      skip @[dec_decode_ctl.scala 293:28]
+    else : @[dec_decode_ctl.scala 298:131]
+      node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 298:37]
+      node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57]
+      node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 298:85]
+      node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 298:64]
+      node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123]
+      node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 298:105]
+      node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 298:44]
+      when _T_185 : @[dec_decode_ctl.scala 298:131]
+        cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23]
+        skip @[dec_decode_ctl.scala 298:131]
+      else : @[dec_decode_ctl.scala 300:16]
+        cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 301:22]
+        cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 301:22]
+        cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 301:22]
+        cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 301:22]
+        skip @[dec_decode_ctl.scala 300:16]
+    node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37]
+    node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 303:92]
+    node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 303:44]
+    node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128]
+    node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 303:113]
+    when _T_190 : @[dec_decode_ctl.scala 303:135]
+      cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25]
+      skip @[dec_decode_ctl.scala 303:135]
+    when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32]
+      cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23]
+      skip @[dec_decode_ctl.scala 307:32]
+    wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70]
+    _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70]
+    reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 311:47]
+    _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 311:47]
+    _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 311:47]
+    _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 311:47]
+    _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 311:47]
+    cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 311:15]
+    cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 311:15]
+    cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 311:15]
+    cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 311:15]
+    node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 312:46]
+    node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 312:71]
+    nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 312:28]
+    io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 315:29]
+    node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 317:49]
+    node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 317:81]
+    node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 318:108]
+    node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 318:108]
+    node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 318:108]
+    node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 318:112]
+    node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 318:77]
+    node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 318:122]
+    node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 318:119]
+    io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 318:28]
+    node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 319:54]
+    node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:66]
+    node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 319:110]
+    node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 319:161]
+    node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:173]
+    node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 319:217]
+    node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 319:142]
+    i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 321:26]
     node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
     node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 329:88]
-    node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:137]
-    node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170]
-    node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 329:152]
-    node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:214]
-    node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247]
-    node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 329:229]
+    node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 323:88]
+    node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:137]
+    node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
+    node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 323:152]
+    node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:214]
+    node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
+    node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 323:229]
     node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
     node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 329:88]
-    node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:137]
-    node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170]
-    node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 329:152]
-    node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:214]
-    node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247]
-    node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 329:229]
+    node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 323:88]
+    node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:137]
+    node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
+    node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 323:152]
+    node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:214]
+    node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
+    node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 323:229]
     node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
     node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 329:88]
-    node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:137]
-    node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170]
-    node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 329:152]
-    node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:214]
-    node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247]
-    node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 329:229]
+    node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 323:88]
+    node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:137]
+    node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
+    node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 323:152]
+    node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:214]
+    node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
+    node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 323:229]
     node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
     node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
-    node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 329:88]
-    node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:137]
-    node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170]
-    node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 329:152]
-    node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:214]
-    node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247]
-    node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 329:229]
-    node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 330:69]
-    node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 330:69]
-    node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 330:69]
-    node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 330:102]
-    node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 330:102]
-    node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 330:102]
-    node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 330:134]
-    node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 330:134]
-    node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 330:134]
-    io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 331:29]
-    node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 332:38]
-    node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 332:51]
-    i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 332:25]
-    node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 341:34]
-    node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 341:32]
+    node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 323:88]
+    node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:137]
+    node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170]
+    node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 323:152]
+    node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:214]
+    node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247]
+    node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 323:229]
+    node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 324:69]
+    node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 324:69]
+    node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 324:69]
+    node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 324:102]
+    node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 324:102]
+    node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 324:102]
+    node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 324:134]
+    node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 324:134]
+    node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 324:134]
+    io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 325:29]
+    node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 326:38]
+    node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 326:51]
+    i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 326:25]
+    node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 335:34]
+    node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 335:32]
     node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
     node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 353:16]
-    node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 353:30]
-    node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 354:6]
-    node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 354:16]
-    node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 354:30]
-    node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 355:18]
-    node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 355:16]
-    node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 355:30]
+    node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 347:16]
+    node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 347:30]
+    node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 348:6]
+    node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 348:16]
+    node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 348:30]
+    node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 349:18]
+    node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 349:16]
+    node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 349:30]
     node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
     node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16]
     node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16]
@@ -67723,244 +67723,244 @@ circuit quasar_wrapper :
     node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16]
     node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16]
     node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16]
-    node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 345:49]
-    d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 345:21]
-    inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 362:22]
+    node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 339:49]
+    d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 339:21]
+    inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 356:22]
     i0_dec.clock <= clock
     i0_dec.reset <= reset
-    i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 363:16]
-    i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 364:12]
-    i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 364:12]
-    reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 366:45]
-    _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 366:45]
-    lsu_idle <= _T_279 @[dec_decode_ctl.scala 366:11]
-    node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 369:73]
-    node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 369:71]
-    node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 369:53]
-    leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 369:21]
-    reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 370:56]
-    _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 370:56]
-    leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 370:21]
-    leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 371:14]
-    node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 372:53]
-    node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 372:91]
-    node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 372:89]
-    node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 372:71]
-    leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 372:21]
-    reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 373:56]
-    _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 373:56]
-    leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 373:21]
-    node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 377:29]
-    node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 377:36]
-    node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 377:46]
-    node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 377:53]
+    i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 357:16]
+    i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 358:12]
+    i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 358:12]
+    reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 360:45]
+    _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 360:45]
+    lsu_idle <= _T_279 @[dec_decode_ctl.scala 360:11]
+    node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 363:73]
+    node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 363:71]
+    node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 363:53]
+    leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 363:21]
+    reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 364:56]
+    _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 364:56]
+    leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 364:21]
+    leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 365:14]
+    node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 366:53]
+    node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 366:91]
+    node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 366:89]
+    node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 366:71]
+    leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 366:21]
+    reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 367:56]
+    _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 367:56]
+    leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 367:21]
+    node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 371:29]
+    node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 371:36]
+    node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 371:46]
+    node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 371:53]
     node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58]
     node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58]
     node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58]
-    node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 378:46]
-    node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 378:51]
-    node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:71]
-    node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 378:79]
-    node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:104]
-    node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 378:112]
-    node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 378:33]
-    node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 379:47]
-    node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 379:76]
-    node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 379:98]
-    node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 379:89]
-    node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 379:65]
-    node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 380:47]
-    node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 380:76]
-    node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 380:98]
-    node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 380:89]
-    node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 380:67]
-    node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 380:65]
-    node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 381:38]
-    i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 381:20]
-    node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 382:38]
-    i0_pcall <= _T_311 @[dec_decode_ctl.scala 382:20]
-    node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 383:38]
-    i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 383:20]
-    node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 384:38]
-    i0_pja <= _T_313 @[dec_decode_ctl.scala 384:20]
-    node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 385:41]
-    node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 385:55]
-    node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 385:75]
-    node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 385:90]
-    node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 385:97]
-    node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 385:103]
-    node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 385:113]
+    node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 372:46]
+    node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 372:51]
+    node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:71]
+    node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 372:79]
+    node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:104]
+    node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 372:112]
+    node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 372:33]
+    node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 373:47]
+    node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 373:76]
+    node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 373:98]
+    node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 373:89]
+    node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 373:65]
+    node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 374:47]
+    node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 374:76]
+    node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 374:98]
+    node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 374:89]
+    node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 374:67]
+    node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 374:65]
+    node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 375:38]
+    i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 375:20]
+    node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 376:38]
+    i0_pcall <= _T_311 @[dec_decode_ctl.scala 376:20]
+    node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 377:38]
+    i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 377:20]
+    node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 378:38]
+    i0_pja <= _T_313 @[dec_decode_ctl.scala 378:20]
+    node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 379:41]
+    node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 379:55]
+    node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 379:75]
+    node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 379:90]
+    node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 379:97]
+    node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 379:103]
+    node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 379:113]
     node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58]
     node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58]
     node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58]
-    node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 385:26]
-    i0_br_offset <= _T_324 @[dec_decode_ctl.scala 385:20]
-    node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 387:37]
-    node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 387:65]
-    node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 387:55]
-    node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 387:89]
-    node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 387:111]
-    node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 387:101]
-    node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 387:79]
-    node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 388:32]
-    i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 388:15]
-    node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 389:32]
-    i0_pret <= _T_332 @[dec_decode_ctl.scala 389:15]
-    node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:35]
-    node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 390:32]
-    node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:52]
-    node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 390:50]
-    node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:67]
-    node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 390:65]
-    i0_jal <= _T_338 @[dec_decode_ctl.scala 390:15]
-    io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 393:29]
-    io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 394:34]
-    io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 395:34]
-    io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 397:32]
-    io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 398:37]
-    io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 399:37]
-    io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 400:37]
-    reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 402:69]
-    _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 402:69]
-    io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 402:34]
-    wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27]
-    io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 404:12]
-    io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 404:12]
-    when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 405:40]
-      io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 406:29]
-      io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 407:29]
-      io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 408:29]
-      io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 409:24]
-      skip @[dec_decode_ctl.scala 405:40]
-    else : @[dec_decode_ctl.scala 410:15]
-      io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 411:35]
-      io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 412:40]
-      io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 413:40]
-      io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 414:40]
-      io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 415:40]
-      io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 416:40]
-      io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 417:40]
-      io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 418:40]
-      io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 419:40]
-      io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 420:40]
-      skip @[dec_decode_ctl.scala 410:15]
-    io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 424:29]
-    node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 425:56]
-    node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 425:36]
-    csr_read <= _T_342 @[dec_decode_ctl.scala 425:18]
-    node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 427:42]
-    node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 427:40]
-    node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 428:61]
-    node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 428:41]
-    node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 429:59]
-    node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 429:39]
-    node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 430:59]
-    node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 430:39]
-    node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 432:41]
-    node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 432:39]
-    i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 432:23]
-    node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 433:42]
-    node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 433:58]
-    io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 433:24]
-    node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 436:30]
-    io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 436:24]
-    io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 437:23]
-    node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 441:39]
-    node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 441:53]
-    node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 441:51]
-    io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 441:20]
-    node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 444:50]
-    node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 444:85]
-    node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 444:64]
-    node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 444:100]
-    node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 444:118]
-    node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 444:132]
-    node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 444:130]
-    io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 444:27]
-    reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 446:52]
-    csr_read_x <= csr_read @[dec_decode_ctl.scala 446:52]
-    reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 447:51]
-    csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 447:51]
-    reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 448:51]
-    csr_set_x <= csr_set_d @[dec_decode_ctl.scala 448:51]
-    reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 449:53]
-    csr_write_x <= csr_write_d @[dec_decode_ctl.scala 449:53]
-    reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 450:51]
-    csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 450:51]
-    node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 453:27]
-    node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 453:48]
+    node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 379:26]
+    i0_br_offset <= _T_324 @[dec_decode_ctl.scala 379:20]
+    node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 381:37]
+    node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 381:65]
+    node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 381:55]
+    node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 381:89]
+    node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 381:111]
+    node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 381:101]
+    node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 381:79]
+    node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 382:32]
+    i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 382:15]
+    node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 383:32]
+    i0_pret <= _T_332 @[dec_decode_ctl.scala 383:15]
+    node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:35]
+    node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 384:32]
+    node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:52]
+    node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 384:50]
+    node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:67]
+    node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 384:65]
+    i0_jal <= _T_338 @[dec_decode_ctl.scala 384:15]
+    io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 387:29]
+    io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 388:34]
+    io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 389:34]
+    io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 391:32]
+    io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 392:37]
+    io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 393:37]
+    io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 394:37]
+    reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 396:69]
+    _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 396:69]
+    io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 396:34]
+    wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27]
+    io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 398:12]
+    io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 398:12]
+    when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 399:40]
+      io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 400:29]
+      io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 401:29]
+      io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 402:29]
+      io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 403:24]
+      skip @[dec_decode_ctl.scala 399:40]
+    else : @[dec_decode_ctl.scala 404:15]
+      io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 405:35]
+      io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 406:40]
+      io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 407:40]
+      io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 408:40]
+      io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 409:40]
+      io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 410:40]
+      io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 411:40]
+      io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 412:40]
+      io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 413:40]
+      io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 414:40]
+      skip @[dec_decode_ctl.scala 404:15]
+    io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 418:29]
+    node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 419:56]
+    node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 419:36]
+    csr_read <= _T_342 @[dec_decode_ctl.scala 419:18]
+    node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 421:42]
+    node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 421:40]
+    node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 422:61]
+    node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 422:41]
+    node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 423:59]
+    node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 423:39]
+    node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 424:59]
+    node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 424:39]
+    node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 426:41]
+    node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 426:39]
+    i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 426:23]
+    node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 427:42]
+    node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 427:58]
+    io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 427:24]
+    node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 430:30]
+    io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 430:24]
+    io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 431:23]
+    node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 435:39]
+    node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 435:53]
+    node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 435:51]
+    io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 435:20]
+    node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 438:50]
+    node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 438:85]
+    node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 438:64]
+    node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 438:100]
+    node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 438:118]
+    node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 438:132]
+    node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 438:130]
+    io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 438:27]
+    reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 440:52]
+    csr_read_x <= csr_read @[dec_decode_ctl.scala 440:52]
+    reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 441:51]
+    csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 441:51]
+    reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:51]
+    csr_set_x <= csr_set_d @[dec_decode_ctl.scala 442:51]
+    reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 443:53]
+    csr_write_x <= csr_write_d @[dec_decode_ctl.scala 443:53]
+    reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:51]
+    csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 444:51]
+    node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 447:27]
+    node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 447:48]
     inst rvclkhdr_1 of rvclkhdr_662 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
@@ -67969,7 +67969,7 @@ circuit quasar_wrapper :
     rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     csrimm_x <= _T_362 @[lib.scala 358:16]
-    node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 454:62]
+    node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 448:62]
     inst rvclkhdr_2 of rvclkhdr_663 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
@@ -67978,7 +67978,7 @@ circuit quasar_wrapper :
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     csr_rddata_x <= io.dec_csr_rddata_d @[lib.scala 358:16]
-    node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 457:15]
+    node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 451:15]
     wire _T_366 : UInt<1>[27] @[lib.scala 5:48]
     _T_366[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_366[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68033,18 +68033,18 @@ circuit quasar_wrapper :
     node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58]
     node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58]
     node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58]
-    node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 457:53]
+    node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 451:53]
     node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58]
-    node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 458:16]
-    node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 458:5]
+    node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 452:16]
+    node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 452:5]
     node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_398 = mux(_T_396, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72]
     wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
     csr_mask_x <= _T_399 @[Mux.scala 27:72]
-    node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 461:38]
-    node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 461:35]
-    node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 462:35]
+    node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 455:38]
+    node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 455:35]
+    node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 456:35]
     node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -68052,42 +68052,42 @@ circuit quasar_wrapper :
     node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72]
     wire write_csr_data_x : UInt @[Mux.scala 27:72]
     write_csr_data_x <= _T_407 @[Mux.scala 27:72]
-    node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 465:49]
-    node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 465:47]
+    node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 459:49]
+    node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 459:47]
     node _T_410 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
-    node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 465:145]
+    node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 459:145]
     node _T_412 = cat(_T_410, _T_411) @[Cat.scala 29:58]
-    node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 465:109]
-    node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 465:91]
-    node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 465:76]
-    node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 466:44]
-    node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 466:61]
-    node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 466:59]
-    pause_state_in <= _T_417 @[dec_decode_ctl.scala 466:18]
-    reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 467:50]
-    _T_418 <= pause_state_in @[dec_decode_ctl.scala 467:50]
-    pause_stall <= _T_418 @[dec_decode_ctl.scala 467:15]
-    io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 468:22]
-    reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 469:55]
-    _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 469:55]
-    tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 469:19]
-    reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 470:55]
-    _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 470:55]
-    tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 470:19]
-    node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 472:44]
-    node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 472:64]
-    node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 472:61]
-    node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 472:41]
-    io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 472:25]
-    node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 475:59]
-    node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 475:59]
-    node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 476:8]
-    node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 475:30]
-    node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 477:34]
-    node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 477:46]
-    node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 477:61]
-    node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 477:75]
-    node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 477:99]
+    node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 459:109]
+    node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 459:91]
+    node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 459:76]
+    node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 460:44]
+    node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 460:61]
+    node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 460:59]
+    pause_state_in <= _T_417 @[dec_decode_ctl.scala 460:18]
+    reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 461:50]
+    _T_418 <= pause_state_in @[dec_decode_ctl.scala 461:50]
+    pause_stall <= _T_418 @[dec_decode_ctl.scala 461:15]
+    io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 462:22]
+    reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 463:55]
+    _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 463:55]
+    tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 463:19]
+    reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 464:55]
+    _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 464:55]
+    tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 464:19]
+    node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 466:44]
+    node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 466:64]
+    node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:61]
+    node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 466:41]
+    io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 466:25]
+    node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 469:59]
+    node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 469:59]
+    node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 470:8]
+    node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 469:30]
+    node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 471:34]
+    node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 471:46]
+    node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 471:61]
+    node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 471:75]
+    node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 471:99]
     inst rvclkhdr_3 of rvclkhdr_664 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
@@ -68096,33 +68096,33 @@ circuit quasar_wrapper :
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_432 <= write_csr_data_in @[lib.scala 358:16]
-    write_csr_data <= _T_432 @[dec_decode_ctl.scala 478:18]
-    node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 484:49]
-    node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 484:30]
-    io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 484:24]
-    node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 486:43]
-    node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 486:63]
-    node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 488:76]
-    node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 488:48]
-    node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 489:76]
-    node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 489:48]
-    node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 490:40]
-    debug_fence <= _T_438 @[dec_decode_ctl.scala 490:21]
-    node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 493:34]
-    node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 493:57]
-    node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 493:73]
-    node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 493:91]
-    node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 496:36]
-    node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 496:60]
-    node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 496:104]
-    node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 496:112]
-    node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 496:99]
-    node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 496:76]
-    node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 498:34]
-    io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 499:24]
-    node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 500:40]
-    node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 500:51]
-    node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 500:37]
+    write_csr_data <= _T_432 @[dec_decode_ctl.scala 472:18]
+    node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 478:49]
+    node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 478:30]
+    io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 478:24]
+    node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 480:43]
+    node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 480:63]
+    node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 482:76]
+    node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 482:48]
+    node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 483:76]
+    node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 483:48]
+    node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 484:40]
+    debug_fence <= _T_438 @[dec_decode_ctl.scala 484:21]
+    node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 487:34]
+    node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 487:57]
+    node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 487:73]
+    node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 487:91]
+    node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 490:36]
+    node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 490:60]
+    node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 490:104]
+    node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 490:112]
+    node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 490:99]
+    node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 490:76]
+    node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 492:34]
+    io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 493:24]
+    node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 494:40]
+    node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 494:51]
+    node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 494:37]
     wire _T_449 : UInt<1>[16] @[lib.scala 5:48]
     _T_449[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_449[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68156,11 +68156,11 @@ circuit quasar_wrapper :
     node _T_463 = cat(_T_462, _T_449[14]) @[Cat.scala 29:58]
     node _T_464 = cat(_T_463, _T_449[15]) @[Cat.scala 29:58]
     node _T_465 = cat(_T_464, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58]
-    node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 501:27]
-    node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 504:57]
-    node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 504:55]
-    node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 505:44]
-    node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 505:42]
+    node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 495:27]
+    node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 498:57]
+    node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 498:55]
+    node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 499:44]
+    node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 499:42]
     inst rvclkhdr_4 of rvclkhdr_665 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
@@ -68169,94 +68169,94 @@ circuit quasar_wrapper :
     rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_468 <= i0_inst_d @[lib.scala 358:16]
-    io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 506:23]
-    node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 507:40]
-    node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 507:61]
-    node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 507:59]
-    illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 507:22]
-    reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 508:54]
-    _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 508:54]
-    illegal_lockout <= _T_472 @[dec_decode_ctl.scala 508:19]
-    node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 509:42]
-    node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 511:40]
-    node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 511:59]
-    node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 511:92]
-    node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 511:106]
-    node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 512:20]
-    node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 512:45]
-    node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 512:62]
-    node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 513:19]
-    node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 513:36]
-    node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 513:34]
-    node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 512:79]
-    node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 513:47]
-    node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 513:72]
-    node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 514:21]
-    node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 514:45]
-    node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 516:65]
-    node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 516:39]
-    node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 517:63]
-    node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 517:38]
-    node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 518:38]
-    node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 518:57]
-    node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:54]
-    node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 522:52]
-    node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:71]
-    node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 522:69]
-    node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:99]
-    node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 522:97]
-    io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 522:30]
-    node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 523:46]
-    node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 523:44]
-    node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:63]
-    node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 523:61]
-    node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:91]
-    node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 523:89]
-    node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 524:46]
-    io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 527:28]
-    node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 528:51]
-    node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 528:49]
-    io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 528:27]
-    node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 529:47]
-    io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 529:29]
-    node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 530:46]
-    io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 530:29]
-    node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 534:41]
-    node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 535:31]
-    node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 537:37]
-    presync_stall <= _T_505 @[dec_decode_ctl.scala 537:22]
-    reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 538:53]
-    _T_506 <= ps_stall_in @[dec_decode_ctl.scala 538:53]
-    postsync_stall <= _T_506 @[dec_decode_ctl.scala 538:18]
-    node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 540:64]
-    node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 540:62]
-    node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 540:47]
-    node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 540:96]
-    node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 540:77]
-    ps_stall_in <= _T_511 @[dec_decode_ctl.scala 540:15]
-    node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 542:58]
-    io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 542:34]
-    node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 544:40]
-    lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 544:16]
-    node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 545:40]
-    mul_decode_d <= _T_514 @[dec_decode_ctl.scala 545:16]
-    node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 546:40]
-    div_decode_d <= _T_515 @[dec_decode_ctl.scala 546:16]
-    node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 548:45]
-    node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 548:43]
-    io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 548:29]
-    d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 551:26]
-    node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 552:40]
-    d_t.icaf <= _T_518 @[dec_decode_ctl.scala 552:26]
-    node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 553:50]
-    d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 553:26]
-    d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 554:26]
-    node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 556:44]
-    node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 556:61]
-    d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 556:26]
-    d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 559:26]
-    d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 560:26]
-    d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 561:26]
+    io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 500:23]
+    node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 501:40]
+    node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 501:61]
+    node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 501:59]
+    illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 501:22]
+    reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 502:54]
+    _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 502:54]
+    illegal_lockout <= _T_472 @[dec_decode_ctl.scala 502:19]
+    node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 503:42]
+    node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 505:40]
+    node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 505:59]
+    node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 505:92]
+    node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 505:106]
+    node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 506:20]
+    node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 506:45]
+    node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 506:62]
+    node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 507:19]
+    node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 507:36]
+    node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 507:34]
+    node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 506:79]
+    node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 507:47]
+    node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 507:72]
+    node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 508:21]
+    node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 508:45]
+    node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 510:65]
+    node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 510:39]
+    node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 511:63]
+    node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 511:38]
+    node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 512:38]
+    node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 512:57]
+    node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 516:54]
+    node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 516:52]
+    node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:71]
+    node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 516:69]
+    node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:99]
+    node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 516:97]
+    io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 516:30]
+    node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 517:46]
+    node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 517:44]
+    node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:63]
+    node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 517:61]
+    node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:91]
+    node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 517:89]
+    node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 518:46]
+    io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 521:28]
+    node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:51]
+    node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 522:49]
+    io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 522:27]
+    node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 523:47]
+    io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 523:29]
+    node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 524:46]
+    io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 524:29]
+    node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 528:41]
+    node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 529:31]
+    node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 531:37]
+    presync_stall <= _T_505 @[dec_decode_ctl.scala 531:22]
+    reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 532:53]
+    _T_506 <= ps_stall_in @[dec_decode_ctl.scala 532:53]
+    postsync_stall <= _T_506 @[dec_decode_ctl.scala 532:18]
+    node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 534:64]
+    node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 534:62]
+    node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 534:47]
+    node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 534:96]
+    node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 534:77]
+    ps_stall_in <= _T_511 @[dec_decode_ctl.scala 534:15]
+    node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 536:58]
+    io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 536:34]
+    node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 538:40]
+    lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 538:16]
+    node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 539:40]
+    mul_decode_d <= _T_514 @[dec_decode_ctl.scala 539:16]
+    node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 540:40]
+    div_decode_d <= _T_515 @[dec_decode_ctl.scala 540:16]
+    node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 542:45]
+    node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 542:43]
+    io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 542:29]
+    d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 545:26]
+    node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 546:40]
+    d_t.icaf <= _T_518 @[dec_decode_ctl.scala 546:26]
+    node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 547:50]
+    d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 547:26]
+    d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 548:26]
+    node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 550:44]
+    node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 550:61]
+    d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 550:26]
+    d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 553:26]
+    d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 554:26]
+    d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 555:26]
     wire _T_522 : UInt<1>[4] @[lib.scala 5:48]
     _T_522[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 5:48]
     _T_522[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 5:48]
@@ -68265,9 +68265,9 @@ circuit quasar_wrapper :
     node _T_523 = cat(_T_522[0], _T_522[1]) @[Cat.scala 29:58]
     node _T_524 = cat(_T_523, _T_522[2]) @[Cat.scala 29:58]
     node _T_525 = cat(_T_524, _T_522[3]) @[Cat.scala 29:58]
-    node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 563:56]
-    d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 563:26]
-    node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 566:33]
+    node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 557:56]
+    d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 557:26]
+    node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 560:33]
     inst rvclkhdr_5 of rvclkhdr_666 @[lib.scala 362:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
@@ -68296,26 +68296,26 @@ circuit quasar_wrapper :
     _T_529.icaf_f1 <= d_t.icaf_f1 @[lib.scala 368:16]
     _T_529.icaf <= d_t.icaf @[lib.scala 368:16]
     _T_529.legal <= d_t.legal @[lib.scala 368:16]
-    x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 566:7]
-    x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 566:7]
-    x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 566:7]
-    x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 566:7]
-    x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 566:7]
-    x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 566:7]
-    x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 566:7]
-    x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 566:7]
-    x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 566:7]
-    x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 566:7]
-    x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 568:10]
-    x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 568:10]
-    x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 568:10]
-    x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 568:10]
-    x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 568:10]
-    x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 568:10]
-    x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 568:10]
-    x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 568:10]
-    x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 568:10]
-    x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 568:10]
+    x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 560:7]
+    x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 560:7]
+    x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 560:7]
+    x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 560:7]
+    x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 560:7]
+    x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 560:7]
+    x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 560:7]
+    x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 560:7]
+    x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 560:7]
+    x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 560:7]
+    x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 562:10]
+    x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 562:10]
+    x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 562:10]
+    x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 562:10]
+    x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 562:10]
+    x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 562:10]
+    x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 562:10]
+    x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 562:10]
+    x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 562:10]
+    x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 562:10]
     wire _T_530 : UInt<1>[4] @[lib.scala 5:48]
     _T_530[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 5:48]
     _T_530[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 5:48]
@@ -68324,10 +68324,10 @@ circuit quasar_wrapper :
     node _T_531 = cat(_T_530[0], _T_530[1]) @[Cat.scala 29:58]
     node _T_532 = cat(_T_531, _T_530[2]) @[Cat.scala 29:58]
     node _T_533 = cat(_T_532, _T_530[3]) @[Cat.scala 29:58]
-    node _T_534 = not(_T_533) @[dec_decode_ctl.scala 569:39]
-    node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 569:37]
-    x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 569:20]
-    node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 571:36]
+    node _T_534 = not(_T_533) @[dec_decode_ctl.scala 563:39]
+    node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 563:37]
+    x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 563:20]
+    node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 565:36]
     inst rvclkhdr_6 of rvclkhdr_667 @[lib.scala 362:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
@@ -68356,31 +68356,31 @@ circuit quasar_wrapper :
     _T_538.icaf_f1 <= x_t_in.icaf_f1 @[lib.scala 368:16]
     _T_538.icaf <= x_t_in.icaf @[lib.scala 368:16]
     _T_538.legal <= x_t_in.legal @[lib.scala 368:16]
-    r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 571:7]
-    r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 571:7]
-    r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 571:7]
-    r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 571:7]
-    r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 571:7]
-    r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 571:7]
-    r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 571:7]
-    r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 571:7]
-    r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 571:7]
-    r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 571:7]
-    reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 572:36]
-    lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 572:36]
-    reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 573:37]
-    lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 573:37]
-    r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 575:10]
-    r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 575:10]
-    r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 575:10]
-    r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 575:10]
-    r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 575:10]
-    r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 575:10]
-    r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 575:10]
-    r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 575:10]
-    r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 575:10]
-    r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 575:10]
-    node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 577:61]
+    r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 565:7]
+    r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 565:7]
+    r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 565:7]
+    r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 565:7]
+    r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 565:7]
+    r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 565:7]
+    r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 565:7]
+    r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 565:7]
+    r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 565:7]
+    r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 565:7]
+    reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 566:36]
+    lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 566:36]
+    reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 567:37]
+    lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 567:37]
+    r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 569:10]
+    r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 569:10]
+    r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 569:10]
+    r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 569:10]
+    r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 569:10]
+    r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 569:10]
+    r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 569:10]
+    r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 569:10]
+    r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 569:10]
+    r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 569:10]
+    node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 571:61]
     wire _T_540 : UInt<1>[4] @[lib.scala 5:48]
     _T_540[0] <= _T_539 @[lib.scala 5:48]
     _T_540[1] <= _T_539 @[lib.scala 5:48]
@@ -68389,83 +68389,83 @@ circuit quasar_wrapper :
     node _T_541 = cat(_T_540[0], _T_540[1]) @[Cat.scala 29:58]
     node _T_542 = cat(_T_541, _T_540[2]) @[Cat.scala 29:58]
     node _T_543 = cat(_T_542, _T_540[3]) @[Cat.scala 29:58]
-    node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 577:82]
-    node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 577:105]
-    r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 577:33]
-    r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 578:33]
-    node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 580:35]
-    when _T_546 : @[dec_decode_ctl.scala 580:43]
-      wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 580:66]
-      _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66]
-      r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 580:51]
-      r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 580:51]
-      r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 580:51]
-      r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 580:51]
-      r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 580:51]
-      r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 580:51]
-      r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 580:51]
-      r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 580:51]
-      r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 580:51]
-      r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 580:51]
-      skip @[dec_decode_ctl.scala 580:43]
-    io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 582:39]
-    io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 582:39]
-    node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 583:58]
-    io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 583:39]
-    reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 586:52]
-    _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 586:52]
-    flush_final_r <= _T_549 @[dec_decode_ctl.scala 586:17]
-    node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 588:54]
-    node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 588:52]
-    node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:68]
-    node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 588:66]
-    node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:96]
-    node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 588:94]
-    io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 588:30]
-    node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 590:16]
-    i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 590:11]
-    node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 591:16]
-    i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 591:11]
-    node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 592:16]
-    i0r.rd <= _T_558 @[dec_decode_ctl.scala 592:11]
-    node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 594:60]
-    node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 594:49]
-    io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 594:35]
-    node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 595:60]
-    node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 595:49]
-    io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 595:35]
-    node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 596:48]
-    node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 596:37]
-    io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 597:19]
-    io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 598:19]
-    node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 600:38]
-    node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 601:27]
-    node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 601:38]
-    node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 605:5]
+    node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 571:82]
+    node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 571:105]
+    r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 571:33]
+    r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 572:33]
+    node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 574:35]
+    when _T_546 : @[dec_decode_ctl.scala 574:43]
+      wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 574:66]
+      _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66]
+      r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 574:51]
+      r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 574:51]
+      r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 574:51]
+      r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 574:51]
+      r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 574:51]
+      r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 574:51]
+      r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 574:51]
+      r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 574:51]
+      r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 574:51]
+      r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 574:51]
+      skip @[dec_decode_ctl.scala 574:43]
+    io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 576:39]
+    io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 576:39]
+    node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 577:58]
+    io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 577:39]
+    reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 580:52]
+    _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 580:52]
+    flush_final_r <= _T_549 @[dec_decode_ctl.scala 580:17]
+    node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 582:54]
+    node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 582:52]
+    node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:68]
+    node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 582:66]
+    node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:96]
+    node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 582:94]
+    io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 582:30]
+    node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 584:16]
+    i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 584:11]
+    node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 585:16]
+    i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 585:11]
+    node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 586:16]
+    i0r.rd <= _T_558 @[dec_decode_ctl.scala 586:11]
+    node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 588:60]
+    node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 588:49]
+    io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 588:35]
+    node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 589:60]
+    node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 589:49]
+    io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 589:35]
+    node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 590:48]
+    node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 590:37]
+    io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 591:19]
+    io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 592:19]
+    node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 594:38]
+    node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 595:27]
+    node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 595:38]
+    node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 599:5]
     node _T_566 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_567 = mux(_T_565, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72]
     wire _T_569 : UInt<32> @[Mux.scala 27:72]
     _T_569 <= _T_568 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 603:32]
-    node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 608:38]
+    io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 597:32]
+    node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 602:38]
     wire _T_571 : UInt<1>[20] @[lib.scala 5:48]
     _T_571[0] <= _T_570 @[lib.scala 5:48]
     _T_571[1] <= _T_570 @[lib.scala 5:48]
@@ -68506,7 +68506,7 @@ circuit quasar_wrapper :
     node _T_588 = cat(_T_587, _T_571[17]) @[Cat.scala 29:58]
     node _T_589 = cat(_T_588, _T_571[18]) @[Cat.scala 29:58]
     node _T_590 = cat(_T_589, _T_571[19]) @[Cat.scala 29:58]
-    node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 608:46]
+    node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 602:46]
     node _T_592 = cat(_T_590, _T_591) @[Cat.scala 29:58]
     wire _T_593 : UInt<1>[27] @[lib.scala 5:48]
     _T_593[0] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68562,9 +68562,9 @@ circuit quasar_wrapper :
     node _T_617 = cat(_T_616, _T_593[24]) @[Cat.scala 29:58]
     node _T_618 = cat(_T_617, _T_593[25]) @[Cat.scala 29:58]
     node _T_619 = cat(_T_618, _T_593[26]) @[Cat.scala 29:58]
-    node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 609:43]
+    node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 603:43]
     node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58]
-    node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 610:38]
+    node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 604:38]
     wire _T_623 : UInt<1>[12] @[lib.scala 5:48]
     _T_623[0] <= _T_622 @[lib.scala 5:48]
     _T_623[1] <= _T_622 @[lib.scala 5:48]
@@ -68589,14 +68589,14 @@ circuit quasar_wrapper :
     node _T_632 = cat(_T_631, _T_623[9]) @[Cat.scala 29:58]
     node _T_633 = cat(_T_632, _T_623[10]) @[Cat.scala 29:58]
     node _T_634 = cat(_T_633, _T_623[11]) @[Cat.scala 29:58]
-    node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 610:46]
-    node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 610:56]
-    node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 610:63]
+    node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 604:46]
+    node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 604:56]
+    node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 604:63]
     node _T_638 = cat(_T_637, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_639 = cat(_T_634, _T_635) @[Cat.scala 29:58]
     node _T_640 = cat(_T_639, _T_636) @[Cat.scala 29:58]
     node _T_641 = cat(_T_640, _T_638) @[Cat.scala 29:58]
-    node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 611:30]
+    node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 605:30]
     wire _T_643 : UInt<1>[12] @[lib.scala 5:48]
     _T_643[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_643[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68622,8 +68622,8 @@ circuit quasar_wrapper :
     node _T_653 = cat(_T_652, _T_643[10]) @[Cat.scala 29:58]
     node _T_654 = cat(_T_653, _T_643[11]) @[Cat.scala 29:58]
     node _T_655 = cat(_T_642, _T_654) @[Cat.scala 29:58]
-    node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 612:26]
-    node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 612:43]
+    node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 606:26]
+    node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 606:43]
     wire _T_658 : UInt<1>[27] @[lib.scala 5:48]
     _T_658[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_658[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68678,7 +68678,7 @@ circuit quasar_wrapper :
     node _T_682 = cat(_T_681, _T_658[24]) @[Cat.scala 29:58]
     node _T_683 = cat(_T_682, _T_658[25]) @[Cat.scala 29:58]
     node _T_684 = cat(_T_683, _T_658[26]) @[Cat.scala 29:58]
-    node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 612:72]
+    node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 606:72]
     node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58]
     node _T_687 = mux(i0_dp.imm12, _T_592, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_688 = mux(i0_dp.shimm5, _T_621, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -68691,87 +68691,87 @@ circuit quasar_wrapper :
     node _T_695 = or(_T_694, _T_691) @[Mux.scala 27:72]
     wire _T_696 : UInt<32> @[Mux.scala 27:72]
     _T_696 <= _T_695 @[Mux.scala 27:72]
-    i0_immed_d <= _T_696 @[dec_decode_ctl.scala 607:14]
-    node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 614:54]
-    i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 614:24]
-    node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 616:44]
-    i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 616:29]
-    node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 617:44]
-    i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 617:29]
-    node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 618:44]
-    i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 618:29]
-    wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 620:70]
-    _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
-    _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
-    _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 620:70]
-    node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 620:92]
+    i0_immed_d <= _T_696 @[dec_decode_ctl.scala 601:14]
+    node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 608:54]
+    i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 608:24]
+    node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 610:44]
+    i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 610:29]
+    node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 611:44]
+    i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 611:29]
+    node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 612:44]
+    i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 612:29]
+    wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 614:70]
+    _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
+    _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
+    _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70]
+    node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 614:92]
     reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_701)) @[Reg.scala 27:20]
     when _T_702 : @[Reg.scala 28:19]
       i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23]
       i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23]
       i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 621:70]
-    _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
-    _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
-    _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 621:70]
-    node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 621:92]
+    wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 615:70]
+    _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
+    _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
+    _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70]
+    node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 615:92]
     reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_703)) @[Reg.scala 27:20]
     when _T_704 : @[Reg.scala 28:19]
       i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23]
       i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23]
       i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 622:91]
-    reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 622:80]
-    _T_706 <= _T_705 @[dec_decode_ctl.scala 622:80]
+    node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 616:91]
+    reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 616:80]
+    _T_706 <= _T_705 @[dec_decode_ctl.scala 616:80]
     node _T_707 = cat(io.dec_aln.dec_i0_decode_d, _T_706) @[Cat.scala 29:58]
-    i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 622:14]
-    node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 624:43]
-    node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 624:49]
-    node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 624:53]
-    i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 624:29]
-    node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 625:43]
-    node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 625:49]
-    node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 625:53]
-    i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 625:29]
-    node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 626:43]
-    node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 626:49]
-    node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 626:53]
-    i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 626:29]
-    node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 627:44]
-    node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 627:50]
-    i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 627:29]
-    node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 628:44]
-    node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 628:50]
-    i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 628:29]
-    node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 629:44]
-    node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 629:50]
-    i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 629:29]
-    node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 630:44]
-    node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 630:50]
-    i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 630:29]
+    i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 616:14]
+    node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 618:43]
+    node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 618:49]
+    node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 618:53]
+    i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 618:29]
+    node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 619:43]
+    node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 619:49]
+    node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 619:53]
+    i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 619:29]
+    node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 620:43]
+    node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 620:49]
+    node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 620:53]
+    i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 620:29]
+    node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 621:44]
+    node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 621:50]
+    i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 621:29]
+    node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 622:44]
+    node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 622:50]
+    i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 622:29]
+    node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 623:44]
+    node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 623:50]
+    i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 623:29]
+    node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 624:44]
+    node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 624:50]
+    i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 624:29]
     node _T_725 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 632:38]
+    io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 626:38]
     node _T_726 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
-    io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 633:38]
-    d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 635:34]
-    node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 636:50]
-    d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 636:34]
-    d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 637:27]
-    node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 639:50]
-    d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 639:34]
-    node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 640:50]
-    d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 640:34]
-    node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 641:50]
-    d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 641:34]
-    node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:61]
-    d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 643:34]
-    node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 644:58]
-    d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 644:34]
-    node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40]
-    d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 645:34]
-    node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34]
+    io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 627:38]
+    d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 629:34]
+    node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 630:50]
+    d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 630:34]
+    d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 631:27]
+    node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 633:50]
+    d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 633:34]
+    node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 634:50]
+    d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 634:34]
+    node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 635:50]
+    d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 635:34]
+    node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 637:61]
+    d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 637:34]
+    node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 638:58]
+    d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 638:34]
+    node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 639:40]
+    d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 639:34]
+    node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 641:34]
     inst rvclkhdr_7 of rvclkhdr_668 @[lib.scala 362:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
@@ -68798,36 +68798,36 @@ circuit quasar_wrapper :
     _T_736.bits.i0load <= d_d.bits.i0load @[lib.scala 368:16]
     _T_736.bits.i0rd <= d_d.bits.i0rd @[lib.scala 368:16]
     _T_736.valid <= d_d.valid @[lib.scala 368:16]
-    x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 647:7]
-    x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 647:7]
-    x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 647:7]
-    x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 647:7]
-    x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 647:7]
-    wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 648:20]
-    x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 649:10]
-    x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 649:10]
-    x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 649:10]
-    node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 650:49]
-    node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 650:47]
-    node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 650:78]
-    node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 650:76]
-    x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 650:27]
-    node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:35]
-    node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 651:33]
-    node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 651:64]
-    node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 651:62]
-    x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 651:20]
-    node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36]
+    x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 641:7]
+    x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 641:7]
+    x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 641:7]
+    x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 641:7]
+    x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 641:7]
+    x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 641:7]
+    x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 641:7]
+    x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 641:7]
+    x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 641:7]
+    wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 642:20]
+    x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 643:10]
+    x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 643:10]
+    x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 643:10]
+    node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 644:49]
+    node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 644:47]
+    node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 644:78]
+    node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 644:76]
+    x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 644:27]
+    node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 645:35]
+    node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 645:33]
+    node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 645:64]
+    node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 645:62]
+    x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 645:20]
+    node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:36]
     inst rvclkhdr_8 of rvclkhdr_669 @[lib.scala 362:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
@@ -68854,38 +68854,38 @@ circuit quasar_wrapper :
     _T_747.bits.i0load <= x_d_in.bits.i0load @[lib.scala 368:16]
     _T_747.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 368:16]
     _T_747.valid <= x_d_in.valid @[lib.scala 368:16]
-    r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 653:7]
-    r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 653:7]
-    r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 653:7]
-    r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 653:7]
-    r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 653:7]
-    r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 654:10]
-    r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 654:10]
-    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 655:22]
-    node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 657:51]
-    node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 657:49]
-    r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 657:27]
-    node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 658:37]
-    node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 658:35]
-    r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 658:20]
-    node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 659:51]
-    node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 659:49]
-    r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 659:27]
-    node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 660:51]
-    node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 660:49]
-    r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 660:27]
-    node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37]
+    r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 647:7]
+    r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 647:7]
+    r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 647:7]
+    r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 647:7]
+    r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 647:7]
+    r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 647:7]
+    r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 647:7]
+    r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 647:7]
+    r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 647:7]
+    r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 648:10]
+    r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 648:10]
+    r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 649:22]
+    node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:51]
+    node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 651:49]
+    r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 651:27]
+    node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 652:37]
+    node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 652:35]
+    r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 652:20]
+    node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 653:51]
+    node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 653:49]
+    r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 653:27]
+    node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 654:51]
+    node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 654:49]
+    r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 654:27]
+    node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 656:37]
     inst rvclkhdr_9 of rvclkhdr_670 @[lib.scala 362:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
@@ -68912,26 +68912,26 @@ circuit quasar_wrapper :
     _T_758.bits.i0load <= r_d_in.bits.i0load @[lib.scala 368:16]
     _T_758.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 368:16]
     _T_758.valid <= r_d_in.valid @[lib.scala 368:16]
-    wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 662:7]
-    wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 662:7]
-    wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 662:7]
-    wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 662:7]
-    wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 662:7]
-    io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 664:27]
-    node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 665:47]
-    node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 665:45]
-    i0_wen_r <= _T_760 @[dec_decode_ctl.scala 665:25]
-    node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 666:49]
-    node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 666:47]
-    node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 666:70]
-    node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 666:68]
-    io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 666:32]
-    io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 667:26]
-    node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57]
+    wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 656:7]
+    wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 656:7]
+    wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 656:7]
+    wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 656:7]
+    wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 656:7]
+    wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 656:7]
+    wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 656:7]
+    wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 656:7]
+    wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 656:7]
+    io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 658:27]
+    node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 659:47]
+    node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 659:45]
+    i0_wen_r <= _T_760 @[dec_decode_ctl.scala 659:25]
+    node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 660:49]
+    node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 660:47]
+    node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 660:70]
+    node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 660:68]
+    io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 660:32]
+    io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 661:26]
+    node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 663:57]
     inst rvclkhdr_10 of rvclkhdr_671 @[lib.scala 352:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
@@ -68940,18 +68940,18 @@ circuit quasar_wrapper :
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_result_r_raw <= i0_result_x @[lib.scala 358:16]
-    node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47]
-    node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 675:66]
-    node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32]
-    i0_result_x <= _T_768 @[dec_decode_ctl.scala 675:26]
-    i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 676:26]
-    node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 680:42]
-    node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 680:61]
-    node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 680:27]
-    i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 680:21]
-    node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73]
-    node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 681:71]
-    node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 681:85]
+    node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 669:47]
+    node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 669:66]
+    node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 669:32]
+    i0_result_x <= _T_768 @[dec_decode_ctl.scala 669:26]
+    i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 670:26]
+    node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 674:42]
+    node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 674:61]
+    node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 674:27]
+    i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 674:21]
+    node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 675:73]
+    node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 675:71]
+    node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 675:85]
     wire _T_775 : UInt<1>[10] @[lib.scala 5:48]
     _T_775[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_775[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -68974,11 +68974,11 @@ circuit quasar_wrapper :
     node _T_784 = cat(_T_783, _T_775[9]) @[Cat.scala 29:58]
     node _T_785 = cat(_T_784, io.dec_i0_pc4_d) @[Cat.scala 29:58]
     node _T_786 = cat(_T_785, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 681:38]
-    io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 681:32]
+    node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 675:38]
+    io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 675:32]
     wire last_br_immed_d : UInt<12>
     last_br_immed_d <= UInt<1>("h00")
-    node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59]
+    node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 677:59]
     wire _T_789 : UInt<1>[10] @[lib.scala 5:48]
     _T_789[0] <= UInt<1>("h00") @[lib.scala 5:48]
     _T_789[1] <= UInt<1>("h00") @[lib.scala 5:48]
@@ -69001,11 +69001,11 @@ circuit quasar_wrapper :
     node _T_798 = cat(_T_797, _T_789[9]) @[Cat.scala 29:58]
     node _T_799 = cat(_T_798, io.dec_i0_pc4_d) @[Cat.scala 29:58]
     node _T_800 = cat(_T_799, i0_ap_pc2) @[Cat.scala 29:58]
-    node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 683:25]
-    last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 683:19]
+    node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 677:25]
+    last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 677:19]
     wire last_br_immed_x : UInt<12>
     last_br_immed_x <= UInt<1>("h00")
-    node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58]
+    node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 679:58]
     inst rvclkhdr_11 of rvclkhdr_672 @[lib.scala 352:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
@@ -69014,54 +69014,54 @@ circuit quasar_wrapper :
     rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_803 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_803 <= last_br_immed_d @[lib.scala 358:16]
-    last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 685:19]
-    node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45]
-    node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76]
-    node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 689:58]
-    node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 691:48]
-    node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 691:77]
-    node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 691:60]
-    node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 692:21]
-    node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 692:33]
-    node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 691:94]
-    node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 693:21]
-    node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 693:33]
-    node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 693:60]
-    node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 692:62]
-    node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 697:51]
-    node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 698:26]
-    node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 698:24]
-    node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 698:56]
-    node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 698:39]
-    node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 698:77]
-    node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 697:65]
-    node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 700:61]
-    io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 700:37]
-    node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 701:55]
-    node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 703:62]
-    node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 703:60]
-    node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 703:81]
-    node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 703:79]
-    node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 703:39]
-    reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 705:54]
-    _T_826 <= div_active_in @[dec_decode_ctl.scala 705:54]
-    io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 705:21]
-    node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 708:60]
-    node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 708:99]
-    node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 708:80]
-    node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 709:36]
-    node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 709:75]
-    node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 709:56]
-    node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 708:113]
-    i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 708:26]
-    node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 711:59]
+    last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 679:19]
+    node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 683:45]
+    node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 683:76]
+    node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 683:58]
+    node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 685:48]
+    node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 685:77]
+    node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 685:60]
+    node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 686:21]
+    node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 686:33]
+    node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 685:94]
+    node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 687:21]
+    node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 687:33]
+    node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 687:60]
+    node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 686:62]
+    node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 691:51]
+    node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 692:26]
+    node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 692:24]
+    node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 692:56]
+    node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 692:39]
+    node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 692:77]
+    node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 691:65]
+    node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 694:61]
+    io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 694:37]
+    node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 695:55]
+    node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 697:62]
+    node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 697:60]
+    node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 697:81]
+    node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 697:79]
+    node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 697:39]
+    reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 699:54]
+    _T_826 <= div_active_in @[dec_decode_ctl.scala 699:54]
+    io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 699:21]
+    node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 702:60]
+    node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 702:99]
+    node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 702:80]
+    node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 703:36]
+    node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 703:75]
+    node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 703:56]
+    node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 702:113]
+    i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 702:26]
+    node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 705:59]
     reg _T_835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_834 : @[Reg.scala 28:19]
       _T_835 <= i0r.rd @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 711:19]
-    node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34]
-    node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57]
+    io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 705:19]
+    node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 712:34]
+    node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 712:57]
     inst rvclkhdr_12 of rvclkhdr_673 @[lib.scala 352:23]
     rvclkhdr_12.clock <= clock
     rvclkhdr_12.reset <= reset
@@ -69070,7 +69070,7 @@ circuit quasar_wrapper :
     rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     div_inst <= _T_836 @[lib.scala 358:16]
-    node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49]
+    node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 713:49]
     inst rvclkhdr_13 of rvclkhdr_674 @[lib.scala 352:23]
     rvclkhdr_13.clock <= clock
     rvclkhdr_13.reset <= reset
@@ -69079,7 +69079,7 @@ circuit quasar_wrapper :
     rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_x <= i0_inst_d @[lib.scala 358:16]
-    node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49]
+    node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 714:49]
     inst rvclkhdr_14 of rvclkhdr_675 @[lib.scala 352:23]
     rvclkhdr_14.clock <= clock
     rvclkhdr_14.reset <= reset
@@ -69088,7 +69088,7 @@ circuit quasar_wrapper :
     rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_r <= i0_inst_x @[lib.scala 358:16]
-    node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50]
+    node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 716:50]
     inst rvclkhdr_15 of rvclkhdr_676 @[lib.scala 352:23]
     rvclkhdr_15.clock <= clock
     rvclkhdr_15.reset <= reset
@@ -69097,7 +69097,7 @@ circuit quasar_wrapper :
     rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_inst_wb <= i0_inst_r @[lib.scala 358:16]
-    node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53]
+    node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 717:53]
     inst rvclkhdr_16 of rvclkhdr_677 @[lib.scala 352:23]
     rvclkhdr_16.clock <= clock
     rvclkhdr_16.reset <= reset
@@ -69106,8 +69106,8 @@ circuit quasar_wrapper :
     rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_842 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_842 <= i0_inst_wb @[lib.scala 358:16]
-    io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 723:22]
-    node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53]
+    io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 717:22]
+    node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 718:53]
     inst rvclkhdr_17 of rvclkhdr_678 @[lib.scala 352:23]
     rvclkhdr_17.clock <= clock
     rvclkhdr_17.reset <= reset
@@ -69116,7 +69116,7 @@ circuit quasar_wrapper :
     rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 358:16]
-    node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49]
+    node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 720:49]
     inst rvclkhdr_18 of rvclkhdr_679 @[lib.scala 352:23]
     rvclkhdr_18.clock <= clock
     rvclkhdr_18.reset <= reset
@@ -69125,8 +69125,8 @@ circuit quasar_wrapper :
     rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_845 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_845 <= i0_pc_wb @[lib.scala 358:16]
-    io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 726:20]
-    node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64]
+    io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 720:20]
+    node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 721:64]
     inst rvclkhdr_19 of rvclkhdr_680 @[lib.scala 352:23]
     rvclkhdr_19.clock <= clock
     rvclkhdr_19.reset <= reset
@@ -69135,7 +69135,7 @@ circuit quasar_wrapper :
     rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 358:16]
-    io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 729:27]
+    io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 723:27]
     node _T_847 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_848 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
     node _T_849 = bits(_T_847, 12, 1) @[lib.scala 52:24]
@@ -69171,124 +69171,124 @@ circuit quasar_wrapper :
     node _T_878 = bits(_T_851, 11, 0) @[lib.scala 58:94]
     node _T_879 = cat(_T_877, _T_878) @[Cat.scala 29:58]
     node temp_pred_correct_npc_x = cat(_T_879, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62]
-    io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 734:36]
-    node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 738:59]
-    node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 738:91]
-    node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 738:74]
-    node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 739:59]
-    node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 739:91]
-    node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 739:74]
-    node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 741:59]
-    node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 741:91]
-    node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 741:74]
-    node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 742:59]
-    node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 742:91]
-    node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 742:74]
-    node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 744:44]
-    node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 744:81]
-    wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 744:109]
-    _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109]
-    node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 744:61]
-    node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 744:24]
-    i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 744:18]
-    i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 744:18]
-    i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 744:18]
-    node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 745:44]
-    node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 745:83]
-    node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 745:63]
-    node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 745:24]
-    i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 745:18]
-    node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 746:44]
-    node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 746:81]
-    wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 746:109]
-    _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109]
-    node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 746:61]
-    node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 746:24]
-    i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 746:18]
-    i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 746:18]
-    i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 746:18]
-    node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 747:44]
-    node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 747:83]
-    node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 747:63]
-    node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 747:24]
-    i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 747:18]
-    i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 757:21]
-    node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 758:43]
-    node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 758:74]
-    node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 758:58]
-    node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 758:78]
-    load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 758:27]
-    node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 759:59]
-    node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 759:43]
-    node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 759:63]
-    store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 759:25]
-    store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 760:25]
-    node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 764:73]
-    node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 764:130]
-    node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 764:100]
-    node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 766:73]
-    node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 766:130]
-    node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 766:100]
-    node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:41]
-    node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:66]
-    node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 769:45]
-    node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:104]
-    node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:108]
-    node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 769:149]
-    node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:175]
-    node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:196]
-    node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 769:153]
+    node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 728:62]
+    io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 728:36]
+    node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 732:59]
+    node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 732:91]
+    node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 732:74]
+    node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 733:59]
+    node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 733:91]
+    node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 733:74]
+    node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 735:59]
+    node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 735:91]
+    node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 735:74]
+    node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 736:59]
+    node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 736:91]
+    node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 736:74]
+    node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 738:44]
+    node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 738:81]
+    wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 738:109]
+    _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
+    _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
+    _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109]
+    node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 738:61]
+    node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 738:24]
+    i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 738:18]
+    i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 738:18]
+    i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 738:18]
+    node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 739:44]
+    node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 739:83]
+    node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 739:63]
+    node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 739:24]
+    i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 739:18]
+    node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 740:44]
+    node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 740:81]
+    wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 740:109]
+    _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
+    _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
+    _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109]
+    node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 740:61]
+    node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 740:24]
+    i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 740:18]
+    i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 740:18]
+    i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 740:18]
+    node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 741:44]
+    node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 741:83]
+    node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 741:63]
+    node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 741:24]
+    i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 741:18]
+    i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 751:21]
+    node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 752:43]
+    node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 752:74]
+    node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 752:58]
+    node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 752:78]
+    load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 752:27]
+    node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 753:59]
+    node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 753:43]
+    node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 753:63]
+    store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 753:25]
+    store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 754:25]
+    node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 758:73]
+    node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 758:130]
+    node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 758:100]
+    node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 760:73]
+    node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 760:130]
+    node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 760:100]
+    node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:41]
+    node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:66]
+    node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 763:45]
+    node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:104]
+    node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:108]
+    node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 763:149]
+    node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:175]
+    node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:196]
+    node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 763:153]
     node _T_927 = cat(_T_920, _T_922) @[Cat.scala 29:58]
     node _T_928 = cat(_T_927, _T_926) @[Cat.scala 29:58]
-    i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 769:18]
-    node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:41]
-    node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:67]
-    node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 771:45]
-    node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:105]
-    node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:109]
-    node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 771:149]
-    node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:175]
-    node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:196]
-    node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 771:153]
+    i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 763:18]
+    node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:41]
+    node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:67]
+    node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 765:45]
+    node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:105]
+    node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:109]
+    node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 765:149]
+    node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:175]
+    node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:196]
+    node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 765:153]
     node _T_938 = cat(_T_931, _T_933) @[Cat.scala 29:58]
     node _T_939 = cat(_T_938, _T_937) @[Cat.scala 29:58]
-    i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 771:18]
-    node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:65]
-    node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 773:82]
-    node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:100]
-    node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 773:86]
-    node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:120]
-    node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 773:107]
-    node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 773:124]
-    node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 773:104]
+    i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 765:18]
+    node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:65]
+    node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 767:82]
+    node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 767:100]
+    node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 767:86]
+    node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:120]
+    node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 767:107]
+    node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 767:124]
+    node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 767:104]
     node _T_948 = cat(_T_940, _T_947) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 773:45]
-    node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:65]
-    node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 774:82]
-    node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 774:100]
-    node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 774:86]
-    node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:120]
-    node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 774:107]
-    node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:124]
-    node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 774:104]
+    io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 767:45]
+    node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:65]
+    node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 768:82]
+    node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 768:100]
+    node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 768:86]
+    node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:120]
+    node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 768:107]
+    node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 768:124]
+    node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 768:104]
     node _T_957 = cat(_T_949, _T_956) @[Cat.scala 29:58]
-    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 774:45]
-    node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 778:17]
-    node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 778:21]
-    node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 779:17]
-    node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 779:21]
-    node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 780:19]
-    node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 780:6]
-    node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 780:38]
-    node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 780:25]
-    node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 780:23]
-    node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 780:42]
-    node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 780:78]
+    io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 768:45]
+    node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 772:17]
+    node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 772:21]
+    node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:17]
+    node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 773:21]
+    node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 774:19]
+    node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 774:6]
+    node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 774:38]
+    node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 774:25]
+    node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 774:23]
+    node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:42]
+    node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 774:78]
     node _T_969 = mux(_T_959, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_970 = mux(_T_961, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_971 = mux(_T_968, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -69296,18 +69296,18 @@ circuit quasar_wrapper :
     node _T_973 = or(_T_972, _T_971) @[Mux.scala 27:72]
     wire _T_974 : UInt<32> @[Mux.scala 27:72]
     _T_974 <= _T_973 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 777:42]
-    node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 783:17]
-    node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 783:21]
-    node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 784:17]
-    node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 784:21]
-    node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 785:19]
-    node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 785:6]
-    node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 785:38]
-    node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 785:25]
-    node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 785:23]
-    node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 785:42]
-    node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 785:78]
+    io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 771:42]
+    node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 777:17]
+    node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 777:21]
+    node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 778:17]
+    node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 778:21]
+    node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 779:19]
+    node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 779:6]
+    node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 779:38]
+    node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 779:25]
+    node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 779:23]
+    node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 779:42]
+    node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 779:78]
     node _T_986 = mux(_T_976, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_987 = mux(_T_978, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_988 = mux(_T_985, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -69315,33 +69315,33 @@ circuit quasar_wrapper :
     node _T_990 = or(_T_989, _T_988) @[Mux.scala 27:72]
     wire _T_991 : UInt<32> @[Mux.scala 27:72]
     _T_991 <= _T_990 @[Mux.scala 27:72]
-    io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 782:42]
-    node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68]
-    node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 787:50]
-    node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89]
-    node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:87]
-    node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123]
-    node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 787:121]
-    node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140]
-    io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 787:26]
-    node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6]
-    node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 789:38]
-    node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 789:50]
-    node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 789:64]
-    node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 789:81]
-    node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 790:6]
-    node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 790:38]
-    node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 790:50]
-    node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 790:65]
-    node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 790:85]
-    node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 790:95]
+    io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 776:42]
+    node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 781:68]
+    node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 781:50]
+    node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 781:89]
+    node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 781:87]
+    node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 781:123]
+    node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 781:121]
+    node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 781:140]
+    io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 781:26]
+    node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 783:6]
+    node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 783:38]
+    node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 783:50]
+    node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 783:64]
+    node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 783:81]
+    node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 784:6]
+    node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 784:38]
+    node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 784:50]
+    node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 784:65]
+    node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 784:85]
+    node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 784:95]
     node _T_1010 = cat(_T_1008, _T_1009) @[Cat.scala 29:58]
     node _T_1011 = mux(_T_1002, _T_1003, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_1012 = mux(_T_1007, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_1013 = or(_T_1011, _T_1012) @[Mux.scala 27:72]
     wire _T_1014 : UInt<12> @[Mux.scala 27:72]
     _T_1014 <= _T_1013 @[Mux.scala 27:72]
-    io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 788:23]
+    io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 782:23]
     
   extmodule gated_latch_681 : 
     output Q : Clock
@@ -81803,6 +81803,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_761 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_761 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_761 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_762 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_762 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_762 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module dbg : 
     input clock : Clock
     input reset : AsyncReset
@@ -82299,10 +82347,14 @@ circuit quasar_wrapper :
     node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58]
     node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32]
     node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59]
-    reg command_reg : UInt, clock with : (reset => (_T_302, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when command_wren : @[Reg.scala 28:19]
-      command_reg <= command_din @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
+    inst rvclkhdr_5 of rvclkhdr_760 @[lib.scala 352:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= _T_302
+    rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
+    rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17]
+    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
+    reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_302, UInt<1>("h00"))) @[lib.scala 358:16]
+    command_reg <= command_din @[lib.scala 358:16]
     node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39]
     node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77]
     node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58]
@@ -82323,10 +82375,14 @@ circuit quasar_wrapper :
     node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64]
     node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30]
     node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57]
-    reg data0_reg : UInt, clock with : (reset => (_T_318, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when data0_reg_wren : @[Reg.scala 28:19]
-      data0_reg <= data0_din @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
+    inst rvclkhdr_6 of rvclkhdr_761 @[lib.scala 352:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= _T_318
+    rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
+    rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17]
+    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
+    reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[lib.scala 358:16]
+    data0_reg <= data0_din @[lib.scala 358:16]
     node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39]
     node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77]
     node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58]
@@ -82337,13 +82393,13 @@ circuit quasar_wrapper :
     node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44]
     node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27]
     node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54]
-    inst rvclkhdr_5 of rvclkhdr_760 @[lib.scala 352:23]
-    rvclkhdr_5.clock <= clock
-    rvclkhdr_5.reset <= _T_326
-    rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_5.io.en <= data1_reg_wren @[lib.scala 355:17]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_327 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16]
+    inst rvclkhdr_7 of rvclkhdr_762 @[lib.scala 352:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= _T_326
+    rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
+    rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17]
+    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
+    reg _T_327 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_327 <= data1_din @[lib.scala 358:16]
     data1_reg <= _T_327 @[dbg.scala 252:13]
     wire dbg_nxtstate : UInt<3>
@@ -82919,54 +82975,6 @@ circuit quasar_wrapper :
     io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 450:39]
     io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 451:39]
     
-  extmodule gated_latch_761 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_761 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_761 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_762 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_762 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_762 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_763 : 
     output Q : Clock
     input CK : Clock
@@ -83399,13 +83407,61 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_781 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_781 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_781 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_782 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_782 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_782 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module exu_alu_ctl : 
     input clock : Clock
     input reset : AsyncReset
     output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}}
     
     node _T = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 30:80]
-    inst rvclkhdr of rvclkhdr_779 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_781 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -83417,7 +83473,7 @@ circuit quasar_wrapper :
     wire result : UInt<32>
     result <= UInt<1>("h00")
     node _T_2 = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 32:62]
-    inst rvclkhdr_1 of rvclkhdr_780 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_782 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -83869,101 +83925,53 @@ circuit quasar_wrapper :
     node _T_302 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu_alu_ctl.scala 111:141]
     node _T_303 = and(_T_301, _T_302) @[exu_alu_ctl.scala 111:139]
     io.flush_upper_out <= _T_303 @[exu_alu_ctl.scala 111:26]
-    node _T_304 = or(io.i0_ap.jal, cond_mispredict) @[exu_alu_ctl.scala 113:45]
-    node _T_305 = or(_T_304, target_mispredict) @[exu_alu_ctl.scala 113:63]
-    node _T_306 = and(_T_305, io.dec_alu.dec_i0_alu_decode_d) @[exu_alu_ctl.scala 113:84]
-    node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[exu_alu_ctl.scala 113:119]
-    node _T_308 = and(_T_306, _T_307) @[exu_alu_ctl.scala 113:117]
-    node _T_309 = or(_T_308, io.dec_tlu_flush_lower_r) @[exu_alu_ctl.scala 113:139]
-    io.flush_final_out <= _T_309 @[exu_alu_ctl.scala 113:26]
+    node _T_304 = or(io.i0_ap.jal, cond_mispredict) @[exu_alu_ctl.scala 112:45]
+    node _T_305 = or(_T_304, target_mispredict) @[exu_alu_ctl.scala 112:63]
+    node _T_306 = and(_T_305, io.dec_alu.dec_i0_alu_decode_d) @[exu_alu_ctl.scala 112:84]
+    node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[exu_alu_ctl.scala 112:119]
+    node _T_308 = and(_T_306, _T_307) @[exu_alu_ctl.scala 112:117]
+    node _T_309 = or(_T_308, io.dec_tlu_flush_lower_r) @[exu_alu_ctl.scala 112:139]
+    io.flush_final_out <= _T_309 @[exu_alu_ctl.scala 112:26]
     wire newhist : UInt<2>
     newhist <= UInt<1>("h00")
-    node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 117:40]
-    node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[exu_alu_ctl.scala 117:65]
-    node _T_312 = and(_T_310, _T_311) @[exu_alu_ctl.scala 117:44]
-    node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[exu_alu_ctl.scala 117:92]
-    node _T_314 = eq(_T_313, UInt<1>("h00")) @[exu_alu_ctl.scala 117:73]
-    node _T_315 = and(_T_314, actual_taken) @[exu_alu_ctl.scala 117:96]
-    node _T_316 = or(_T_312, _T_315) @[exu_alu_ctl.scala 117:70]
-    node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 118:25]
-    node _T_318 = eq(_T_317, UInt<1>("h00")) @[exu_alu_ctl.scala 118:6]
-    node _T_319 = eq(actual_taken, UInt<1>("h00")) @[exu_alu_ctl.scala 118:31]
-    node _T_320 = and(_T_318, _T_319) @[exu_alu_ctl.scala 118:29]
-    node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 118:68]
-    node _T_322 = and(_T_321, actual_taken) @[exu_alu_ctl.scala 118:72]
-    node _T_323 = or(_T_320, _T_322) @[exu_alu_ctl.scala 118:47]
+    node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 116:40]
+    node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[exu_alu_ctl.scala 116:65]
+    node _T_312 = and(_T_310, _T_311) @[exu_alu_ctl.scala 116:44]
+    node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[exu_alu_ctl.scala 116:92]
+    node _T_314 = eq(_T_313, UInt<1>("h00")) @[exu_alu_ctl.scala 116:73]
+    node _T_315 = and(_T_314, actual_taken) @[exu_alu_ctl.scala 116:96]
+    node _T_316 = or(_T_312, _T_315) @[exu_alu_ctl.scala 116:70]
+    node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 117:25]
+    node _T_318 = eq(_T_317, UInt<1>("h00")) @[exu_alu_ctl.scala 117:6]
+    node _T_319 = eq(actual_taken, UInt<1>("h00")) @[exu_alu_ctl.scala 117:31]
+    node _T_320 = and(_T_318, _T_319) @[exu_alu_ctl.scala 117:29]
+    node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[exu_alu_ctl.scala 117:68]
+    node _T_322 = and(_T_321, actual_taken) @[exu_alu_ctl.scala 117:72]
+    node _T_323 = or(_T_320, _T_322) @[exu_alu_ctl.scala 117:47]
     node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
-    newhist <= _T_324 @[exu_alu_ctl.scala 117:14]
-    io.predict_p_out.bits.way <= io.pp_in.bits.way @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[exu_alu_ctl.scala 120:30]
-    io.predict_p_out.valid <= io.pp_in.valid @[exu_alu_ctl.scala 120:30]
-    node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[exu_alu_ctl.scala 121:38]
-    node _T_326 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu_alu_ctl.scala 121:58]
-    node _T_327 = and(_T_325, _T_326) @[exu_alu_ctl.scala 121:56]
-    node _T_328 = or(cond_mispredict, target_mispredict) @[exu_alu_ctl.scala 121:103]
-    node _T_329 = and(_T_327, _T_328) @[exu_alu_ctl.scala 121:84]
-    io.predict_p_out.bits.misp <= _T_329 @[exu_alu_ctl.scala 121:35]
-    io.predict_p_out.bits.ataken <= actual_taken @[exu_alu_ctl.scala 122:35]
-    io.predict_p_out.bits.hist <= newhist @[exu_alu_ctl.scala 123:35]
-    
-  extmodule gated_latch_781 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_781 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_781 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_782 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_782 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_782 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    newhist <= _T_324 @[exu_alu_ctl.scala 116:14]
+    io.predict_p_out.bits.way <= io.pp_in.bits.way @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[exu_alu_ctl.scala 119:30]
+    io.predict_p_out.valid <= io.pp_in.valid @[exu_alu_ctl.scala 119:30]
+    node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[exu_alu_ctl.scala 120:38]
+    node _T_326 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu_alu_ctl.scala 120:58]
+    node _T_327 = and(_T_325, _T_326) @[exu_alu_ctl.scala 120:56]
+    node _T_328 = or(cond_mispredict, target_mispredict) @[exu_alu_ctl.scala 120:103]
+    node _T_329 = and(_T_327, _T_328) @[exu_alu_ctl.scala 120:84]
+    io.predict_p_out.bits.misp <= _T_329 @[exu_alu_ctl.scala 120:35]
+    io.predict_p_out.bits.ataken <= actual_taken @[exu_alu_ctl.scala 121:35]
+    io.predict_p_out.bits.hist <= newhist @[exu_alu_ctl.scala 122:35]
     
   extmodule gated_latch_783 : 
     output Q : Clock
@@ -83989,77 +83997,6 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
-  module exu_mul_ctl : 
-    input clock : Clock
-    input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
-    
-    wire rs1_ext_in : SInt<33>
-    rs1_ext_in <= asSInt(UInt<1>("h00"))
-    wire rs2_ext_in : SInt<33>
-    rs2_ext_in <= asSInt(UInt<1>("h00"))
-    wire rs1_x : SInt<33>
-    rs1_x <= asSInt(UInt<1>("h00"))
-    wire rs2_x : SInt<33>
-    rs2_x <= asSInt(UInt<1>("h00"))
-    wire prod_x : SInt<66>
-    prod_x <= asSInt(UInt<1>("h00"))
-    wire low_x : UInt<1>
-    low_x <= UInt<1>("h00")
-    node _T = bits(io.rs1_in, 31, 31) @[exu_mul_ctl.scala 26:55]
-    node _T_1 = and(io.mul_p.bits.rs1_sign, _T) @[exu_mul_ctl.scala 26:44]
-    node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
-    node _T_3 = asSInt(_T_2) @[exu_mul_ctl.scala 26:71]
-    rs1_ext_in <= _T_3 @[exu_mul_ctl.scala 26:14]
-    node _T_4 = bits(io.rs2_in, 31, 31) @[exu_mul_ctl.scala 27:55]
-    node _T_5 = and(io.mul_p.bits.rs2_sign, _T_4) @[exu_mul_ctl.scala 27:44]
-    node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
-    node _T_7 = asSInt(_T_6) @[exu_mul_ctl.scala 27:71]
-    rs2_ext_in <= _T_7 @[exu_mul_ctl.scala 27:14]
-    node _T_8 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 29:52]
-    inst rvclkhdr of rvclkhdr_781 @[lib.scala 352:23]
-    rvclkhdr.clock <= clock
-    rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr.io.en <= _T_8 @[lib.scala 355:17]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_9 <= io.mul_p.bits.low @[lib.scala 358:16]
-    low_x <= _T_9 @[exu_mul_ctl.scala 29:9]
-    node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 30:44]
-    inst rvclkhdr_1 of rvclkhdr_782 @[lib.scala 372:23]
-    rvclkhdr_1.clock <= clock
-    rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 374:18]
-    rvclkhdr_1.io.en <= _T_10 @[lib.scala 375:17]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 376:24]
-    reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 378:16]
-    _T_11 <= rs1_ext_in @[lib.scala 378:16]
-    rs1_x <= _T_11 @[exu_mul_ctl.scala 30:9]
-    node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 31:45]
-    inst rvclkhdr_2 of rvclkhdr_783 @[lib.scala 372:23]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 374:18]
-    rvclkhdr_2.io.en <= _T_12 @[lib.scala 375:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 376:24]
-    reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 378:16]
-    _T_13 <= rs2_ext_in @[lib.scala 378:16]
-    rs2_x <= _T_13 @[exu_mul_ctl.scala 31:9]
-    node _T_14 = mul(rs1_x, rs2_x) @[exu_mul_ctl.scala 33:20]
-    prod_x <= _T_14 @[exu_mul_ctl.scala 33:10]
-    node _T_15 = bits(low_x, 0, 0) @[exu_mul_ctl.scala 34:36]
-    node _T_16 = eq(_T_15, UInt<1>("h00")) @[exu_mul_ctl.scala 34:29]
-    node _T_17 = bits(prod_x, 63, 32) @[exu_mul_ctl.scala 34:52]
-    node _T_18 = bits(low_x, 0, 0) @[exu_mul_ctl.scala 34:67]
-    node _T_19 = bits(prod_x, 31, 0) @[exu_mul_ctl.scala 34:83]
-    node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
-    wire _T_23 : UInt<32> @[Mux.scala 27:72]
-    _T_23 <= _T_22 @[Mux.scala 27:72]
-    io.result_x <= _T_23 @[exu_mul_ctl.scala 34:15]
-    
   extmodule gated_latch_784 : 
     output Q : Clock
     input CK : Clock
@@ -84108,6 +84045,77 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  module exu_mul_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
+    
+    wire rs1_ext_in : SInt<33>
+    rs1_ext_in <= asSInt(UInt<1>("h00"))
+    wire rs2_ext_in : SInt<33>
+    rs2_ext_in <= asSInt(UInt<1>("h00"))
+    wire rs1_x : SInt<33>
+    rs1_x <= asSInt(UInt<1>("h00"))
+    wire rs2_x : SInt<33>
+    rs2_x <= asSInt(UInt<1>("h00"))
+    wire prod_x : SInt<66>
+    prod_x <= asSInt(UInt<1>("h00"))
+    wire low_x : UInt<1>
+    low_x <= UInt<1>("h00")
+    node _T = bits(io.rs1_in, 31, 31) @[exu_mul_ctl.scala 26:55]
+    node _T_1 = and(io.mul_p.bits.rs1_sign, _T) @[exu_mul_ctl.scala 26:44]
+    node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
+    node _T_3 = asSInt(_T_2) @[exu_mul_ctl.scala 26:71]
+    rs1_ext_in <= _T_3 @[exu_mul_ctl.scala 26:14]
+    node _T_4 = bits(io.rs2_in, 31, 31) @[exu_mul_ctl.scala 27:55]
+    node _T_5 = and(io.mul_p.bits.rs2_sign, _T_4) @[exu_mul_ctl.scala 27:44]
+    node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
+    node _T_7 = asSInt(_T_6) @[exu_mul_ctl.scala 27:71]
+    rs2_ext_in <= _T_7 @[exu_mul_ctl.scala 27:14]
+    node _T_8 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 29:52]
+    inst rvclkhdr of rvclkhdr_783 @[lib.scala 352:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 354:18]
+    rvclkhdr.io.en <= _T_8 @[lib.scala 355:17]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
+    reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
+    _T_9 <= io.mul_p.bits.low @[lib.scala 358:16]
+    low_x <= _T_9 @[exu_mul_ctl.scala 29:9]
+    node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 30:44]
+    inst rvclkhdr_1 of rvclkhdr_784 @[lib.scala 372:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 374:18]
+    rvclkhdr_1.io.en <= _T_10 @[lib.scala 375:17]
+    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 376:24]
+    reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 378:16]
+    _T_11 <= rs1_ext_in @[lib.scala 378:16]
+    rs1_x <= _T_11 @[exu_mul_ctl.scala 30:9]
+    node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 31:45]
+    inst rvclkhdr_2 of rvclkhdr_785 @[lib.scala 372:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 374:18]
+    rvclkhdr_2.io.en <= _T_12 @[lib.scala 375:17]
+    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 376:24]
+    reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 378:16]
+    _T_13 <= rs2_ext_in @[lib.scala 378:16]
+    rs2_x <= _T_13 @[exu_mul_ctl.scala 31:9]
+    node _T_14 = mul(rs1_x, rs2_x) @[exu_mul_ctl.scala 33:20]
+    prod_x <= _T_14 @[exu_mul_ctl.scala 33:10]
+    node _T_15 = bits(low_x, 0, 0) @[exu_mul_ctl.scala 34:36]
+    node _T_16 = eq(_T_15, UInt<1>("h00")) @[exu_mul_ctl.scala 34:29]
+    node _T_17 = bits(prod_x, 63, 32) @[exu_mul_ctl.scala 34:52]
+    node _T_18 = bits(low_x, 0, 0) @[exu_mul_ctl.scala 34:67]
+    node _T_19 = bits(prod_x, 31, 0) @[exu_mul_ctl.scala 34:83]
+    node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
+    wire _T_23 : UInt<32> @[Mux.scala 27:72]
+    _T_23 <= _T_22 @[Mux.scala 27:72]
+    io.result_x <= _T_23 @[exu_mul_ctl.scala 34:15]
+    
   extmodule gated_latch_786 : 
     output Q : Clock
     input CK : Clock
@@ -84156,6 +84164,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_788 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_788 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_788 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_789 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_789 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_789 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module exu_div_ctl : 
     input clock : Clock
     input reset : AsyncReset
@@ -85826,7 +85882,7 @@ circuit quasar_wrapper :
     _T_1469 <= _T_1468 @[Mux.scala 27:72]
     io.exu_div_result <= _T_1469 @[exu_div_ctl.scala 186:21]
     node _T_1470 = bits(div_clken, 0, 0) @[exu_div_ctl.scala 192:46]
-    inst rvclkhdr of rvclkhdr_784 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_786 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
@@ -85887,7 +85943,7 @@ circuit quasar_wrapper :
     _T_1492 <= shortq_shift @[exu_div_ctl.scala 206:31]
     shortq_shift_xx <= _T_1492 @[exu_div_ctl.scala 206:21]
     node _T_1493 = bits(qff_enable, 0, 0) @[exu_div_ctl.scala 208:35]
-    inst rvclkhdr_1 of rvclkhdr_785 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_787 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -85897,7 +85953,7 @@ circuit quasar_wrapper :
     _T_1494 <= q_in @[lib.scala 358:16]
     q_ff <= _T_1494 @[exu_div_ctl.scala 208:8]
     node _T_1495 = bits(aff_enable, 0, 0) @[exu_div_ctl.scala 209:35]
-    inst rvclkhdr_2 of rvclkhdr_786 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_788 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
@@ -85911,7 +85967,7 @@ circuit quasar_wrapper :
     node _T_1499 = and(_T_1497, _T_1498) @[exu_div_ctl.scala 210:52]
     node _T_1500 = cat(_T_1499, io.divisor) @[Cat.scala 29:58]
     node _T_1501 = bits(io.dec_div.div_p.valid, 0, 0) @[exu_div_ctl.scala 210:106]
-    inst rvclkhdr_3 of rvclkhdr_787 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_789 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
@@ -85956,7 +86012,7 @@ circuit quasar_wrapper :
     node _T = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58]
     node predpipe_d = cat(_T, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58]
     node _T_1 = bits(x_data_en, 0, 0) @[exu.scala 63:59]
-    inst rvclkhdr of rvclkhdr_761 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_763 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -85965,7 +86021,7 @@ circuit quasar_wrapper :
     reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_flush_path_x <= i0_flush_path_d @[lib.scala 358:16]
     node _T_2 = bits(x_data_en, 0, 0) @[exu.scala 64:89]
-    inst rvclkhdr_1 of rvclkhdr_762 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_764 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -85975,7 +86031,7 @@ circuit quasar_wrapper :
     _T_3 <= csr_rs1_in_d @[lib.scala 358:16]
     io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_3 @[exu.scala 64:57]
     node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 65:83]
-    inst rvclkhdr_2 of rvclkhdr_763 @[lib.scala 362:23]
+    inst rvclkhdr_2 of rvclkhdr_765 @[lib.scala 362:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 364:18]
@@ -86026,7 +86082,7 @@ circuit quasar_wrapper :
     i0_predict_p_x.bits.misp <= _T_6.bits.misp @[exu.scala 65:49]
     i0_predict_p_x.valid <= _T_6.valid @[exu.scala 65:49]
     node _T_7 = bits(x_data_en, 0, 0) @[exu.scala 66:70]
-    inst rvclkhdr_3 of rvclkhdr_764 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_766 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
@@ -86035,7 +86091,7 @@ circuit quasar_wrapper :
     reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     predpipe_x <= predpipe_d @[lib.scala 358:16]
     node _T_8 = bits(r_data_en, 0, 0) @[exu.scala 67:79]
-    inst rvclkhdr_4 of rvclkhdr_765 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_767 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -86044,7 +86100,7 @@ circuit quasar_wrapper :
     reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     predpipe_r <= predpipe_x @[lib.scala 358:16]
     node _T_9 = bits(x_ctl_en, 0, 0) @[exu.scala 68:80]
-    inst rvclkhdr_5 of rvclkhdr_766 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_768 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -86053,7 +86109,7 @@ circuit quasar_wrapper :
     reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     ghr_x <= ghr_x_ns @[lib.scala 358:16]
     node _T_10 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75]
-    inst rvclkhdr_6 of rvclkhdr_767 @[lib.scala 352:23]
+    inst rvclkhdr_6 of rvclkhdr_769 @[lib.scala 352:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
@@ -86062,7 +86118,7 @@ circuit quasar_wrapper :
     reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[lib.scala 358:16]
     node _T_11 = bits(x_ctl_en, 0, 0) @[exu.scala 70:60]
-    inst rvclkhdr_7 of rvclkhdr_768 @[lib.scala 352:23]
+    inst rvclkhdr_7 of rvclkhdr_770 @[lib.scala 352:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
@@ -86071,7 +86127,7 @@ circuit quasar_wrapper :
     reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_flush_upper_x <= i0_flush_upper_d @[lib.scala 358:16]
     node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 71:78]
-    inst rvclkhdr_8 of rvclkhdr_769 @[lib.scala 352:23]
+    inst rvclkhdr_8 of rvclkhdr_771 @[lib.scala 352:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 354:18]
@@ -86080,7 +86136,7 @@ circuit quasar_wrapper :
     reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_taken_x <= i0_taken_d @[lib.scala 358:16]
     node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 72:78]
-    inst rvclkhdr_9 of rvclkhdr_770 @[lib.scala 352:23]
+    inst rvclkhdr_9 of rvclkhdr_772 @[lib.scala 352:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 354:18]
@@ -86089,7 +86145,7 @@ circuit quasar_wrapper :
     reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_valid_x <= i0_valid_d @[lib.scala 358:16]
     node _T_14 = bits(r_ctl_en, 0, 0) @[exu.scala 73:58]
-    inst rvclkhdr_10 of rvclkhdr_771 @[lib.scala 362:23]
+    inst rvclkhdr_10 of rvclkhdr_773 @[lib.scala 362:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 364:18]
@@ -86141,7 +86197,7 @@ circuit quasar_wrapper :
     i0_pp_r.valid <= _T_16.valid @[exu.scala 73:25]
     node _T_17 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:85]
     node _T_18 = bits(r_ctl_en, 0, 0) @[exu.scala 74:101]
-    inst rvclkhdr_11 of rvclkhdr_772 @[lib.scala 352:23]
+    inst rvclkhdr_11 of rvclkhdr_774 @[lib.scala 352:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 354:18]
@@ -86150,7 +86206,7 @@ circuit quasar_wrapper :
     reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     pred_temp1 <= _T_17 @[lib.scala 358:16]
     node _T_19 = bits(r_ctl_en, 0, 0) @[exu.scala 75:75]
-    inst rvclkhdr_12 of rvclkhdr_773 @[lib.scala 352:23]
+    inst rvclkhdr_12 of rvclkhdr_775 @[lib.scala 352:23]
     rvclkhdr_12.clock <= clock
     rvclkhdr_12.reset <= reset
     rvclkhdr_12.io.clk <= clock @[lib.scala 354:18]
@@ -86159,7 +86215,7 @@ circuit quasar_wrapper :
     reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[lib.scala 358:16]
     node _T_20 = bits(r_data_en, 0, 0) @[exu.scala 76:68]
-    inst rvclkhdr_13 of rvclkhdr_774 @[lib.scala 352:23]
+    inst rvclkhdr_13 of rvclkhdr_776 @[lib.scala 352:23]
     rvclkhdr_13.clock <= clock
     rvclkhdr_13.reset <= reset
     rvclkhdr_13.io.clk <= clock @[lib.scala 354:18]
@@ -86169,7 +86225,7 @@ circuit quasar_wrapper :
     i0_flush_path_upper_r <= i0_flush_path_x @[lib.scala 358:16]
     node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:97]
     node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 77:115]
-    inst rvclkhdr_14 of rvclkhdr_775 @[lib.scala 352:23]
+    inst rvclkhdr_14 of rvclkhdr_777 @[lib.scala 352:23]
     rvclkhdr_14.clock <= clock
     rvclkhdr_14.reset <= reset
     rvclkhdr_14.io.clk <= clock @[lib.scala 354:18]
@@ -86204,7 +86260,7 @@ circuit quasar_wrapper :
       skip @[exu.scala 80:58]
     else : @[exu.scala 84:14]
       node _T_33 = bits(data_gate_en, 0, 0) @[exu.scala 85:65]
-      inst rvclkhdr_15 of rvclkhdr_776 @[lib.scala 352:23]
+      inst rvclkhdr_15 of rvclkhdr_778 @[lib.scala 352:23]
       rvclkhdr_15.clock <= clock
       rvclkhdr_15.reset <= reset
       rvclkhdr_15.io.clk <= clock @[lib.scala 354:18]
@@ -86214,7 +86270,7 @@ circuit quasar_wrapper :
       _T_34 <= ghr_d_ns @[lib.scala 358:16]
       ghr_d <= _T_34 @[exu.scala 85:33]
       node _T_35 = bits(data_gate_en, 0, 0) @[exu.scala 86:82]
-      inst rvclkhdr_16 of rvclkhdr_777 @[lib.scala 352:23]
+      inst rvclkhdr_16 of rvclkhdr_779 @[lib.scala 352:23]
       rvclkhdr_16.clock <= clock
       rvclkhdr_16.reset <= reset
       rvclkhdr_16.io.clk <= clock @[lib.scala 354:18]
@@ -86224,7 +86280,7 @@ circuit quasar_wrapper :
       _T_36 <= io.dec_exu.decode_exu.mul_p.valid @[lib.scala 358:16]
       mul_valid_x <= _T_36 @[exu.scala 86:25]
       node _T_37 = bits(data_gate_en, 0, 0) @[exu.scala 87:89]
-      inst rvclkhdr_17 of rvclkhdr_778 @[lib.scala 352:23]
+      inst rvclkhdr_17 of rvclkhdr_780 @[lib.scala 352:23]
       rvclkhdr_17.clock <= clock
       rvclkhdr_17.reset <= reset
       rvclkhdr_17.io.clk <= clock @[lib.scala 354:18]
@@ -87368,7 +87424,7 @@ circuit quasar_wrapper :
     node _T_253 = or(_T_248, _T_252) @[lsu_lsc_ctl.scala 267:144]
     io.lsu_result_corr_r <= _T_253 @[lsu_lsc_ctl.scala 264:27]
     
-  extmodule gated_latch_788 : 
+  extmodule gated_latch_790 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -87377,12 +87433,12 @@ circuit quasar_wrapper :
     defname = gated_latch
     
     
-  module rvclkhdr_788 : 
+  module rvclkhdr_790 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_788 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_790 @[lib.scala 318:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -87392,7 +87448,7 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
-  extmodule gated_latch_789 : 
+  extmodule gated_latch_791 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -87401,12 +87457,12 @@ circuit quasar_wrapper :
     defname = gated_latch
     
     
-  module rvclkhdr_789 : 
+  module rvclkhdr_791 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_789 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_791 @[lib.scala 318:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -88315,7 +88371,7 @@ circuit quasar_wrapper :
     node _T_824 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 171:49]
     node _T_825 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 171:90]
     node _T_826 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 171:116]
-    inst rvclkhdr of rvclkhdr_788 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_790 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -88326,7 +88382,7 @@ circuit quasar_wrapper :
     node _T_827 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 172:49]
     node _T_828 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 172:90]
     node _T_829 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 172:116]
-    inst rvclkhdr_1 of rvclkhdr_789 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_791 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -89477,54 +89533,6 @@ circuit quasar_wrapper :
     _T_1883 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 280:61]
     io.lsu_dccm_rden_r <= _T_1883 @[lsu_dccm_ctl.scala 280:24]
     
-  extmodule gated_latch_790 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_790 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_790 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_791 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_791 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_791 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_792 : 
     output Q : Clock
     input CK : Clock
@@ -89669,6 +89677,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_798 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_798 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_798 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_799 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_799 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_799 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module lsu_stbuf : 
     input clock : Clock
     input reset : AsyncReset
@@ -90502,7 +90558,7 @@ circuit quasar_wrapper :
     stbuf_byteen[3] <= _T_662 @[lsu_stbuf.scala 165:16]
     node _T_663 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 167:56]
     node _T_664 = bits(_T_663, 0, 0) @[lsu_stbuf.scala 167:66]
-    inst rvclkhdr of rvclkhdr_790 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_792 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -90513,7 +90569,7 @@ circuit quasar_wrapper :
     stbuf_addr[0] <= _T_665 @[lsu_stbuf.scala 167:19]
     node _T_666 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 168:56]
     node _T_667 = bits(_T_666, 0, 0) @[lsu_stbuf.scala 168:66]
-    inst rvclkhdr_1 of rvclkhdr_791 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_793 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -90524,7 +90580,7 @@ circuit quasar_wrapper :
     stbuf_data[0] <= _T_668 @[lsu_stbuf.scala 168:19]
     node _T_669 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 167:56]
     node _T_670 = bits(_T_669, 0, 0) @[lsu_stbuf.scala 167:66]
-    inst rvclkhdr_2 of rvclkhdr_792 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_794 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
@@ -90535,7 +90591,7 @@ circuit quasar_wrapper :
     stbuf_addr[1] <= _T_671 @[lsu_stbuf.scala 167:19]
     node _T_672 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 168:56]
     node _T_673 = bits(_T_672, 0, 0) @[lsu_stbuf.scala 168:66]
-    inst rvclkhdr_3 of rvclkhdr_793 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_795 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
@@ -90546,7 +90602,7 @@ circuit quasar_wrapper :
     stbuf_data[1] <= _T_674 @[lsu_stbuf.scala 168:19]
     node _T_675 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 167:56]
     node _T_676 = bits(_T_675, 0, 0) @[lsu_stbuf.scala 167:66]
-    inst rvclkhdr_4 of rvclkhdr_794 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_796 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -90557,7 +90613,7 @@ circuit quasar_wrapper :
     stbuf_addr[2] <= _T_677 @[lsu_stbuf.scala 167:19]
     node _T_678 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 168:56]
     node _T_679 = bits(_T_678, 0, 0) @[lsu_stbuf.scala 168:66]
-    inst rvclkhdr_5 of rvclkhdr_795 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_797 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -90568,7 +90624,7 @@ circuit quasar_wrapper :
     stbuf_data[2] <= _T_680 @[lsu_stbuf.scala 168:19]
     node _T_681 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 167:56]
     node _T_682 = bits(_T_681, 0, 0) @[lsu_stbuf.scala 167:66]
-    inst rvclkhdr_6 of rvclkhdr_796 @[lib.scala 352:23]
+    inst rvclkhdr_6 of rvclkhdr_798 @[lib.scala 352:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
@@ -90579,7 +90635,7 @@ circuit quasar_wrapper :
     stbuf_addr[3] <= _T_683 @[lsu_stbuf.scala 167:19]
     node _T_684 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 168:56]
     node _T_685 = bits(_T_684, 0, 0) @[lsu_stbuf.scala 168:66]
-    inst rvclkhdr_7 of rvclkhdr_797 @[lib.scala 352:23]
+    inst rvclkhdr_7 of rvclkhdr_799 @[lib.scala 352:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
@@ -91341,7 +91397,7 @@ circuit quasar_wrapper :
     node _T_1314 = cat(_T_1313, _T_1312) @[Cat.scala 29:58]
     io.stbuf_fwddata_hi_m <= _T_1314 @[lsu_stbuf.scala 266:25]
     
-  extmodule gated_latch_798 : 
+  extmodule gated_latch_800 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -91350,12 +91406,12 @@ circuit quasar_wrapper :
     defname = gated_latch
     
     
-  module rvclkhdr_798 : 
+  module rvclkhdr_800 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_798 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_800 @[lib.scala 318:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -91365,7 +91421,7 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
-  extmodule gated_latch_799 : 
+  extmodule gated_latch_801 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -91374,12 +91430,12 @@ circuit quasar_wrapper :
     defname = gated_latch
     
     
-  module rvclkhdr_799 : 
+  module rvclkhdr_801 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_799 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_801 @[lib.scala 318:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -92927,7 +92983,7 @@ circuit quasar_wrapper :
     io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 153:28]
     io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 154:28]
     io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 155:28]
-    inst rvclkhdr of rvclkhdr_798 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_800 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -92936,7 +92992,7 @@ circuit quasar_wrapper :
     reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_1164 <= io.sec_data_hi_r @[lib.scala 358:16]
     io.sec_data_hi_r_ff <= _T_1164 @[lsu_ecc.scala 157:23]
-    inst rvclkhdr_1 of rvclkhdr_799 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_801 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -94200,54 +94256,6 @@ circuit quasar_wrapper :
     node _T_1109 = cat(_T_1108, _T_305) @[Cat.scala 29:58]
     io.lsu_trigger_match_m <= _T_1109 @[lsu_trigger.scala 18:26]
     
-  extmodule gated_latch_800 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_800 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_800 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_801 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_801 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_801 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_802 : 
     output Q : Clock
     input CK : Clock
@@ -94488,6 +94496,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_812 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_812 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_812 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_813 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_813 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_813 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module lsu_clkdomain : 
     input clock : Clock
     input reset : AsyncReset
@@ -94544,7 +94600,7 @@ circuit quasar_wrapper :
     _T_24 <= lsu_c1_r_clken @[lsu_clkdomain.scala 83:67]
     lsu_c1_r_clken_q <= _T_24 @[lsu_clkdomain.scala 83:26]
     node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 85:59]
-    inst rvclkhdr of rvclkhdr_800 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_802 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
@@ -94552,7 +94608,7 @@ circuit quasar_wrapper :
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 85:26]
     node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 86:59]
-    inst rvclkhdr_1 of rvclkhdr_801 @[lib.scala 327:22]
+    inst rvclkhdr_1 of rvclkhdr_803 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
@@ -94560,7 +94616,7 @@ circuit quasar_wrapper :
     rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 86:26]
     node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59]
-    inst rvclkhdr_2 of rvclkhdr_802 @[lib.scala 327:22]
+    inst rvclkhdr_2 of rvclkhdr_804 @[lib.scala 327:22]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 328:17]
@@ -94568,7 +94624,7 @@ circuit quasar_wrapper :
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 87:26]
     node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59]
-    inst rvclkhdr_3 of rvclkhdr_803 @[lib.scala 327:22]
+    inst rvclkhdr_3 of rvclkhdr_805 @[lib.scala 327:22]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 328:17]
@@ -94576,7 +94632,7 @@ circuit quasar_wrapper :
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 88:26]
     node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 89:65]
-    inst rvclkhdr_4 of rvclkhdr_804 @[lib.scala 327:22]
+    inst rvclkhdr_4 of rvclkhdr_806 @[lib.scala 327:22]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 328:17]
@@ -94584,7 +94640,7 @@ circuit quasar_wrapper :
     rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 89:26]
     node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 90:65]
-    inst rvclkhdr_5 of rvclkhdr_805 @[lib.scala 327:22]
+    inst rvclkhdr_5 of rvclkhdr_807 @[lib.scala 327:22]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 328:17]
@@ -94592,7 +94648,7 @@ circuit quasar_wrapper :
     rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 90:26]
     node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 91:63]
-    inst rvclkhdr_6 of rvclkhdr_806 @[lib.scala 327:22]
+    inst rvclkhdr_6 of rvclkhdr_808 @[lib.scala 327:22]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 328:17]
@@ -94600,7 +94656,7 @@ circuit quasar_wrapper :
     rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 91:26]
     node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 92:66]
-    inst rvclkhdr_7 of rvclkhdr_807 @[lib.scala 327:22]
+    inst rvclkhdr_7 of rvclkhdr_809 @[lib.scala 327:22]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 328:17]
@@ -94608,7 +94664,7 @@ circuit quasar_wrapper :
     rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 92:26]
     node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:66]
-    inst rvclkhdr_8 of rvclkhdr_808 @[lib.scala 327:22]
+    inst rvclkhdr_8 of rvclkhdr_810 @[lib.scala 327:22]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 328:17]
@@ -94616,7 +94672,7 @@ circuit quasar_wrapper :
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 93:26]
     node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:65]
-    inst rvclkhdr_9 of rvclkhdr_809 @[lib.scala 327:22]
+    inst rvclkhdr_9 of rvclkhdr_811 @[lib.scala 327:22]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 328:17]
@@ -94624,7 +94680,7 @@ circuit quasar_wrapper :
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 94:26]
     node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_clkdomain.scala 95:62]
-    inst rvclkhdr_10 of rvclkhdr_810 @[lib.scala 327:22]
+    inst rvclkhdr_10 of rvclkhdr_812 @[lib.scala 327:22]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 328:17]
@@ -94632,7 +94688,7 @@ circuit quasar_wrapper :
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 95:26]
     node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 96:62]
-    inst rvclkhdr_11 of rvclkhdr_811 @[lib.scala 327:22]
+    inst rvclkhdr_11 of rvclkhdr_813 @[lib.scala 327:22]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 328:17]
@@ -94640,54 +94696,6 @@ circuit quasar_wrapper :
     rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 96:26]
     
-  extmodule gated_latch_812 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_812 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_812 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_813 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_813 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_813 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_814 : 
     output Q : Clock
     input CK : Clock
@@ -94928,6 +94936,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_824 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_824 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_824 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_825 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_825 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_825 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module lsu_bus_buffer : 
     input clock : Clock
     input reset : AsyncReset
@@ -96224,7 +96280,7 @@ circuit quasar_wrapper :
     when ibuf_wr_en : @[Reg.scala 28:19]
       ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr of rvclkhdr_812 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_814 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -96238,7 +96294,7 @@ circuit quasar_wrapper :
       _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 249:15]
-    inst rvclkhdr_1 of rvclkhdr_813 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_815 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -97278,7 +97334,7 @@ circuit quasar_wrapper :
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_sz <= obuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_2 of rvclkhdr_814 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_816 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
@@ -97291,7 +97347,7 @@ circuit quasar_wrapper :
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_3 of rvclkhdr_815 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_817 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
@@ -100346,7 +100402,7 @@ circuit quasar_wrapper :
     buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 513:10]
     buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 513:10]
     node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:80]
-    inst rvclkhdr_4 of rvclkhdr_816 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_818 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -100355,7 +100411,7 @@ circuit quasar_wrapper :
     reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4373 <= buf_addr_in[0] @[lib.scala 358:16]
     node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:80]
-    inst rvclkhdr_5 of rvclkhdr_817 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_819 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -100364,7 +100420,7 @@ circuit quasar_wrapper :
     reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4375 <= buf_addr_in[1] @[lib.scala 358:16]
     node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:80]
-    inst rvclkhdr_6 of rvclkhdr_818 @[lib.scala 352:23]
+    inst rvclkhdr_6 of rvclkhdr_820 @[lib.scala 352:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
@@ -100373,7 +100429,7 @@ circuit quasar_wrapper :
     reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4377 <= buf_addr_in[2] @[lib.scala 358:16]
     node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:80]
-    inst rvclkhdr_7 of rvclkhdr_819 @[lib.scala 352:23]
+    inst rvclkhdr_7 of rvclkhdr_821 @[lib.scala 352:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
@@ -100409,7 +100465,7 @@ circuit quasar_wrapper :
     buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 515:14]
     buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 515:14]
     buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 515:14]
-    inst rvclkhdr_8 of rvclkhdr_820 @[lib.scala 352:23]
+    inst rvclkhdr_8 of rvclkhdr_822 @[lib.scala 352:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 354:18]
@@ -100417,7 +100473,7 @@ circuit quasar_wrapper :
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4388 <= buf_data_in[0] @[lib.scala 358:16]
-    inst rvclkhdr_9 of rvclkhdr_821 @[lib.scala 352:23]
+    inst rvclkhdr_9 of rvclkhdr_823 @[lib.scala 352:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 354:18]
@@ -100425,7 +100481,7 @@ circuit quasar_wrapper :
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4389 <= buf_data_in[1] @[lib.scala 358:16]
-    inst rvclkhdr_10 of rvclkhdr_822 @[lib.scala 352:23]
+    inst rvclkhdr_10 of rvclkhdr_824 @[lib.scala 352:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 354:18]
@@ -100433,7 +100489,7 @@ circuit quasar_wrapper :
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_4390 <= buf_data_in[2] @[lib.scala 358:16]
-    inst rvclkhdr_11 of rvclkhdr_823 @[lib.scala 352:23]
+    inst rvclkhdr_11 of rvclkhdr_825 @[lib.scala 352:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 354:18]
@@ -102402,54 +102458,6 @@ circuit quasar_wrapper :
     _T_54 <= lsu_raw_fwd_lo_m @[lsu.scala 319:67]
     lsu_raw_fwd_lo_r <= _T_54 @[lsu.scala 319:57]
     
-  extmodule gated_latch_824 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_824 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_824 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_825 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_825 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_825 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_826 : 
     output Q : Clock
     input CK : Clock
@@ -102522,6 +102530,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_829 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_829 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_829 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_830 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_830 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_830 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module pic_ctrl : 
     input clock : Clock
     input reset : AsyncReset
@@ -102725,14 +102781,14 @@ circuit quasar_wrapper :
     node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 129:108]
     node _T_28 = or(_T_26, _T_27) @[pic_ctrl.scala 129:76]
     node gw_config_c1_clken = or(_T_28, io.clk_override) @[pic_ctrl.scala 129:124]
-    inst rvclkhdr of rvclkhdr_824 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_826 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr.io.en <= pic_raddr_c1_clken @[lib.scala 329:16]
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[pic_ctrl.scala 132:21]
-    inst rvclkhdr_1 of rvclkhdr_825 @[lib.scala 327:22]
+    inst rvclkhdr_1 of rvclkhdr_827 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
@@ -102740,7 +102796,7 @@ circuit quasar_wrapper :
     rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[pic_ctrl.scala 133:21]
     node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[pic_ctrl.scala 134:56]
-    inst rvclkhdr_2 of rvclkhdr_826 @[lib.scala 327:22]
+    inst rvclkhdr_2 of rvclkhdr_828 @[lib.scala 327:22]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 328:17]
@@ -102748,7 +102804,7 @@ circuit quasar_wrapper :
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[pic_ctrl.scala 134:21]
     node _T_30 = bits(pic_int_c1_clken, 0, 0) @[pic_ctrl.scala 135:56]
-    inst rvclkhdr_3 of rvclkhdr_827 @[lib.scala 327:22]
+    inst rvclkhdr_3 of rvclkhdr_829 @[lib.scala 327:22]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 328:17]
@@ -102756,7 +102812,7 @@ circuit quasar_wrapper :
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[pic_ctrl.scala 135:21]
     node _T_31 = bits(gw_config_c1_clken, 0, 0) @[pic_ctrl.scala 136:58]
-    inst rvclkhdr_4 of rvclkhdr_828 @[lib.scala 327:22]
+    inst rvclkhdr_4 of rvclkhdr_830 @[lib.scala 327:22]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 328:17]
@@ -106695,54 +106751,6 @@ circuit quasar_wrapper :
                                                                                                                                                                                                 mask <= UInt<4>("h02") @[pic_ctrl.scala 403:44]
                                                                                                                                                                                                 skip @[Conditional.scala 39:67]
     
-  extmodule gated_latch_829 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_829 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_829 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_830 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_830 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_830 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_831 : 
     output Q : Clock
     input CK : Clock
@@ -107079,6 +107087,54 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_845 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_845 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_845 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_846 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_846 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_846 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module dma_ctrl : 
     input clock : Clock
     input reset : AsyncReset
@@ -108088,7 +108144,7 @@ circuit quasar_wrapper :
     node _T_803 = cat(_T_802, _T_771) @[Cat.scala 29:58]
     fifo_done_bus <= _T_803 @[dma_ctrl.scala 236:21]
     node _T_804 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 238:84]
-    inst rvclkhdr of rvclkhdr_829 @[lib.scala 352:23]
+    inst rvclkhdr of rvclkhdr_831 @[lib.scala 352:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 354:18]
@@ -108098,7 +108154,7 @@ circuit quasar_wrapper :
     _T_805 <= fifo_addr_in @[lib.scala 358:16]
     fifo_addr[0] <= _T_805 @[dma_ctrl.scala 238:49]
     node _T_806 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 238:84]
-    inst rvclkhdr_1 of rvclkhdr_830 @[lib.scala 352:23]
+    inst rvclkhdr_1 of rvclkhdr_832 @[lib.scala 352:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 354:18]
@@ -108108,7 +108164,7 @@ circuit quasar_wrapper :
     _T_807 <= fifo_addr_in @[lib.scala 358:16]
     fifo_addr[1] <= _T_807 @[dma_ctrl.scala 238:49]
     node _T_808 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 238:84]
-    inst rvclkhdr_2 of rvclkhdr_831 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_833 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
@@ -108118,7 +108174,7 @@ circuit quasar_wrapper :
     _T_809 <= fifo_addr_in @[lib.scala 358:16]
     fifo_addr[2] <= _T_809 @[dma_ctrl.scala 238:49]
     node _T_810 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 238:84]
-    inst rvclkhdr_3 of rvclkhdr_832 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_834 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
@@ -108128,7 +108184,7 @@ circuit quasar_wrapper :
     _T_811 <= fifo_addr_in @[lib.scala 358:16]
     fifo_addr[3] <= _T_811 @[dma_ctrl.scala 238:49]
     node _T_812 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 238:84]
-    inst rvclkhdr_4 of rvclkhdr_833 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_835 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -108303,7 +108359,7 @@ circuit quasar_wrapper :
     node _T_890 = cat(_T_889, _T_878) @[Cat.scala 29:58]
     fifo_dbg <= _T_890 @[dma_ctrl.scala 248:21]
     node _T_891 = bits(fifo_data_en, 0, 0) @[dma_ctrl.scala 250:88]
-    inst rvclkhdr_5 of rvclkhdr_834 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_836 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -108313,7 +108369,7 @@ circuit quasar_wrapper :
     _T_892 <= fifo_data_in[0] @[lib.scala 358:16]
     fifo_data[0] <= _T_892 @[dma_ctrl.scala 250:49]
     node _T_893 = bits(fifo_data_en, 1, 1) @[dma_ctrl.scala 250:88]
-    inst rvclkhdr_6 of rvclkhdr_835 @[lib.scala 352:23]
+    inst rvclkhdr_6 of rvclkhdr_837 @[lib.scala 352:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
@@ -108323,7 +108379,7 @@ circuit quasar_wrapper :
     _T_894 <= fifo_data_in[1] @[lib.scala 358:16]
     fifo_data[1] <= _T_894 @[dma_ctrl.scala 250:49]
     node _T_895 = bits(fifo_data_en, 2, 2) @[dma_ctrl.scala 250:88]
-    inst rvclkhdr_7 of rvclkhdr_836 @[lib.scala 352:23]
+    inst rvclkhdr_7 of rvclkhdr_838 @[lib.scala 352:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
@@ -108333,7 +108389,7 @@ circuit quasar_wrapper :
     _T_896 <= fifo_data_in[2] @[lib.scala 358:16]
     fifo_data[2] <= _T_896 @[dma_ctrl.scala 250:49]
     node _T_897 = bits(fifo_data_en, 3, 3) @[dma_ctrl.scala 250:88]
-    inst rvclkhdr_8 of rvclkhdr_837 @[lib.scala 352:23]
+    inst rvclkhdr_8 of rvclkhdr_839 @[lib.scala 352:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 354:18]
@@ -108343,7 +108399,7 @@ circuit quasar_wrapper :
     _T_898 <= fifo_data_in[3] @[lib.scala 358:16]
     fifo_data[3] <= _T_898 @[dma_ctrl.scala 250:49]
     node _T_899 = bits(fifo_data_en, 4, 4) @[dma_ctrl.scala 250:88]
-    inst rvclkhdr_9 of rvclkhdr_838 @[lib.scala 352:23]
+    inst rvclkhdr_9 of rvclkhdr_840 @[lib.scala 352:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 354:18]
@@ -108525,7 +108581,7 @@ circuit quasar_wrapper :
     node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 295:45]
     node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 295:45]
     num_fifo_vld <= _T_988 @[dma_ctrl.scala 295:25]
-    node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[dma_ctrl.scala 297:46]
+    node fifo_full_spec = geq(num_fifo_vld, UInt<3>("h05")) @[dma_ctrl.scala 297:41]
     node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 299:39]
     node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 299:27]
     node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 303:38]
@@ -108598,230 +108654,250 @@ circuit quasar_wrapper :
     node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:26]
     node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 313:32]
     node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 313:59]
-    node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1062 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_1063 = or(_T_1059, _T_1060) @[Mux.scala 27:72]
-    node _T_1064 = or(_T_1063, _T_1061) @[Mux.scala 27:72]
-    node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72]
-    wire _T_1066 : UInt<4> @[Mux.scala 27:72]
-    _T_1066 <= _T_1065 @[Mux.scala 27:72]
-    node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[dma_ctrl.scala 313:68]
-    node _T_1068 = and(_T_1046, _T_1067) @[dma_ctrl.scala 310:78]
-    node _T_1069 = or(_T_1043, _T_1068) @[dma_ctrl.scala 309:145]
-    node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 314:62]
-    node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[dma_ctrl.scala 314:69]
-    node _T_1072 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1071) @[dma_ctrl.scala 314:45]
-    node _T_1073 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:97]
-    node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[dma_ctrl.scala 314:103]
-    node _T_1075 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:133]
-    node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[dma_ctrl.scala 314:139]
-    node _T_1077 = or(_T_1074, _T_1076) @[dma_ctrl.scala 314:116]
-    node _T_1078 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:169]
-    node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[dma_ctrl.scala 314:175]
-    node _T_1080 = or(_T_1077, _T_1079) @[dma_ctrl.scala 314:152]
-    node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[dma_ctrl.scala 314:80]
-    node _T_1082 = and(_T_1072, _T_1081) @[dma_ctrl.scala 314:78]
-    node _T_1083 = or(_T_1069, _T_1082) @[dma_ctrl.scala 313:79]
-    node _T_1084 = and(_T_1010, _T_1083) @[dma_ctrl.scala 304:87]
-    dma_alignment_error <= _T_1084 @[dma_ctrl.scala 304:25]
-    node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 319:50]
-    io.dbg_dma_io.dma_dbg_ready <= _T_1085 @[dma_ctrl.scala 319:36]
-    node _T_1086 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 320:39]
-    node _T_1087 = bits(_T_1086, 0, 0) @[dma_ctrl.scala 320:39]
-    node _T_1088 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 320:58]
-    node _T_1089 = bits(_T_1088, 0, 0) @[dma_ctrl.scala 320:58]
-    node _T_1090 = and(_T_1087, _T_1089) @[dma_ctrl.scala 320:48]
-    node _T_1091 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 320:78]
-    node _T_1092 = bits(_T_1091, 0, 0) @[dma_ctrl.scala 320:78]
-    node _T_1093 = and(_T_1090, _T_1092) @[dma_ctrl.scala 320:67]
-    io.dma_dbg_cmd_done <= _T_1093 @[dma_ctrl.scala 320:25]
-    node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 321:49]
-    node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 321:71]
-    node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 321:98]
-    node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[dma_ctrl.scala 321:31]
-    io.dma_dbg_rddata <= _T_1097 @[dma_ctrl.scala 321:25]
-    node _T_1098 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 322:47]
-    io.dma_dbg_cmd_fail <= _T_1098 @[dma_ctrl.scala 322:25]
-    node _T_1099 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 324:38]
-    node _T_1100 = bits(_T_1099, 0, 0) @[dma_ctrl.scala 324:38]
-    node _T_1101 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 324:58]
-    node _T_1102 = bits(_T_1101, 0, 0) @[dma_ctrl.scala 324:58]
-    node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[dma_ctrl.scala 324:48]
-    node _T_1104 = and(_T_1100, _T_1103) @[dma_ctrl.scala 324:46]
-    node _T_1105 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 324:76]
-    node _T_1106 = bits(_T_1105, 0, 0) @[dma_ctrl.scala 324:76]
-    node _T_1107 = and(_T_1104, _T_1106) @[dma_ctrl.scala 324:66]
-    node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 324:111]
-    node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[dma_ctrl.scala 324:134]
-    node _T_1110 = not(_T_1109) @[dma_ctrl.scala 324:88]
-    node _T_1111 = bits(_T_1110, 0, 0) @[dma_ctrl.scala 324:164]
-    node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 324:184]
-    node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[dma_ctrl.scala 324:191]
-    node _T_1114 = or(_T_1111, _T_1113) @[dma_ctrl.scala 324:167]
-    node _T_1115 = and(_T_1107, _T_1114) @[dma_ctrl.scala 324:84]
-    dma_dbg_cmd_error <= _T_1115 @[dma_ctrl.scala 324:25]
-    node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:80]
-    node _T_1117 = and(dma_mem_req, _T_1116) @[dma_ctrl.scala 328:56]
-    node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 328:121]
-    node _T_1119 = and(_T_1117, _T_1118) @[dma_ctrl.scala 328:103]
-    io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1119 @[dma_ctrl.scala 328:41]
-    node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 329:56]
-    node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 329:97]
-    node _T_1122 = and(_T_1120, _T_1121) @[dma_ctrl.scala 329:79]
-    io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1122 @[dma_ctrl.scala 329:41]
-    io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 330:41]
-    io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 331:42]
-    node _T_1123 = orr(fifo_valid) @[dma_ctrl.scala 334:30]
-    node _T_1124 = not(_T_1123) @[dma_ctrl.scala 334:17]
-    fifo_empty <= _T_1124 @[dma_ctrl.scala 334:14]
-    dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 338:22]
-    node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 339:45]
-    node _T_1126 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:115]
-    node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[dma_ctrl.scala 339:77]
-    node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_1130 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:171]
-    node _T_1131 = and(_T_1129, _T_1130) @[dma_ctrl.scala 339:155]
-    node _T_1132 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 339:196]
-    node _T_1133 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:243]
-    node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dma_ctrl.scala 339:205]
-    node _T_1135 = and(_T_1132, _T_1134) @[dma_ctrl.scala 339:203]
-    node _T_1136 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:298]
-    node _T_1137 = add(_T_1136, UInt<1>("h01")) @[dma_ctrl.scala 339:304]
-    node _T_1138 = tail(_T_1137, 1) @[dma_ctrl.scala 339:304]
-    node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[dma_ctrl.scala 339:182]
-    node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[dma_ctrl.scala 339:29]
-    node _T_1140 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 342:31]
-    node _T_1141 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 342:55]
-    reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_1141 : @[Reg.scala 28:19]
-      _T_1142 <= _T_1140 @[Reg.scala 28:23]
+    node _T_1059 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 314:26]
+    node _T_1060 = eq(_T_1059, UInt<3>("h04")) @[dma_ctrl.scala 314:32]
+    node _T_1061 = bits(dma_mem_byteen, 7, 4) @[dma_ctrl.scala 314:59]
+    node _T_1062 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 315:26]
+    node _T_1063 = eq(_T_1062, UInt<3>("h05")) @[dma_ctrl.scala 315:32]
+    node _T_1064 = bits(dma_mem_byteen, 7, 5) @[dma_ctrl.scala 315:59]
+    node _T_1065 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 316:26]
+    node _T_1066 = eq(_T_1065, UInt<3>("h06")) @[dma_ctrl.scala 316:32]
+    node _T_1067 = bits(dma_mem_byteen, 7, 6) @[dma_ctrl.scala 316:59]
+    node _T_1068 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 317:26]
+    node _T_1069 = eq(_T_1068, UInt<3>("h07")) @[dma_ctrl.scala 317:32]
+    node _T_1070 = bits(dma_mem_byteen, 7, 7) @[dma_ctrl.scala 317:59]
+    node _T_1071 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1072 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1073 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1074 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1075 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1076 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1077 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1078 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1079 = or(_T_1071, _T_1072) @[Mux.scala 27:72]
+    node _T_1080 = or(_T_1079, _T_1073) @[Mux.scala 27:72]
+    node _T_1081 = or(_T_1080, _T_1074) @[Mux.scala 27:72]
+    node _T_1082 = or(_T_1081, _T_1075) @[Mux.scala 27:72]
+    node _T_1083 = or(_T_1082, _T_1076) @[Mux.scala 27:72]
+    node _T_1084 = or(_T_1083, _T_1077) @[Mux.scala 27:72]
+    node _T_1085 = or(_T_1084, _T_1078) @[Mux.scala 27:72]
+    wire _T_1086 : UInt<4> @[Mux.scala 27:72]
+    _T_1086 <= _T_1085 @[Mux.scala 27:72]
+    node _T_1087 = neq(_T_1086, UInt<4>("h0f")) @[dma_ctrl.scala 317:66]
+    node _T_1088 = and(_T_1046, _T_1087) @[dma_ctrl.scala 310:78]
+    node _T_1089 = or(_T_1043, _T_1088) @[dma_ctrl.scala 309:145]
+    node _T_1090 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 318:62]
+    node _T_1091 = eq(_T_1090, UInt<2>("h03")) @[dma_ctrl.scala 318:69]
+    node _T_1092 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1091) @[dma_ctrl.scala 318:45]
+    node _T_1093 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:97]
+    node _T_1094 = eq(_T_1093, UInt<4>("h0f")) @[dma_ctrl.scala 318:103]
+    node _T_1095 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:133]
+    node _T_1096 = eq(_T_1095, UInt<8>("h0f0")) @[dma_ctrl.scala 318:139]
+    node _T_1097 = or(_T_1094, _T_1096) @[dma_ctrl.scala 318:116]
+    node _T_1098 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:169]
+    node _T_1099 = eq(_T_1098, UInt<8>("h0ff")) @[dma_ctrl.scala 318:175]
+    node _T_1100 = or(_T_1097, _T_1099) @[dma_ctrl.scala 318:152]
+    node _T_1101 = eq(_T_1100, UInt<1>("h00")) @[dma_ctrl.scala 318:80]
+    node _T_1102 = and(_T_1092, _T_1101) @[dma_ctrl.scala 318:78]
+    node _T_1103 = or(_T_1089, _T_1102) @[dma_ctrl.scala 317:79]
+    node _T_1104 = and(_T_1010, _T_1103) @[dma_ctrl.scala 304:87]
+    dma_alignment_error <= _T_1104 @[dma_ctrl.scala 304:25]
+    node _T_1105 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 323:50]
+    io.dbg_dma_io.dma_dbg_ready <= _T_1105 @[dma_ctrl.scala 323:36]
+    node _T_1106 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 324:39]
+    node _T_1107 = bits(_T_1106, 0, 0) @[dma_ctrl.scala 324:39]
+    node _T_1108 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 324:58]
+    node _T_1109 = bits(_T_1108, 0, 0) @[dma_ctrl.scala 324:58]
+    node _T_1110 = and(_T_1107, _T_1109) @[dma_ctrl.scala 324:48]
+    node _T_1111 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 324:78]
+    node _T_1112 = bits(_T_1111, 0, 0) @[dma_ctrl.scala 324:78]
+    node _T_1113 = and(_T_1110, _T_1112) @[dma_ctrl.scala 324:67]
+    io.dma_dbg_cmd_done <= _T_1113 @[dma_ctrl.scala 324:25]
+    node _T_1114 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 325:49]
+    node _T_1115 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 325:71]
+    node _T_1116 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 325:98]
+    node _T_1117 = mux(_T_1114, _T_1115, _T_1116) @[dma_ctrl.scala 325:31]
+    io.dma_dbg_rddata <= _T_1117 @[dma_ctrl.scala 325:25]
+    node _T_1118 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 326:47]
+    io.dma_dbg_cmd_fail <= _T_1118 @[dma_ctrl.scala 326:25]
+    node _T_1119 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 328:38]
+    node _T_1120 = bits(_T_1119, 0, 0) @[dma_ctrl.scala 328:38]
+    node _T_1121 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 328:58]
+    node _T_1122 = bits(_T_1121, 0, 0) @[dma_ctrl.scala 328:58]
+    node _T_1123 = eq(_T_1122, UInt<1>("h00")) @[dma_ctrl.scala 328:48]
+    node _T_1124 = and(_T_1120, _T_1123) @[dma_ctrl.scala 328:46]
+    node _T_1125 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 328:76]
+    node _T_1126 = bits(_T_1125, 0, 0) @[dma_ctrl.scala 328:76]
+    node _T_1127 = and(_T_1124, _T_1126) @[dma_ctrl.scala 328:66]
+    node _T_1128 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 328:111]
+    node _T_1129 = or(_T_1128, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:134]
+    node _T_1130 = not(_T_1129) @[dma_ctrl.scala 328:88]
+    node _T_1131 = bits(_T_1130, 0, 0) @[dma_ctrl.scala 328:164]
+    node _T_1132 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 328:184]
+    node _T_1133 = neq(_T_1132, UInt<2>("h02")) @[dma_ctrl.scala 328:191]
+    node _T_1134 = or(_T_1131, _T_1133) @[dma_ctrl.scala 328:167]
+    node _T_1135 = and(_T_1127, _T_1134) @[dma_ctrl.scala 328:84]
+    dma_dbg_cmd_error <= _T_1135 @[dma_ctrl.scala 328:25]
+    node _T_1136 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 332:80]
+    node _T_1137 = and(dma_mem_req, _T_1136) @[dma_ctrl.scala 332:56]
+    node _T_1138 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 332:121]
+    node _T_1139 = and(_T_1137, _T_1138) @[dma_ctrl.scala 332:103]
+    io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1139 @[dma_ctrl.scala 332:41]
+    node _T_1140 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 333:56]
+    node _T_1141 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 333:97]
+    node _T_1142 = and(_T_1140, _T_1141) @[dma_ctrl.scala 333:79]
+    io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1142 @[dma_ctrl.scala 333:41]
+    io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 334:41]
+    io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 335:42]
+    node _T_1143 = orr(fifo_valid) @[dma_ctrl.scala 338:30]
+    node _T_1144 = not(_T_1143) @[dma_ctrl.scala 338:17]
+    fifo_empty <= _T_1144 @[dma_ctrl.scala 338:14]
+    dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 342:22]
+    node _T_1145 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 343:45]
+    node _T_1146 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:115]
+    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 343:77]
+    node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15]
+    node _T_1149 = mux(_T_1148, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_1150 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:171]
+    node _T_1151 = and(_T_1149, _T_1150) @[dma_ctrl.scala 343:155]
+    node _T_1152 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 343:196]
+    node _T_1153 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:243]
+    node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[dma_ctrl.scala 343:205]
+    node _T_1155 = and(_T_1152, _T_1154) @[dma_ctrl.scala 343:203]
+    node _T_1156 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:298]
+    node _T_1157 = add(_T_1156, UInt<1>("h01")) @[dma_ctrl.scala 343:304]
+    node _T_1158 = tail(_T_1157, 1) @[dma_ctrl.scala 343:304]
+    node _T_1159 = mux(_T_1155, _T_1158, UInt<1>("h00")) @[dma_ctrl.scala 343:182]
+    node dma_nack_count_d = mux(_T_1145, _T_1151, _T_1159) @[dma_ctrl.scala 343:29]
+    node _T_1160 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 346:31]
+    node _T_1161 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 346:55]
+    reg _T_1162 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1161 : @[Reg.scala 28:19]
+      _T_1162 <= _T_1160 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    dma_nack_count <= _T_1142 @[dma_ctrl.scala 341:22]
-    node _T_1143 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 347:33]
-    node _T_1144 = bits(_T_1143, 0, 0) @[dma_ctrl.scala 347:33]
-    node _T_1145 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 347:54]
-    node _T_1146 = bits(_T_1145, 0, 0) @[dma_ctrl.scala 347:54]
-    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 347:43]
-    node _T_1148 = and(_T_1144, _T_1147) @[dma_ctrl.scala 347:41]
-    node _T_1149 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 347:74]
-    node _T_1150 = bits(_T_1149, 0, 0) @[dma_ctrl.scala 347:74]
-    node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[dma_ctrl.scala 347:64]
-    node _T_1152 = and(_T_1148, _T_1151) @[dma_ctrl.scala 347:62]
-    node _T_1153 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 347:104]
-    node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[dma_ctrl.scala 347:126]
-    node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dma_ctrl.scala 347:84]
-    node _T_1156 = and(_T_1152, _T_1155) @[dma_ctrl.scala 347:82]
-    dma_mem_req <= _T_1156 @[dma_ctrl.scala 347:20]
-    node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 348:79]
-    node _T_1158 = and(dma_mem_req, _T_1157) @[dma_ctrl.scala 348:55]
-    node _T_1159 = and(_T_1158, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 348:102]
-    io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1159 @[dma_ctrl.scala 348:40]
-    node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 349:55]
-    node _T_1161 = and(_T_1160, io.iccm_ready) @[dma_ctrl.scala 349:78]
-    io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1161 @[dma_ctrl.scala 349:40]
-    io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 350:28]
-    dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 351:20]
-    dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 352:20]
-    node _T_1162 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 353:101]
-    node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[dma_ctrl.scala 353:107]
-    node _T_1164 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1163) @[dma_ctrl.scala 353:84]
-    node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 353:141]
-    node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 353:171]
-    node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58]
-    node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58]
-    node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 353:196]
-    node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[dma_ctrl.scala 353:46]
-    io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1170 @[dma_ctrl.scala 353:40]
-    node _T_1171 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:102]
-    node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[dma_ctrl.scala 354:108]
-    node _T_1173 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:138]
-    node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[dma_ctrl.scala 354:144]
-    node _T_1175 = or(_T_1172, _T_1174) @[dma_ctrl.scala 354:121]
-    node _T_1176 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1175) @[dma_ctrl.scala 354:84]
-    node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 354:178]
-    node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[dma_ctrl.scala 354:46]
-    io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1178 @[dma_ctrl.scala 354:40]
-    dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 355:20]
-    node _T_1179 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 356:53]
-    node _T_1180 = bits(_T_1179, 0, 0) @[dma_ctrl.scala 356:53]
-    io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1180 @[dma_ctrl.scala 356:40]
-    io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 357:40]
-    node _T_1181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 361:83]
-    node _T_1182 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1181) @[dma_ctrl.scala 361:81]
-    io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1182 @[dma_ctrl.scala 361:42]
-    node _T_1183 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 362:81]
-    io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1183 @[dma_ctrl.scala 362:42]
-    node _T_1184 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 363:82]
-    node _T_1185 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 363:123]
-    node _T_1186 = and(_T_1184, _T_1185) @[dma_ctrl.scala 363:121]
-    io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1186 @[dma_ctrl.scala 363:42]
-    node _T_1187 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 364:82]
-    node _T_1188 = and(_T_1187, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 364:121]
-    io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1188 @[dma_ctrl.scala 364:42]
-    reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 369:12]
-    _T_1189 <= fifo_full_spec @[dma_ctrl.scala 369:12]
-    fifo_full <= _T_1189 @[dma_ctrl.scala 368:22]
-    reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12]
-    _T_1190 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 373:12]
-    dbg_dma_bubble_bus <= _T_1190 @[dma_ctrl.scala 372:22]
-    reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12]
-    _T_1191 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 377:12]
-    dma_dbg_cmd_done_q <= _T_1191 @[dma_ctrl.scala 376:22]
-    node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 382:44]
-    node _T_1193 = or(_T_1192, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 382:65]
-    node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[dma_ctrl.scala 382:99]
-    node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 383:44]
-    node _T_1195 = or(_T_1194, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 383:60]
-    node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[dma_ctrl.scala 383:94]
-    node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[dma_ctrl.scala 383:116]
-    node _T_1198 = orr(fifo_valid) @[dma_ctrl.scala 383:151]
-    node _T_1199 = or(_T_1197, _T_1198) @[dma_ctrl.scala 383:137]
-    node dma_free_clken = or(_T_1199, io.clk_override) @[dma_ctrl.scala 383:156]
-    inst dma_buffer_c1cgc of rvclkhdr_839 @[dma_ctrl.scala 385:32]
+    dma_nack_count <= _T_1162 @[dma_ctrl.scala 345:22]
+    node _T_1163 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 351:33]
+    node _T_1164 = bits(_T_1163, 0, 0) @[dma_ctrl.scala 351:33]
+    node _T_1165 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 351:54]
+    node _T_1166 = bits(_T_1165, 0, 0) @[dma_ctrl.scala 351:54]
+    node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dma_ctrl.scala 351:43]
+    node _T_1168 = and(_T_1164, _T_1167) @[dma_ctrl.scala 351:41]
+    node _T_1169 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 351:74]
+    node _T_1170 = bits(_T_1169, 0, 0) @[dma_ctrl.scala 351:74]
+    node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dma_ctrl.scala 351:64]
+    node _T_1172 = and(_T_1168, _T_1171) @[dma_ctrl.scala 351:62]
+    node _T_1173 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 351:104]
+    node _T_1174 = or(_T_1173, dma_dbg_cmd_error) @[dma_ctrl.scala 351:126]
+    node _T_1175 = eq(_T_1174, UInt<1>("h00")) @[dma_ctrl.scala 351:84]
+    node _T_1176 = and(_T_1172, _T_1175) @[dma_ctrl.scala 351:82]
+    dma_mem_req <= _T_1176 @[dma_ctrl.scala 351:20]
+    node _T_1177 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 352:79]
+    node _T_1178 = and(dma_mem_req, _T_1177) @[dma_ctrl.scala 352:55]
+    node _T_1179 = and(_T_1178, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 352:102]
+    io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1179 @[dma_ctrl.scala 352:40]
+    node _T_1180 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 353:55]
+    node _T_1181 = and(_T_1180, io.iccm_ready) @[dma_ctrl.scala 353:78]
+    io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1181 @[dma_ctrl.scala 353:40]
+    io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 354:28]
+    dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 355:20]
+    dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 356:20]
+    node _T_1182 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 357:101]
+    node _T_1183 = eq(_T_1182, UInt<8>("h0f0")) @[dma_ctrl.scala 357:107]
+    node _T_1184 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1183) @[dma_ctrl.scala 357:84]
+    node _T_1185 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 357:141]
+    node _T_1186 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 357:171]
+    node _T_1187 = cat(_T_1185, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_1188 = cat(_T_1187, _T_1186) @[Cat.scala 29:58]
+    node _T_1189 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 357:196]
+    node _T_1190 = mux(_T_1184, _T_1188, _T_1189) @[dma_ctrl.scala 357:46]
+    io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1190 @[dma_ctrl.scala 357:40]
+    node _T_1191 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:102]
+    node _T_1192 = eq(_T_1191, UInt<4>("h0f")) @[dma_ctrl.scala 358:108]
+    node _T_1193 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:138]
+    node _T_1194 = eq(_T_1193, UInt<8>("h0f0")) @[dma_ctrl.scala 358:144]
+    node _T_1195 = or(_T_1192, _T_1194) @[dma_ctrl.scala 358:121]
+    node _T_1196 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1195) @[dma_ctrl.scala 358:84]
+    node _T_1197 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 358:178]
+    node _T_1198 = mux(_T_1196, UInt<2>("h02"), _T_1197) @[dma_ctrl.scala 358:46]
+    io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1198 @[dma_ctrl.scala 358:40]
+    dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 359:20]
+    node _T_1199 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 360:53]
+    node _T_1200 = bits(_T_1199, 0, 0) @[dma_ctrl.scala 360:53]
+    io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1200 @[dma_ctrl.scala 360:40]
+    io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 361:40]
+    node _T_1201 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 365:83]
+    node _T_1202 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1201) @[dma_ctrl.scala 365:81]
+    io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1202 @[dma_ctrl.scala 365:42]
+    node _T_1203 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 366:81]
+    io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1203 @[dma_ctrl.scala 366:42]
+    node _T_1204 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 367:82]
+    node _T_1205 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 367:123]
+    node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 367:121]
+    io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1206 @[dma_ctrl.scala 367:42]
+    node _T_1207 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 368:82]
+    node _T_1208 = and(_T_1207, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 368:121]
+    io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1208 @[dma_ctrl.scala 368:42]
+    reg _T_1209 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12]
+    _T_1209 <= fifo_full_spec @[dma_ctrl.scala 373:12]
+    fifo_full <= _T_1209 @[dma_ctrl.scala 372:22]
+    reg _T_1210 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12]
+    _T_1210 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 377:12]
+    dbg_dma_bubble_bus <= _T_1210 @[dma_ctrl.scala 376:22]
+    reg _T_1211 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 381:12]
+    _T_1211 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 381:12]
+    dma_dbg_cmd_done_q <= _T_1211 @[dma_ctrl.scala 380:22]
+    node _T_1212 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 386:44]
+    node _T_1213 = or(_T_1212, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 386:65]
+    node dma_buffer_c1_clken = or(_T_1213, io.clk_override) @[dma_ctrl.scala 386:99]
+    node _T_1214 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 387:44]
+    node _T_1215 = or(_T_1214, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 387:60]
+    node _T_1216 = or(_T_1215, io.dma_dbg_cmd_done) @[dma_ctrl.scala 387:94]
+    node _T_1217 = or(_T_1216, dma_dbg_cmd_done_q) @[dma_ctrl.scala 387:116]
+    node _T_1218 = orr(fifo_valid) @[dma_ctrl.scala 387:151]
+    node _T_1219 = or(_T_1217, _T_1218) @[dma_ctrl.scala 387:137]
+    node dma_free_clken = or(_T_1219, io.clk_override) @[dma_ctrl.scala 387:156]
+    inst dma_buffer_c1cgc of rvclkhdr_841 @[dma_ctrl.scala 389:32]
     dma_buffer_c1cgc.clock <= clock
     dma_buffer_c1cgc.reset <= reset
-    dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 386:33]
-    dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 387:33]
-    dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 388:33]
-    dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 389:33]
-    inst dma_free_cgc of rvclkhdr_840 @[dma_ctrl.scala 391:28]
+    dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 390:33]
+    dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 391:33]
+    dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 392:33]
+    dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 393:33]
+    inst dma_free_cgc of rvclkhdr_842 @[dma_ctrl.scala 395:28]
     dma_free_cgc.clock <= clock
     dma_free_cgc.reset <= reset
-    dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 392:29]
-    dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 393:29]
-    dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 394:29]
-    dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 395:29]
-    inst dma_bus_cgc of rvclkhdr_841 @[dma_ctrl.scala 397:27]
+    dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 396:29]
+    dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 397:29]
+    dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 398:29]
+    dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 399:29]
+    inst dma_bus_cgc of rvclkhdr_843 @[dma_ctrl.scala 401:27]
     dma_bus_cgc.clock <= clock
     dma_bus_cgc.reset <= reset
-    dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 398:28]
-    dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 399:28]
-    dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 400:28]
-    dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 401:28]
-    node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 405:47]
-    node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 406:46]
-    node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 407:40]
-    node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 408:42]
-    node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 408:51]
-    node wrbuf_rst = and(_T_1200, _T_1201) @[dma_ctrl.scala 408:49]
-    node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 409:42]
-    node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 409:51]
-    node wrbuf_data_rst = and(_T_1202, _T_1203) @[dma_ctrl.scala 409:49]
-    node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 411:63]
-    node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 411:92]
-    node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 411:90]
-    reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 411:59]
-    _T_1207 <= _T_1206 @[dma_ctrl.scala 411:59]
-    wrbuf_vld <= _T_1207 @[dma_ctrl.scala 411:25]
-    node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 413:63]
-    node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 413:102]
-    node _T_1210 = and(_T_1208, _T_1209) @[dma_ctrl.scala 413:100]
-    reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 413:59]
-    _T_1211 <= _T_1210 @[dma_ctrl.scala 413:59]
-    wrbuf_data_vld <= _T_1211 @[dma_ctrl.scala 413:25]
+    dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 402:28]
+    dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 403:28]
+    dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 404:28]
+    dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 405:28]
+    node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 409:47]
+    node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 410:46]
+    node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 411:40]
+    node _T_1220 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 412:42]
+    node _T_1221 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 412:51]
+    node wrbuf_rst = and(_T_1220, _T_1221) @[dma_ctrl.scala 412:49]
+    node _T_1222 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 413:42]
+    node _T_1223 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 413:51]
+    node wrbuf_data_rst = and(_T_1222, _T_1223) @[dma_ctrl.scala 413:49]
+    node _T_1224 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 415:63]
+    node _T_1225 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 415:92]
+    node _T_1226 = and(_T_1224, _T_1225) @[dma_ctrl.scala 415:90]
+    reg _T_1227 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 415:59]
+    _T_1227 <= _T_1226 @[dma_ctrl.scala 415:59]
+    wrbuf_vld <= _T_1227 @[dma_ctrl.scala 415:25]
+    node _T_1228 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 417:63]
+    node _T_1229 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 417:102]
+    node _T_1230 = and(_T_1228, _T_1229) @[dma_ctrl.scala 417:100]
+    reg _T_1231 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 417:59]
+    _T_1231 <= _T_1230 @[dma_ctrl.scala 417:59]
+    wrbuf_data_vld <= _T_1231 @[dma_ctrl.scala 417:25]
     reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when wrbuf_en : @[Reg.scala 28:19]
       wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23]
@@ -108830,21 +108906,21 @@ circuit quasar_wrapper :
     when wrbuf_en : @[Reg.scala 28:19]
       wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 423:68]
-    inst rvclkhdr_10 of rvclkhdr_842 @[lib.scala 352:23]
+    node _T_1232 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 427:68]
+    inst rvclkhdr_10 of rvclkhdr_844 @[lib.scala 352:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
     rvclkhdr_10.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_10.io.en <= _T_1212 @[lib.scala 355:17]
+    rvclkhdr_10.io.en <= _T_1232 @[lib.scala 355:17]
     rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 358:16]
-    node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 425:72]
-    inst rvclkhdr_11 of rvclkhdr_843 @[lib.scala 352:23]
+    node _T_1233 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 429:72]
+    inst rvclkhdr_11 of rvclkhdr_845 @[lib.scala 352:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
     rvclkhdr_11.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_11.io.en <= _T_1213 @[lib.scala 355:17]
+    rvclkhdr_11.io.en <= _T_1233 @[lib.scala 355:17]
     rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 358:16]
@@ -108852,18 +108928,18 @@ circuit quasar_wrapper :
     when wrbuf_data_en : @[Reg.scala 28:19]
       wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 433:59]
-    node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 434:44]
-    node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[dma_ctrl.scala 434:42]
-    node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 435:54]
-    node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 435:63]
-    node rdbuf_rst = and(_T_1215, _T_1216) @[dma_ctrl.scala 435:61]
-    node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 437:51]
-    node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 437:80]
-    node _T_1219 = and(_T_1217, _T_1218) @[dma_ctrl.scala 437:78]
-    reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 437:47]
-    _T_1220 <= _T_1219 @[dma_ctrl.scala 437:47]
-    rdbuf_vld <= _T_1220 @[dma_ctrl.scala 437:13]
+    node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 437:59]
+    node _T_1234 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 438:44]
+    node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1234) @[dma_ctrl.scala 438:42]
+    node _T_1235 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 439:54]
+    node _T_1236 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 439:63]
+    node rdbuf_rst = and(_T_1235, _T_1236) @[dma_ctrl.scala 439:61]
+    node _T_1237 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 441:51]
+    node _T_1238 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 441:80]
+    node _T_1239 = and(_T_1237, _T_1238) @[dma_ctrl.scala 441:78]
+    reg _T_1240 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 441:47]
+    _T_1240 <= _T_1239 @[dma_ctrl.scala 441:47]
+    rdbuf_vld <= _T_1240 @[dma_ctrl.scala 441:13]
     reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when rdbuf_en : @[Reg.scala 28:19]
       rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23]
@@ -108872,150 +108948,102 @@ circuit quasar_wrapper :
     when rdbuf_en : @[Reg.scala 28:19]
       rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 447:61]
-    inst rvclkhdr_12 of rvclkhdr_844 @[lib.scala 352:23]
+    node _T_1241 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 451:61]
+    inst rvclkhdr_12 of rvclkhdr_846 @[lib.scala 352:23]
     rvclkhdr_12.clock <= clock
     rvclkhdr_12.reset <= reset
     rvclkhdr_12.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_12.io.en <= _T_1221 @[lib.scala 355:17]
+    rvclkhdr_12.io.en <= _T_1241 @[lib.scala 355:17]
     rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 358:16]
-    node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 449:44]
-    node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 449:42]
-    node _T_1224 = not(_T_1223) @[dma_ctrl.scala 449:30]
-    io.dma_axi.aw.ready <= _T_1224 @[dma_ctrl.scala 449:27]
-    node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 450:49]
-    node _T_1226 = and(wrbuf_data_vld, _T_1225) @[dma_ctrl.scala 450:47]
-    node _T_1227 = not(_T_1226) @[dma_ctrl.scala 450:30]
-    io.dma_axi.w.ready <= _T_1227 @[dma_ctrl.scala 450:27]
-    node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 451:44]
-    node _T_1229 = and(rdbuf_vld, _T_1228) @[dma_ctrl.scala 451:42]
-    node _T_1230 = not(_T_1229) @[dma_ctrl.scala 451:30]
-    io.dma_axi.ar.ready <= _T_1230 @[dma_ctrl.scala 451:27]
-    node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 455:51]
-    node _T_1232 = or(_T_1231, rdbuf_vld) @[dma_ctrl.scala 455:69]
-    bus_cmd_valid <= _T_1232 @[dma_ctrl.scala 455:37]
-    node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 456:54]
-    axi_mstr_prty_en <= _T_1233 @[dma_ctrl.scala 456:37]
-    bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 457:37]
-    bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 458:25]
-    node _T_1234 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 459:57]
-    node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 459:43]
-    bus_cmd_addr <= _T_1235 @[dma_ctrl.scala 459:37]
-    node _T_1236 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 460:59]
-    node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 460:45]
-    bus_cmd_sz <= _T_1237 @[dma_ctrl.scala 460:39]
-    bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 461:37]
-    bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 462:37]
-    node _T_1238 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57]
-    node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 463:43]
-    bus_cmd_tag <= _T_1239 @[dma_ctrl.scala 463:37]
-    bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 464:37]
-    bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 465:37]
-    node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:43]
-    node _T_1241 = and(_T_1240, rdbuf_vld) @[dma_ctrl.scala 469:60]
-    node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[dma_ctrl.scala 469:73]
-    node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:111]
-    node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[dma_ctrl.scala 469:31]
-    axi_mstr_sel <= _T_1244 @[dma_ctrl.scala 469:25]
-    node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 470:27]
-    node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 474:55]
-    reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_1245 : @[Reg.scala 28:19]
-      _T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23]
+    node _T_1242 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 453:44]
+    node _T_1243 = and(wrbuf_vld, _T_1242) @[dma_ctrl.scala 453:42]
+    node _T_1244 = not(_T_1243) @[dma_ctrl.scala 453:30]
+    io.dma_axi.aw.ready <= _T_1244 @[dma_ctrl.scala 453:27]
+    node _T_1245 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 454:49]
+    node _T_1246 = and(wrbuf_data_vld, _T_1245) @[dma_ctrl.scala 454:47]
+    node _T_1247 = not(_T_1246) @[dma_ctrl.scala 454:30]
+    io.dma_axi.w.ready <= _T_1247 @[dma_ctrl.scala 454:27]
+    node _T_1248 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 455:44]
+    node _T_1249 = and(rdbuf_vld, _T_1248) @[dma_ctrl.scala 455:42]
+    node _T_1250 = not(_T_1249) @[dma_ctrl.scala 455:30]
+    io.dma_axi.ar.ready <= _T_1250 @[dma_ctrl.scala 455:27]
+    node _T_1251 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 459:51]
+    node _T_1252 = or(_T_1251, rdbuf_vld) @[dma_ctrl.scala 459:69]
+    bus_cmd_valid <= _T_1252 @[dma_ctrl.scala 459:37]
+    node _T_1253 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 460:54]
+    axi_mstr_prty_en <= _T_1253 @[dma_ctrl.scala 460:37]
+    bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 461:37]
+    bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 462:25]
+    node _T_1254 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57]
+    node _T_1255 = mux(_T_1254, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 463:43]
+    bus_cmd_addr <= _T_1255 @[dma_ctrl.scala 463:37]
+    node _T_1256 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 464:59]
+    node _T_1257 = mux(_T_1256, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 464:45]
+    bus_cmd_sz <= _T_1257 @[dma_ctrl.scala 464:39]
+    bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 465:37]
+    bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 466:37]
+    node _T_1258 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 467:57]
+    node _T_1259 = mux(_T_1258, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 467:43]
+    bus_cmd_tag <= _T_1259 @[dma_ctrl.scala 467:37]
+    bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 468:37]
+    bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 469:37]
+    node _T_1260 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:43]
+    node _T_1261 = and(_T_1260, rdbuf_vld) @[dma_ctrl.scala 473:60]
+    node _T_1262 = eq(_T_1261, UInt<1>("h01")) @[dma_ctrl.scala 473:73]
+    node _T_1263 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:111]
+    node _T_1264 = mux(_T_1262, axi_mstr_priority, _T_1263) @[dma_ctrl.scala 473:31]
+    axi_mstr_sel <= _T_1264 @[dma_ctrl.scala 473:25]
+    node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 474:27]
+    node _T_1265 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 478:55]
+    reg _T_1266 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1265 : @[Reg.scala 28:19]
+      _T_1266 <= axi_mstr_prty_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    axi_mstr_priority <= _T_1246 @[dma_ctrl.scala 473:27]
-    node _T_1247 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 477:39]
-    node _T_1248 = bits(_T_1247, 0, 0) @[dma_ctrl.scala 477:39]
-    node _T_1249 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 477:59]
-    node _T_1250 = bits(_T_1249, 0, 0) @[dma_ctrl.scala 477:59]
-    node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dma_ctrl.scala 477:50]
-    node _T_1252 = and(_T_1248, _T_1251) @[dma_ctrl.scala 477:48]
-    node _T_1253 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 477:83]
-    node _T_1254 = bits(_T_1253, 0, 0) @[dma_ctrl.scala 477:83]
-    node axi_rsp_valid = and(_T_1252, _T_1254) @[dma_ctrl.scala 477:68]
-    node _T_1255 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 479:39]
-    node axi_rsp_write = bits(_T_1255, 0, 0) @[dma_ctrl.scala 479:39]
-    node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 480:51]
-    node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 480:83]
-    node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 480:64]
-    node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[dma_ctrl.scala 480:32]
-    node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 486:44]
-    io.dma_axi.b.valid <= _T_1259 @[dma_ctrl.scala 486:27]
-    node _T_1260 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 487:57]
-    io.dma_axi.b.bits.resp <= _T_1260 @[dma_ctrl.scala 487:41]
-    io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 488:33]
-    node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 490:46]
-    node _T_1262 = and(axi_rsp_valid, _T_1261) @[dma_ctrl.scala 490:44]
-    io.dma_axi.r.valid <= _T_1262 @[dma_ctrl.scala 490:27]
-    io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 491:41]
-    node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 492:59]
-    io.dma_axi.r.bits.data <= _T_1263 @[dma_ctrl.scala 492:43]
-    io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 493:41]
-    io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 494:37]
-    bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 496:25]
-    node _T_1264 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 497:60]
-    bus_rsp_valid <= _T_1264 @[dma_ctrl.scala 497:37]
-    node _T_1265 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 498:61]
-    node _T_1266 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 498:105]
-    node _T_1267 = or(_T_1265, _T_1266) @[dma_ctrl.scala 498:83]
-    bus_rsp_sent <= _T_1267 @[dma_ctrl.scala 498:37]
-    io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 499:40]
-    io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 500:41]
-    io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 501:37]
-    io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 502:39]
-    io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 503:40]
-    io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 504:40]
-    io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 505:38]
-    
-  extmodule gated_latch_845 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_845 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_845 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_846 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_846 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_846 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    axi_mstr_priority <= _T_1266 @[dma_ctrl.scala 477:27]
+    node _T_1267 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 481:39]
+    node _T_1268 = bits(_T_1267, 0, 0) @[dma_ctrl.scala 481:39]
+    node _T_1269 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 481:59]
+    node _T_1270 = bits(_T_1269, 0, 0) @[dma_ctrl.scala 481:59]
+    node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[dma_ctrl.scala 481:50]
+    node _T_1272 = and(_T_1268, _T_1271) @[dma_ctrl.scala 481:48]
+    node _T_1273 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 481:83]
+    node _T_1274 = bits(_T_1273, 0, 0) @[dma_ctrl.scala 481:83]
+    node axi_rsp_valid = and(_T_1272, _T_1274) @[dma_ctrl.scala 481:68]
+    node _T_1275 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 483:39]
+    node axi_rsp_write = bits(_T_1275, 0, 0) @[dma_ctrl.scala 483:39]
+    node _T_1276 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 484:51]
+    node _T_1277 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 484:83]
+    node _T_1278 = mux(_T_1277, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 484:64]
+    node axi_rsp_error = mux(_T_1276, UInt<2>("h02"), _T_1278) @[dma_ctrl.scala 484:32]
+    node _T_1279 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 490:44]
+    io.dma_axi.b.valid <= _T_1279 @[dma_ctrl.scala 490:27]
+    node _T_1280 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 491:57]
+    io.dma_axi.b.bits.resp <= _T_1280 @[dma_ctrl.scala 491:41]
+    io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 492:33]
+    node _T_1281 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 494:46]
+    node _T_1282 = and(axi_rsp_valid, _T_1281) @[dma_ctrl.scala 494:44]
+    io.dma_axi.r.valid <= _T_1282 @[dma_ctrl.scala 494:27]
+    io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 495:41]
+    node _T_1283 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 496:59]
+    io.dma_axi.r.bits.data <= _T_1283 @[dma_ctrl.scala 496:43]
+    io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 497:41]
+    io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 498:37]
+    bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 500:25]
+    node _T_1284 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 501:60]
+    bus_rsp_valid <= _T_1284 @[dma_ctrl.scala 501:37]
+    node _T_1285 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 502:61]
+    node _T_1286 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 502:105]
+    node _T_1287 = or(_T_1285, _T_1286) @[dma_ctrl.scala 502:83]
+    bus_rsp_sent <= _T_1287 @[dma_ctrl.scala 502:37]
+    io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 503:40]
+    io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 504:41]
+    io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 505:37]
+    io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 506:39]
+    io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 507:40]
+    io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 508:40]
+    io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 509:38]
     
   extmodule gated_latch_847 : 
     output Q : Clock
@@ -109257,10 +109285,58 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_857 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_857 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_857 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_858 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_858 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_858 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module axi4_to_ahb : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
+    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
     
     wire buf_rst : UInt<1>
     buf_rst <= UInt<1>("h00")
@@ -109486,7 +109562,7 @@ circuit quasar_wrapper :
     node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74]
     node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37]
     bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20]
-    inst rvclkhdr of rvclkhdr_847 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_849 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
@@ -109494,7 +109570,7 @@ circuit quasar_wrapper :
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11]
     node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59]
-    inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 327:22]
+    inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
@@ -110254,7 +110330,7 @@ circuit quasar_wrapper :
       skip @[Reg.scala 28:19]
     wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21]
     node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55]
-    inst rvclkhdr_2 of rvclkhdr_849 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= bus_clk @[lib.scala 354:18]
@@ -110264,7 +110340,7 @@ circuit quasar_wrapper :
     _T_652 <= io.axi_awaddr @[lib.scala 358:16]
     wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21]
     node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59]
-    inst rvclkhdr_3 of rvclkhdr_850 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= bus_clk @[lib.scala 354:18]
@@ -110303,7 +110379,7 @@ circuit quasar_wrapper :
     node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42]
     node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61]
     node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78]
-    inst rvclkhdr_4 of rvclkhdr_851 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -110335,7 +110411,7 @@ circuit quasar_wrapper :
     node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42]
     node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66]
     node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89]
-    inst rvclkhdr_5 of rvclkhdr_852 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -110407,28 +110483,28 @@ circuit quasar_wrapper :
     node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60]
     node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36]
     ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19]
-    inst rvclkhdr_6 of rvclkhdr_853 @[lib.scala 327:22]
+    inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 327:22]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16]
     rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12]
-    inst rvclkhdr_7 of rvclkhdr_854 @[lib.scala 327:22]
+    inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 327:22]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16]
     rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12]
-    inst rvclkhdr_8 of rvclkhdr_855 @[lib.scala 327:22]
+    inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 327:22]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16]
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17]
-    inst rvclkhdr_9 of rvclkhdr_856 @[lib.scala 327:22]
+    inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 327:22]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 328:17]
@@ -110436,54 +110512,6 @@ circuit quasar_wrapper :
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17]
     
-  extmodule gated_latch_857 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_857 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_857 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_858 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_858 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_858 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_859 : 
     output Q : Clock
     input CK : Clock
@@ -110676,10 +110704,58 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_867 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_867 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_867 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_868 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_868 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_868 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module axi4_to_ahb_1 : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
+    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
     
     wire buf_rst : UInt<1>
     buf_rst <= UInt<1>("h00")
@@ -110905,7 +110981,7 @@ circuit quasar_wrapper :
     node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74]
     node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37]
     bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20]
-    inst rvclkhdr of rvclkhdr_857 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_859 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
@@ -110913,7 +110989,7 @@ circuit quasar_wrapper :
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11]
     node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59]
-    inst rvclkhdr_1 of rvclkhdr_858 @[lib.scala 327:22]
+    inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
@@ -111673,7 +111749,7 @@ circuit quasar_wrapper :
       skip @[Reg.scala 28:19]
     wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21]
     node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55]
-    inst rvclkhdr_2 of rvclkhdr_859 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= bus_clk @[lib.scala 354:18]
@@ -111683,7 +111759,7 @@ circuit quasar_wrapper :
     _T_652 <= io.axi_awaddr @[lib.scala 358:16]
     wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21]
     node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59]
-    inst rvclkhdr_3 of rvclkhdr_860 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= bus_clk @[lib.scala 354:18]
@@ -111722,7 +111798,7 @@ circuit quasar_wrapper :
     node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42]
     node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61]
     node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78]
-    inst rvclkhdr_4 of rvclkhdr_861 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -111754,7 +111830,7 @@ circuit quasar_wrapper :
     node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42]
     node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66]
     node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89]
-    inst rvclkhdr_5 of rvclkhdr_862 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -111826,28 +111902,28 @@ circuit quasar_wrapper :
     node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60]
     node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36]
     ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19]
-    inst rvclkhdr_6 of rvclkhdr_863 @[lib.scala 327:22]
+    inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 327:22]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16]
     rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12]
-    inst rvclkhdr_7 of rvclkhdr_864 @[lib.scala 327:22]
+    inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 327:22]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16]
     rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12]
-    inst rvclkhdr_8 of rvclkhdr_865 @[lib.scala 327:22]
+    inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 327:22]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16]
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17]
-    inst rvclkhdr_9 of rvclkhdr_866 @[lib.scala 327:22]
+    inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 327:22]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 328:17]
@@ -111855,54 +111931,6 @@ circuit quasar_wrapper :
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17]
     
-  extmodule gated_latch_867 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_867 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_867 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_868 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_868 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_868 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_869 : 
     output Q : Clock
     input CK : Clock
@@ -112095,10 +112123,58 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_877 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_877 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_877 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_878 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_878 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_878 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module axi4_to_ahb_2 : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
+    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
     
     wire buf_rst : UInt<1>
     buf_rst <= UInt<1>("h00")
@@ -112324,7 +112400,7 @@ circuit quasar_wrapper :
     node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 193:74]
     node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 193:37]
     bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 193:20]
-    inst rvclkhdr of rvclkhdr_867 @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr_869 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
@@ -112332,7 +112408,7 @@ circuit quasar_wrapper :
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 195:11]
     node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 196:59]
-    inst rvclkhdr_1 of rvclkhdr_868 @[lib.scala 327:22]
+    inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
@@ -113092,7 +113168,7 @@ circuit quasar_wrapper :
       skip @[Reg.scala 28:19]
     wrbuf_size <= _T_650 @[axi4_to_ahb.scala 375:21]
     node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:55]
-    inst rvclkhdr_2 of rvclkhdr_869 @[lib.scala 352:23]
+    inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 352:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= bus_clk @[lib.scala 354:18]
@@ -113102,7 +113178,7 @@ circuit quasar_wrapper :
     _T_652 <= io.axi_awaddr @[lib.scala 358:16]
     wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 376:21]
     node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:59]
-    inst rvclkhdr_3 of rvclkhdr_870 @[lib.scala 352:23]
+    inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= bus_clk @[lib.scala 354:18]
@@ -113141,7 +113217,7 @@ circuit quasar_wrapper :
     node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 382:42]
     node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 382:61]
     node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 382:78]
-    inst rvclkhdr_4 of rvclkhdr_871 @[lib.scala 352:23]
+    inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
@@ -113173,7 +113249,7 @@ circuit quasar_wrapper :
     node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 386:42]
     node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 386:66]
     node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 386:89]
-    inst rvclkhdr_5 of rvclkhdr_872 @[lib.scala 352:23]
+    inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 352:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
@@ -113245,28 +113321,28 @@ circuit quasar_wrapper :
     node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 400:60]
     node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 400:36]
     ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 400:19]
-    inst rvclkhdr_6 of rvclkhdr_873 @[lib.scala 327:22]
+    inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 327:22]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
     rvclkhdr_6.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_6.io.en <= buf_clken @[lib.scala 329:16]
     rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 403:12]
-    inst rvclkhdr_7 of rvclkhdr_874 @[lib.scala 327:22]
+    inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 327:22]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
     rvclkhdr_7.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 329:16]
     rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 404:12]
-    inst rvclkhdr_8 of rvclkhdr_875 @[lib.scala 327:22]
+    inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 327:22]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
     rvclkhdr_8.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 329:16]
     rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 405:17]
-    inst rvclkhdr_9 of rvclkhdr_876 @[lib.scala 327:22]
+    inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 327:22]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
     rvclkhdr_9.io.clk <= clock @[lib.scala 328:17]
@@ -113274,54 +113350,6 @@ circuit quasar_wrapper :
     rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
     ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 406:17]
     
-  extmodule gated_latch_877 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_877 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_877 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
-  extmodule gated_latch_878 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_878 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_878 @[lib.scala 318:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
-    
   extmodule gated_latch_879 : 
     output Q : Clock
     input CK : Clock
@@ -113418,10 +113446,58 @@ circuit quasar_wrapper :
     clkhdr.EN <= io.en @[lib.scala 321:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
     
+  extmodule gated_latch_883 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_883 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_883 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
+  extmodule gated_latch_884 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_884 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_884 @[lib.scala 318:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
+    clkhdr.CK <= io.clk @[lib.scala 320:18]
+    clkhdr.EN <= io.en @[lib.scala 321:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    
   module ahb_to_axi4 : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, flip ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}}
+    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}}
     
     wire master_wstrb : UInt<8>
     master_wstrb <= UInt<8>("h00")
@@ -113457,9 +113533,9 @@ circuit quasar_wrapper :
     ahb_bus_addr_clk_en <= UInt<1>("h00")
     wire buf_rdata_clk_en : UInt<1>
     buf_rdata_clk_en <= UInt<1>("h00")
-    wire ahb_clk : Clock @[ahb_to_axi4.scala 86:33]
-    wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 87:33]
-    wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 88:33]
+    wire ahb_clk : Clock @[ahb_to_axi4.scala 89:33]
+    wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 90:33]
+    wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 91:33]
     wire cmdbuf_wr_en : UInt<1>
     cmdbuf_wr_en <= UInt<1>("h00")
     wire cmdbuf_rst : UInt<1>
@@ -113478,7 +113554,7 @@ circuit quasar_wrapper :
     cmdbuf_addr <= UInt<32>("h00")
     wire cmdbuf_wdata : UInt<64>
     cmdbuf_wdata <= UInt<64>("h00")
-    wire bus_clk : Clock @[ahb_to_axi4.scala 100:33]
+    wire bus_clk : Clock @[ahb_to_axi4.scala 103:33]
     node _T = bits(ahb_haddr_q, 31, 28) @[lib.scala 68:25]
     node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[lib.scala 68:47]
     node _T_1 = bits(ahb_haddr_q, 31, 16) @[lib.scala 71:14]
@@ -113495,261 +113571,261 @@ circuit quasar_wrapper :
     buf_state <= UInt<2>("h00")
     wire buf_nxtstate : UInt<2>
     buf_nxtstate <= UInt<2>("h00")
-    buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 110:31]
-    buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 111:31]
-    buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 112:31]
-    buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 113:31]
-    cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 114:31]
+    buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 113:31]
+    buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 114:31]
+    buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 115:31]
+    buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 116:31]
+    cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 117:31]
     node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
     when _T_6 : @[Conditional.scala 40:58]
-      node _T_7 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 118:26]
-      buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 118:20]
-      node _T_8 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 119:53]
-      node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 119:34]
-      node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 119:57]
-      buf_state_en <= _T_10 @[ahb_to_axi4.scala 119:20]
+      node _T_7 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 121:26]
+      buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 121:20]
+      node _T_8 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 122:57]
+      node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 122:34]
+      node _T_10 = and(_T_9, io.ahb.hsel) @[ahb_to_axi4.scala 122:61]
+      buf_state_en <= _T_10 @[ahb_to_axi4.scala 122:20]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
       node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
       when _T_11 : @[Conditional.scala 39:67]
-        node _T_12 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 122:64]
-        node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 122:71]
-        node _T_14 = or(io.ahb.in.hresp, _T_13) @[ahb_to_axi4.scala 122:44]
-        node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 122:85]
-        node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 122:83]
-        node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 122:99]
-        node _T_18 = mux(io.ahb.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 122:116]
-        node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 122:26]
-        buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 122:20]
-        node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 123:24]
-        node _T_21 = or(_T_20, io.ahb.in.hresp) @[ahb_to_axi4.scala 123:37]
-        buf_state_en <= _T_21 @[ahb_to_axi4.scala 123:20]
-        node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 124:23]
-        node _T_23 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 124:77]
-        node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 124:84]
-        node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 124:102]
-        node _T_26 = or(io.ahb.in.hresp, _T_25) @[ahb_to_axi4.scala 124:56]
-        node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 124:38]
-        node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 124:36]
-        cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 124:20]
+        node _T_12 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 125:72]
+        node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 125:79]
+        node _T_14 = or(io.ahb.sig.in.hresp, _T_13) @[ahb_to_axi4.scala 125:48]
+        node _T_15 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 125:93]
+        node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 125:91]
+        node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 125:107]
+        node _T_18 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 125:124]
+        node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 125:26]
+        buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 125:20]
+        node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 126:24]
+        node _T_21 = or(_T_20, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 126:37]
+        buf_state_en <= _T_21 @[ahb_to_axi4.scala 126:20]
+        node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 127:23]
+        node _T_23 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 127:85]
+        node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 127:92]
+        node _T_25 = and(_T_24, io.ahb.hsel) @[ahb_to_axi4.scala 127:110]
+        node _T_26 = or(io.ahb.sig.in.hresp, _T_25) @[ahb_to_axi4.scala 127:60]
+        node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 127:38]
+        node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 127:36]
+        cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 127:20]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
         node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
         when _T_29 : @[Conditional.scala 39:67]
-          node _T_30 = mux(io.ahb.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 127:26]
-          buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 127:20]
-          node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 128:24]
-          node _T_32 = or(_T_31, io.ahb.in.hresp) @[ahb_to_axi4.scala 128:37]
-          buf_state_en <= _T_32 @[ahb_to_axi4.scala 128:20]
-          node _T_33 = eq(io.ahb.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 129:23]
-          node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 129:42]
-          node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 129:40]
-          cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 129:20]
+          node _T_30 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 130:26]
+          buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 130:20]
+          node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 131:24]
+          node _T_32 = or(_T_31, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 131:37]
+          buf_state_en <= _T_32 @[ahb_to_axi4.scala 131:20]
+          node _T_33 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 132:23]
+          node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:46]
+          node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 132:44]
+          cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 132:20]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
           node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
           when _T_36 : @[Conditional.scala 39:67]
-            buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 132:20]
-            node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 133:39]
-            node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 133:37]
-            buf_state_en <= _T_38 @[ahb_to_axi4.scala 133:20]
-            buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 134:20]
-            node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 135:55]
-            node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 135:62]
-            node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 135:41]
-            buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 135:25]
+            buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 135:20]
+            node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 136:39]
+            node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 136:37]
+            buf_state_en <= _T_38 @[ahb_to_axi4.scala 136:20]
+            buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 137:20]
+            node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 138:55]
+            node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 138:62]
+            node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 138:41]
+            buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 138:25]
             skip @[Conditional.scala 39:67]
-    node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 138:99]
+    node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 141:99]
     reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_42 : @[Reg.scala 28:19]
       _T_43 <= buf_nxtstate @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_state <= _T_43 @[ahb_to_axi4.scala 138:31]
-    node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 140:54]
-    node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 140:60]
+    buf_state <= _T_43 @[ahb_to_axi4.scala 141:31]
+    node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 143:54]
+    node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 143:60]
     node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15]
     node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 140:92]
-    node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 140:78]
-    node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 140:70]
-    node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 141:24]
-    node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 141:30]
+    node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 143:92]
+    node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 143:78]
+    node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 143:70]
+    node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 144:24]
+    node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 144:30]
     node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15]
     node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 141:62]
-    node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 141:48]
-    node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 141:40]
-    node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 140:109]
-    node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 142:24]
-    node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 142:30]
+    node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 144:62]
+    node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 144:48]
+    node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 144:40]
+    node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 143:109]
+    node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 145:24]
+    node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 145:30]
     node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
     node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 142:62]
-    node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 142:48]
-    node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 142:40]
-    node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 141:79]
-    node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 143:24]
-    node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 143:30]
+    node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 145:62]
+    node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 145:48]
+    node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 145:40]
+    node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 144:79]
+    node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 146:24]
+    node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 146:30]
     node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15]
     node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 143:40]
-    node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 142:79]
-    master_wstrb <= _T_72 @[ahb_to_axi4.scala 140:31]
-    node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 146:72]
-    node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 146:70]
-    node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 146:90]
-    node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 146:116]
-    node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 146:103]
-    node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 146:141]
-    node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 146:160]
-    node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 146:148]
-    node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 146:129]
-    node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 146:127]
-    node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 146:173]
-    node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 146:171]
-    node _T_85 = mux(io.ahb.in.hresp, _T_74, _T_84) @[ahb_to_axi4.scala 146:40]
-    io.ahb.in.hready <= _T_85 @[ahb_to_axi4.scala 146:34]
-    node _T_86 = and(io.ahb.in.hready, io.ahb_hreadyin) @[ahb_to_axi4.scala 147:51]
-    ahb_hready <= _T_86 @[ahb_to_axi4.scala 147:31]
-    node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15]
+    node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 146:40]
+    node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 145:79]
+    master_wstrb <= _T_72 @[ahb_to_axi4.scala 143:31]
+    node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 149:80]
+    node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 149:78]
+    node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 149:98]
+    node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 149:124]
+    node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 149:111]
+    node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 149:149]
+    node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 149:168]
+    node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 149:156]
+    node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 149:137]
+    node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 149:135]
+    node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 149:181]
+    node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 149:179]
+    node _T_85 = mux(io.ahb.sig.in.hresp, _T_74, _T_84) @[ahb_to_axi4.scala 149:44]
+    io.ahb.sig.in.hready <= _T_85 @[ahb_to_axi4.scala 149:38]
+    node _T_86 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 150:55]
+    ahb_hready <= _T_86 @[ahb_to_axi4.scala 150:31]
+    node _T_87 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
     node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_89 = bits(io.ahb.out.htrans, 1, 0) @[ahb_to_axi4.scala 148:73]
-    node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 148:54]
-    ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 148:31]
-    node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 149:46]
-    io.ahb.in.hrdata <= _T_91 @[ahb_to_axi4.scala 149:34]
-    node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 150:51]
-    node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 150:57]
-    node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 150:79]
-    node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 150:66]
-    node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 151:26]
-    node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 151:7]
-    node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 152:46]
-    node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 152:26]
-    node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:80]
-    node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 152:86]
-    node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 152:109]
-    node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 152:115]
-    node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 152:95]
-    node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 152:66]
-    node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 152:64]
-    node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 151:47]
-    node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 153:20]
-    node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 153:26]
-    node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 153:48]
-    node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 153:35]
-    node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 152:126]
-    node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 154:20]
-    node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 154:26]
-    node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 154:49]
-    node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 154:56]
-    node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 154:35]
-    node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 153:55]
-    node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 155:20]
-    node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 155:26]
-    node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 155:49]
-    node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 155:56]
-    node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 155:35]
-    node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 154:61]
-    node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 150:90]
-    node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 155:63]
-    node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 157:20]
-    node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 157:18]
-    node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 156:20]
-    io.ahb.in.hresp <= _T_129 @[ahb_to_axi4.scala 150:34]
-    reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 160:66]
-    _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 160:66]
-    buf_rdata <= _T_130 @[ahb_to_axi4.scala 160:31]
-    reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 161:60]
-    _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 161:60]
-    buf_read_error <= _T_131 @[ahb_to_axi4.scala 161:31]
-    reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60]
-    _T_132 <= io.ahb.in.hresp @[ahb_to_axi4.scala 164:60]
-    ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 164:31]
-    reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 165:60]
-    _T_133 <= ahb_hready @[ahb_to_axi4.scala 165:60]
-    ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 165:31]
-    reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 166:60]
-    _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 166:60]
-    ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 166:31]
-    reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:65]
-    _T_135 <= io.ahb.out.hsize @[ahb_to_axi4.scala 167:65]
-    ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 167:31]
-    reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:65]
-    _T_136 <= io.ahb.out.hwrite @[ahb_to_axi4.scala 168:65]
-    ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 168:31]
-    reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:65]
-    _T_137 <= io.ahb.out.haddr @[ahb_to_axi4.scala 169:65]
-    ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 169:31]
-    node _T_138 = bits(io.ahb.out.htrans, 1, 1) @[ahb_to_axi4.scala 172:81]
-    node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 172:62]
-    node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 172:48]
-    ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 172:31]
-    node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 173:48]
-    buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 173:31]
-    inst rvclkhdr of rvclkhdr_877 @[lib.scala 327:22]
+    node _T_89 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 151:77]
+    node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 151:54]
+    ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 151:31]
+    node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 152:50]
+    io.ahb.sig.in.hrdata <= _T_91 @[ahb_to_axi4.scala 152:38]
+    node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 153:55]
+    node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 153:61]
+    node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 153:83]
+    node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 153:70]
+    node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 154:26]
+    node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 154:7]
+    node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 155:46]
+    node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 155:26]
+    node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 155:80]
+    node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 155:86]
+    node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 155:109]
+    node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 155:115]
+    node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 155:95]
+    node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 155:66]
+    node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 155:64]
+    node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 154:47]
+    node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 156:20]
+    node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 156:26]
+    node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 156:48]
+    node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 156:35]
+    node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 155:126]
+    node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 157:20]
+    node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 157:26]
+    node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 157:49]
+    node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 157:56]
+    node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 157:35]
+    node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 156:55]
+    node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 158:20]
+    node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 158:26]
+    node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 158:49]
+    node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 158:56]
+    node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 158:35]
+    node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 157:61]
+    node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 153:94]
+    node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 158:63]
+    node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 160:20]
+    node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 160:18]
+    node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 159:20]
+    io.ahb.sig.in.hresp <= _T_129 @[ahb_to_axi4.scala 153:38]
+    reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 163:66]
+    _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 163:66]
+    buf_rdata <= _T_130 @[ahb_to_axi4.scala 163:31]
+    reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 164:60]
+    _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 164:60]
+    buf_read_error <= _T_131 @[ahb_to_axi4.scala 164:31]
+    reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 167:60]
+    _T_132 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 167:60]
+    ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 167:31]
+    reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:60]
+    _T_133 <= ahb_hready @[ahb_to_axi4.scala 168:60]
+    ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 168:31]
+    reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:60]
+    _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 169:60]
+    ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 169:31]
+    reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 170:65]
+    _T_135 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 170:65]
+    ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 170:31]
+    reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 171:65]
+    _T_136 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 171:65]
+    ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 171:31]
+    reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 172:65]
+    _T_137 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 172:65]
+    ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 172:31]
+    node _T_138 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 175:85]
+    node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 175:62]
+    node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 175:48]
+    ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 175:31]
+    node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 176:48]
+    buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 176:31]
+    inst rvclkhdr of rvclkhdr_879 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 329:16]
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 175:31]
-    inst rvclkhdr_1 of rvclkhdr_878 @[lib.scala 327:22]
+    ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 178:31]
+    inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 329:16]
     rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 176:31]
-    inst rvclkhdr_2 of rvclkhdr_879 @[lib.scala 327:22]
+    ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 179:31]
+    inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 327:22]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 329:16]
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 177:31]
-    node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 179:52]
-    node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 179:88]
-    node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 179:70]
-    node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 179:109]
-    node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 179:107]
-    node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 179:145]
-    node _T_148 = and(io.ahb.in.hresp, _T_147) @[ahb_to_axi4.scala 179:143]
-    node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 179:124]
-    cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 179:31]
-    node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 180:66]
-    node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 180:102]
-    node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 180:84]
-    node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 180:48]
-    node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 180:46]
-    cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 180:31]
-    node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 182:86]
-    node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 182:66]
-    node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 182:110]
-    node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 182:108]
-    reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 182:61]
-    _T_159 <= _T_158 @[ahb_to_axi4.scala 182:61]
-    cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 182:31]
-    node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 186:53]
+    buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 180:31]
+    node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 182:52]
+    node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 182:88]
+    node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 182:70]
+    node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 182:109]
+    node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 182:107]
+    node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 182:149]
+    node _T_148 = and(io.ahb.sig.in.hresp, _T_147) @[ahb_to_axi4.scala 182:147]
+    node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 182:124]
+    cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 182:31]
+    node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 183:66]
+    node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 183:102]
+    node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 183:84]
+    node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 183:48]
+    node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 183:46]
+    cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 183:31]
+    node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 185:86]
+    node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 185:66]
+    node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 185:110]
+    node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 185:108]
+    reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 185:61]
+    _T_159 <= _T_158 @[ahb_to_axi4.scala 185:61]
+    cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 185:31]
+    node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 189:53]
     reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_160 : @[Reg.scala 28:19]
       _T_161 <= ahb_hwrite_q @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 185:31]
-    node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 189:52]
+    cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 188:31]
+    node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 192:52]
     reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_162 : @[Reg.scala 28:19]
       _T_163 <= ahb_hsize_q @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 188:31]
-    node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 192:53]
+    cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 191:31]
+    node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:53]
     reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_164 : @[Reg.scala 28:19]
       _T_165 <= master_wstrb @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 191:31]
-    node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:57]
-    inst rvclkhdr_3 of rvclkhdr_880 @[lib.scala 352:23]
+    cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 194:31]
+    node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 198:57]
+    inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 352:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= bus_clk @[lib.scala 354:18]
@@ -113757,995 +113833,995 @@ circuit quasar_wrapper :
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
     _T_167 <= ahb_haddr_q @[lib.scala 358:16]
-    cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 195:15]
-    node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 196:64]
-    inst rvclkhdr_4 of rvclkhdr_881 @[lib.scala 352:23]
+    cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 198:15]
+    node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 199:68]
+    inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 352:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= bus_clk @[lib.scala 354:18]
     rvclkhdr_4.io.en <= _T_168 @[lib.scala 355:17]
     rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
     reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_169 <= io.ahb.out.hwdata @[lib.scala 358:16]
-    cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 196:16]
-    node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 199:41]
-    io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 199:27]
-    io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 200:27]
-    io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 201:27]
-    node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 202:53]
+    _T_169 <= io.ahb.sig.out.hwdata @[lib.scala 358:16]
+    cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 199:16]
+    node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 202:41]
+    io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 202:27]
+    io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 203:27]
+    io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 204:27]
+    node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 205:53]
     node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58]
-    io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 202:27]
+    io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 205:27]
     node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 203:27]
+    io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 206:27]
     node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 204:27]
-    io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 205:27]
-    node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 207:41]
-    io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 207:27]
-    io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 208:27]
-    io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 209:27]
-    io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 210:27]
-    io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 212:27]
-    node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 214:43]
-    node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 214:41]
-    io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 214:27]
-    io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 215:27]
-    io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 216:27]
-    node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 217:53]
+    io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 207:27]
+    io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 208:27]
+    node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 210:41]
+    io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 210:27]
+    io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 211:27]
+    io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 212:27]
+    io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 213:27]
+    io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 215:27]
+    node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 217:43]
+    node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 217:41]
+    io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 217:27]
+    io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 218:27]
+    io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 219:27]
+    node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 220:53]
     node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58]
-    io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 217:27]
+    io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 220:27]
     node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 218:27]
+    io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 221:27]
     node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 219:27]
-    io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 220:27]
-    io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 222:27]
-    inst rvclkhdr_5 of rvclkhdr_882 @[lib.scala 327:22]
+    io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 222:27]
+    io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 223:27]
+    io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 225:27]
+    inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 327:22]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 329:16]
     rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 225:27]
+    bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 228:27]
     
   module quasar : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip dma_hsel : UInt<1>, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst ifu of ifu @[quasar.scala 122:19]
+    inst ifu of ifu @[quasar.scala 125:19]
     ifu.clock <= clock
     ifu.reset <= reset
-    inst dec of dec @[quasar.scala 123:19]
+    inst dec of dec @[quasar.scala 126:19]
     dec.clock <= clock
     dec.reset <= reset
-    inst dbg of dbg @[quasar.scala 124:19]
+    inst dbg of dbg @[quasar.scala 127:19]
     dbg.clock <= clock
     dbg.reset <= reset
-    inst exu of exu @[quasar.scala 125:19]
+    inst exu of exu @[quasar.scala 128:19]
     exu.clock <= clock
     exu.reset <= reset
-    inst lsu of lsu @[quasar.scala 126:19]
+    inst lsu of lsu @[quasar.scala 129:19]
     lsu.clock <= clock
     lsu.reset <= reset
-    inst pic_ctrl_inst of pic_ctrl @[quasar.scala 127:29]
+    inst pic_ctrl_inst of pic_ctrl @[quasar.scala 130:29]
     pic_ctrl_inst.clock <= clock
     pic_ctrl_inst.reset <= reset
-    inst dma_ctrl of dma_ctrl @[quasar.scala 128:24]
+    inst dma_ctrl of dma_ctrl @[quasar.scala 131:24]
     dma_ctrl.clock <= clock
     dma_ctrl.reset <= reset
-    node _T = asUInt(reset) @[quasar.scala 130:33]
-    node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 130:67]
-    node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 130:70]
-    node _T_3 = and(_T, _T_2) @[quasar.scala 130:36]
-    node _T_4 = asAsyncReset(_T_3) @[quasar.scala 130:99]
-    io.core_rst_l <= _T_4 @[quasar.scala 130:17]
-    node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 131:23]
-    node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 131:50]
-    node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 131:98]
-    inst rvclkhdr of rvclkhdr_845 @[lib.scala 327:22]
+    node _T = asUInt(reset) @[quasar.scala 133:33]
+    node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 133:67]
+    node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 133:70]
+    node _T_3 = and(_T, _T_2) @[quasar.scala 133:36]
+    node _T_4 = asAsyncReset(_T_3) @[quasar.scala 133:99]
+    io.core_rst_l <= _T_4 @[quasar.scala 133:17]
+    node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 134:23]
+    node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 134:50]
+    node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 134:98]
+    inst rvclkhdr of rvclkhdr_847 @[lib.scala 327:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
     rvclkhdr.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 329:16]
     rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    node _T_7 = bits(active_state, 0, 0) @[quasar.scala 133:49]
-    inst rvclkhdr_1 of rvclkhdr_846 @[lib.scala 327:22]
+    node _T_7 = bits(active_state, 0, 0) @[quasar.scala 136:49]
+    inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 327:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
     rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
     rvclkhdr_1.io.en <= _T_7 @[lib.scala 329:16]
     rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 134:56]
-    node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 135:56]
-    node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 136:28]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 139:18]
-    dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 139:18]
-    ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 139:18]
-    ifu.reset <= io.core_rst_l @[quasar.scala 141:13]
-    ifu.io.scan_mode <= io.scan_mode @[quasar.scala 142:20]
-    ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 143:19]
-    ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 144:21]
-    ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 146:26]
-    ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 147:31]
-    ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 149:25]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 150:18]
-    ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 150:18]
-    io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 151:13]
-    io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 151:13]
-    io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 151:13]
-    io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 151:13]
-    io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 151:13]
-    io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 151:13]
-    ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 151:13]
-    ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 151:13]
-    ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 151:13]
-    ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 151:13]
-    ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 151:13]
-    ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 151:13]
-    ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 151:13]
-    io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 151:13]
-    io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 151:13]
-    io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 151:13]
-    io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 151:13]
-    io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 151:13]
-    io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 151:13]
-    io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 151:13]
-    io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 151:13]
-    ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 152:15]
-    ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 152:15]
-    io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 152:15]
-    io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 152:15]
-    io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 152:15]
-    io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 152:15]
-    io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 152:15]
-    io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 152:15]
-    io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 152:15]
-    ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 153:25]
-    ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 154:42]
-    ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 155:43]
-    ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 156:33]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 157:51]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 157:51]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 157:51]
-    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 157:51]
-    dec.reset <= io.core_rst_l @[quasar.scala 160:13]
-    dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 161:19]
-    dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 162:21]
-    dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 163:32]
-    dec.io.rst_vec <= io.rst_vec @[quasar.scala 164:18]
-    dec.io.nmi_int <= io.nmi_int @[quasar.scala 165:18]
-    dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 166:18]
-    dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 167:25]
-    dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 168:24]
-    dec.io.core_id <= io.core_id @[quasar.scala 169:18]
-    dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 170:29]
-    dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 171:28]
-    dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 172:28]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 173:18]
-    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 173:18]
-    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 173:18]
-    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 173:18]
-    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 173:18]
-    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 173:18]
-    dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 174:18]
-    dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 174:18]
-    dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 175:31]
-    dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 176:18]
-    dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 176:18]
-    dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 176:18]
-    dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 176:18]
-    dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 176:18]
-    dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 176:18]
-    dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 176:18]
-    dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 176:18]
-    dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 178:23]
-    dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 179:24]
-    dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 180:30]
-    dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 181:18]
-    dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 181:18]
-    dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 181:18]
-    dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 181:18]
-    dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 181:18]
-    dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 182:23]
-    dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 183:26]
-    dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 183:26]
-    dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 183:26]
-    dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 183:26]
-    dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 183:26]
-    dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 183:26]
-    dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 184:36]
-    dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 185:25]
-    dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 186:23]
-    dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 187:23]
-    dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 188:28]
-    dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 189:29]
-    dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 190:30]
-    dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 191:28]
-    dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 192:26]
-    dec.io.soft_int <= io.soft_int @[quasar.scala 194:19]
-    dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 195:23]
-    dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 196:25]
-    dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 197:26]
-    dec.io.timer_int <= io.timer_int @[quasar.scala 198:20]
-    dec.io.scan_mode <= io.scan_mode @[quasar.scala 199:20]
-    exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 202:18]
-    exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 202:18]
-    exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 202:18]
-    exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 202:18]
-    dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 202:18]
-    exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 202:18]
-    exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 202:18]
-    exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 202:18]
-    dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 202:18]
-    dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 202:18]
-    exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 202:18]
-    dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 202:18]
-    exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 202:18]
-    exu.reset <= io.core_rst_l @[quasar.scala 203:13]
-    exu.io.scan_mode <= io.scan_mode @[quasar.scala 204:20]
-    exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 205:25]
-    lsu.reset <= io.core_rst_l @[quasar.scala 208:13]
-    lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 209:23]
-    lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 210:32]
-    lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 211:35]
-    lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 212:29]
-    lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 213:35]
-    lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 214:18]
-    lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 214:18]
-    lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 215:27]
-    lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 216:16]
-    lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 216:16]
-    lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 216:16]
-    lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 217:30]
-    lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 218:26]
-    lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 219:26]
-    lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 219:26]
-    lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 221:25]
-    lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 222:18]
-    dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 222:18]
-    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 222:18]
-    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 222:18]
-    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 222:18]
-    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 222:18]
-    lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 222:18]
-    lsu.io.scan_mode <= io.scan_mode @[quasar.scala 223:20]
-    lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 224:19]
-    dbg.reset <= io.core_rst_l @[quasar.scala 227:13]
-    node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 228:32]
-    dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 228:26]
-    node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 229:60]
-    dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 229:28]
-    node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 230:60]
-    dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 230:28]
-    dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 231:29]
-    dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 232:29]
-    dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 233:34]
-    dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 234:29]
-    dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 235:21]
-    dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 236:23]
-    dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 237:24]
-    dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 238:24]
-    dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 239:17]
-    dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 239:17]
-    dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 239:17]
-    dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 239:17]
-    dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 239:17]
-    io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 239:17]
-    io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 239:17]
-    io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 239:17]
-    dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 239:17]
-    dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 239:17]
-    dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 239:17]
-    dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 239:17]
-    io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 239:17]
-    io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 239:17]
-    io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 239:17]
-    io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 239:17]
-    io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 239:17]
-    dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 239:17]
-    io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 239:17]
-    io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 239:17]
-    dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 239:17]
-    dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 240:25]
-    node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 241:42]
-    dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 241:20]
-    dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 242:23]
-    dbg.io.scan_mode <= io.scan_mode @[quasar.scala 243:20]
-    dma_ctrl.reset <= io.core_rst_l @[quasar.scala 247:18]
-    dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 248:24]
-    dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 249:30]
-    dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 250:28]
-    dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 251:25]
-    dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 252:23]
-    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 252:23]
-    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 252:23]
-    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 252:23]
-    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 252:23]
-    dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 253:26]
-    dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 253:26]
-    dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 254:28]
-    dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 255:31]
-    dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 256:29]
-    dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 257:30]
-    dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 258:26]
-    dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 259:34]
-    pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 262:30]
-    pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 263:23]
-    pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 264:29]
-    pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 265:31]
-    pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 266:33]
-    pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 267:34]
-    lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 268:28]
-    pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 268:28]
-    dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 269:28]
-    pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 269:28]
-    pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 269:28]
-    dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 269:28]
-    dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 269:28]
-    dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 269:28]
-    io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 271:19]
-    io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 271:19]
-    io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 274:24]
-    io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 275:23]
-    io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 276:31]
-    io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 277:21]
-    io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 278:24]
-    io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 279:20]
-    io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 280:26]
-    io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 281:25]
-    io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 282:24]
-    io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 283:25]
-    io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 284:23]
-    io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 285:23]
-    io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 286:23]
-    io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 287:23]
-    lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 289:11]
-    lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 289:11]
-    io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 289:11]
-    io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 289:11]
-    io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 289:11]
-    io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 289:11]
-    io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 289:11]
-    io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 289:11]
-    io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 289:11]
-    io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 289:11]
-    lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 292:14]
-    lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 292:14]
-    lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 292:14]
-    lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 292:14]
-    lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 292:14]
-    io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 292:14]
-    io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 292:14]
-    io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 292:14]
-    lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 292:14]
-    lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 292:14]
-    lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 292:14]
-    lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 292:14]
-    io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 292:14]
-    io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 292:14]
-    io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 292:14]
-    io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 292:14]
-    io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 292:14]
-    lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 292:14]
-    io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 292:14]
-    io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 292:14]
-    lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 292:14]
-    ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 295:14]
-    ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 295:14]
-    ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 295:14]
-    ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 295:14]
-    ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 295:14]
-    io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 295:14]
-    io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 295:14]
-    io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 295:14]
-    ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 295:14]
-    ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 295:14]
-    ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 295:14]
-    ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 295:14]
-    io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 295:14]
-    io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 295:14]
-    io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 295:14]
-    io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 295:14]
-    io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 295:14]
-    ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 295:14]
-    io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 295:14]
-    io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 295:14]
-    ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 295:14]
-    io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 296:14]
-    io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 296:14]
-    io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 296:14]
-    io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 296:14]
-    io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 296:14]
-    io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 296:14]
-    io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 296:14]
-    io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 296:14]
-    io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 296:14]
-    io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 296:14]
-    dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 296:14]
-    io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 296:14]
-    when UInt<1>("h00") : @[quasar.scala 302:26]
-      inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 303:33]
+    node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 137:56]
+    node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 138:56]
+    node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 139:28]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 142:18]
+    dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 142:18]
+    ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 142:18]
+    ifu.reset <= io.core_rst_l @[quasar.scala 144:13]
+    ifu.io.scan_mode <= io.scan_mode @[quasar.scala 145:20]
+    ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 146:19]
+    ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 147:21]
+    ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 149:26]
+    ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 150:31]
+    ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 152:25]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 153:18]
+    ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 153:18]
+    io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 154:13]
+    io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 154:13]
+    io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 154:13]
+    io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 154:13]
+    io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 154:13]
+    io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 154:13]
+    ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 154:13]
+    ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 154:13]
+    ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 154:13]
+    ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 154:13]
+    ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 154:13]
+    ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 154:13]
+    ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 154:13]
+    io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 154:13]
+    io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 154:13]
+    io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 154:13]
+    io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 154:13]
+    io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 154:13]
+    io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 154:13]
+    io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 154:13]
+    io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 154:13]
+    ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 155:15]
+    ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 155:15]
+    io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 155:15]
+    io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 155:15]
+    io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 155:15]
+    io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 155:15]
+    io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 155:15]
+    io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 155:15]
+    io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 155:15]
+    ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 156:25]
+    ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 157:42]
+    ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 158:43]
+    ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 159:33]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 160:51]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 160:51]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 160:51]
+    ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 160:51]
+    dec.reset <= io.core_rst_l @[quasar.scala 163:13]
+    dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 164:19]
+    dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 165:21]
+    dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 166:32]
+    dec.io.rst_vec <= io.rst_vec @[quasar.scala 167:18]
+    dec.io.nmi_int <= io.nmi_int @[quasar.scala 168:18]
+    dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 169:18]
+    dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 170:25]
+    dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 171:24]
+    dec.io.core_id <= io.core_id @[quasar.scala 172:18]
+    dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 173:29]
+    dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 174:28]
+    dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 175:28]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 176:18]
+    dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 176:18]
+    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 176:18]
+    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 176:18]
+    lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 176:18]
+    dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 176:18]
+    dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 177:18]
+    dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 177:18]
+    dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 178:31]
+    dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 179:18]
+    dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 179:18]
+    dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 179:18]
+    dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 179:18]
+    dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 179:18]
+    dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 179:18]
+    dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 179:18]
+    dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 179:18]
+    dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 181:23]
+    dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 182:24]
+    dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 183:30]
+    dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 184:18]
+    dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 184:18]
+    dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 184:18]
+    dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 184:18]
+    dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 184:18]
+    dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 185:23]
+    dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 186:26]
+    dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 186:26]
+    dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 186:26]
+    dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 186:26]
+    dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 186:26]
+    dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 186:26]
+    dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 187:36]
+    dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 188:25]
+    dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 189:23]
+    dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 190:23]
+    dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 191:28]
+    dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 192:29]
+    dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 193:30]
+    dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 194:28]
+    dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 195:26]
+    dec.io.soft_int <= io.soft_int @[quasar.scala 197:19]
+    dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 198:23]
+    dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 199:25]
+    dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 200:26]
+    dec.io.timer_int <= io.timer_int @[quasar.scala 201:20]
+    dec.io.scan_mode <= io.scan_mode @[quasar.scala 202:20]
+    exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 205:18]
+    exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 205:18]
+    exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 205:18]
+    exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 205:18]
+    dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 205:18]
+    exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 205:18]
+    exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 205:18]
+    exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 205:18]
+    dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 205:18]
+    dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 205:18]
+    exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 205:18]
+    dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 205:18]
+    exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 205:18]
+    exu.reset <= io.core_rst_l @[quasar.scala 206:13]
+    exu.io.scan_mode <= io.scan_mode @[quasar.scala 207:20]
+    exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 208:25]
+    lsu.reset <= io.core_rst_l @[quasar.scala 211:13]
+    lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 212:23]
+    lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 213:32]
+    lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 214:35]
+    lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 215:29]
+    lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 216:35]
+    lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 217:18]
+    lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 217:18]
+    lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 218:27]
+    lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 219:16]
+    lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 219:16]
+    lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 219:16]
+    lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 220:30]
+    lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 221:26]
+    lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 222:26]
+    lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 222:26]
+    lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 224:25]
+    lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 225:18]
+    dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 225:18]
+    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 225:18]
+    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 225:18]
+    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 225:18]
+    dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 225:18]
+    lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 225:18]
+    lsu.io.scan_mode <= io.scan_mode @[quasar.scala 226:20]
+    lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 227:19]
+    dbg.reset <= io.core_rst_l @[quasar.scala 230:13]
+    node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 231:32]
+    dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 231:26]
+    node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 232:60]
+    dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 232:28]
+    node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 233:60]
+    dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 233:28]
+    dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 234:29]
+    dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 235:29]
+    dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 236:34]
+    dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 237:29]
+    dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 238:21]
+    dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 239:23]
+    dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 240:24]
+    dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 241:24]
+    dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 242:17]
+    dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 242:17]
+    dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 242:17]
+    dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 242:17]
+    dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 242:17]
+    io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 242:17]
+    io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 242:17]
+    io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 242:17]
+    dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 242:17]
+    dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 242:17]
+    dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 242:17]
+    dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 242:17]
+    io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 242:17]
+    io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 242:17]
+    io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 242:17]
+    io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 242:17]
+    io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 242:17]
+    dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 242:17]
+    io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 242:17]
+    io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 242:17]
+    dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 242:17]
+    dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 243:25]
+    node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 244:42]
+    dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 244:20]
+    dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 245:23]
+    dbg.io.scan_mode <= io.scan_mode @[quasar.scala 246:20]
+    dma_ctrl.reset <= io.core_rst_l @[quasar.scala 250:18]
+    dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 251:24]
+    dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 252:30]
+    dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 253:28]
+    dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 254:25]
+    dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 255:23]
+    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 255:23]
+    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 255:23]
+    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 255:23]
+    dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 255:23]
+    dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 256:26]
+    dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 256:26]
+    dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 257:28]
+    dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 258:31]
+    dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 259:29]
+    dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 260:30]
+    dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 261:26]
+    dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 262:34]
+    pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 265:30]
+    pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 266:23]
+    pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 267:29]
+    pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 268:31]
+    pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 269:33]
+    pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 270:34]
+    lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 271:28]
+    pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 271:28]
+    dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 272:28]
+    pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 272:28]
+    pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 272:28]
+    dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 272:28]
+    dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 272:28]
+    dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 272:28]
+    io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 274:19]
+    io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 274:19]
+    io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 277:24]
+    io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 278:23]
+    io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 279:31]
+    io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 280:21]
+    io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 281:24]
+    io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 282:20]
+    io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 283:26]
+    io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 284:25]
+    io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 285:24]
+    io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 286:25]
+    io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 287:23]
+    io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 288:23]
+    io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 289:23]
+    io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 290:23]
+    lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 292:11]
+    lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 292:11]
+    io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 292:11]
+    io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 292:11]
+    io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 292:11]
+    io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 292:11]
+    io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 292:11]
+    io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 292:11]
+    io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 292:11]
+    io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 292:11]
+    lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 295:14]
+    lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 295:14]
+    lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 295:14]
+    lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 295:14]
+    lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 295:14]
+    io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 295:14]
+    io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 295:14]
+    io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 295:14]
+    lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 295:14]
+    lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 295:14]
+    lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 295:14]
+    lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 295:14]
+    io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 295:14]
+    io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 295:14]
+    io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 295:14]
+    io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 295:14]
+    io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 295:14]
+    lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 295:14]
+    io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 295:14]
+    io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 295:14]
+    lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 295:14]
+    ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 298:14]
+    ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 298:14]
+    ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 298:14]
+    ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 298:14]
+    ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 298:14]
+    io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 298:14]
+    io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 298:14]
+    io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 298:14]
+    ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 298:14]
+    ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 298:14]
+    ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 298:14]
+    ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 298:14]
+    io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 298:14]
+    io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 298:14]
+    io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 298:14]
+    io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 298:14]
+    io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 298:14]
+    ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 298:14]
+    io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 298:14]
+    io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 298:14]
+    ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 298:14]
+    io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 299:14]
+    io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 299:14]
+    io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 299:14]
+    io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 299:14]
+    io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 299:14]
+    io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 299:14]
+    io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 299:14]
+    io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 299:14]
+    io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 299:14]
+    io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 299:14]
+    dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 299:14]
+    io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 299:14]
+    when UInt<1>("h00") : @[quasar.scala 305:26]
+      inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 306:33]
       axi4_to_ahb.clock <= clock
       axi4_to_ahb.reset <= reset
-      axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 304:36]
-      axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 305:34]
-      axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 306:35]
-      axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 307:37]
-      axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 308:33]
-      axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 309:35]
-      axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 310:35]
-      axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 311:35]
-      axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 313:35]
-      axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 314:34]
-      axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 315:34]
-      axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 316:34]
-      axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 317:35]
-      axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 319:36]
-      axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 320:33]
-      axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 321:35]
-      axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 322:35]
-      axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 323:35]
-      axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 325:35]
-      inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 330:33]
+      axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 307:36]
+      axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 308:34]
+      axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 309:35]
+      axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 310:37]
+      axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 311:33]
+      axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 312:35]
+      axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 313:35]
+      axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 314:35]
+      axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 316:35]
+      axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 317:34]
+      axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 318:34]
+      axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 319:34]
+      axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 320:35]
+      axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 322:36]
+      axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 323:33]
+      axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 324:35]
+      axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 325:35]
+      axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 326:35]
+      axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 328:35]
+      inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 333:33]
       axi4_to_ahb_1.clock <= clock
       axi4_to_ahb_1.reset <= reset
-      axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 331:36]
-      axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 332:34]
-      axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 333:35]
-      axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 334:37]
-      axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 335:33]
-      axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 336:35]
-      axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 337:35]
-      axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 338:35]
-      axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 340:35]
-      axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 341:34]
-      axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 342:34]
-      axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 343:34]
-      axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 344:35]
-      axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 346:36]
-      axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 347:33]
-      axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 348:35]
-      axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 349:35]
-      axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 350:35]
-      axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 352:35]
-      inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 358:32]
+      axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 334:36]
+      axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 335:34]
+      axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 336:35]
+      axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 337:37]
+      axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 338:33]
+      axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 339:35]
+      axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 340:35]
+      axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 341:35]
+      axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 343:35]
+      axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 344:34]
+      axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 345:34]
+      axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 346:34]
+      axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 347:35]
+      axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 349:36]
+      axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 350:33]
+      axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 351:35]
+      axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 352:35]
+      axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 353:35]
+      axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 355:35]
+      inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 361:32]
       axi4_to_ahb_2.clock <= clock
       axi4_to_ahb_2.reset <= reset
-      axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 359:35]
-      axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 360:33]
-      axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 361:34]
-      axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 362:36]
-      axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 363:32]
-      axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 364:34]
-      axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 365:34]
-      axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 366:34]
-      axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 368:34]
-      axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 369:33]
-      axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 370:33]
-      axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 371:33]
-      axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 372:34]
-      axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 374:35]
-      axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 375:32]
-      axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 376:34]
-      axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 377:34]
-      axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 378:34]
-      axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 380:34]
-      inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 385:33]
+      axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 362:35]
+      axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 363:33]
+      axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 364:34]
+      axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 365:36]
+      axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 366:32]
+      axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 367:34]
+      axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 368:34]
+      axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 369:34]
+      axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 371:34]
+      axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 372:33]
+      axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 373:33]
+      axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 374:33]
+      axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 375:34]
+      axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 377:35]
+      axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 378:32]
+      axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 379:34]
+      axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 380:34]
+      axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 381:34]
+      axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 383:34]
+      inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 388:33]
       ahb_to_axi4.clock <= clock
       ahb_to_axi4.reset <= reset
-      ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 386:34]
-      ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 387:35]
-      ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 388:37]
-      ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 389:36]
-      ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 390:35]
-      ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 391:35]
-      ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 392:34]
-      ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 393:32]
-      ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 396:36]
-      ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 397:35]
-      ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 398:32]
-      ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 399:34]
-      ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 400:34]
-      ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 411:33]
-      ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 412:37]
-      node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 413:31]
-      lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 413:25]
-      node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 414:30]
-      lsu.io.axi.w.ready <= _T_13 @[quasar.scala 414:24]
-      node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 415:30]
-      lsu.io.axi.b.valid <= _T_14 @[quasar.scala 415:24]
-      node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 416:34]
-      lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 416:28]
-      node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 417:32]
-      lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 417:26]
-      node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 418:31]
-      lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 418:25]
-      node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 419:30]
-      lsu.io.axi.r.valid <= _T_18 @[quasar.scala 419:24]
-      node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 420:32]
-      lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 420:26]
-      node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 421:34]
-      lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 421:28]
-      node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 422:34]
-      lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 422:28]
-      node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 423:34]
-      lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 423:28]
-      node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 425:31]
-      ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 425:25]
-      node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 426:30]
-      ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 426:24]
-      node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 427:31]
-      ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 427:25]
-      node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 428:30]
-      ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 428:24]
-      node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 429:32]
-      ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 429:26]
-      node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 430:34]
-      ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 430:28]
-      node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 431:34]
-      ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 431:28]
-      node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 432:34]
-      ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 432:28]
-      node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 434:34]
-      dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 434:28]
-      node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 435:33]
-      dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 435:27]
-      node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 436:33]
-      dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 436:27]
-      node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 437:37]
-      dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 437:31]
-      node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 438:34]
-      dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 438:28]
-      node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 439:33]
-      dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 439:27]
-      node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 440:35]
-      dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 440:29]
-      node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 441:37]
-      dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 441:31]
-      node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 442:37]
-      dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 442:31]
-      node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 444:40]
-      dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 444:34]
-      node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 445:42]
-      dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 445:36]
-      node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 446:44]
-      dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 446:38]
-      node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 447:44]
-      dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 447:38]
-      node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 448:39]
-      dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 448:33]
-      node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 449:43]
-      dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 449:37]
-      node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 450:43]
-      dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 450:37]
-      node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 451:39]
-      dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 451:33]
-      node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 452:40]
-      dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 452:34]
-      node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 453:42]
-      dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 453:36]
-      node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 454:44]
-      dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 454:38]
-      node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 455:44]
-      dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 455:38]
-      node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 456:39]
-      dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 456:33]
-      io.ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 458:12]
-      io.ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 458:12]
-      io.ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 458:12]
-      io.ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 458:12]
-      io.ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 458:12]
-      io.ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 458:12]
-      io.ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 458:12]
-      io.ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 458:12]
-      axi4_to_ahb_1.io.ahb.in.hresp <= io.ahb.in.hresp @[quasar.scala 458:12]
-      axi4_to_ahb_1.io.ahb.in.hready <= io.ahb.in.hready @[quasar.scala 458:12]
-      axi4_to_ahb_1.io.ahb.in.hrdata <= io.ahb.in.hrdata @[quasar.scala 458:12]
-      io.lsu_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 467:16]
-      io.lsu_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 467:16]
-      io.lsu_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 467:16]
-      io.lsu_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 467:16]
-      io.lsu_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 467:16]
-      io.lsu_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 467:16]
-      io.lsu_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 467:16]
-      io.lsu_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 467:16]
-      axi4_to_ahb.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 467:16]
-      axi4_to_ahb.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 467:16]
-      axi4_to_ahb.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 467:16]
-      io.sb_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 477:15]
-      io.sb_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 477:15]
-      io.sb_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 477:15]
-      io.sb_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 477:15]
-      io.sb_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 477:15]
-      io.sb_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 477:15]
-      io.sb_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 477:15]
-      io.sb_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 477:15]
-      axi4_to_ahb_2.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 477:15]
-      axi4_to_ahb_2.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 477:15]
-      axi4_to_ahb_2.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 477:15]
-      ahb_to_axi4.io.ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar.scala 487:16]
-      ahb_to_axi4.io.ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar.scala 487:16]
-      io.dma_ahb.in.hresp <= ahb_to_axi4.io.ahb.in.hresp @[quasar.scala 487:16]
-      io.dma_ahb.in.hready <= ahb_to_axi4.io.ahb.in.hready @[quasar.scala 487:16]
-      io.dma_ahb.in.hrdata <= ahb_to_axi4.io.ahb.in.hrdata @[quasar.scala 487:16]
-      skip @[quasar.scala 302:26]
-    else : @[quasar.scala 494:15]
-      wire _T_53 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 496:33]
-      _T_53.hwdata <= UInt<64>("h00") @[quasar.scala 496:33]
-      _T_53.hwrite <= UInt<1>("h00") @[quasar.scala 496:33]
-      _T_53.htrans <= UInt<2>("h00") @[quasar.scala 496:33]
-      _T_53.hsize <= UInt<3>("h00") @[quasar.scala 496:33]
-      _T_53.hprot <= UInt<4>("h00") @[quasar.scala 496:33]
-      _T_53.hmastlock <= UInt<1>("h00") @[quasar.scala 496:33]
-      _T_53.hburst <= UInt<3>("h00") @[quasar.scala 496:33]
-      _T_53.haddr <= UInt<32>("h00") @[quasar.scala 496:33]
-      io.ahb.out.hwdata <= _T_53.hwdata @[quasar.scala 496:18]
-      io.ahb.out.hwrite <= _T_53.hwrite @[quasar.scala 496:18]
-      io.ahb.out.htrans <= _T_53.htrans @[quasar.scala 496:18]
-      io.ahb.out.hsize <= _T_53.hsize @[quasar.scala 496:18]
-      io.ahb.out.hprot <= _T_53.hprot @[quasar.scala 496:18]
-      io.ahb.out.hmastlock <= _T_53.hmastlock @[quasar.scala 496:18]
-      io.ahb.out.hburst <= _T_53.hburst @[quasar.scala 496:18]
-      io.ahb.out.haddr <= _T_53.haddr @[quasar.scala 496:18]
-      wire _T_54 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 505:37]
-      _T_54.hwdata <= UInt<64>("h00") @[quasar.scala 505:37]
-      _T_54.hwrite <= UInt<1>("h00") @[quasar.scala 505:37]
-      _T_54.htrans <= UInt<2>("h00") @[quasar.scala 505:37]
-      _T_54.hsize <= UInt<3>("h00") @[quasar.scala 505:37]
-      _T_54.hprot <= UInt<4>("h00") @[quasar.scala 505:37]
-      _T_54.hmastlock <= UInt<1>("h00") @[quasar.scala 505:37]
-      _T_54.hburst <= UInt<3>("h00") @[quasar.scala 505:37]
-      _T_54.haddr <= UInt<32>("h00") @[quasar.scala 505:37]
-      io.lsu_ahb.out.hwdata <= _T_54.hwdata @[quasar.scala 505:22]
-      io.lsu_ahb.out.hwrite <= _T_54.hwrite @[quasar.scala 505:22]
-      io.lsu_ahb.out.htrans <= _T_54.htrans @[quasar.scala 505:22]
-      io.lsu_ahb.out.hsize <= _T_54.hsize @[quasar.scala 505:22]
-      io.lsu_ahb.out.hprot <= _T_54.hprot @[quasar.scala 505:22]
-      io.lsu_ahb.out.hmastlock <= _T_54.hmastlock @[quasar.scala 505:22]
-      io.lsu_ahb.out.hburst <= _T_54.hburst @[quasar.scala 505:22]
-      io.lsu_ahb.out.haddr <= _T_54.haddr @[quasar.scala 505:22]
-      wire _T_55 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 515:36]
-      _T_55.hwdata <= UInt<64>("h00") @[quasar.scala 515:36]
-      _T_55.hwrite <= UInt<1>("h00") @[quasar.scala 515:36]
-      _T_55.htrans <= UInt<2>("h00") @[quasar.scala 515:36]
-      _T_55.hsize <= UInt<3>("h00") @[quasar.scala 515:36]
-      _T_55.hprot <= UInt<4>("h00") @[quasar.scala 515:36]
-      _T_55.hmastlock <= UInt<1>("h00") @[quasar.scala 515:36]
-      _T_55.hburst <= UInt<3>("h00") @[quasar.scala 515:36]
-      _T_55.haddr <= UInt<32>("h00") @[quasar.scala 515:36]
-      io.sb_ahb.out.hwdata <= _T_55.hwdata @[quasar.scala 515:21]
-      io.sb_ahb.out.hwrite <= _T_55.hwrite @[quasar.scala 515:21]
-      io.sb_ahb.out.htrans <= _T_55.htrans @[quasar.scala 515:21]
-      io.sb_ahb.out.hsize <= _T_55.hsize @[quasar.scala 515:21]
-      io.sb_ahb.out.hprot <= _T_55.hprot @[quasar.scala 515:21]
-      io.sb_ahb.out.hmastlock <= _T_55.hmastlock @[quasar.scala 515:21]
-      io.sb_ahb.out.hburst <= _T_55.hburst @[quasar.scala 515:21]
-      io.sb_ahb.out.haddr <= _T_55.haddr @[quasar.scala 515:21]
-      wire _T_56 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar.scala 525:36]
-      _T_56.hresp <= UInt<1>("h00") @[quasar.scala 525:36]
-      _T_56.hready <= UInt<1>("h00") @[quasar.scala 525:36]
-      _T_56.hrdata <= UInt<64>("h00") @[quasar.scala 525:36]
-      io.dma_ahb.in.hresp <= _T_56.hresp @[quasar.scala 525:21]
-      io.dma_ahb.in.hready <= _T_56.hready @[quasar.scala 525:21]
-      io.dma_ahb.in.hrdata <= _T_56.hrdata @[quasar.scala 525:21]
-      skip @[quasar.scala 494:15]
-    io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 530:20]
+      ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 389:34]
+      ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 390:35]
+      ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 391:37]
+      ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 392:36]
+      ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 393:35]
+      ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 394:35]
+      ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 395:34]
+      ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 396:32]
+      ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 399:36]
+      ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 400:35]
+      ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 401:32]
+      ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 402:34]
+      ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 403:34]
+      ahb_to_axi4.io.ahb.hsel <= io.dma.hsel @[quasar.scala 414:33]
+      ahb_to_axi4.io.ahb.hreadyin <= io.dma.hreadyin @[quasar.scala 415:37]
+      node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 416:31]
+      lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 416:25]
+      node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 417:30]
+      lsu.io.axi.w.ready <= _T_13 @[quasar.scala 417:24]
+      node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 418:30]
+      lsu.io.axi.b.valid <= _T_14 @[quasar.scala 418:24]
+      node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 419:34]
+      lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 419:28]
+      node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 420:32]
+      lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 420:26]
+      node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 421:31]
+      lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 421:25]
+      node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 422:30]
+      lsu.io.axi.r.valid <= _T_18 @[quasar.scala 422:24]
+      node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 423:32]
+      lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 423:26]
+      node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 424:34]
+      lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 424:28]
+      node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 425:34]
+      lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 425:28]
+      node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 426:34]
+      lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 426:28]
+      node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 428:31]
+      ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 428:25]
+      node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 429:30]
+      ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 429:24]
+      node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 430:31]
+      ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 430:25]
+      node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 431:30]
+      ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 431:24]
+      node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 432:32]
+      ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 432:26]
+      node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 433:34]
+      ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 433:28]
+      node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 434:34]
+      ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 434:28]
+      node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 435:34]
+      ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 435:28]
+      node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 437:34]
+      dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 437:28]
+      node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 438:33]
+      dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 438:27]
+      node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 439:33]
+      dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 439:27]
+      node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 440:37]
+      dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 440:31]
+      node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 441:34]
+      dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 441:28]
+      node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 442:33]
+      dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 442:27]
+      node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 443:35]
+      dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 443:29]
+      node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 444:37]
+      dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 444:31]
+      node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 445:37]
+      dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 445:31]
+      node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 447:40]
+      dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 447:34]
+      node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 448:42]
+      dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 448:36]
+      node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 449:44]
+      dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 449:38]
+      node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 450:44]
+      dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 450:38]
+      node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 451:39]
+      dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 451:33]
+      node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 452:43]
+      dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 452:37]
+      node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 453:43]
+      dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 453:37]
+      node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 454:39]
+      dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 454:33]
+      node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 455:40]
+      dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 455:34]
+      node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 456:42]
+      dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 456:36]
+      node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 457:44]
+      dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 457:38]
+      node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 458:44]
+      dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 458:38]
+      node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 459:39]
+      dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 459:33]
+      io.ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 461:12]
+      io.ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 461:12]
+      io.ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 461:12]
+      io.ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 461:12]
+      io.ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 461:12]
+      io.ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 461:12]
+      io.ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 461:12]
+      io.ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 461:12]
+      axi4_to_ahb_1.io.ahb.in.hresp <= io.ahb.in.hresp @[quasar.scala 461:12]
+      axi4_to_ahb_1.io.ahb.in.hready <= io.ahb.in.hready @[quasar.scala 461:12]
+      axi4_to_ahb_1.io.ahb.in.hrdata <= io.ahb.in.hrdata @[quasar.scala 461:12]
+      io.lsu_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 470:16]
+      io.lsu_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 470:16]
+      io.lsu_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 470:16]
+      io.lsu_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 470:16]
+      io.lsu_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 470:16]
+      io.lsu_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 470:16]
+      io.lsu_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 470:16]
+      io.lsu_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 470:16]
+      axi4_to_ahb.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 470:16]
+      axi4_to_ahb.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 470:16]
+      axi4_to_ahb.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 470:16]
+      io.sb_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 480:15]
+      io.sb_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 480:15]
+      io.sb_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 480:15]
+      io.sb_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 480:15]
+      io.sb_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 480:15]
+      io.sb_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 480:15]
+      io.sb_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 480:15]
+      io.sb_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 480:15]
+      axi4_to_ahb_2.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 480:15]
+      axi4_to_ahb_2.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 480:15]
+      axi4_to_ahb_2.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 480:15]
+      ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma.ahb.out.hwdata @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma.ahb.out.hwrite @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma.ahb.out.htrans @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma.ahb.out.hsize @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma.ahb.out.hprot @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma.ahb.out.hmastlock @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma.ahb.out.hburst @[quasar.scala 490:16]
+      ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma.ahb.out.haddr @[quasar.scala 490:16]
+      io.dma.ahb.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 490:16]
+      io.dma.ahb.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 490:16]
+      io.dma.ahb.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 490:16]
+      skip @[quasar.scala 305:26]
+    else : @[quasar.scala 497:15]
+      wire _T_53 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 499:33]
+      _T_53.hwdata <= UInt<64>("h00") @[quasar.scala 499:33]
+      _T_53.hwrite <= UInt<1>("h00") @[quasar.scala 499:33]
+      _T_53.htrans <= UInt<2>("h00") @[quasar.scala 499:33]
+      _T_53.hsize <= UInt<3>("h00") @[quasar.scala 499:33]
+      _T_53.hprot <= UInt<4>("h00") @[quasar.scala 499:33]
+      _T_53.hmastlock <= UInt<1>("h00") @[quasar.scala 499:33]
+      _T_53.hburst <= UInt<3>("h00") @[quasar.scala 499:33]
+      _T_53.haddr <= UInt<32>("h00") @[quasar.scala 499:33]
+      io.ahb.out.hwdata <= _T_53.hwdata @[quasar.scala 499:18]
+      io.ahb.out.hwrite <= _T_53.hwrite @[quasar.scala 499:18]
+      io.ahb.out.htrans <= _T_53.htrans @[quasar.scala 499:18]
+      io.ahb.out.hsize <= _T_53.hsize @[quasar.scala 499:18]
+      io.ahb.out.hprot <= _T_53.hprot @[quasar.scala 499:18]
+      io.ahb.out.hmastlock <= _T_53.hmastlock @[quasar.scala 499:18]
+      io.ahb.out.hburst <= _T_53.hburst @[quasar.scala 499:18]
+      io.ahb.out.haddr <= _T_53.haddr @[quasar.scala 499:18]
+      wire _T_54 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 508:37]
+      _T_54.hwdata <= UInt<64>("h00") @[quasar.scala 508:37]
+      _T_54.hwrite <= UInt<1>("h00") @[quasar.scala 508:37]
+      _T_54.htrans <= UInt<2>("h00") @[quasar.scala 508:37]
+      _T_54.hsize <= UInt<3>("h00") @[quasar.scala 508:37]
+      _T_54.hprot <= UInt<4>("h00") @[quasar.scala 508:37]
+      _T_54.hmastlock <= UInt<1>("h00") @[quasar.scala 508:37]
+      _T_54.hburst <= UInt<3>("h00") @[quasar.scala 508:37]
+      _T_54.haddr <= UInt<32>("h00") @[quasar.scala 508:37]
+      io.lsu_ahb.out.hwdata <= _T_54.hwdata @[quasar.scala 508:22]
+      io.lsu_ahb.out.hwrite <= _T_54.hwrite @[quasar.scala 508:22]
+      io.lsu_ahb.out.htrans <= _T_54.htrans @[quasar.scala 508:22]
+      io.lsu_ahb.out.hsize <= _T_54.hsize @[quasar.scala 508:22]
+      io.lsu_ahb.out.hprot <= _T_54.hprot @[quasar.scala 508:22]
+      io.lsu_ahb.out.hmastlock <= _T_54.hmastlock @[quasar.scala 508:22]
+      io.lsu_ahb.out.hburst <= _T_54.hburst @[quasar.scala 508:22]
+      io.lsu_ahb.out.haddr <= _T_54.haddr @[quasar.scala 508:22]
+      wire _T_55 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 518:36]
+      _T_55.hwdata <= UInt<64>("h00") @[quasar.scala 518:36]
+      _T_55.hwrite <= UInt<1>("h00") @[quasar.scala 518:36]
+      _T_55.htrans <= UInt<2>("h00") @[quasar.scala 518:36]
+      _T_55.hsize <= UInt<3>("h00") @[quasar.scala 518:36]
+      _T_55.hprot <= UInt<4>("h00") @[quasar.scala 518:36]
+      _T_55.hmastlock <= UInt<1>("h00") @[quasar.scala 518:36]
+      _T_55.hburst <= UInt<3>("h00") @[quasar.scala 518:36]
+      _T_55.haddr <= UInt<32>("h00") @[quasar.scala 518:36]
+      io.sb_ahb.out.hwdata <= _T_55.hwdata @[quasar.scala 518:21]
+      io.sb_ahb.out.hwrite <= _T_55.hwrite @[quasar.scala 518:21]
+      io.sb_ahb.out.htrans <= _T_55.htrans @[quasar.scala 518:21]
+      io.sb_ahb.out.hsize <= _T_55.hsize @[quasar.scala 518:21]
+      io.sb_ahb.out.hprot <= _T_55.hprot @[quasar.scala 518:21]
+      io.sb_ahb.out.hmastlock <= _T_55.hmastlock @[quasar.scala 518:21]
+      io.sb_ahb.out.hburst <= _T_55.hburst @[quasar.scala 518:21]
+      io.sb_ahb.out.haddr <= _T_55.haddr @[quasar.scala 518:21]
+      wire _T_56 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar.scala 528:36]
+      _T_56.hresp <= UInt<1>("h00") @[quasar.scala 528:36]
+      _T_56.hready <= UInt<1>("h00") @[quasar.scala 528:36]
+      _T_56.hrdata <= UInt<64>("h00") @[quasar.scala 528:36]
+      io.dma.ahb.in.hresp <= _T_56.hresp @[quasar.scala 528:21]
+      io.dma.ahb.in.hready <= _T_56.hready @[quasar.scala 528:21]
+      io.dma.ahb.in.hrdata <= _T_56.hrdata @[quasar.scala 528:21]
+      skip @[quasar.scala 497:15]
+    io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 533:20]
     
   module quasar_wrapper : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_ahb : {flip in : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip dma_hreadyin : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>}
+    output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, dma : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>}
     
-    inst mem of mem @[quasar_wrapper.scala 79:19]
+    inst mem of mem @[quasar_wrapper.scala 82:19]
     mem.scan_mode is invalid
     mem.ic is invalid
     mem.iccm is invalid
@@ -114755,7 +114831,7 @@ circuit quasar_wrapper :
     mem.dccm_clk_override is invalid
     mem.rst_l is invalid
     mem.clk is invalid
-    inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 80:27]
+    inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 83:27]
     dmi_wrapper.dmi_hard_reset is invalid
     dmi_wrapper.reg_wr_en is invalid
     dmi_wrapper.reg_en is invalid
@@ -114771,298 +114847,298 @@ circuit quasar_wrapper :
     dmi_wrapper.tms is invalid
     dmi_wrapper.tck is invalid
     dmi_wrapper.trst_n is invalid
-    inst swerv of quasar @[quasar_wrapper.scala 81:21]
+    inst swerv of quasar @[quasar_wrapper.scala 84:21]
     swerv.clock <= clock
     swerv.reset <= reset
-    dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 82:25]
-    dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 83:22]
-    dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 84:22]
-    dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 85:22]
-    dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 86:27]
-    dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 87:26]
-    dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 88:26]
-    dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 91:29]
-    swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 92:26]
-    swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 93:25]
-    swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 94:23]
-    swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 95:26]
-    swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 96:27]
-    io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 97:15]
-    mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 100:28]
-    mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 101:27]
-    mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 102:35]
-    swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 103:15]
-    swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 103:15]
-    mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 103:15]
-    mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 103:15]
-    mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 103:15]
-    mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 103:15]
-    mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 103:15]
-    mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 103:15]
-    mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 103:15]
-    mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 103:15]
-    mem.rst_l <= reset @[quasar_wrapper.scala 104:16]
-    mem.clk <= clock @[quasar_wrapper.scala 105:14]
-    mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 106:20]
-    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 108:22]
-    mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 109:15]
-    mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 109:15]
-    swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 109:15]
-    mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 109:15]
-    mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 109:15]
-    mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 109:15]
-    mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 109:15]
-    mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 109:15]
-    mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 109:15]
-    mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 109:15]
-    swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 110:17]
-    swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 110:17]
-    mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 110:17]
-    mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 110:17]
-    mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 110:17]
-    mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 110:17]
-    mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 110:17]
-    mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 110:17]
-    mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 110:17]
-    wire _T : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 112:39]
-    _T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:39]
-    _T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 112:39]
-    _T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 112:39]
-    swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 112:24]
-    swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 112:24]
-    swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 112:24]
-    wire _T_1 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 113:39]
-    _T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 113:39]
-    _T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 113:39]
-    _T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 113:39]
-    swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 113:24]
-    swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 113:24]
-    swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 113:24]
-    wire _T_2 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 114:39]
-    _T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:39]
-    _T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 114:39]
-    _T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 114:39]
-    swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 114:24]
-    swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 114:24]
-    swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 114:24]
-    wire _T_3 : {hrdata : UInt<64>, hready : UInt<1>, hresp : UInt<1>} @[quasar_wrapper.scala 115:34]
-    _T_3.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 115:34]
-    _T_3.hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:34]
-    _T_3.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 115:34]
-    io.dma_ahb.in.hresp <= _T_3.hresp @[quasar_wrapper.scala 115:19]
-    io.dma_ahb.in.hready <= _T_3.hready @[quasar_wrapper.scala 115:19]
-    io.dma_ahb.in.hrdata <= _T_3.hrdata @[quasar_wrapper.scala 115:19]
-    swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 125:22]
-    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 127:22]
-    swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 128:20]
-    swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 129:20]
-    swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 130:20]
-    swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 133:27]
-    swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 134:26]
-    swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 135:20]
-    swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 138:31]
-    swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 139:30]
-    swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 140:30]
-    swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 144:20]
-    io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 144:20]
-    swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 144:20]
-    swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 147:20]
-    io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 147:20]
-    swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 147:20]
-    swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 150:19]
-    io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 150:19]
-    io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 150:19]
-    io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 150:19]
-    io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 150:19]
-    io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 150:19]
-    io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 150:19]
-    io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 150:19]
-    io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 150:19]
-    swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 150:19]
-    io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 154:20]
-    io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 154:20]
-    io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 154:20]
-    io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 154:20]
-    io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 154:20]
-    io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 154:20]
-    io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 154:20]
-    io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 154:20]
-    io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 154:20]
-    io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 154:20]
-    io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 154:20]
-    swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 157:21]
-    swerv.io.dma_ahb.out.hwdata <= io.dma_ahb.out.hwdata @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.hwrite <= io.dma_ahb.out.hwrite @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.htrans <= io.dma_ahb.out.htrans @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.hsize <= io.dma_ahb.out.hsize @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.hprot <= io.dma_ahb.out.hprot @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.hmastlock <= io.dma_ahb.out.hmastlock @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.hburst <= io.dma_ahb.out.hburst @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_ahb.out.haddr <= io.dma_ahb.out.haddr @[quasar_wrapper.scala 158:24]
-    swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 167:25]
-    swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 185:27]
-    swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 186:27]
-    swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 187:27]
-    swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 188:27]
-    swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 190:22]
-    swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 191:21]
-    swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 192:26]
-    io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 196:19]
-    io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 196:19]
-    io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 199:21]
-    io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 200:24]
-    io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 201:20]
-    io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 202:26]
-    io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 204:25]
-    io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 205:24]
-    io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 206:25]
-    io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 208:23]
-    io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 209:23]
-    io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 210:23]
-    io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 211:23]
+    dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 85:25]
+    dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 86:22]
+    dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 87:22]
+    dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 88:22]
+    dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 89:27]
+    dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 90:26]
+    dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 91:26]
+    dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 94:29]
+    swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 95:26]
+    swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 96:25]
+    swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 97:23]
+    swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 98:26]
+    swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 99:27]
+    io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 100:15]
+    mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 103:28]
+    mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 104:27]
+    mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 105:35]
+    swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 106:15]
+    swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 106:15]
+    mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 106:15]
+    mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 106:15]
+    mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 106:15]
+    mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 106:15]
+    mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 106:15]
+    mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 106:15]
+    mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 106:15]
+    mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 106:15]
+    mem.rst_l <= reset @[quasar_wrapper.scala 107:16]
+    mem.clk <= clock @[quasar_wrapper.scala 108:14]
+    mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 109:20]
+    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 111:22]
+    mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 112:15]
+    mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 112:15]
+    swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 112:15]
+    mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 112:15]
+    mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 112:15]
+    mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 112:15]
+    mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 112:15]
+    mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 112:15]
+    mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 112:15]
+    mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 112:15]
+    swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 113:17]
+    swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 113:17]
+    mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 113:17]
+    mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 113:17]
+    mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 113:17]
+    mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 113:17]
+    mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 113:17]
+    mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 113:17]
+    mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 113:17]
+    wire _T : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 115:39]
+    _T.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 115:39]
+    _T.hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:39]
+    _T.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 115:39]
+    swerv.io.ahb.in.hresp <= _T.hresp @[quasar_wrapper.scala 115:24]
+    swerv.io.ahb.in.hready <= _T.hready @[quasar_wrapper.scala 115:24]
+    swerv.io.ahb.in.hrdata <= _T.hrdata @[quasar_wrapper.scala 115:24]
+    wire _T_1 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 116:39]
+    _T_1.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 116:39]
+    _T_1.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:39]
+    _T_1.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 116:39]
+    swerv.io.lsu_ahb.in.hresp <= _T_1.hresp @[quasar_wrapper.scala 116:24]
+    swerv.io.lsu_ahb.in.hready <= _T_1.hready @[quasar_wrapper.scala 116:24]
+    swerv.io.lsu_ahb.in.hrdata <= _T_1.hrdata @[quasar_wrapper.scala 116:24]
+    wire _T_2 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 117:39]
+    _T_2.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:39]
+    _T_2.hready <= UInt<1>("h00") @[quasar_wrapper.scala 117:39]
+    _T_2.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 117:39]
+    swerv.io.sb_ahb.in.hresp <= _T_2.hresp @[quasar_wrapper.scala 117:24]
+    swerv.io.sb_ahb.in.hready <= _T_2.hready @[quasar_wrapper.scala 117:24]
+    swerv.io.sb_ahb.in.hrdata <= _T_2.hrdata @[quasar_wrapper.scala 117:24]
+    wire _T_3 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar_wrapper.scala 118:34]
+    _T_3.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 118:34]
+    _T_3.hready <= UInt<1>("h00") @[quasar_wrapper.scala 118:34]
+    _T_3.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 118:34]
+    io.dma.ahb.in.hresp <= _T_3.hresp @[quasar_wrapper.scala 118:19]
+    io.dma.ahb.in.hready <= _T_3.hready @[quasar_wrapper.scala 118:19]
+    io.dma.ahb.in.hrdata <= _T_3.hrdata @[quasar_wrapper.scala 118:19]
+    swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 128:22]
+    swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 130:22]
+    swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 131:20]
+    swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 132:20]
+    swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 133:20]
+    swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 136:27]
+    swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 137:26]
+    swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 138:20]
+    swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 141:31]
+    swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 142:30]
+    swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 143:30]
+    swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 147:20]
+    io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 147:20]
+    swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 147:20]
+    swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 150:20]
+    io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 150:20]
+    swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 150:20]
+    swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 153:19]
+    io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 153:19]
+    io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 153:19]
+    io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 153:19]
+    io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 153:19]
+    io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 153:19]
+    io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 153:19]
+    io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 153:19]
+    io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 153:19]
+    swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 153:19]
+    io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 157:20]
+    io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 157:20]
+    io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 157:20]
+    io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 157:20]
+    io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 157:20]
+    io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 157:20]
+    io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 157:20]
+    io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 157:20]
+    io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 157:20]
+    io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 157:20]
+    swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 157:20]
+    io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 157:20]
+    swerv.io.dma.hsel <= io.dma.hsel @[quasar_wrapper.scala 160:21]
+    swerv.io.dma.ahb.out.hwdata <= io.dma.ahb.out.hwdata @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.hwrite <= io.dma.ahb.out.hwrite @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.htrans <= io.dma.ahb.out.htrans @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.hsize <= io.dma.ahb.out.hsize @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.hprot <= io.dma.ahb.out.hprot @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.hmastlock <= io.dma.ahb.out.hmastlock @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.hburst <= io.dma.ahb.out.hburst @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.ahb.out.haddr <= io.dma.ahb.out.haddr @[quasar_wrapper.scala 161:24]
+    swerv.io.dma.hreadyin <= io.dma.hreadyin @[quasar_wrapper.scala 170:25]
+    swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 188:27]
+    swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 189:27]
+    swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 190:27]
+    swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 191:27]
+    swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 193:22]
+    swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 194:21]
+    swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 195:26]
+    io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 199:19]
+    io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 199:19]
+    io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 202:21]
+    io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 203:24]
+    io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 204:20]
+    io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 205:26]
+    io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 207:25]
+    io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 208:24]
+    io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 209:25]
+    io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 211:23]
+    io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 212:23]
+    io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 213:23]
+    io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 214:23]
     
diff --git a/quasar_wrapper.v b/quasar_wrapper.v
index 84067792..64773469 100644
--- a/quasar_wrapper.v
+++ b/quasar_wrapper.v
@@ -44555,222 +44555,222 @@ module ifu(
   input         io_dec_tlu_flush_lower_wb,
   input         io_scan_mode
 );
-  wire  mem_ctl_clock; // @[ifu.scala 36:23]
-  wire  mem_ctl_reset; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_free_clk; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_active_clk; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_exu_flush_final; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 36:23]
-  wire [16:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 36:23]
-  wire [30:0] mem_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 36:23]
-  wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 36:23]
-  wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 36:23]
-  wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dma_mem_ctl_dma_mem_write; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 36:23]
-  wire [14:0] mem_ctl_io_iccm_rw_addr; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_correction_state; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_wren; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_rden; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_iccm_wr_size; // @[ifu.scala 36:23]
-  wire [77:0] mem_ctl_io_iccm_wr_data; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_iccm_rd_data; // @[ifu.scala 36:23]
-  wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 36:23]
-  wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_rd_en; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 36:23]
-  wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 36:23]
-  wire [70:0] mem_ctl_io_ic_debug_rd_data; // @[ifu.scala 36:23]
-  wire [25:0] mem_ctl_io_ic_tag_debug_rd_data; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_eccerr; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_rd_hit; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_tag_perr; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_debug_way; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_ic_premux_data; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_dma_active; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_write_stall; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 36:23]
-  wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 36:23]
-  wire [2:0] mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_ready; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_hit_f; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ic_access_fault_f; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_ifu_async_error_start; // @[ifu.scala 36:23]
-  wire [1:0] mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 36:23]
-  wire [31:0] mem_ctl_io_ic_data_f; // @[ifu.scala 36:23]
-  wire  mem_ctl_io_scan_mode; // @[ifu.scala 36:23]
-  wire  bp_ctl_clock; // @[ifu.scala 37:22]
-  wire  bp_ctl_reset; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_active_clk; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_ic_hit_f; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_flush_final; // @[ifu.scala 37:22]
-  wire [30:0] bp_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_ifc_fetch_req_f; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_index_r; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 37:22]
-  wire [11:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_exu_bp_exu_mp_eghr; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_exu_bp_exu_mp_fghr; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_exu_bp_exu_mp_index; // @[ifu.scala 37:22]
-  wire [4:0] bp_ctl_io_exu_bp_exu_mp_btag; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:22]
-  wire [30:0] bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 37:22]
-  wire [7:0] bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 37:22]
-  wire [1:0] bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 37:22]
-  wire [11:0] bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 37:22]
-  wire  bp_ctl_io_scan_mode; // @[ifu.scala 37:22]
-  wire  aln_ctl_clock; // @[ifu.scala 38:23]
-  wire  aln_ctl_reset; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_scan_mode; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_active_clk; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_ifu_async_error_start; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_ic_access_fault_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ic_access_fault_type_f; // @[ifu.scala 38:23]
-  wire [7:0] aln_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 38:23]
-  wire [30:0] aln_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 38:23]
-  wire [11:0] aln_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_way_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_valid_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_bp_ret_f; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_exu_flush_final; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 38:23]
-  wire [15:0] aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 38:23]
-  wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 38:23]
-  wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 38:23]
-  wire [4:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 38:23]
-  wire [31:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 38:23]
-  wire [30:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 38:23]
-  wire [11:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 38:23]
-  wire [30:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 38:23]
-  wire [31:0] aln_ctl_io_ifu_fetch_data_f; // @[ifu.scala 38:23]
-  wire [1:0] aln_ctl_io_ifu_fetch_val; // @[ifu.scala 38:23]
-  wire [30:0] aln_ctl_io_ifu_fetch_pc; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 38:23]
-  wire  aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 38:23]
-  wire  ifc_ctl_clock; // @[ifu.scala 39:23]
-  wire  ifc_ctl_reset; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_exu_flush_final; // @[ifu.scala 39:23]
-  wire [30:0] ifc_ctl_io_exu_flush_path_final; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_free_clk; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_active_clk; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_scan_mode; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ic_hit_f; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifu_fb_consume1; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifu_fb_consume2; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 39:23]
-  wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ic_dma_active; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ic_write_stall; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 39:23]
-  wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 39:23]
-  wire [30:0] ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 39:23]
-  wire [30:0] ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 39:23]
-  wire  ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 39:23]
-  ifu_mem_ctl mem_ctl ( // @[ifu.scala 36:23]
+  wire  mem_ctl_clock; // @[ifu.scala 34:23]
+  wire  mem_ctl_reset; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_free_clk; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_active_clk; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_exu_flush_final; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 34:23]
+  wire [16:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 34:23]
+  wire [30:0] mem_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23]
+  wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23]
+  wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 34:23]
+  wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dma_mem_ctl_dma_mem_write; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 34:23]
+  wire [14:0] mem_ctl_io_iccm_rw_addr; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_correction_state; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_wren; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_rden; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_iccm_wr_size; // @[ifu.scala 34:23]
+  wire [77:0] mem_ctl_io_iccm_wr_data; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_iccm_rd_data; // @[ifu.scala 34:23]
+  wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 34:23]
+  wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_rd_en; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 34:23]
+  wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 34:23]
+  wire [70:0] mem_ctl_io_ic_debug_rd_data; // @[ifu.scala 34:23]
+  wire [25:0] mem_ctl_io_ic_tag_debug_rd_data; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_eccerr; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_rd_hit; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_tag_perr; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_debug_way; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_ic_premux_data; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_dma_active; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_write_stall; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 34:23]
+  wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 34:23]
+  wire [2:0] mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_ready; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_hit_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ic_access_fault_f; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_ifu_async_error_start; // @[ifu.scala 34:23]
+  wire [1:0] mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 34:23]
+  wire [31:0] mem_ctl_io_ic_data_f; // @[ifu.scala 34:23]
+  wire  mem_ctl_io_scan_mode; // @[ifu.scala 34:23]
+  wire  bp_ctl_clock; // @[ifu.scala 35:22]
+  wire  bp_ctl_reset; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_active_clk; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_ic_hit_f; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_flush_final; // @[ifu.scala 35:22]
+  wire [30:0] bp_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_ifc_fetch_req_f; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_index_r; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 35:22]
+  wire [11:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_exu_bp_exu_mp_eghr; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_exu_bp_exu_mp_fghr; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_exu_bp_exu_mp_index; // @[ifu.scala 35:22]
+  wire [4:0] bp_ctl_io_exu_bp_exu_mp_btag; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 35:22]
+  wire [30:0] bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 35:22]
+  wire [7:0] bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 35:22]
+  wire [1:0] bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 35:22]
+  wire [11:0] bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 35:22]
+  wire  bp_ctl_io_scan_mode; // @[ifu.scala 35:22]
+  wire  aln_ctl_clock; // @[ifu.scala 36:23]
+  wire  aln_ctl_reset; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_scan_mode; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_active_clk; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_ifu_async_error_start; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_ic_access_fault_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ic_access_fault_type_f; // @[ifu.scala 36:23]
+  wire [7:0] aln_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 36:23]
+  wire [30:0] aln_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 36:23]
+  wire [11:0] aln_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_way_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_valid_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_bp_ret_f; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_exu_flush_final; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 36:23]
+  wire [15:0] aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 36:23]
+  wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 36:23]
+  wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 36:23]
+  wire [4:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 36:23]
+  wire [31:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 36:23]
+  wire [30:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 36:23]
+  wire [11:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 36:23]
+  wire [30:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 36:23]
+  wire [31:0] aln_ctl_io_ifu_fetch_data_f; // @[ifu.scala 36:23]
+  wire [1:0] aln_ctl_io_ifu_fetch_val; // @[ifu.scala 36:23]
+  wire [30:0] aln_ctl_io_ifu_fetch_pc; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 36:23]
+  wire  aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 36:23]
+  wire  ifc_ctl_clock; // @[ifu.scala 37:23]
+  wire  ifc_ctl_reset; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_exu_flush_final; // @[ifu.scala 37:23]
+  wire [30:0] ifc_ctl_io_exu_flush_path_final; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_free_clk; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_active_clk; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_scan_mode; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ic_hit_f; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifu_fb_consume1; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifu_fb_consume2; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:23]
+  wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ic_dma_active; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ic_write_stall; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 37:23]
+  wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 37:23]
+  wire [30:0] ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 37:23]
+  wire [30:0] ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 37:23]
+  wire  ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 37:23]
+  ifu_mem_ctl mem_ctl ( // @[ifu.scala 34:23]
     .clock(mem_ctl_clock),
     .reset(mem_ctl_reset),
     .io_free_clk(mem_ctl_io_free_clk),
@@ -44870,7 +44870,7 @@ module ifu(
     .io_ic_data_f(mem_ctl_io_ic_data_f),
     .io_scan_mode(mem_ctl_io_scan_mode)
   );
-  ifu_bp_ctl bp_ctl ( // @[ifu.scala 37:22]
+  ifu_bp_ctl bp_ctl ( // @[ifu.scala 35:22]
     .clock(bp_ctl_clock),
     .reset(bp_ctl_reset),
     .io_active_clk(bp_ctl_io_active_clk),
@@ -44916,7 +44916,7 @@ module ifu(
     .io_ifu_bp_poffset_f(bp_ctl_io_ifu_bp_poffset_f),
     .io_scan_mode(bp_ctl_io_scan_mode)
   );
-  ifu_aln_ctl aln_ctl ( // @[ifu.scala 38:23]
+  ifu_aln_ctl aln_ctl ( // @[ifu.scala 36:23]
     .clock(aln_ctl_clock),
     .reset(aln_ctl_reset),
     .io_scan_mode(aln_ctl_io_scan_mode),
@@ -44963,7 +44963,7 @@ module ifu(
     .io_ifu_fb_consume1(aln_ctl_io_ifu_fb_consume1),
     .io_ifu_fb_consume2(aln_ctl_io_ifu_fb_consume2)
   );
-  ifu_ifc_ctl ifc_ctl ( // @[ifu.scala 39:23]
+  ifu_ifc_ctl ifc_ctl ( // @[ifu.scala 37:23]
     .clock(ifc_ctl_clock),
     .reset(ifc_ctl_reset),
     .io_exu_flush_final(ifc_ctl_io_exu_flush_final),
@@ -44993,63 +44993,63 @@ module ifu(
     .io_ifc_region_acc_fault_bf(ifc_ctl_io_ifc_region_acc_fault_bf),
     .io_ifc_dma_access_ok(ifc_ctl_io_ifc_dma_access_ok)
   );
-  assign io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 75:22]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 94:27]
-  assign io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 48:22]
-  assign io_iccm_rw_addr = mem_ctl_io_iccm_rw_addr; // @[ifu.scala 108:19]
-  assign io_iccm_buf_correct_ecc = mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 108:19]
-  assign io_iccm_correction_state = mem_ctl_io_iccm_correction_state; // @[ifu.scala 108:19]
-  assign io_iccm_wren = mem_ctl_io_iccm_wren; // @[ifu.scala 108:19]
-  assign io_iccm_rden = mem_ctl_io_iccm_rden; // @[ifu.scala 108:19]
-  assign io_iccm_wr_size = mem_ctl_io_iccm_wr_size; // @[ifu.scala 108:19]
-  assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 108:19]
-  assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 107:17]
-  assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 107:17]
-  assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 107:17]
-  assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 107:17]
-  assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 107:17]
-  assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 107:17]
-  assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 107:17]
-  assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 107:17]
-  assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 107:17]
-  assign io_ic_debug_wr_en = mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 107:17]
-  assign io_ic_debug_tag_array = mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 107:17]
-  assign io_ic_debug_way = mem_ctl_io_ic_debug_way; // @[ifu.scala 107:17]
-  assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 107:17]
-  assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 107:17]
-  assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 104:22]
-  assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 104:22]
-  assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 104:22]
-  assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 104:22]
+  assign io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 73:22]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 93:27]
+  assign io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 46:22]
+  assign io_iccm_rw_addr = mem_ctl_io_iccm_rw_addr; // @[ifu.scala 107:19]
+  assign io_iccm_buf_correct_ecc = mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 107:19]
+  assign io_iccm_correction_state = mem_ctl_io_iccm_correction_state; // @[ifu.scala 107:19]
+  assign io_iccm_wren = mem_ctl_io_iccm_wren; // @[ifu.scala 107:19]
+  assign io_iccm_rden = mem_ctl_io_iccm_rden; // @[ifu.scala 107:19]
+  assign io_iccm_wr_size = mem_ctl_io_iccm_wr_size; // @[ifu.scala 107:19]
+  assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 107:19]
+  assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 106:17]
+  assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 106:17]
+  assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 106:17]
+  assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 106:17]
+  assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 106:17]
+  assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 106:17]
+  assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 106:17]
+  assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 106:17]
+  assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 106:17]
+  assign io_ic_debug_wr_en = mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 106:17]
+  assign io_ic_debug_tag_array = mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 106:17]
+  assign io_ic_debug_way = mem_ctl_io_ic_debug_way; // @[ifu.scala 106:17]
+  assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 106:17]
+  assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 106:17]
+  assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22]
+  assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22]
+  assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22]
+  assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22]
   assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25]
   assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22]
   assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21]
@@ -45058,123 +45058,123 @@ module ifu(
   assign io_iccm_dma_sb_error = mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 118:24]
   assign mem_ctl_clock = clock;
   assign mem_ctl_reset = reset;
-  assign mem_ctl_io_free_clk = io_free_clk; // @[ifu.scala 91:23]
-  assign mem_ctl_io_active_clk = io_active_clk; // @[ifu.scala 92:25]
-  assign mem_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 93:30]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt = io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt = io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 94:27]
-  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable = io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 94:27]
-  assign mem_ctl_io_ifc_fetch_addr_bf = ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 95:32]
-  assign mem_ctl_io_ifc_fetch_uncacheable_bf = ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 96:39]
-  assign mem_ctl_io_ifc_fetch_req_bf = ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 97:31]
-  assign mem_ctl_io_ifc_fetch_req_bf_raw = ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 98:35]
-  assign mem_ctl_io_ifc_iccm_access_bf = ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 99:33]
-  assign mem_ctl_io_ifc_region_acc_fault_bf = ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 100:38]
-  assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 101:32]
-  assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 102:33]
-  assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 103:33]
-  assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 104:22]
-  assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 104:22]
-  assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 104:22]
-  assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 104:22]
-  assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 104:22]
-  assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 105:29]
-  assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 106:26]
-  assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 106:26]
-  assign mem_ctl_io_dma_mem_ctl_dma_mem_sz = io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 106:26]
-  assign mem_ctl_io_dma_mem_ctl_dma_mem_write = io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[ifu.scala 106:26]
-  assign mem_ctl_io_dma_mem_ctl_dma_mem_wdata = io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 106:26]
-  assign mem_ctl_io_dma_mem_ctl_dma_mem_tag = io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 106:26]
-  assign mem_ctl_io_iccm_rd_data = io_iccm_rd_data; // @[ifu.scala 108:19]
-  assign mem_ctl_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[ifu.scala 108:19]
-  assign mem_ctl_io_ic_rd_data = io_ic_rd_data; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ic_eccerr = io_ic_eccerr; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ic_rd_hit = io_ic_rd_hit; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ic_tag_perr = io_ic_tag_perr; // @[ifu.scala 107:17]
-  assign mem_ctl_io_ifu_fetch_val = mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 109:28]
-  assign mem_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 110:37]
-  assign mem_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 111:24]
+  assign mem_ctl_io_free_clk = io_free_clk; // @[ifu.scala 90:23]
+  assign mem_ctl_io_active_clk = io_active_clk; // @[ifu.scala 91:25]
+  assign mem_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 92:30]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt = io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt = io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 93:27]
+  assign mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable = io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 93:27]
+  assign mem_ctl_io_ifc_fetch_addr_bf = ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 94:32]
+  assign mem_ctl_io_ifc_fetch_uncacheable_bf = ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 95:39]
+  assign mem_ctl_io_ifc_fetch_req_bf = ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 96:31]
+  assign mem_ctl_io_ifc_fetch_req_bf_raw = ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 97:35]
+  assign mem_ctl_io_ifc_iccm_access_bf = ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 98:33]
+  assign mem_ctl_io_ifc_region_acc_fault_bf = ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 99:38]
+  assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 100:32]
+  assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 101:33]
+  assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 102:33]
+  assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 103:22]
+  assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 104:29]
+  assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 105:26]
+  assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 105:26]
+  assign mem_ctl_io_dma_mem_ctl_dma_mem_sz = io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 105:26]
+  assign mem_ctl_io_dma_mem_ctl_dma_mem_write = io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[ifu.scala 105:26]
+  assign mem_ctl_io_dma_mem_ctl_dma_mem_wdata = io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 105:26]
+  assign mem_ctl_io_dma_mem_ctl_dma_mem_tag = io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 105:26]
+  assign mem_ctl_io_iccm_rd_data = io_iccm_rd_data; // @[ifu.scala 107:19]
+  assign mem_ctl_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[ifu.scala 107:19]
+  assign mem_ctl_io_ic_rd_data = io_ic_rd_data; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ic_eccerr = io_ic_eccerr; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ic_rd_hit = io_ic_rd_hit; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ic_tag_perr = io_ic_tag_perr; // @[ifu.scala 106:17]
+  assign mem_ctl_io_ifu_fetch_val = mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 108:28]
+  assign mem_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 109:37]
+  assign mem_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 110:24]
   assign bp_ctl_clock = clock;
   assign bp_ctl_reset = reset;
-  assign bp_ctl_io_active_clk = io_active_clk; // @[ifu.scala 82:24]
-  assign bp_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 83:22]
-  assign bp_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 88:29]
-  assign bp_ctl_io_ifc_fetch_addr_f = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 84:30]
-  assign bp_ctl_io_ifc_fetch_req_f = ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 85:29]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb = io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_bp_dec_tlu_bpred_disable = io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 86:20]
-  assign bp_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 89:36]
-  assign bp_ctl_io_exu_bp_exu_i0_br_index_r = io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_i0_br_fghr_r = io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp = io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken = io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4 = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist = io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_way = io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_eghr = io_exu_ifu_exu_bp_exu_mp_eghr; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_fghr = io_exu_ifu_exu_bp_exu_mp_fghr; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_index = io_exu_ifu_exu_bp_exu_mp_index; // @[ifu.scala 87:20]
-  assign bp_ctl_io_exu_bp_exu_mp_btag = io_exu_ifu_exu_bp_exu_mp_btag; // @[ifu.scala 87:20]
-  assign bp_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 81:23]
+  assign bp_ctl_io_active_clk = io_active_clk; // @[ifu.scala 80:24]
+  assign bp_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 81:22]
+  assign bp_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 86:29]
+  assign bp_ctl_io_ifc_fetch_addr_f = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 82:30]
+  assign bp_ctl_io_ifc_fetch_req_f = ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 83:29]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb = io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_bp_dec_tlu_bpred_disable = io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 84:20]
+  assign bp_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 87:36]
+  assign bp_ctl_io_exu_bp_exu_i0_br_index_r = io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_i0_br_fghr_r = io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp = io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken = io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4 = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist = io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_way = io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_eghr = io_exu_ifu_exu_bp_exu_mp_eghr; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_fghr = io_exu_ifu_exu_bp_exu_mp_fghr; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_index = io_exu_ifu_exu_bp_exu_mp_index; // @[ifu.scala 85:20]
+  assign bp_ctl_io_exu_bp_exu_mp_btag = io_exu_ifu_exu_bp_exu_mp_btag; // @[ifu.scala 85:20]
+  assign bp_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 79:23]
   assign aln_ctl_clock = clock;
   assign aln_ctl_reset = reset;
-  assign aln_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 59:24]
-  assign aln_ctl_io_active_clk = io_active_clk; // @[ifu.scala 60:25]
-  assign aln_ctl_io_ifu_async_error_start = mem_ctl_io_ifu_async_error_start; // @[ifu.scala 61:36]
-  assign aln_ctl_io_iccm_rd_ecc_double_err = mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 62:37]
-  assign aln_ctl_io_ic_access_fault_f = mem_ctl_io_ic_access_fault_f; // @[ifu.scala 63:32]
-  assign aln_ctl_io_ic_access_fault_type_f = mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 64:37]
-  assign aln_ctl_io_ifu_bp_fghr_f = bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 65:28]
-  assign aln_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 66:34]
-  assign aln_ctl_io_ifu_bp_poffset_f = bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 67:31]
-  assign aln_ctl_io_ifu_bp_hist0_f = bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 68:29]
-  assign aln_ctl_io_ifu_bp_hist1_f = bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 69:29]
-  assign aln_ctl_io_ifu_bp_pc4_f = bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 70:27]
-  assign aln_ctl_io_ifu_bp_way_f = bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 71:27]
-  assign aln_ctl_io_ifu_bp_valid_f = bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 72:29]
-  assign aln_ctl_io_ifu_bp_ret_f = bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 73:27]
-  assign aln_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 74:30]
-  assign aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d = io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 75:22]
-  assign aln_ctl_io_ifu_fetch_data_f = mem_ctl_io_ic_data_f; // @[ifu.scala 76:31]
-  assign aln_ctl_io_ifu_fetch_val = mem_ctl_io_ifu_fetch_val; // @[ifu.scala 77:28]
-  assign aln_ctl_io_ifu_fetch_pc = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 78:27]
+  assign aln_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 57:24]
+  assign aln_ctl_io_active_clk = io_active_clk; // @[ifu.scala 58:25]
+  assign aln_ctl_io_ifu_async_error_start = mem_ctl_io_ifu_async_error_start; // @[ifu.scala 59:36]
+  assign aln_ctl_io_iccm_rd_ecc_double_err = mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 60:37]
+  assign aln_ctl_io_ic_access_fault_f = mem_ctl_io_ic_access_fault_f; // @[ifu.scala 61:32]
+  assign aln_ctl_io_ic_access_fault_type_f = mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 62:37]
+  assign aln_ctl_io_ifu_bp_fghr_f = bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 63:28]
+  assign aln_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 64:34]
+  assign aln_ctl_io_ifu_bp_poffset_f = bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 65:31]
+  assign aln_ctl_io_ifu_bp_hist0_f = bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 66:29]
+  assign aln_ctl_io_ifu_bp_hist1_f = bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 67:29]
+  assign aln_ctl_io_ifu_bp_pc4_f = bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 68:27]
+  assign aln_ctl_io_ifu_bp_way_f = bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 69:27]
+  assign aln_ctl_io_ifu_bp_valid_f = bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 70:29]
+  assign aln_ctl_io_ifu_bp_ret_f = bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 71:27]
+  assign aln_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 72:30]
+  assign aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d = io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 73:22]
+  assign aln_ctl_io_ifu_fetch_data_f = mem_ctl_io_ic_data_f; // @[ifu.scala 74:31]
+  assign aln_ctl_io_ifu_fetch_val = mem_ctl_io_ifu_fetch_val; // @[ifu.scala 75:28]
+  assign aln_ctl_io_ifu_fetch_pc = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 76:27]
   assign ifc_ctl_clock = clock;
   assign ifc_ctl_reset = reset;
-  assign ifc_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 49:30]
-  assign ifc_ctl_io_exu_flush_path_final = io_exu_flush_path_final; // @[ifu.scala 56:35]
-  assign ifc_ctl_io_free_clk = io_free_clk; // @[ifu.scala 43:23]
-  assign ifc_ctl_io_active_clk = io_active_clk; // @[ifu.scala 42:25]
-  assign ifc_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 44:24]
-  assign ifc_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 45:23]
-  assign ifc_ctl_io_ifu_ic_mb_empty = mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 55:30]
-  assign ifc_ctl_io_ifu_fb_consume1 = aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 46:30]
-  assign ifc_ctl_io_ifu_fb_consume2 = aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 47:30]
-  assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 50:33]
-  assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 51:34]
-  assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 52:28]
-  assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 53:29]
-  assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 48:22]
-  assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 48:22]
-  assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 54:22]
+  assign ifc_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 47:30]
+  assign ifc_ctl_io_exu_flush_path_final = io_exu_flush_path_final; // @[ifu.scala 54:35]
+  assign ifc_ctl_io_free_clk = io_free_clk; // @[ifu.scala 41:23]
+  assign ifc_ctl_io_active_clk = io_active_clk; // @[ifu.scala 40:25]
+  assign ifc_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 42:24]
+  assign ifc_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 43:23]
+  assign ifc_ctl_io_ifu_ic_mb_empty = mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 53:30]
+  assign ifc_ctl_io_ifu_fb_consume1 = aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 44:30]
+  assign ifc_ctl_io_ifu_fb_consume2 = aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 45:30]
+  assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 48:33]
+  assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 49:34]
+  assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 50:28]
+  assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 51:29]
+  assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 46:22]
+  assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 46:22]
+  assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 52:22]
 endmodule
 module dec_ib_ctl(
   input         io_ifu_ib_ifu_i0_icaf,
@@ -46049,6 +46049,9 @@ module dec_decode_ctl(
   input  [1:0]  io_dctl_busbuff_lsu_nonblock_load_data_tag,
   input  [31:0] io_dctl_busbuff_lsu_nonblock_load_data,
   input         io_dctl_dma_dma_dccm_stall_any,
+  output        io_dec_aln_dec_i0_decode_d,
+  input  [15:0] io_dec_aln_ifu_i0_cinst,
+  input  [31:0] io_dbg_dctl_dbg_cmd_wrdata,
   input         io_dec_tlu_flush_extint,
   input         io_dec_tlu_force_halt,
   output [31:0] io_dec_i0_inst_wb1,
@@ -46145,10 +46148,7 @@ module dec_decode_ctl(
   output        io_dec_pause_state,
   output        io_dec_pause_state_cg,
   output        io_dec_div_active,
-  input         io_scan_mode,
-  output        io_dec_aln_dec_i0_decode_d,
-  input  [15:0] io_dec_aln_ifu_i0_cinst,
-  input  [31:0] io_dbg_dctl_dbg_cmd_wrdata
+  input         io_scan_mode
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -46247,57 +46247,57 @@ module dec_decode_ctl(
   wire  rvclkhdr_io_clk; // @[lib.scala 327:22]
   wire  rvclkhdr_io_en; // @[lib.scala 327:22]
   wire  rvclkhdr_io_scan_mode; // @[lib.scala 327:22]
-  wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_alu; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rd; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_pc; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_load; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_store; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_add; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_sub; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_land; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_lor; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_sll; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_sra; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_srl; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_slt; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_beq; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_bne; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_bge; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_blt; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_jal; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_by; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_half; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_word; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_presync; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_mret; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_mul; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_low; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_div; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_rem; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_fence; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 362:22]
-  wire  i0_dec_io_out_legal; // @[dec_decode_ctl.scala 362:22]
+  wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_alu; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rd; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_pc; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_load; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_store; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_add; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_sub; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_land; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_lor; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_sll; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_sra; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_srl; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_slt; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_beq; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_bne; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_bge; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_blt; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_jal; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_by; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_half; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_word; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_presync; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_mret; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_mul; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_low; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_div; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_rem; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_fence; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 356:22]
+  wire  i0_dec_io_out_legal; // @[dec_decode_ctl.scala 356:22]
   wire  rvclkhdr_1_io_l1clk; // @[lib.scala 352:23]
   wire  rvclkhdr_1_io_clk; // @[lib.scala 352:23]
   wire  rvclkhdr_1_io_en; // @[lib.scala 352:23]
@@ -46374,249 +46374,249 @@ module dec_decode_ctl(
   wire  rvclkhdr_19_io_clk; // @[lib.scala 352:23]
   wire  rvclkhdr_19_io_en; // @[lib.scala 352:23]
   wire  rvclkhdr_19_io_scan_mode; // @[lib.scala 352:23]
-  reg  tlu_wr_pause_r1; // @[dec_decode_ctl.scala 469:55]
-  wire  _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 181:51]
-  reg  tlu_wr_pause_r2; // @[dec_decode_ctl.scala 470:55]
-  wire  _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 182:32]
-  wire  _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 181:73]
-  wire  _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 183:32]
-  wire  _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 182:56]
-  reg  leak1_i1_stall; // @[dec_decode_ctl.scala 370:56]
-  wire  _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 369:73]
-  wire  _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 369:71]
-  wire  leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 369:53]
-  wire  _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 184:32]
-  wire  _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 183:67]
-  wire  _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 372:53]
-  reg  leak1_i0_stall; // @[dec_decode_ctl.scala 373:56]
-  wire  _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 372:89]
-  wire  leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 372:71]
-  wire  _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 185:32]
-  wire  _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 184:56]
-  reg  pause_stall; // @[dec_decode_ctl.scala 467:50]
-  wire  _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 466:44]
-  wire  _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 465:49]
-  wire  _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 465:47]
+  reg  tlu_wr_pause_r1; // @[dec_decode_ctl.scala 463:55]
+  wire  _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 178:54]
+  reg  tlu_wr_pause_r2; // @[dec_decode_ctl.scala 464:55]
+  wire  _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 179:54]
+  wire  _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 178:89]
+  wire  _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 180:54]
+  wire  _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 179:89]
+  reg  leak1_i1_stall; // @[dec_decode_ctl.scala 364:56]
+  wire  _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 363:73]
+  wire  _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 363:71]
+  wire  leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 363:53]
+  wire  _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 181:54]
+  wire  _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 180:89]
+  wire  _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 366:53]
+  reg  leak1_i0_stall; // @[dec_decode_ctl.scala 367:56]
+  wire  _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 366:89]
+  wire  leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 366:71]
+  wire  _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 182:54]
+  wire  _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 181:89]
+  reg  pause_stall; // @[dec_decode_ctl.scala 461:50]
+  wire  _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 460:44]
+  wire  _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 459:49]
+  wire  _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 459:47]
   reg [31:0] write_csr_data; // @[lib.scala 358:16]
   wire [31:0] _T_412 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58]
-  wire  _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 465:109]
-  wire  _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 465:91]
-  wire  clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 465:76]
-  wire  _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 466:61]
-  wire  pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 466:59]
-  wire  _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 186:32]
-  wire  _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 185:56]
-  wire  _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 196:62]
-  wire  i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 196:60]
-  wire  i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
+  wire  _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 459:109]
+  wire  _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 459:91]
+  wire  clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 459:76]
+  wire  _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 460:61]
+  wire  pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 460:59]
+  wire  _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 183:54]
+  wire  _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 182:89]
+  wire  _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 192:80]
+  wire  i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 192:78]
+  wire  i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
   wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58]
-  wire  _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 378:79]
-  wire  _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 378:112]
-  wire  i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 378:33]
-  wire  i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 379:47]
-  wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 592:16]
-  wire  _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 379:76]
-  wire  _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 379:98]
-  wire  _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 379:89]
-  wire  i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 379:65]
-  wire  i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 381:38]
-  wire  _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 207:75]
-  wire  _T_309 = ~_T_304; // @[dec_decode_ctl.scala 380:67]
-  wire  i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 380:65]
-  wire  i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 383:38]
-  wire  _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 207:90]
-  wire  i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 387:37]
-  wire  _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 387:65]
-  wire  _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 387:55]
-  wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 590:16]
-  wire  _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 387:89]
-  wire  _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 387:111]
-  wire  _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 387:101]
-  wire  i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 387:79]
-  wire  i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 388:32]
-  wire  _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 207:103]
-  wire  _T_23 = ~_T_22; // @[dec_decode_ctl.scala 207:56]
-  wire  i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 207:54]
-  wire  _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 212:62]
-  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 210:47]
-  wire  _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 385:41]
+  wire  _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 372:79]
+  wire  _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 372:112]
+  wire  i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 372:33]
+  wire  i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 373:47]
+  wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 586:16]
+  wire  _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 373:76]
+  wire  _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 373:98]
+  wire  _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 373:89]
+  wire  i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 373:65]
+  wire  i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 375:38]
+  wire  _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 203:92]
+  wire  _T_309 = ~_T_304; // @[dec_decode_ctl.scala 374:67]
+  wire  i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 374:65]
+  wire  i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 377:38]
+  wire  _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 203:107]
+  wire  i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 381:37]
+  wire  _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 381:65]
+  wire  _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 381:55]
+  wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 584:16]
+  wire  _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 381:89]
+  wire  _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 381:111]
+  wire  _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 381:101]
+  wire  i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 381:79]
+  wire  i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 382:32]
+  wire  _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 203:120]
+  wire  _T_23 = ~_T_22; // @[dec_decode_ctl.scala 203:73]
+  wire  i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 203:71]
+  wire  _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 208:87]
+  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 206:72]
+  wire  _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 379:41]
   wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
-  wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 385:26]
-  wire  _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 210:106]
-  wire  _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 210:76]
-  wire  _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 210:126]
-  wire  i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 210:124]
-  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 212:79]
-  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 211:47]
-  wire  i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 211:72]
-  wire  i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 212:101]
-  wire  _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 217:47]
-  wire  i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 217:84]
-  wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 226:36]
-  wire  _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 230:25]
-  wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 230:50]
-  wire  _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 496:36]
-  wire  debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 488:48]
-  wire  _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 496:60]
-  wire  i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 230:50]
-  wire  _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 427:42]
-  wire  i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 427:40]
-  wire  i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 230:50]
-  wire  _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 432:41]
-  wire  i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 432:39]
-  wire  _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 496:112]
-  wire  _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 496:99]
-  wire  i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 496:76]
-  wire  i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 230:50]
-  wire  any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 498:34]
-  wire  _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 500:40]
-  wire  _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 500:51]
-  wire  i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 500:37]
-  wire  _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 540:64]
-  wire  _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 540:62]
-  wire  _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 540:47]
-  reg  postsync_stall; // @[dec_decode_ctl.scala 538:53]
+  wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 379:26]
+  wire  _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 206:131]
+  wire  _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 206:101]
+  wire  _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 206:151]
+  wire  i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 206:149]
+  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 208:104]
+  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 207:72]
+  wire  i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 207:97]
+  wire  i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 208:126]
+  wire  _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 213:72]
+  wire  i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 213:109]
+  wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 222:43]
+  wire  _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 225:25]
+  wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 225:50]
+  wire  _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 490:36]
+  wire  debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 482:48]
+  wire  _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 490:60]
+  wire  i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 225:50]
+  wire  _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 421:42]
+  wire  i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 421:40]
+  wire  i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 225:50]
+  wire  _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 426:41]
+  wire  i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 426:39]
+  wire  _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 490:112]
+  wire  _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 490:99]
+  wire  i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 490:76]
+  wire  i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 225:50]
+  wire  any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 492:34]
+  wire  _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 494:40]
+  wire  _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 494:51]
+  wire  i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 494:37]
+  wire  _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 534:64]
+  wire  _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 534:62]
+  wire  _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 534:47]
+  reg  postsync_stall; // @[dec_decode_ctl.scala 532:53]
   reg  x_d_valid; // @[lib.scala 368:16]
-  wire  _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 540:96]
-  wire  ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 540:77]
-  wire  _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 187:32]
-  wire  _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 186:56]
-  reg  flush_final_r; // @[dec_decode_ctl.scala 586:52]
-  wire  _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 188:32]
-  wire  _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 187:56]
-  wire  shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 504:55]
-  reg  illegal_lockout; // @[dec_decode_ctl.scala 508:54]
-  wire  _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 507:40]
-  wire  _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 507:61]
-  wire  illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 507:59]
-  wire  _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 189:32]
-  wire  i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 614:54]
-  wire  _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 213:83]
-  wire  _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 214:105]
-  wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12]
-  wire  i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 230:50]
-  wire  i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 382:38]
-  wire  _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 244:40]
-  wire  i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 384:38]
-  wire  _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 244:51]
-  wire  i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 389:32]
-  wire  i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 244:60]
-  wire  _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 246:55]
-  wire  _T_48 = ~_T_47; // @[dec_decode_ctl.scala 246:26]
-  wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 248:20]
-  wire  cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 281:76]
-  reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 317:47]
-  wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 292:67]
-  wire  _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 292:67]
-  wire  _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 292:45]
-  reg  cam_raw_0_valid; // @[dec_decode_ctl.scala 317:47]
-  wire  cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 292:88]
-  wire  cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 296:39]
-  wire  _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 273:78]
-  reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 292:67]
-  wire  _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 292:45]
-  reg  cam_raw_1_valid; // @[dec_decode_ctl.scala 317:47]
-  wire  cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 292:88]
-  wire  cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 296:39]
-  wire  _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 273:78]
-  wire  _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 273:126]
-  wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 273:158]
-  reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 292:67]
-  wire  _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 292:45]
-  reg  cam_raw_2_valid; // @[dec_decode_ctl.scala 317:47]
-  wire  cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 292:88]
-  wire  cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 296:39]
-  wire  _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 273:78]
-  wire  _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 273:126]
-  wire  _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 273:126]
-  wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 273:158]
-  reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 292:67]
-  wire  _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 292:45]
-  reg  cam_raw_3_valid; // @[dec_decode_ctl.scala 317:47]
-  wire  cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 292:88]
-  wire  cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 296:39]
-  wire  _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 273:78]
-  wire  _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 273:126]
-  wire  _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 273:126]
-  wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 273:158]
+  wire  _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 534:96]
+  wire  ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 534:77]
+  wire  _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 184:54]
+  wire  _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 183:89]
+  reg  flush_final_r; // @[dec_decode_ctl.scala 580:52]
+  wire  _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 185:54]
+  wire  _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 184:89]
+  wire  shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 498:55]
+  reg  illegal_lockout; // @[dec_decode_ctl.scala 502:54]
+  wire  _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 501:40]
+  wire  _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 501:61]
+  wire  illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 501:59]
+  wire  _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 186:54]
+  wire  i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 608:54]
+  wire  _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 209:72]
+  wire  _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 210:94]
+  wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12]
+  wire  i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 225:50]
+  wire  i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 376:38]
+  wire  _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 239:54]
+  wire  i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 378:38]
+  wire  _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 239:65]
+  wire  i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 383:32]
+  wire  i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 239:74]
+  wire  _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 240:69]
+  wire  _T_48 = ~_T_47; // @[dec_decode_ctl.scala 240:40]
+  wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 242:40]
+  wire  cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 275:76]
+  reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 311:47]
+  wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 286:67]
+  wire  _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 286:67]
+  wire  _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 286:45]
+  reg  cam_raw_0_valid; // @[dec_decode_ctl.scala 311:47]
+  wire  cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 286:88]
+  wire  cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 290:39]
+  wire  _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 267:78]
+  reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 286:67]
+  wire  _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 286:45]
+  reg  cam_raw_1_valid; // @[dec_decode_ctl.scala 311:47]
+  wire  cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 286:88]
+  wire  cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 290:39]
+  wire  _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 267:78]
+  wire  _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 267:126]
+  wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 267:158]
+  reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 286:67]
+  wire  _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 286:45]
+  reg  cam_raw_2_valid; // @[dec_decode_ctl.scala 311:47]
+  wire  cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 286:88]
+  wire  cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 290:39]
+  wire  _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 267:78]
+  wire  _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 267:126]
+  wire  _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 267:126]
+  wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 267:158]
+  reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 286:67]
+  wire  _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 286:45]
+  reg  cam_raw_3_valid; // @[dec_decode_ctl.scala 311:47]
+  wire  cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 286:88]
+  wire  cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 290:39]
+  wire  _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 267:78]
+  wire  _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 267:126]
+  wire  _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 267:126]
+  wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 267:158]
   wire  _T_81 = _T_51 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72]
   wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72]
@@ -46629,150 +46629,150 @@ module dec_decode_ctl(
   wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72]
   reg  x_d_bits_i0load; // @[lib.scala 368:16]
   reg [4:0] x_d_bits_i0rd; // @[lib.scala 368:16]
-  wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31]
-  reg [2:0] _T_706; // @[dec_decode_ctl.scala 622:80]
+  wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 278:31]
+  reg [2:0] _T_706; // @[dec_decode_ctl.scala 616:80]
   wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_706}; // @[Cat.scala 29:58]
-  wire  _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49]
-  wire  i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 625:53]
+  wire  _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 619:49]
+  wire  i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 619:53]
   reg  nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
   reg  r_d_bits_i0load; // @[lib.scala 368:16]
-  wire  i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56]
-  wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 291:66]
-  wire  _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 291:66]
-  wire  _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45]
-  wire  cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87]
+  wire  i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 283:56]
+  wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 285:66]
+  wire  _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 285:66]
+  wire  _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 285:45]
+  wire  cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 285:87]
   reg  r_d_bits_i0v; // @[lib.scala 368:16]
-  wire  _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51]
-  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 657:49]
-  wire  _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47]
-  wire  i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 665:45]
+  wire  _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 651:51]
+  wire  r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 651:49]
+  wire  _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 659:47]
+  wire  i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 659:45]
   reg [4:0] r_d_bits_i0rd; // @[lib.scala 368:16]
-  reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85]
-  wire  _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 304:64]
-  reg  cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:105]
-  wire  _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 304:44]
-  wire  _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 299:28]
-  wire  _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 299:28]
-  wire  _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 309:44]
-  wire  _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 309:113]
-  wire  nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 318:71]
-  wire  _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 291:66]
-  wire  _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 291:45]
-  wire  cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 291:87]
-  reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 304:85]
-  wire  _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 304:64]
-  reg  cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:105]
-  wire  _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 304:44]
-  wire  _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 299:28]
-  wire  _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 299:28]
-  wire  _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 309:44]
-  wire  _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 309:113]
-  wire  nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 318:71]
-  wire  _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 291:66]
-  wire  _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 291:45]
-  wire  cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 291:87]
-  reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 304:85]
-  wire  _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 304:64]
-  reg  cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:105]
-  wire  _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 304:44]
-  wire  _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 299:28]
-  wire  _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 299:28]
-  wire  _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 309:44]
-  wire  _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 309:113]
-  wire  nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 318:71]
-  wire  _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 291:66]
-  wire  _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 291:45]
-  wire  cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 291:87]
-  reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 304:85]
-  wire  _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 304:64]
-  reg  cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 317:47]
-  wire  _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:105]
-  wire  _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 304:44]
-  wire  _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:131]
-  wire  _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 299:28]
-  wire  _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 299:28]
-  wire  _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 309:44]
-  wire  _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 309:113]
-  wire  nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 318:71]
-  wire  _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 323:49]
-  wire  nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 323:81]
-  wire  _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 324:108]
-  wire  _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 324:108]
-  wire  _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 324:108]
-  wire  _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 324:77]
-  wire  _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 324:122]
-  wire  _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 325:54]
-  wire  _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:66]
-  wire  _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 325:110]
-  wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 591:16]
-  wire  _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 325:161]
-  wire  _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:173]
-  wire  _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 325:217]
-  wire  i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 325:142]
+  reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 298:85]
+  wire  _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 298:64]
+  reg  cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:105]
+  wire  _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 298:44]
+  wire  _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 293:28]
+  wire  _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 293:28]
+  wire  _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 303:44]
+  wire  _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 303:113]
+  wire  nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 312:71]
+  wire  _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 285:66]
+  wire  _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 285:45]
+  wire  cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 285:87]
+  reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 298:85]
+  wire  _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 298:64]
+  reg  cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:105]
+  wire  _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 298:44]
+  wire  _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 293:28]
+  wire  _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 293:28]
+  wire  _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 303:44]
+  wire  _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 303:113]
+  wire  nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 312:71]
+  wire  _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 285:66]
+  wire  _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 285:45]
+  wire  cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 285:87]
+  reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 298:85]
+  wire  _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 298:64]
+  reg  cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:105]
+  wire  _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 298:44]
+  wire  _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 293:28]
+  wire  _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 293:28]
+  wire  _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 303:44]
+  wire  _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 303:113]
+  wire  nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 312:71]
+  wire  _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 285:66]
+  wire  _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 285:45]
+  wire  cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 285:87]
+  reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 298:85]
+  wire  _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 298:64]
+  reg  cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 311:47]
+  wire  _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:105]
+  wire  _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 298:44]
+  wire  _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:131]
+  wire  _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 293:28]
+  wire  _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 293:28]
+  wire  _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 303:44]
+  wire  _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 303:113]
+  wire  nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 312:71]
+  wire  _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 317:49]
+  wire  nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 317:81]
+  wire  _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 318:108]
+  wire  _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 318:108]
+  wire  _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 318:108]
+  wire  _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 318:77]
+  wire  _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 318:122]
+  wire  _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 319:54]
+  wire  _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:66]
+  wire  _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 319:110]
+  wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 585:16]
+  wire  _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 319:161]
+  wire  _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:173]
+  wire  _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 319:217]
+  wire  i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 319:142]
   wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 329:88]
-  wire  _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:137]
-  wire  _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170]
-  wire  _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 329:152]
-  wire  _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:214]
-  wire  _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247]
-  wire  _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 329:229]
+  wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 323:88]
+  wire  _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:137]
+  wire  _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170]
+  wire  _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 323:152]
+  wire  _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:214]
+  wire  _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247]
+  wire  _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 323:229]
   wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 329:88]
-  wire  _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:137]
-  wire  _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170]
-  wire  _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 329:152]
-  wire  _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:214]
-  wire  _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247]
-  wire  _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 329:229]
+  wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 323:88]
+  wire  _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:137]
+  wire  _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170]
+  wire  _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 323:152]
+  wire  _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:214]
+  wire  _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247]
+  wire  _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 323:229]
   wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 329:88]
-  wire  _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:137]
-  wire  _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170]
-  wire  _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 329:152]
-  wire  _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:214]
-  wire  _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247]
-  wire  _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 329:229]
+  wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 323:88]
+  wire  _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:137]
+  wire  _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170]
+  wire  _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 323:152]
+  wire  _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:214]
+  wire  _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247]
+  wire  _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 323:229]
   wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 329:88]
-  wire  _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:137]
-  wire  _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170]
-  wire  _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 329:152]
-  wire  _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:214]
-  wire  _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247]
-  wire  _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 329:229]
-  wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 330:69]
-  wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 330:69]
-  wire  _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 330:102]
-  wire  _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 330:102]
-  wire  ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 330:102]
-  wire  _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 330:134]
-  wire  _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 330:134]
-  wire  ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 330:134]
-  wire  _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 332:38]
-  wire  i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 332:51]
-  wire  _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 341:34]
+  wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 323:88]
+  wire  _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:137]
+  wire  _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170]
+  wire  _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 323:152]
+  wire  _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:214]
+  wire  _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247]
+  wire  _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 323:229]
+  wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 324:69]
+  wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 324:69]
+  wire  _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 324:102]
+  wire  _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 324:102]
+  wire  ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 324:102]
+  wire  _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 324:134]
+  wire  _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 324:134]
+  wire  ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 324:134]
+  wire  _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 326:38]
+  wire  i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 326:51]
+  wire  _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 335:34]
   wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire  csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 425:36]
-  wire  _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 353:16]
-  wire  _T_258 = ~csr_read; // @[dec_decode_ctl.scala 354:6]
-  wire  _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 354:16]
-  wire  _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 355:18]
-  wire  _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 355:16]
+  wire  csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 419:36]
+  wire  _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 347:16]
+  wire  _T_258 = ~csr_read; // @[dec_decode_ctl.scala 348:6]
+  wire  _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 348:16]
+  wire  _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 349:18]
+  wire  _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 349:16]
   wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16]
   wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16]
   wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16]
@@ -46787,143 +46787,143 @@ module dec_decode_ctl(
   wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16]
   wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16]
   wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16]
-  reg  lsu_idle; // @[dec_decode_ctl.scala 366:45]
-  wire  _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 390:35]
-  wire  _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 390:32]
-  wire  _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 390:52]
-  wire  _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 390:50]
-  wire  _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67]
-  reg  _T_339; // @[dec_decode_ctl.scala 402:69]
-  wire  lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40]
-  wire  _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43]
+  reg  lsu_idle; // @[dec_decode_ctl.scala 360:45]
+  wire  _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 384:35]
+  wire  _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 384:32]
+  wire  _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 384:52]
+  wire  _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 384:50]
+  wire  _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 384:67]
+  reg  _T_339; // @[dec_decode_ctl.scala 396:69]
+  wire  lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 538:40]
+  wire  _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 752:43]
   reg  x_d_bits_i0v; // @[lib.scala 368:16]
-  wire  _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59]
-  wire  _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91]
-  wire  i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 738:74]
-  wire  _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59]
-  wire  _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91]
-  wire  i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 739:74]
-  wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63]
-  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 745:24]
-  wire  _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58]
+  wire  _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 732:59]
+  wire  _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 732:91]
+  wire  i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 732:74]
+  wire  _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 733:59]
+  wire  _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 733:91]
+  wire  i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 733:74]
+  wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 739:63]
+  wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 739:24]
+  wire  _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 752:58]
   reg  i0_x_c_load; // @[Reg.scala 27:20]
   reg  i0_r_c_load; // @[Reg.scala 27:20]
-  wire  _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61]
-  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 744:24]
-  wire  load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78]
-  wire  _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59]
-  wire  _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91]
-  wire  i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 741:74]
-  wire  _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59]
-  wire  _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91]
-  wire  i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 742:74]
-  wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63]
-  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 747:24]
-  wire  _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43]
-  wire  _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61]
-  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 746:24]
-  wire  store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63]
-  wire  _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42]
+  wire  _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 738:61]
+  wire  i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 738:24]
+  wire  load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 752:78]
+  wire  _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 735:59]
+  wire  _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 735:91]
+  wire  i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 735:74]
+  wire  _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 736:59]
+  wire  _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 736:91]
+  wire  i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 736:74]
+  wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 741:63]
+  wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 741:24]
+  wire  _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 753:43]
+  wire  _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 740:61]
+  wire  i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 740:24]
+  wire  store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 753:63]
+  wire  _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 427:42]
   reg  r_d_bits_csrwen; // @[lib.scala 368:16]
   reg  r_d_valid; // @[lib.scala 368:16]
-  wire  _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 441:39]
+  wire  _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 435:39]
   reg [11:0] r_d_bits_csrwaddr; // @[lib.scala 368:16]
-  wire  _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 444:50]
-  wire  _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 444:85]
-  wire  _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 444:64]
-  wire  _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 444:100]
-  wire  _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 444:118]
-  wire  _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 444:132]
-  reg  csr_read_x; // @[dec_decode_ctl.scala 446:52]
-  reg  csr_clr_x; // @[dec_decode_ctl.scala 447:51]
-  reg  csr_set_x; // @[dec_decode_ctl.scala 448:51]
-  reg  csr_write_x; // @[dec_decode_ctl.scala 449:53]
-  reg  csr_imm_x; // @[dec_decode_ctl.scala 450:51]
-  wire  i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 627:50]
+  wire  _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 438:50]
+  wire  _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 438:85]
+  wire  _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 438:64]
+  wire  _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 438:100]
+  wire  _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 438:118]
+  wire  _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 438:132]
+  reg  csr_read_x; // @[dec_decode_ctl.scala 440:52]
+  reg  csr_clr_x; // @[dec_decode_ctl.scala 441:51]
+  reg  csr_set_x; // @[dec_decode_ctl.scala 442:51]
+  reg  csr_write_x; // @[dec_decode_ctl.scala 443:53]
+  reg  csr_imm_x; // @[dec_decode_ctl.scala 444:51]
+  wire  i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 621:50]
   reg [4:0] csrimm_x; // @[lib.scala 358:16]
   reg [31:0] csr_rddata_x; // @[lib.scala 358:16]
   wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58]
-  wire  _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 458:5]
+  wire  _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 452:5]
   wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_398 = _T_396 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72]
-  wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 461:38]
-  wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 461:35]
-  wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 462:35]
+  wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 455:38]
+  wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 455:35]
+  wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 456:35]
   wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72]
   wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72]
-  wire  _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 472:44]
-  wire  _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 472:64]
-  wire  _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 472:61]
-  wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 475:59]
-  wire  _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 477:34]
-  wire  _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 477:46]
-  wire  _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61]
-  wire  _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75]
+  wire  _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 466:44]
+  wire  _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 466:64]
+  wire  _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 466:61]
+  wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 469:59]
+  wire  _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 471:34]
+  wire  _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 471:46]
+  wire  _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 471:61]
+  wire  _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 471:75]
   reg  r_d_bits_csrwonly; // @[lib.scala 368:16]
-  wire  _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42]
+  wire  _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 674:42]
   reg [31:0] i0_result_r_raw; // @[lib.scala 358:16]
-  wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27]
+  wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 674:27]
   reg  x_d_bits_csrwonly; // @[lib.scala 368:16]
-  wire  _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43]
+  wire  _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 480:43]
   reg  wbd_bits_csrwonly; // @[lib.scala 368:16]
-  wire  prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 486:63]
-  wire  debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 489:48]
-  wire  debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 490:40]
-  wire  _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 493:34]
-  wire  _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 493:57]
-  wire  _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 493:73]
-  wire  i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 493:91]
+  wire  prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 480:63]
+  wire  debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 483:48]
+  wire  debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 484:40]
+  wire  _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 487:34]
+  wire  _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 487:57]
+  wire  _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 487:73]
+  wire  i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 487:91]
   wire [31:0] _T_465 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58]
-  wire  _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 505:44]
+  wire  _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 499:44]
   reg [31:0] _T_468; // @[lib.scala 358:16]
-  wire  i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 509:42]
-  wire  _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 511:40]
-  wire  _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 511:59]
-  wire  _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 511:92]
-  wire  _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 511:106]
-  wire  _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 512:20]
-  wire  _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 512:45]
-  wire  prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 534:41]
-  wire  prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 535:31]
-  wire  presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 537:37]
-  wire  _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 512:62]
-  wire  _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 513:19]
-  wire  _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 513:36]
-  wire  _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34]
-  wire  _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79]
-  wire  _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47]
-  wire  _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60]
-  wire  _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99]
-  wire  _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 708:80]
-  wire  _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36]
-  wire  _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75]
-  wire  _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 709:56]
-  wire  i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 708:113]
-  wire  _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21]
-  wire  i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45]
-  wire  _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65]
-  wire  i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 516:39]
-  wire  _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 517:63]
-  wire  i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 517:38]
-  wire  _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 518:38]
-  wire  i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 518:57]
-  wire  _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 522:54]
-  wire  _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 522:52]
-  wire  _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 522:69]
-  wire  _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 523:46]
-  wire  _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 523:44]
-  wire  _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 523:61]
-  wire  i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 523:89]
-  wire  i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 524:46]
-  wire  _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51]
-  wire  _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44]
+  wire  i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 503:42]
+  wire  _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 505:40]
+  wire  _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 505:59]
+  wire  _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 505:92]
+  wire  _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 505:106]
+  wire  _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 506:20]
+  wire  _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 506:45]
+  wire  prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 528:41]
+  wire  prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 529:31]
+  wire  presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 531:37]
+  wire  _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 506:62]
+  wire  _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 507:19]
+  wire  _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 507:36]
+  wire  _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 507:34]
+  wire  _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 506:79]
+  wire  _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 507:47]
+  wire  _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 702:60]
+  wire  _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 702:99]
+  wire  _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 702:80]
+  wire  _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 703:36]
+  wire  _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 703:75]
+  wire  _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 703:56]
+  wire  i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 702:113]
+  wire  _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 508:21]
+  wire  i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 508:45]
+  wire  _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 510:65]
+  wire  i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 510:39]
+  wire  _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 511:63]
+  wire  i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 511:38]
+  wire  _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 512:38]
+  wire  i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 512:57]
+  wire  _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 516:54]
+  wire  _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 516:52]
+  wire  _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 516:69]
+  wire  _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 517:46]
+  wire  _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 517:44]
+  wire  _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 517:61]
+  wire  i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 517:89]
+  wire  i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 518:46]
+  wire  _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 522:51]
+  wire  _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 550:44]
   wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58]
-  wire  _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49]
-  wire  i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 624:53]
+  wire  _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 618:49]
+  wire  i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 618:53]
   reg  x_t_legal; // @[lib.scala 368:16]
   reg  x_t_icaf; // @[lib.scala 368:16]
   reg  x_t_icaf_f1; // @[lib.scala 368:16]
@@ -46933,7 +46933,7 @@ module dec_decode_ctl(
   reg [3:0] x_t_pmu_i0_itype; // @[lib.scala 368:16]
   reg  x_t_pmu_i0_br_unpred; // @[lib.scala 368:16]
   wire [3:0] _T_533 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58]
-  wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 569:39]
+  wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 563:39]
   reg  r_t_legal; // @[lib.scala 368:16]
   reg  r_t_icaf; // @[lib.scala 368:16]
   reg  r_t_icaf_f1; // @[lib.scala 368:16]
@@ -46942,22 +46942,22 @@ module dec_decode_ctl(
   reg [3:0] r_t_i0trigger; // @[lib.scala 368:16]
   reg [3:0] r_t_pmu_i0_itype; // @[lib.scala 368:16]
   reg  r_t_pmu_i0_br_unpred; // @[lib.scala 368:16]
-  reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 572:36]
-  reg  lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 573:37]
+  reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 566:36]
+  reg  lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 567:37]
   reg  r_d_bits_i0store; // @[lib.scala 368:16]
-  wire  _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 577:61]
+  wire  _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 571:61]
   wire [3:0] _T_543 = {_T_539,_T_539,_T_539,_T_539}; // @[Cat.scala 29:58]
-  wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 577:82]
-  wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 577:105]
+  wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 571:82]
+  wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 571:105]
   reg  r_d_bits_i0div; // @[lib.scala 368:16]
-  wire  _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 583:58]
-  wire  _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 594:60]
-  wire  _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 595:60]
-  wire  _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 596:48]
-  wire  i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 596:37]
-  wire  i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 600:38]
-  wire  _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 601:27]
-  wire  i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 601:38]
+  wire  _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 577:58]
+  wire  _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 588:60]
+  wire  _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 589:60]
+  wire  _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 590:48]
+  wire  i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 590:37]
+  wire  i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 594:38]
+  wire  _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 595:27]
+  wire  i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 595:38]
   wire [31:0] _T_566 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72]
   wire [9:0] _T_580 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
   wire [18:0] _T_589 = {_T_580,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
@@ -46972,55 +46972,55 @@ module dec_decode_ctl(
   wire [31:0] _T_655 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58]
   wire [31:0] _T_690 = i0_uiimm20 ? _T_655 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_694 = _T_693 | _T_690; // @[Mux.scala 27:72]
-  wire  _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 612:26]
+  wire  _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 606:26]
   wire [31:0] _T_686 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58]
   wire [31:0] _T_691 = _T_656 ? _T_686 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] i0_immed_d = _T_694 | _T_691; // @[Mux.scala 27:72]
   wire [31:0] _T_567 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72]
-  wire  i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44]
-  wire  i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44]
-  wire  i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44]
+  wire  i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 610:44]
+  wire  i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 611:44]
+  wire  i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 612:44]
   reg  i0_x_c_mul; // @[Reg.scala 27:20]
   reg  i0_x_c_alu; // @[Reg.scala 27:20]
   reg  i0_r_c_mul; // @[Reg.scala 27:20]
   reg  i0_r_c_alu; // @[Reg.scala 27:20]
-  wire  _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49]
-  wire  i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50]
+  wire  _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 620:49]
+  wire  i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 622:50]
   reg  x_d_bits_i0store; // @[lib.scala 368:16]
   reg  x_d_bits_i0div; // @[lib.scala 368:16]
   reg  x_d_bits_csrwen; // @[lib.scala 368:16]
   reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 368:16]
-  wire  _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 650:47]
-  wire  _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 651:33]
-  wire  _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49]
-  wire  _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 666:47]
-  wire  _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70]
-  wire  _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47]
-  wire  _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71]
+  wire  _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 644:47]
+  wire  _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 645:33]
+  wire  _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 660:49]
+  wire  _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 660:47]
+  wire  _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 660:70]
+  wire  _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 669:47]
+  wire  _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 675:71]
   wire [11:0] _T_786 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
   reg [11:0] last_br_immed_x; // @[lib.scala 358:16]
-  wire  _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45]
-  wire  div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 689:58]
-  wire  _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77]
-  wire  _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 691:60]
-  wire  _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33]
-  wire  _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 691:94]
-  wire  _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33]
-  wire  _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60]
-  wire  div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 692:62]
-  wire  _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51]
-  wire  _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26]
-  wire  _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 698:24]
-  wire  _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56]
-  wire  _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 698:39]
-  wire  _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 698:77]
-  wire  nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 697:65]
-  wire  i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55]
-  wire  _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62]
-  wire  _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 703:60]
-  wire  _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81]
-  wire  _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 703:79]
-  reg  _T_826; // @[dec_decode_ctl.scala 705:54]
+  wire  _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 683:45]
+  wire  div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 683:58]
+  wire  _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 685:77]
+  wire  _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 685:60]
+  wire  _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 686:33]
+  wire  _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 685:94]
+  wire  _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 687:33]
+  wire  _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 687:60]
+  wire  div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 686:62]
+  wire  _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 691:51]
+  wire  _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 692:26]
+  wire  _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 692:24]
+  wire  _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 692:56]
+  wire  _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 692:39]
+  wire  _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 692:77]
+  wire  nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 691:65]
+  wire  i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 695:55]
+  wire  _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 697:62]
+  wire  _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 697:60]
+  wire  _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 697:81]
+  wire  _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 697:79]
+  reg  _T_826; // @[dec_decode_ctl.scala 699:54]
   reg [4:0] _T_835; // @[Reg.scala 27:20]
   reg [31:0] i0_inst_x; // @[lib.scala 358:16]
   reg [31:0] i0_inst_r; // @[lib.scala 358:16]
@@ -47045,65 +47045,65 @@ module dec_decode_ctl(
   wire [18:0] _T_875 = _T_872 | _T_873; // @[Mux.scala 27:72]
   wire [18:0] _T_876 = _T_875 | _T_874; // @[Mux.scala 27:72]
   wire [31:0] temp_pred_correct_npc_x = {_T_876,_T_851[11:0],1'h0}; // @[Cat.scala 29:58]
-  wire  _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61]
-  wire  _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61]
-  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 744:24]
-  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 744:24]
-  wire  _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61]
-  wire  _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61]
-  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 746:24]
-  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 746:24]
-  wire  _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73]
-  wire  _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130]
-  wire  i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 764:100]
-  wire  _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73]
-  wire  _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130]
-  wire  i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 766:100]
-  wire  _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66]
-  wire  _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 769:45]
-  wire  _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108]
-  wire  _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196]
-  wire  _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 769:153]
+  wire  _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 738:61]
+  wire  _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 738:61]
+  wire  i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 738:24]
+  wire  i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 738:24]
+  wire  _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 740:61]
+  wire  _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 740:61]
+  wire  i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 740:24]
+  wire  i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 740:24]
+  wire  _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 758:73]
+  wire  _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 758:130]
+  wire  i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 758:100]
+  wire  _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 760:73]
+  wire  _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 760:130]
+  wire  i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 760:100]
+  wire  _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 763:66]
+  wire  _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 763:45]
+  wire  _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:108]
+  wire  _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:196]
+  wire  _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 763:153]
   wire [2:0] i0_rs1bypass = {_T_920,_T_922,_T_926}; // @[Cat.scala 29:58]
-  wire  _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67]
-  wire  _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 771:45]
-  wire  _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109]
-  wire  _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196]
-  wire  _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 771:153]
+  wire  _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 765:67]
+  wire  _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 765:45]
+  wire  _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:109]
+  wire  _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:196]
+  wire  _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 765:153]
   wire [2:0] i0_rs2bypass = {_T_931,_T_933,_T_937}; // @[Cat.scala 29:58]
-  wire  _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86]
-  wire  _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107]
-  wire  _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124]
-  wire  _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 773:104]
-  wire  _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86]
-  wire  _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107]
-  wire  _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124]
-  wire  _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 774:104]
-  wire  _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6]
-  wire  _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25]
-  wire  _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 780:23]
-  wire  _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42]
+  wire  _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 767:86]
+  wire  _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 767:107]
+  wire  _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 767:124]
+  wire  _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 767:104]
+  wire  _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 768:86]
+  wire  _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 768:107]
+  wire  _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 768:124]
+  wire  _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 768:104]
+  wire  _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 774:6]
+  wire  _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 774:25]
+  wire  _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 774:23]
+  wire  _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:42]
   wire [31:0] _T_969 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_970 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_971 = _T_967 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_972 = _T_969 | _T_970; // @[Mux.scala 27:72]
-  wire  _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6]
-  wire  _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25]
-  wire  _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 785:23]
-  wire  _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42]
+  wire  _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 779:6]
+  wire  _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 779:25]
+  wire  _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 779:23]
+  wire  _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 779:42]
   wire [31:0] _T_986 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_987 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_988 = _T_984 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72]
-  wire  _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68]
-  wire  _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 787:50]
-  wire  _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89]
-  wire  _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 787:87]
-  wire  _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 787:121]
-  wire  _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6]
-  wire  _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38]
-  wire  _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 789:50]
-  wire  _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 790:50]
+  wire  _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 781:68]
+  wire  _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 781:50]
+  wire  _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 781:89]
+  wire  _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 781:87]
+  wire  _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 781:121]
+  wire  _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 783:6]
+  wire  _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 783:38]
+  wire  _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 783:50]
+  wire  _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 784:50]
   wire [11:0] _T_1010 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
   wire [11:0] _T_1011 = _T_1001 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
   wire [11:0] _T_1012 = _T_1006 ? _T_1010 : 12'h0; // @[Mux.scala 27:72]
@@ -47113,7 +47113,7 @@ module dec_decode_ctl(
     .io_en(rvclkhdr_io_en),
     .io_scan_mode(rvclkhdr_io_scan_mode)
   );
-  dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 362:22]
+  dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 356:22]
     .io_ins(i0_dec_io_ins),
     .io_out_alu(i0_dec_io_out_alu),
     .io_out_rs1(i0_dec_io_out_rs1),
@@ -47280,116 +47280,116 @@ module dec_decode_ctl(
     .io_en(rvclkhdr_19_io_en),
     .io_scan_mode(rvclkhdr_19_io_scan_mode)
   );
-  assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 632:38]
-  assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 633:38]
-  assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 255:31]
-  assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 256:31]
-  assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 257:31]
-  assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 258:31]
-  assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 259:31]
-  assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 260:31]
-  assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 263:31]
-  assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 264:31]
-  assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 265:31]
-  assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 266:31]
-  assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 253:31]
-  assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 254:31]
-  assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 261:31]
-  assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 262:31]
-  assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 269:33]
-  assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 251:37]
-  assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 250:37]
-  assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 267:33]
-  assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 268:33]
-  assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 206:49]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 204:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 205:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 218:60]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 213:67]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 214:67]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 203:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 200:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 202:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 201:54]
-  assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 220:67]
-  assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 219:43]
-  assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 215:43]
-  assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 216:43]
-  assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35]
-  assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35]
-  assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32]
-  assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 777:42]
-  assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 782:42]
-  assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36]
-  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 773:45]
-  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 774:45]
-  assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32]
-  assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37]
-  assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37]
-  assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 400:37]
-  assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 734:36]
-  assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34]
-  assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34]
-  assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29]
-  assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 681:32]
-  assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29]
-  assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34]
-  assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34]
-  assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 700:37]
-  assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 723:22]
-  assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 726:20]
-  assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19]
-  assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19]
-  assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27]
-  assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 666:32]
-  assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26]
-  assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35]
-  assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29]
-  assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40]
-  assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 415:40]
-  assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 407:29 dec_decode_ctl.scala 416:40]
-  assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 406:29 dec_decode_ctl.scala 412:40]
-  assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 413:40]
-  assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40]
-  assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40]
-  assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40]
-  assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 711:19]
-  assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26]
-  assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 788:23]
-  assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24]
-  assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24]
-  assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24]
-  assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 441:20]
-  assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23]
-  assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24]
-  assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27]
-  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 548:29]
-  assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 582:39 dec_decode_ctl.scala 583:39]
-  assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 582:39]
-  assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 729:27]
-  assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 506:23]
-  assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 527:28]
-  assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 528:27]
-  assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 530:29]
-  assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 529:29]
-  assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 324:28]
-  assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29]
-  assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22]
-  assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25]
-  assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 705:21]
-  assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30]
+  assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 626:38]
+  assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 627:38]
+  assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 249:37]
+  assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 250:37]
+  assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 251:37]
+  assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 252:37]
+  assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 253:37]
+  assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 254:37]
+  assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 257:37]
+  assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 258:37]
+  assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 259:37]
+  assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 260:37]
+  assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 247:37]
+  assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 248:37]
+  assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 255:37]
+  assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 256:37]
+  assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 263:37]
+  assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 245:37]
+  assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 244:37]
+  assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 261:37]
+  assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 262:37]
+  assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 202:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 200:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 201:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 214:56]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 209:56]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 210:56]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 199:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 196:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 198:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 197:55]
+  assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 216:56]
+  assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 215:56]
+  assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 211:56]
+  assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 212:56]
+  assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 588:35]
+  assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 589:35]
+  assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 597:32]
+  assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 771:42]
+  assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 776:42]
+  assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 236:36]
+  assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 767:45]
+  assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 768:45]
+  assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 391:32]
+  assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 392:37]
+  assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 393:37]
+  assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 394:37]
+  assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 728:36]
+  assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 396:34]
+  assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 536:34]
+  assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 418:29]
+  assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 675:32]
+  assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 387:29]
+  assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 388:34]
+  assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 389:34]
+  assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 694:37]
+  assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 516:30 dec_decode_ctl.scala 582:30]
+  assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 717:22]
+  assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 720:20]
+  assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 591:19]
+  assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 592:19]
+  assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 658:27]
+  assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 660:32]
+  assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 661:26]
+  assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 403:24 dec_decode_ctl.scala 405:35]
+  assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 402:29]
+  assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 408:40]
+  assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 409:40]
+  assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 401:29 dec_decode_ctl.scala 410:40]
+  assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 400:29 dec_decode_ctl.scala 406:40]
+  assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 407:40]
+  assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 414:40]
+  assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 412:40]
+  assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 411:40]
+  assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 705:19]
+  assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 781:26]
+  assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 782:23]
+  assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 427:24]
+  assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 493:24]
+  assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 430:24]
+  assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 435:20]
+  assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 431:23]
+  assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 478:24]
+  assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 438:27]
+  assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 542:29]
+  assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 576:39 dec_decode_ctl.scala 577:39]
+  assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 576:39]
+  assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 723:27]
+  assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 500:23]
+  assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 521:28]
+  assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 522:27]
+  assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 524:29]
+  assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 523:29]
+  assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 318:28]
+  assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 315:29 dec_decode_ctl.scala 325:29]
+  assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 462:22]
+  assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 466:25]
+  assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 699:21]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
   assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 329:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
-  assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 363:16]
+  assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 357:16]
   assign rvclkhdr_1_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 355:17]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@@ -58233,6 +58233,9 @@ module dec(
   wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 118:22]
   wire [31:0] decode_io_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 118:22]
   wire  decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 118:22]
+  wire  decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22]
+  wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22]
+  wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22]
   wire  decode_io_dec_tlu_flush_extint; // @[dec.scala 118:22]
   wire  decode_io_dec_tlu_force_halt; // @[dec.scala 118:22]
   wire [31:0] decode_io_dec_i0_inst_wb1; // @[dec.scala 118:22]
@@ -58330,9 +58333,6 @@ module dec(
   wire  decode_io_dec_pause_state_cg; // @[dec.scala 118:22]
   wire  decode_io_dec_div_active; // @[dec.scala 118:22]
   wire  decode_io_scan_mode; // @[dec.scala 118:22]
-  wire  decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22]
-  wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22]
-  wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22]
   wire  gpr_clock; // @[dec.scala 119:19]
   wire  gpr_reset; // @[dec.scala 119:19]
   wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19]
@@ -58686,6 +58686,9 @@ module dec(
     .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag),
     .io_dctl_busbuff_lsu_nonblock_load_data(decode_io_dctl_busbuff_lsu_nonblock_load_data),
     .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any),
+    .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d),
+    .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst),
+    .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata),
     .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint),
     .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt),
     .io_dec_i0_inst_wb1(decode_io_dec_i0_inst_wb1),
@@ -58782,10 +58785,7 @@ module dec(
     .io_dec_pause_state(decode_io_dec_pause_state),
     .io_dec_pause_state_cg(decode_io_dec_pause_state_cg),
     .io_dec_div_active(decode_io_dec_div_active),
-    .io_scan_mode(decode_io_scan_mode),
-    .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d),
-    .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst),
-    .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata)
+    .io_scan_mode(decode_io_scan_mode)
   );
   dec_gpr_ctl gpr ( // @[dec.scala 119:19]
     .clock(gpr_clock),
@@ -59219,6 +59219,8 @@ module dec(
   assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 141:26]
   assign decode_io_dctl_busbuff_lsu_nonblock_load_data = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 141:26]
   assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 138:22]
+  assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21]
+  assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22]
   assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 139:48]
   assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 140:48]
   assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 142:48]
@@ -59267,8 +59269,6 @@ module dec(
   assign decode_io_active_clk = io_active_clk; // @[dec.scala 180:48]
   assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 181:48]
   assign decode_io_scan_mode = io_scan_mode; // @[dec.scala 182:48]
-  assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21]
-  assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22]
   assign gpr_clock = clock;
   assign gpr_reset = reset;
   assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 189:23]
@@ -59709,29 +59709,36 @@ module dbg(
   wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58]
   wire  _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100]
   wire  command_wren = _T_235 & _T_294; // @[dbg.scala 235:87]
-  wire [31:0] command_din = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20],3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
-  reg [31:0] command_reg; // @[Reg.scala 27:20]
+  wire [19:0] _T_298 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
+  wire [11:0] _T_300 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 352:23]
+  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23]
+  reg [31:0] command_reg; // @[lib.scala 358:16]
   wire  _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58]
   wire  data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89]
   wire  _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59]
   wire  _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46]
   wire  _T_310 = ~command_reg[16]; // @[dbg.scala 242:83]
   wire  data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81]
-  wire  data0_reg_wren = data0_reg_wren0 | data0_reg_wren1; // @[dbg.scala 244:40]
   wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45]
   wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
   wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92]
-  wire [31:0] data0_din = _T_313 | _T_316; // @[dbg.scala 245:64]
-  reg [31:0] data0_reg; // @[Reg.scala 27:20]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 352:23]
+  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23]
+  reg [31:0] data0_reg; // @[lib.scala 358:16]
   wire  _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77]
   wire  _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58]
   wire  data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89]
   wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 352:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 352:23]
+  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23]
   reg [31:0] _T_327; // @[lib.scala 358:16]
   wire [2:0] dbg_nxtstate;
   wire  _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30]
@@ -59779,30 +59786,30 @@ module dbg(
   wire  _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30]
   wire  _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30]
   wire  _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40]
-  wire  _GEN_13 = _T_433 & _T_436; // @[Conditional.scala 39:67]
-  wire  _GEN_14 = _T_433 & _T_356; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_15 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67]
-  wire  _GEN_16 = _T_424 | _GEN_13; // @[Conditional.scala 39:67]
-  wire  _GEN_17 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67]
-  wire  _GEN_19 = _T_424 ? _T_356 : _GEN_14; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_20 = _T_413 ? _T_415 : _GEN_15; // @[Conditional.scala 39:67]
-  wire  _GEN_21 = _T_413 ? _T_417 : _GEN_16; // @[Conditional.scala 39:67]
-  wire  _GEN_22 = _T_413 ? _T_356 : _GEN_19; // @[Conditional.scala 39:67]
-  wire  _GEN_23 = _T_413 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_25 = _T_396 ? _T_401 : _GEN_20; // @[Conditional.scala 39:67]
-  wire  _GEN_26 = _T_396 ? _T_406 : _GEN_21; // @[Conditional.scala 39:67]
-  wire  _GEN_27 = _T_396 ? _T_356 : _GEN_22; // @[Conditional.scala 39:67]
-  wire  _GEN_28 = _T_396 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_30 = _T_358 ? _T_370 : _GEN_25; // @[Conditional.scala 39:67]
-  wire  _GEN_31 = _T_358 ? _T_384 : _GEN_26; // @[Conditional.scala 39:67]
-  wire  _GEN_32 = _T_358 ? _T_386 : _GEN_28; // @[Conditional.scala 39:67]
-  wire  _GEN_34 = _T_358 & _T_388; // @[Conditional.scala 39:67]
-  wire  _GEN_35 = _T_358 ? _T_356 : _GEN_27; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_36 = _T_346 ? _T_348 : _GEN_30; // @[Conditional.scala 39:67]
-  wire  _GEN_37 = _T_346 ? _T_351 : _GEN_31; // @[Conditional.scala 39:67]
-  wire  _GEN_38 = _T_346 ? _T_356 : _GEN_35; // @[Conditional.scala 39:67]
+  wire  _GEN_11 = _T_433 & _T_436; // @[Conditional.scala 39:67]
+  wire  _GEN_12 = _T_433 & _T_356; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_13 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67]
+  wire  _GEN_14 = _T_424 | _GEN_11; // @[Conditional.scala 39:67]
+  wire  _GEN_15 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67]
+  wire  _GEN_17 = _T_424 ? _T_356 : _GEN_12; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_18 = _T_413 ? _T_415 : _GEN_13; // @[Conditional.scala 39:67]
+  wire  _GEN_19 = _T_413 ? _T_417 : _GEN_14; // @[Conditional.scala 39:67]
+  wire  _GEN_20 = _T_413 ? _T_356 : _GEN_17; // @[Conditional.scala 39:67]
+  wire  _GEN_21 = _T_413 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_23 = _T_396 ? _T_401 : _GEN_18; // @[Conditional.scala 39:67]
+  wire  _GEN_24 = _T_396 ? _T_406 : _GEN_19; // @[Conditional.scala 39:67]
+  wire  _GEN_25 = _T_396 ? _T_356 : _GEN_20; // @[Conditional.scala 39:67]
+  wire  _GEN_26 = _T_396 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_28 = _T_358 ? _T_370 : _GEN_23; // @[Conditional.scala 39:67]
+  wire  _GEN_29 = _T_358 ? _T_384 : _GEN_24; // @[Conditional.scala 39:67]
+  wire  _GEN_30 = _T_358 ? _T_386 : _GEN_26; // @[Conditional.scala 39:67]
+  wire  _GEN_32 = _T_358 & _T_388; // @[Conditional.scala 39:67]
+  wire  _GEN_33 = _T_358 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_34 = _T_346 ? _T_348 : _GEN_28; // @[Conditional.scala 39:67]
+  wire  _GEN_35 = _T_346 ? _T_351 : _GEN_29; // @[Conditional.scala 39:67]
+  wire  _GEN_36 = _T_346 ? _T_356 : _GEN_33; // @[Conditional.scala 39:67]
+  wire  _GEN_37 = _T_346 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
   wire  _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
-  wire  _GEN_41 = _T_346 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
   wire  _T_498 = _T_29 & reset; // @[dbg.scala 315:87]
   reg [2:0] _T_499; // @[Reg.scala 27:20]
   wire  _T_504 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62]
@@ -59819,8 +59826,8 @@ module dbg(
   wire  _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65]
   wire  _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38]
   wire  _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27]
-  wire [2:0] _GEN_118 = {{2'd0}, _T_543}; // @[dbg.scala 347:53]
-  wire [2:0] _T_545 = _GEN_118 & sbcs_reg[14:12]; // @[dbg.scala 347:53]
+  wire [2:0] _GEN_116 = {{2'd0}, _T_543}; // @[dbg.scala 347:53]
+  wire [2:0] _T_545 = _GEN_116 & sbcs_reg[14:12]; // @[dbg.scala 347:53]
   wire  _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
   wire  _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41]
   wire  _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40]
@@ -59842,39 +59849,39 @@ module dbg(
   wire  _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
   wire  _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39]
   wire  _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
-  wire  _GEN_53 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67]
-  wire  _GEN_55 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67]
-  wire  _GEN_56 = _T_575 & _T_574; // @[Conditional.scala 39:67]
-  wire  _GEN_58 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67]
-  wire  _GEN_60 = _T_575 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
-  wire  _GEN_62 = _T_572 ? _T_573 : _GEN_55; // @[Conditional.scala 39:67]
-  wire  _GEN_63 = _T_572 ? _T_574 : _GEN_56; // @[Conditional.scala 39:67]
+  wire  _GEN_51 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67]
+  wire  _GEN_54 = _T_575 & _T_574; // @[Conditional.scala 39:67]
+  wire  _GEN_56 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67]
+  wire  _GEN_58 = _T_575 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_572 ? _T_573 : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_61 = _T_572 ? _T_574 : _GEN_54; // @[Conditional.scala 39:67]
+  wire  _GEN_63 = _T_572 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67]
   wire  _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67]
-  wire  _GEN_67 = _T_572 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
-  wire  _GEN_69 = _T_570 ? _T_571 : _GEN_62; // @[Conditional.scala 39:67]
+  wire  _GEN_67 = _T_570 ? _T_571 : _GEN_60; // @[Conditional.scala 39:67]
+  wire  _GEN_68 = _T_570 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67]
   wire  _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
   wire  _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67]
-  wire  _GEN_74 = _T_570 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
-  wire  _GEN_76 = _T_568 ? _T_569 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  _GEN_74 = _T_568 ? _T_569 : _GEN_67; // @[Conditional.scala 39:67]
+  wire  _GEN_75 = _T_568 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
   wire  _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
   wire  _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
-  wire  _GEN_81 = _T_568 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
-  wire  _GEN_83 = _T_562 ? _T_567 : _GEN_76; // @[Conditional.scala 39:67]
+  wire  _GEN_81 = _T_562 ? _T_567 : _GEN_74; // @[Conditional.scala 39:67]
+  wire  _GEN_82 = _T_562 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
   wire  _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67]
   wire  _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
-  wire  _GEN_88 = _T_562 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
-  wire  _GEN_90 = _T_560 ? _T_561 : _GEN_83; // @[Conditional.scala 39:67]
+  wire  _GEN_88 = _T_560 ? _T_561 : _GEN_81; // @[Conditional.scala 39:67]
+  wire  _GEN_89 = _T_560 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67]
   wire  _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67]
   wire  _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67]
-  wire  _GEN_95 = _T_560 ? 1'h0 : _GEN_88; // @[Conditional.scala 39:67]
-  wire  _GEN_97 = _T_553 ? _T_550 : _GEN_90; // @[Conditional.scala 39:67]
-  wire  _GEN_98 = _T_553 ? _T_547 : _GEN_91; // @[Conditional.scala 39:67]
+  wire  _GEN_95 = _T_553 ? _T_550 : _GEN_88; // @[Conditional.scala 39:67]
+  wire  _GEN_96 = _T_553 ? _T_547 : _GEN_89; // @[Conditional.scala 39:67]
+  wire  _GEN_98 = _T_553 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67]
   wire  _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67]
-  wire  _GEN_102 = _T_553 ? 1'h0 : _GEN_95; // @[Conditional.scala 39:67]
-  wire  _GEN_104 = _T_546 ? _T_550 : _GEN_97; // @[Conditional.scala 39:67]
-  wire  _GEN_105 = _T_546 ? _T_547 : _GEN_98; // @[Conditional.scala 39:67]
+  wire  _GEN_102 = _T_546 ? _T_550 : _GEN_95; // @[Conditional.scala 39:67]
+  wire  _GEN_103 = _T_546 ? _T_547 : _GEN_96; // @[Conditional.scala 39:67]
+  wire  _GEN_105 = _T_546 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67]
   wire  _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67]
-  wire  _GEN_109 = _T_546 ? 1'h0 : _GEN_102; // @[Conditional.scala 39:67]
   reg [3:0] _T_582; // @[Reg.scala 27:20]
   wire  _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69]
   wire  _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39]
@@ -59899,37 +59906,37 @@ module dbg(
   wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119]
   wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82]
-  wire [14:0] _GEN_119 = {{7'd0}, _T_643}; // @[dbg.scala 422:67]
-  wire [14:0] _T_646 = _GEN_119 & _T_645; // @[dbg.scala 422:67]
+  wire [14:0] _GEN_117 = {{7'd0}, _T_643}; // @[dbg.scala 422:67]
+  wire [14:0] _T_646 = _GEN_117 & _T_645; // @[dbg.scala 422:67]
   wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58]
   wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59]
-  wire [14:0] _GEN_120 = {{7'd0}, _T_650}; // @[dbg.scala 423:44]
-  wire [14:0] _T_654 = _GEN_120 & _T_653; // @[dbg.scala 423:44]
+  wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 423:44]
+  wire [14:0] _T_654 = _GEN_118 & _T_653; // @[dbg.scala 423:44]
   wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107]
   wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58]
   wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59]
-  wire [10:0] _GEN_121 = {{3'd0}, _T_659}; // @[dbg.scala 424:44]
-  wire [10:0] _T_663 = _GEN_121 & _T_662; // @[dbg.scala 424:44]
-  wire [14:0] _GEN_122 = {{4'd0}, _T_663}; // @[dbg.scala 423:97]
-  wire [14:0] _T_664 = _T_655 | _GEN_122; // @[dbg.scala 423:97]
+  wire [10:0] _GEN_119 = {{3'd0}, _T_659}; // @[dbg.scala 424:44]
+  wire [10:0] _T_663 = _GEN_119 & _T_662; // @[dbg.scala 424:44]
+  wire [14:0] _GEN_120 = {{4'd0}, _T_663}; // @[dbg.scala 423:97]
+  wire [14:0] _T_664 = _T_655 | _GEN_120; // @[dbg.scala 423:97]
   wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [14:0] _GEN_123 = {{7'd0}, _T_668}; // @[dbg.scala 424:95]
-  wire [14:0] _T_670 = _T_664 | _GEN_123; // @[dbg.scala 424:95]
-  wire [3:0] _GEN_124 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99]
-  wire [6:0] _T_681 = 4'h8 * _GEN_124; // @[dbg.scala 441:99]
+  wire [14:0] _GEN_121 = {{7'd0}, _T_668}; // @[dbg.scala 424:95]
+  wire [14:0] _T_670 = _T_664 | _GEN_121; // @[dbg.scala 424:95]
+  wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99]
+  wire [6:0] _T_681 = 4'h8 * _GEN_122; // @[dbg.scala 441:99]
   wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92]
   wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123]
   wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59]
-  wire [4:0] _GEN_125 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86]
-  wire [6:0] _T_691 = 5'h10 * _GEN_125; // @[dbg.scala 442:86]
+  wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86]
+  wire [6:0] _T_691 = 5'h10 * _GEN_123; // @[dbg.scala 442:86]
   wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78]
   wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110]
   wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45]
   wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140]
-  wire [5:0] _GEN_126 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86]
-  wire [6:0] _T_702 = 6'h20 * _GEN_126; // @[dbg.scala 443:86]
+  wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86]
+  wire [6:0] _T_702 = 6'h20 * _GEN_124; // @[dbg.scala 443:86]
   wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78]
   wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107]
   wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45]
@@ -59971,10 +59978,22 @@ module dbg(
     .io_en(rvclkhdr_5_io_en),
     .io_scan_mode(rvclkhdr_5_io_scan_mode)
   );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:23]
+    .io_l1clk(rvclkhdr_6_io_l1clk),
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en),
+    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:23]
+    .io_l1clk(rvclkhdr_7_io_l1clk),
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en),
+    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+  );
   assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19]
   assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21]
-  assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_38; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23]
-  assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_41; // @[dbg.scala 262:21 dbg.scala 282:25]
+  assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_36; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23]
+  assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 262:21 dbg.scala 282:25]
   assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22]
   assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26]
   assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28]
@@ -60000,22 +60019,22 @@ module dbg(
   assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39]
   assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32]
   assign dbg_state = _T_499; // @[dbg.scala 315:13]
-  assign dbg_state_en = _T_328 ? _T_340 : _GEN_37; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20]
+  assign dbg_state_en = _T_328 ? _T_340 : _GEN_35; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20]
   assign sb_state = _T_582; // @[dbg.scala 397:12]
-  assign sb_state_en = _T_535 ? _T_538 : _GEN_104; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19]
+  assign sb_state_en = _T_535 ? _T_538 : _GEN_102; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19]
   assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17]
   assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18]
-  assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_107; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24]
-  assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_105; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25]
+  assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_105; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24]
+  assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_103; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25]
   assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16]
-  assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_109; // @[dbg.scala 339:24 dbg.scala 394:28]
+  assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_107; // @[dbg.scala 339:24 dbg.scala 394:28]
   assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16]
   assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22]
   assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22]
   assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20]
   assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20]
   assign dmstatus_halted = _T_206; // @[dbg.scala 197:19]
-  assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28]
+  assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_37; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28]
   assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19]
   assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25]
   assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25]
@@ -60042,9 +60061,15 @@ module dbg(
   assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
   assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18]
   assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_5_io_en = _T_321 & _T_294; // @[lib.scala 355:17]
+  assign rvclkhdr_5_io_en = _T_235 & _T_294; // @[lib.scala 355:17]
   assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_36; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18]
+  assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17]
+  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18]
+  assign rvclkhdr_7_io_en = _T_321 & _T_294; // @[lib.scala 355:17]
+  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
+  assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_34; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -60338,21 +60363,21 @@ end // initial
       abs_temp_10_8 <= _T_276 | _T_281;
     end
   end
-  always @(posedge clock or posedge _T_30) begin
+  always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin
     if (_T_30) begin
       command_reg <= 32'h0;
-    end else if (command_wren) begin
-      command_reg <= command_din;
+    end else begin
+      command_reg <= {_T_300,_T_298};
     end
   end
-  always @(posedge clock or posedge _T_30) begin
+  always @(posedge rvclkhdr_6_io_l1clk or posedge _T_30) begin
     if (_T_30) begin
       data0_reg <= 32'h0;
-    end else if (data0_reg_wren) begin
-      data0_reg <= data0_din;
+    end else begin
+      data0_reg <= _T_313 | _T_316;
     end
   end
-  always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin
+  always @(posedge rvclkhdr_7_io_l1clk or posedge _T_30) begin
     if (_T_30) begin
       _T_327 <= 32'h0;
     end else begin
@@ -60666,16 +60691,16 @@ module exu_alu_ctl(
   wire  _T_300 = ~io_flush_upper_x; // @[exu_alu_ctl.scala 111:119]
   wire  _T_301 = _T_299 & _T_300; // @[exu_alu_ctl.scala 111:117]
   wire  _T_302 = ~io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 111:141]
-  wire  _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 117:44]
-  wire  _T_314 = ~io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 117:73]
-  wire  _T_315 = _T_314 & actual_taken; // @[exu_alu_ctl.scala 117:96]
-  wire  _T_316 = _T_312 | _T_315; // @[exu_alu_ctl.scala 117:70]
-  wire  _T_318 = ~io_pp_in_bits_hist[1]; // @[exu_alu_ctl.scala 118:6]
-  wire  _T_320 = _T_318 & _T_279; // @[exu_alu_ctl.scala 118:29]
-  wire  _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[exu_alu_ctl.scala 118:72]
-  wire  _T_323 = _T_320 | _T_322; // @[exu_alu_ctl.scala 118:47]
-  wire  _T_327 = _T_300 & _T_302; // @[exu_alu_ctl.scala 121:56]
-  wire  _T_328 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 121:103]
+  wire  _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 116:44]
+  wire  _T_314 = ~io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 116:73]
+  wire  _T_315 = _T_314 & actual_taken; // @[exu_alu_ctl.scala 116:96]
+  wire  _T_316 = _T_312 | _T_315; // @[exu_alu_ctl.scala 116:70]
+  wire  _T_318 = ~io_pp_in_bits_hist[1]; // @[exu_alu_ctl.scala 117:6]
+  wire  _T_320 = _T_318 & _T_279; // @[exu_alu_ctl.scala 117:29]
+  wire  _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[exu_alu_ctl.scala 117:72]
+  wire  _T_323 = _T_320 | _T_322; // @[exu_alu_ctl.scala 117:47]
+  wire  _T_327 = _T_300 & _T_302; // @[exu_alu_ctl.scala 120:56]
+  wire  _T_328 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 120:103]
   rvclkhdr rvclkhdr ( // @[lib.scala 352:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -60691,22 +60716,22 @@ module exu_alu_ctl(
   assign io_dec_alu_exu_i0_pc_x = _T_1; // @[exu_alu_ctl.scala 30:26]
   assign io_result_ff = _T_3; // @[exu_alu_ctl.scala 32:16]
   assign io_flush_upper_out = _T_301 & _T_302; // @[exu_alu_ctl.scala 111:26]
-  assign io_flush_final_out = _T_301 | io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 113:26]
+  assign io_flush_final_out = _T_301 | io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 112:26]
   assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[exu_alu_ctl.scala 103:22]
   assign io_pred_correct_out = _T_282 | _T_286; // @[exu_alu_ctl.scala 101:26]
-  assign io_predict_p_out_valid = io_pp_in_valid; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[exu_alu_ctl.scala 120:30 exu_alu_ctl.scala 121:35]
-  assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[exu_alu_ctl.scala 120:30 exu_alu_ctl.scala 122:35]
-  assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[exu_alu_ctl.scala 120:30 exu_alu_ctl.scala 123:35]
-  assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 120:30]
-  assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 120:30]
+  assign io_predict_p_out_valid = io_pp_in_valid; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[exu_alu_ctl.scala 119:30 exu_alu_ctl.scala 120:35]
+  assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[exu_alu_ctl.scala 119:30 exu_alu_ctl.scala 121:35]
+  assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[exu_alu_ctl.scala 119:30 exu_alu_ctl.scala 122:35]
+  assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 119:30]
+  assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 119:30]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_io_en = io_enable; // @[lib.scala 355:17]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@@ -78633,18 +78658,18 @@ module dma_ctrl(
   wire  rvclkhdr_9_io_clk; // @[lib.scala 352:23]
   wire  rvclkhdr_9_io_en; // @[lib.scala 352:23]
   wire  rvclkhdr_9_io_scan_mode; // @[lib.scala 352:23]
-  wire  dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 385:32]
-  wire  dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 385:32]
-  wire  dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 385:32]
-  wire  dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 385:32]
-  wire  dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 391:28]
-  wire  dma_free_cgc_io_clk; // @[dma_ctrl.scala 391:28]
-  wire  dma_free_cgc_io_en; // @[dma_ctrl.scala 391:28]
-  wire  dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 391:28]
-  wire  dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 397:27]
-  wire  dma_bus_cgc_io_clk; // @[dma_ctrl.scala 397:27]
-  wire  dma_bus_cgc_io_en; // @[dma_ctrl.scala 397:27]
-  wire  dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 397:27]
+  wire  dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 389:32]
+  wire  dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 389:32]
+  wire  dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 389:32]
+  wire  dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 389:32]
+  wire  dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 395:28]
+  wire  dma_free_cgc_io_clk; // @[dma_ctrl.scala 395:28]
+  wire  dma_free_cgc_io_en; // @[dma_ctrl.scala 395:28]
+  wire  dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 395:28]
+  wire  dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 401:27]
+  wire  dma_bus_cgc_io_clk; // @[dma_ctrl.scala 401:27]
+  wire  dma_bus_cgc_io_en; // @[dma_ctrl.scala 401:27]
+  wire  dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 401:27]
   wire  rvclkhdr_10_io_l1clk; // @[lib.scala 352:23]
   wire  rvclkhdr_10_io_clk; // @[lib.scala 352:23]
   wire  rvclkhdr_10_io_en; // @[lib.scala 352:23]
@@ -78657,31 +78682,31 @@ module dma_ctrl(
   wire  rvclkhdr_12_io_clk; // @[lib.scala 352:23]
   wire  rvclkhdr_12_io_en; // @[lib.scala 352:23]
   wire  rvclkhdr_12_io_scan_mode; // @[lib.scala 352:23]
-  wire  dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 395:29]
+  wire  dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 399:29]
   reg [2:0] RdPtr; // @[Reg.scala 27:20]
   reg [31:0] fifo_addr_4; // @[lib.scala 358:16]
   reg [31:0] fifo_addr_3; // @[lib.scala 358:16]
   reg [31:0] fifo_addr_2; // @[lib.scala 358:16]
   reg [31:0] fifo_addr_1; // @[lib.scala 358:16]
   reg [31:0] fifo_addr_0; // @[lib.scala 358:16]
-  wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 351:20]
-  wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 351:20]
-  wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 351:20]
-  wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 351:20]
+  wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 355:20]
+  wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 355:20]
+  wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 355:20]
+  wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 355:20]
   wire  dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 345:39]
   wire  dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 345:39]
   wire  dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 345:39]
-  wire  dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 401:28]
-  reg  wrbuf_vld; // @[dma_ctrl.scala 411:59]
-  reg  wrbuf_data_vld; // @[dma_ctrl.scala 413:59]
-  wire  _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 469:43]
-  reg  rdbuf_vld; // @[dma_ctrl.scala 437:47]
-  wire  _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 469:60]
+  wire  dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28]
+  reg  wrbuf_vld; // @[dma_ctrl.scala 415:59]
+  reg  wrbuf_data_vld; // @[dma_ctrl.scala 417:59]
+  wire  _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43]
+  reg  rdbuf_vld; // @[dma_ctrl.scala 441:47]
+  wire  _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60]
   reg  axi_mstr_priority; // @[Reg.scala 27:20]
-  wire  axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 469:31]
+  wire  axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31]
   reg [31:0] wrbuf_addr; // @[lib.scala 358:16]
   reg [31:0] rdbuf_addr; // @[lib.scala 358:16]
-  wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 459:43]
+  wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43]
   wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91]
   wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91]
   wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83]
@@ -78690,15 +78715,15 @@ module dma_ctrl(
   wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
   reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
   reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
-  wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 460:45]
+  wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45]
   wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33]
   wire  fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33]
-  wire  bus_cmd_valid = _T_1240 | rdbuf_vld; // @[dma_ctrl.scala 455:69]
-  reg  fifo_full; // @[dma_ctrl.scala 369:12]
-  reg  dbg_dma_bubble_bus; // @[dma_ctrl.scala 373:12]
+  wire  bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69]
+  reg  fifo_full; // @[dma_ctrl.scala 373:12]
+  reg  dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12]
   wire  _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39]
   wire  dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27]
-  wire  axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 456:54]
+  wire  axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54]
   wire  _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80]
   wire  _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136]
   wire  _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101]
@@ -78735,7 +78760,7 @@ module dma_ctrl(
   wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58]
   wire  _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48]
   wire  _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46]
-  wire  dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 389:33]
+  wire  dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 393:33]
   reg  _T_886; // @[Reg.scala 27:20]
   reg  _T_884; // @[Reg.scala 27:20]
   reg  _T_882; // @[Reg.scala 27:20]
@@ -78755,10 +78780,10 @@ module dma_ctrl(
   reg [2:0] fifo_sz_2; // @[Reg.scala 27:20]
   reg [2:0] fifo_sz_1; // @[Reg.scala 27:20]
   reg [2:0] fifo_sz_0; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 352:20]
-  wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 352:20]
-  wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 352:20]
-  wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 352:20]
+  wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 356:20]
+  wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 356:20]
+  wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 356:20]
+  wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 356:20]
   wire  _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 305:28]
   wire  _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 305:37]
   wire  _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 306:29]
@@ -78785,33 +78810,48 @@ module dma_ctrl(
   reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20]
   reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20]
   reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20]
-  wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 355:20]
-  wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 355:20]
-  wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 355:20]
-  wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 355:20]
-  wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
+  wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 359:20]
+  wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 359:20]
+  wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 359:20]
+  wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 359:20]
+  wire [3:0] _T_1071 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
   wire  _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 311:32]
-  wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72]
+  wire [3:0] _T_1072 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1079 = _T_1071 | _T_1072; // @[Mux.scala 27:72]
   wire  _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 312:32]
-  wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72]
+  wire [3:0] _T_1073 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1080 = _T_1079 | _T_1073; // @[Mux.scala 27:72]
   wire  _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 313:32]
-  wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72]
-  wire  _T_1067 = _T_1065 != 4'hf; // @[dma_ctrl.scala 313:68]
-  wire  _T_1068 = _T_1046 & _T_1067; // @[dma_ctrl.scala 310:78]
-  wire  _T_1069 = _T_1043 | _T_1068; // @[dma_ctrl.scala 309:145]
-  wire  _T_1072 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 314:45]
-  wire  _T_1074 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 314:103]
-  wire  _T_1076 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 314:139]
-  wire  _T_1077 = _T_1074 | _T_1076; // @[dma_ctrl.scala 314:116]
-  wire  _T_1079 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 314:175]
-  wire  _T_1080 = _T_1077 | _T_1079; // @[dma_ctrl.scala 314:152]
-  wire  _T_1081 = ~_T_1080; // @[dma_ctrl.scala 314:80]
-  wire  _T_1082 = _T_1072 & _T_1081; // @[dma_ctrl.scala 314:78]
-  wire  _T_1083 = _T_1069 | _T_1082; // @[dma_ctrl.scala 313:79]
-  wire  dma_alignment_error = _T_1010 & _T_1083; // @[dma_ctrl.scala 304:87]
+  wire [3:0] _T_1074 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1081 = _T_1080 | _T_1074; // @[Mux.scala 27:72]
+  wire  _T_1060 = dma_mem_addr_int[2:0] == 3'h4; // @[dma_ctrl.scala 314:32]
+  wire [3:0] _T_1075 = _T_1060 ? dma_mem_byteen[7:4] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1082 = _T_1081 | _T_1075; // @[Mux.scala 27:72]
+  wire  _T_1063 = dma_mem_addr_int[2:0] == 3'h5; // @[dma_ctrl.scala 315:32]
+  wire [2:0] _T_1076 = _T_1063 ? dma_mem_byteen[7:5] : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_91 = {{1'd0}, _T_1076}; // @[Mux.scala 27:72]
+  wire [3:0] _T_1083 = _T_1082 | _GEN_91; // @[Mux.scala 27:72]
+  wire  _T_1066 = dma_mem_addr_int[2:0] == 3'h6; // @[dma_ctrl.scala 316:32]
+  wire [1:0] _T_1077 = _T_1066 ? dma_mem_byteen[7:6] : 2'h0; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_92 = {{2'd0}, _T_1077}; // @[Mux.scala 27:72]
+  wire [3:0] _T_1084 = _T_1083 | _GEN_92; // @[Mux.scala 27:72]
+  wire  _T_1069 = dma_mem_addr_int[2:0] == 3'h7; // @[dma_ctrl.scala 317:32]
+  wire  _T_1078 = _T_1069 & dma_mem_byteen[7]; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_93 = {{3'd0}, _T_1078}; // @[Mux.scala 27:72]
+  wire [3:0] _T_1085 = _T_1084 | _GEN_93; // @[Mux.scala 27:72]
+  wire  _T_1087 = _T_1085 != 4'hf; // @[dma_ctrl.scala 317:66]
+  wire  _T_1088 = _T_1046 & _T_1087; // @[dma_ctrl.scala 310:78]
+  wire  _T_1089 = _T_1043 | _T_1088; // @[dma_ctrl.scala 309:145]
+  wire  _T_1092 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 318:45]
+  wire  _T_1094 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 318:103]
+  wire  _T_1096 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 318:139]
+  wire  _T_1097 = _T_1094 | _T_1096; // @[dma_ctrl.scala 318:116]
+  wire  _T_1099 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 318:175]
+  wire  _T_1100 = _T_1097 | _T_1099; // @[dma_ctrl.scala 318:152]
+  wire  _T_1101 = ~_T_1100; // @[dma_ctrl.scala 318:80]
+  wire  _T_1102 = _T_1092 & _T_1101; // @[dma_ctrl.scala 318:78]
+  wire  _T_1103 = _T_1089 | _T_1102; // @[dma_ctrl.scala 317:79]
+  wire  dma_alignment_error = _T_1010 & _T_1103; // @[dma_ctrl.scala 304:87]
   wire  _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 208:258]
   wire  _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 208:288]
   wire  _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 208:281]
@@ -78872,12 +78912,12 @@ module dma_ctrl(
   wire  _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 210:174]
   wire  _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 210:174]
   wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58]
-  wire  _T_1107 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 324:66]
-  wire  _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 324:134]
-  wire  _T_1110 = ~_T_1109; // @[dma_ctrl.scala 324:88]
-  wire  _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 324:191]
-  wire  _T_1114 = _T_1110 | _T_1113; // @[dma_ctrl.scala 324:167]
-  wire  dma_dbg_cmd_error = _T_1107 & _T_1114; // @[dma_ctrl.scala 324:84]
+  wire  _T_1127 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 328:66]
+  wire  _T_1129 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:134]
+  wire  _T_1130 = ~_T_1129; // @[dma_ctrl.scala 328:88]
+  wire  _T_1133 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 328:191]
+  wire  _T_1134 = _T_1130 | _T_1133; // @[dma_ctrl.scala 328:167]
+  wire  dma_dbg_cmd_error = _T_1127 & _T_1134; // @[dma_ctrl.scala 328:84]
   wire  _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 212:114]
   wire  _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 212:135]
   wire  _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 212:198]
@@ -78973,9 +79013,9 @@ module dma_ctrl(
   wire  _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75]
   wire  _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91]
   wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
-  wire  _T_1265 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 498:61]
-  wire  _T_1266 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 498:105]
-  wire  bus_rsp_sent = _T_1265 | _T_1266; // @[dma_ctrl.scala 498:83]
+  wire  _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61]
+  wire  _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105]
+  wire  bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83]
   wire  _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99]
   wire  _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120]
   reg [2:0] RspPtr; // @[Reg.scala 27:20]
@@ -79060,7 +79100,7 @@ module dma_ctrl(
   reg  fifo_tag_0; // @[Reg.scala 27:20]
   reg  wrbuf_tag; // @[Reg.scala 27:20]
   reg  rdbuf_tag; // @[Reg.scala 27:20]
-  wire  bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 463:43]
+  wire  bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43]
   reg  fifo_tag_1; // @[Reg.scala 27:20]
   reg  fifo_tag_2; // @[Reg.scala 27:20]
   reg  fifo_tag_3; // @[Reg.scala 27:20]
@@ -79074,6 +79114,9 @@ module dma_ctrl(
   wire  WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30]
   wire  RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93]
   wire  RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39]
+  wire [3:0] _T_959 = {3'h0,axi_mstr_prty_en}; // @[Cat.scala 29:58]
+  wire [3:0] _T_961 = {3'h0,bus_rsp_sent}; // @[Cat.scala 29:58]
+  wire [3:0] num_fifo_vld_tmp = _T_959 - _T_961; // @[dma_ctrl.scala 291:62]
   wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
   wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
   wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
@@ -79083,91 +79126,92 @@ module dma_ctrl(
   wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102]
   wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102]
   wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102]
-  wire  _T_1123 = |fifo_valid; // @[dma_ctrl.scala 334:30]
-  wire  fifo_empty = ~_T_1123; // @[dma_ctrl.scala 334:17]
-  wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 320:39]
-  wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 320:58]
-  wire  _T_1090 = _T_1086[0] & _T_1088[0]; // @[dma_ctrl.scala 320:48]
-  wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[dma_ctrl.scala 320:78]
-  wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 321:49]
-  wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 321:49]
-  wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 321:49]
-  wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 321:49]
-  wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 321:71]
-  wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 321:71]
-  wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 321:71]
-  wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 321:71]
-  wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 322:47]
-  wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 322:47]
-  wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 322:47]
-  wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 322:47]
-  wire  _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:80]
-  wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 347:54]
-  wire  _T_1147 = ~_T_1145[0]; // @[dma_ctrl.scala 347:43]
-  wire  _T_1148 = _T_990[0] & _T_1147; // @[dma_ctrl.scala 347:41]
-  wire  _T_1152 = _T_1148 & _T_994; // @[dma_ctrl.scala 347:62]
-  wire  _T_1155 = ~_T_197; // @[dma_ctrl.scala 347:84]
-  wire  dma_mem_req = _T_1152 & _T_1155; // @[dma_ctrl.scala 347:82]
-  wire  _T_1117 = dma_mem_req & _T_1116; // @[dma_ctrl.scala 328:56]
+  wire [3:0] num_fifo_vld = num_fifo_vld_tmp + num_fifo_vld_tmp2; // @[dma_ctrl.scala 295:45]
+  wire  _T_1143 = |fifo_valid; // @[dma_ctrl.scala 338:30]
+  wire  fifo_empty = ~_T_1143; // @[dma_ctrl.scala 338:17]
+  wire [4:0] _T_1106 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 324:39]
+  wire [4:0] _T_1108 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 324:58]
+  wire  _T_1110 = _T_1106[0] & _T_1108[0]; // @[dma_ctrl.scala 324:48]
+  wire [4:0] _T_1111 = fifo_done >> RspPtr; // @[dma_ctrl.scala 324:78]
+  wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 325:49]
+  wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 325:49]
+  wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 325:49]
+  wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 325:49]
+  wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 325:71]
+  wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 325:71]
+  wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 325:71]
+  wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 325:71]
+  wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 326:47]
+  wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 326:47]
+  wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 326:47]
+  wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 326:47]
+  wire  _T_1136 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 332:80]
+  wire [4:0] _T_1165 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 351:54]
+  wire  _T_1167 = ~_T_1165[0]; // @[dma_ctrl.scala 351:43]
+  wire  _T_1168 = _T_990[0] & _T_1167; // @[dma_ctrl.scala 351:41]
+  wire  _T_1172 = _T_1168 & _T_994; // @[dma_ctrl.scala 351:62]
+  wire  _T_1175 = ~_T_197; // @[dma_ctrl.scala 351:84]
+  wire  dma_mem_req = _T_1172 & _T_1175; // @[dma_ctrl.scala 351:82]
+  wire  _T_1137 = dma_mem_req & _T_1136; // @[dma_ctrl.scala 332:56]
   reg [2:0] dma_nack_count; // @[Reg.scala 27:20]
-  wire  _T_1118 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 328:121]
-  wire  _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 329:56]
-  wire  _T_1127 = ~_T_165; // @[dma_ctrl.scala 339:77]
-  wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[dma_ctrl.scala 339:155]
-  wire  _T_1135 = dma_mem_req & _T_1127; // @[dma_ctrl.scala 339:203]
-  wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 339:304]
-  wire  _T_1164 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1076; // @[dma_ctrl.scala 353:84]
-  wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
-  wire  _T_1176 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1077; // @[dma_ctrl.scala 354:84]
-  wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[dma_ctrl.scala 356:53]
-  wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 357:40]
-  wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 357:40]
-  wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 357:40]
-  reg  dma_dbg_cmd_done_q; // @[dma_ctrl.scala 377:12]
-  wire  _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 382:44]
-  wire  _T_1193 = _T_1192 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 382:65]
-  wire  bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 497:60]
-  wire  _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 383:44]
-  wire  _T_1195 = _T_1194 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 383:60]
-  wire  _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 383:94]
-  wire  _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 383:116]
-  wire  _T_1199 = _T_1197 | _T_1123; // @[dma_ctrl.scala 383:137]
-  wire  wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 405:47]
-  wire  wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 406:46]
-  wire  wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 407:40]
-  wire  _T_1201 = ~wrbuf_en; // @[dma_ctrl.scala 408:51]
-  wire  wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[dma_ctrl.scala 408:49]
-  wire  _T_1203 = ~wrbuf_data_en; // @[dma_ctrl.scala 409:51]
-  wire  wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[dma_ctrl.scala 409:49]
-  wire  _T_1204 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 411:63]
-  wire  _T_1205 = ~wrbuf_rst; // @[dma_ctrl.scala 411:92]
-  wire  _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 413:63]
-  wire  _T_1209 = ~wrbuf_data_rst; // @[dma_ctrl.scala 413:102]
-  wire  rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 433:59]
-  wire  _T_1214 = ~axi_mstr_sel; // @[dma_ctrl.scala 434:44]
-  wire  rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[dma_ctrl.scala 434:42]
-  wire  _T_1216 = ~rdbuf_en; // @[dma_ctrl.scala 435:63]
-  wire  rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[dma_ctrl.scala 435:61]
-  wire  _T_1217 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 437:51]
-  wire  _T_1218 = ~rdbuf_rst; // @[dma_ctrl.scala 437:80]
-  wire  _T_1222 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 449:44]
-  wire  _T_1223 = wrbuf_vld & _T_1222; // @[dma_ctrl.scala 449:42]
-  wire  _T_1226 = wrbuf_data_vld & _T_1222; // @[dma_ctrl.scala 450:47]
-  wire  _T_1228 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 451:44]
-  wire  _T_1229 = rdbuf_vld & _T_1228; // @[dma_ctrl.scala 451:42]
-  wire  axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 470:27]
-  wire  _T_1251 = ~_T_1088[0]; // @[dma_ctrl.scala 477:50]
-  wire  _T_1252 = _T_1086[0] & _T_1251; // @[dma_ctrl.scala 477:48]
-  wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 477:83]
-  wire  axi_rsp_valid = _T_1252 & _T_1253[0]; // @[dma_ctrl.scala 477:68]
-  wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[dma_ctrl.scala 479:39]
-  wire  axi_rsp_write = _T_1255[0]; // @[dma_ctrl.scala 479:39]
-  wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 480:64]
-  wire  _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 488:33]
-  wire  _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 488:33]
-  wire  _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 488:33]
-  wire  _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 490:46]
+  wire  _T_1138 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 332:121]
+  wire  _T_1140 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 333:56]
+  wire  _T_1147 = ~_T_165; // @[dma_ctrl.scala 343:77]
+  wire [2:0] _T_1149 = _T_1147 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_1151 = _T_1149 & dma_nack_count; // @[dma_ctrl.scala 343:155]
+  wire  _T_1155 = dma_mem_req & _T_1147; // @[dma_ctrl.scala 343:203]
+  wire [2:0] _T_1158 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 343:304]
+  wire  _T_1184 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1096; // @[dma_ctrl.scala 357:84]
+  wire [31:0] _T_1188 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_1196 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1097; // @[dma_ctrl.scala 358:84]
+  wire [4:0] _T_1199 = fifo_write >> RdPtr; // @[dma_ctrl.scala 360:53]
+  wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 361:40]
+  wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40]
+  wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40]
+  reg  dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12]
+  wire  _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44]
+  wire  _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65]
+  wire  bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60]
+  wire  _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44]
+  wire  _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60]
+  wire  _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94]
+  wire  _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116]
+  wire  _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137]
+  wire  wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47]
+  wire  wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46]
+  wire  wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40]
+  wire  _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51]
+  wire  wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49]
+  wire  _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51]
+  wire  wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49]
+  wire  _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63]
+  wire  _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92]
+  wire  _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63]
+  wire  _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102]
+  wire  rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59]
+  wire  _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44]
+  wire  rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42]
+  wire  _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63]
+  wire  rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61]
+  wire  _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51]
+  wire  _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80]
+  wire  _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44]
+  wire  _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42]
+  wire  _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47]
+  wire  _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44]
+  wire  _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42]
+  wire  axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27]
+  wire  _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50]
+  wire  _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48]
+  wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83]
+  wire  axi_rsp_valid = _T_1272 & _T_1273[0]; // @[dma_ctrl.scala 481:68]
+  wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39]
+  wire  axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39]
+  wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64]
+  wire  _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33]
+  wire  _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33]
+  wire  _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33]
+  wire  _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46]
   rvclkhdr rvclkhdr ( // @[lib.scala 352:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -79228,19 +79272,19 @@ module dma_ctrl(
     .io_en(rvclkhdr_9_io_en),
     .io_scan_mode(rvclkhdr_9_io_scan_mode)
   );
-  rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 385:32]
+  rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 389:32]
     .io_l1clk(dma_buffer_c1cgc_io_l1clk),
     .io_clk(dma_buffer_c1cgc_io_clk),
     .io_en(dma_buffer_c1cgc_io_en),
     .io_scan_mode(dma_buffer_c1cgc_io_scan_mode)
   );
-  rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 391:28]
+  rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 395:28]
     .io_l1clk(dma_free_cgc_io_l1clk),
     .io_clk(dma_free_cgc_io_clk),
     .io_en(dma_free_cgc_io_en),
     .io_scan_mode(dma_free_cgc_io_scan_mode)
   );
-  rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 397:27]
+  rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 401:27]
     .io_l1clk(dma_bus_cgc_io_l1clk),
     .io_clk(dma_bus_cgc_io_clk),
     .io_en(dma_bus_cgc_io_en),
@@ -79264,42 +79308,42 @@ module dma_ctrl(
     .io_en(rvclkhdr_12_io_en),
     .io_scan_mode(rvclkhdr_12_io_scan_mode)
   );
-  assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 321:25]
-  assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[dma_ctrl.scala 320:25]
-  assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 322:25]
-  assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 319:36]
-  assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 331:42]
-  assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 361:42]
-  assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 362:42]
-  assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 363:42]
-  assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 364:42]
-  assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1117 & _T_1118; // @[dma_ctrl.scala 328:41]
-  assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 330:41]
-  assign io_dma_axi_aw_ready = ~_T_1223; // @[dma_ctrl.scala 449:27]
-  assign io_dma_axi_w_ready = ~_T_1226; // @[dma_ctrl.scala 450:27]
-  assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 486:27]
-  assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 487:41]
-  assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 488:33]
-  assign io_dma_axi_ar_ready = ~_T_1229; // @[dma_ctrl.scala 451:27]
-  assign io_dma_axi_r_valid = axi_rsp_valid & _T_1261; // @[dma_ctrl.scala 490:27]
-  assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 494:37]
-  assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 492:43]
-  assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 491:41]
-  assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1117 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 348:40]
-  assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[dma_ctrl.scala 353:40]
-  assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 354:40]
-  assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1179[0]; // @[dma_ctrl.scala 356:40]
-  assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 357:40]
-  assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 499:40]
-  assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 500:41]
-  assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 350:28]
-  assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1120 & _T_1118; // @[dma_ctrl.scala 329:41]
-  assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1120 & io_iccm_ready; // @[dma_ctrl.scala 349:40]
-  assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 502:39]
-  assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 501:37]
-  assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 504:40]
-  assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 503:40]
-  assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 505:38]
+  assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 325:25]
+  assign io_dma_dbg_cmd_done = _T_1110 & _T_1111[0]; // @[dma_ctrl.scala 324:25]
+  assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 326:25]
+  assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 323:36]
+  assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 335:42]
+  assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 365:42]
+  assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 366:42]
+  assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 367:42]
+  assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42]
+  assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41]
+  assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41]
+  assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27]
+  assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27]
+  assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27]
+  assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41]
+  assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33]
+  assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27]
+  assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27]
+  assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37]
+  assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43]
+  assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41]
+  assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40]
+  assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40]
+  assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1196 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 358:40]
+  assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1199[0]; // @[dma_ctrl.scala 360:40]
+  assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 361:40]
+  assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 503:40]
+  assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 504:41]
+  assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 354:28]
+  assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1140 & _T_1138; // @[dma_ctrl.scala 333:41]
+  assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1140 & io_iccm_ready; // @[dma_ctrl.scala 353:40]
+  assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 506:39]
+  assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 505:37]
+  assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 508:40]
+  assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 507:40]
+  assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 509:38]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 355:17]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@@ -79330,15 +79374,15 @@ module dma_ctrl(
   assign rvclkhdr_9_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 355:17]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 388:33]
-  assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 386:33]
-  assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 387:33]
-  assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 394:29]
-  assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[dma_ctrl.scala 392:29]
-  assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 393:29]
-  assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 400:28]
-  assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 398:28]
-  assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 399:28]
+  assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33]
+  assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33]
+  assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33]
+  assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29]
+  assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29]
+  assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 397:29]
+  assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 404:28]
+  assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28]
+  assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18]
   assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 355:17]
   assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
@@ -79853,21 +79897,21 @@ end // initial
     if (reset) begin
       wrbuf_vld <= 1'h0;
     end else begin
-      wrbuf_vld <= _T_1204 & _T_1205;
+      wrbuf_vld <= _T_1224 & _T_1225;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
     if (reset) begin
       wrbuf_data_vld <= 1'h0;
     end else begin
-      wrbuf_data_vld <= _T_1208 & _T_1209;
+      wrbuf_data_vld <= _T_1228 & _T_1229;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
     if (reset) begin
       rdbuf_vld <= 1'h0;
     end else begin
-      rdbuf_vld <= _T_1217 & _T_1218;
+      rdbuf_vld <= _T_1237 & _T_1238;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
@@ -79916,7 +79960,7 @@ end // initial
     if (reset) begin
       fifo_full <= 1'h0;
     end else begin
-      fifo_full <= num_fifo_vld_tmp2 >= 4'h5;
+      fifo_full <= num_fifo_vld >= 4'h5;
     end
   end
   always @(posedge dma_bus_clk or posedge reset) begin
@@ -80265,10 +80309,10 @@ end // initial
     end else if (fifo_cmd_en[0]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1241) begin
+      end else if (_T_1261) begin
         _T_850 <= axi_mstr_priority;
       end else begin
-        _T_850 <= _T_1240;
+        _T_850 <= _T_1260;
       end
     end
   end
@@ -80278,10 +80322,10 @@ end // initial
     end else if (fifo_cmd_en[1]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1241) begin
+      end else if (_T_1261) begin
         _T_852 <= axi_mstr_priority;
       end else begin
-        _T_852 <= _T_1240;
+        _T_852 <= _T_1260;
       end
     end
   end
@@ -80291,10 +80335,10 @@ end // initial
     end else if (fifo_cmd_en[2]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1241) begin
+      end else if (_T_1261) begin
         _T_854 <= axi_mstr_priority;
       end else begin
-        _T_854 <= _T_1240;
+        _T_854 <= _T_1260;
       end
     end
   end
@@ -80304,10 +80348,10 @@ end // initial
     end else if (fifo_cmd_en[3]) begin
       if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
         _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
-      end else if (_T_1241) begin
+      end else if (_T_1261) begin
         _T_856 <= axi_mstr_priority;
       end else begin
-        _T_856 <= _T_1240;
+        _T_856 <= _T_1260;
       end
     end
   end
@@ -80460,10 +80504,10 @@ end // initial
     if (reset) begin
       dma_nack_count <= 3'h0;
     end else if (dma_mem_req) begin
-      if (_T_1118) begin
-        dma_nack_count <= _T_1131;
-      end else if (_T_1135) begin
-        dma_nack_count <= _T_1138;
+      if (_T_1138) begin
+        dma_nack_count <= _T_1151;
+      end else if (_T_1155) begin
+        dma_nack_count <= _T_1158;
       end else begin
         dma_nack_count <= 3'h0;
       end
@@ -80859,16 +80903,16 @@ module ahb_to_axi4(
   input         io_axi_arready,
   input         io_axi_rvalid,
   input  [1:0]  io_axi_rresp,
-  input         io_ahb_hsel,
-  input         io_ahb_hreadyin,
   output        io_axi_awvalid,
   output        io_axi_arvalid,
-  output        io_ahb_in_hready,
-  output        io_ahb_in_hresp,
-  input  [31:0] io_ahb_out_haddr,
-  input  [2:0]  io_ahb_out_hsize,
-  input  [1:0]  io_ahb_out_htrans,
-  input         io_ahb_out_hwrite
+  output        io_ahb_sig_in_hready,
+  output        io_ahb_sig_in_hresp,
+  input  [31:0] io_ahb_sig_out_haddr,
+  input  [2:0]  io_ahb_sig_out_hsize,
+  input  [1:0]  io_ahb_sig_out_htrans,
+  input         io_ahb_sig_out_hwrite,
+  input         io_ahb_hsel,
+  input         io_ahb_hreadyin
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -80906,48 +80950,48 @@ module ahb_to_axi4(
   wire  rvclkhdr_5_io_clk; // @[lib.scala 327:22]
   wire  rvclkhdr_5_io_en; // @[lib.scala 327:22]
   wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 327:22]
-  wire  ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 87:33 ahb_to_axi4.scala 176:31]
-  reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 169:65]
+  wire  ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 90:33 ahb_to_axi4.scala 179:31]
+  reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 172:65]
   wire  ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 71:29]
   wire  ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 71:29]
-  wire  ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 86:33 ahb_to_axi4.scala 175:31]
+  wire  ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 89:33 ahb_to_axi4.scala 178:31]
   reg [1:0] buf_state; // @[Reg.scala 27:20]
   wire  _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
-  wire  ahb_hready = io_ahb_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 147:51]
-  wire  _T_9 = ahb_hready & io_ahb_out_htrans[1]; // @[ahb_to_axi4.scala 119:34]
-  wire  _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 119:57]
+  wire  ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 150:55]
+  wire  _T_9 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 122:34]
+  wire  _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 122:61]
   wire  _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
-  wire  _T_13 = io_ahb_out_htrans == 2'h0; // @[ahb_to_axi4.scala 122:71]
-  wire  _T_14 = io_ahb_in_hresp | _T_13; // @[ahb_to_axi4.scala 122:44]
-  wire  _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 122:85]
-  wire  _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 122:83]
-  wire  bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 100:33 ahb_to_axi4.scala 225:27]
-  reg  cmdbuf_vld; // @[ahb_to_axi4.scala 182:61]
-  wire  _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 180:66]
-  wire  _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 180:102]
-  wire  _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 180:84]
-  wire  _T_153 = ~_T_152; // @[ahb_to_axi4.scala 180:48]
-  wire  cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 180:46]
-  wire  _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 123:24]
-  wire  _T_21 = _T_20 | io_ahb_in_hresp; // @[ahb_to_axi4.scala 123:37]
-  wire  _T_24 = io_ahb_out_htrans == 2'h1; // @[ahb_to_axi4.scala 124:84]
-  wire  _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 124:102]
-  wire  _T_26 = io_ahb_in_hresp | _T_25; // @[ahb_to_axi4.scala 124:56]
-  wire  _T_27 = ~_T_26; // @[ahb_to_axi4.scala 124:38]
-  wire  _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 124:36]
+  wire  _T_13 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 125:79]
+  wire  _T_14 = io_ahb_sig_in_hresp | _T_13; // @[ahb_to_axi4.scala 125:48]
+  wire  _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 125:93]
+  wire  _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 125:91]
+  wire  bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 103:33 ahb_to_axi4.scala 228:27]
+  reg  cmdbuf_vld; // @[ahb_to_axi4.scala 185:61]
+  wire  _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 183:66]
+  wire  _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 183:102]
+  wire  _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 183:84]
+  wire  _T_153 = ~_T_152; // @[ahb_to_axi4.scala 183:48]
+  wire  cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 183:46]
+  wire  _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 126:24]
+  wire  _T_21 = _T_20 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 126:37]
+  wire  _T_24 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 127:92]
+  wire  _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 127:110]
+  wire  _T_26 = io_ahb_sig_in_hresp | _T_25; // @[ahb_to_axi4.scala 127:60]
+  wire  _T_27 = ~_T_26; // @[ahb_to_axi4.scala 127:38]
+  wire  _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 127:36]
   wire  _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
-  wire  _T_33 = ~io_ahb_in_hresp; // @[ahb_to_axi4.scala 129:23]
-  wire  _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 129:40]
+  wire  _T_33 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 132:23]
+  wire  _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 132:44]
   wire  _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
   reg  cmdbuf_write; // @[Reg.scala 27:20]
-  wire  _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 133:39]
-  wire  _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 133:37]
-  wire  _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 135:62]
+  wire  _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 136:39]
+  wire  _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 136:37]
+  wire  _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 138:62]
   wire  _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67]
   wire  _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67]
   wire  _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67]
   wire  buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58]
-  wire  _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 135:41]
+  wire  _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 138:41]
   wire  _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67]
   wire  _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67]
   wire  _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67]
@@ -80956,56 +81000,56 @@ module ahb_to_axi4(
   wire  _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
   wire  cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
   wire  buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
-  reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 167:65]
-  wire  _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 141:30]
-  wire  _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 142:30]
-  wire  _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 143:30]
-  reg  ahb_hready_q; // @[ahb_to_axi4.scala 165:60]
-  wire  _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 146:72]
-  reg  ahb_hresp_q; // @[ahb_to_axi4.scala 164:60]
-  wire  _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 146:70]
-  wire  _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 146:116]
-  wire  _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 146:103]
-  wire  _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 146:141]
-  wire  _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 146:160]
-  wire  _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 146:148]
-  wire  _T_81 = ~_T_80; // @[ahb_to_axi4.scala 146:129]
-  wire  _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 146:127]
-  reg  buf_read_error; // @[ahb_to_axi4.scala 161:60]
-  wire  _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 146:173]
-  wire  _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 146:171]
+  reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 170:65]
+  wire  _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 144:30]
+  wire  _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 145:30]
+  wire  _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 146:30]
+  reg  ahb_hready_q; // @[ahb_to_axi4.scala 168:60]
+  wire  _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 149:80]
+  reg  ahb_hresp_q; // @[ahb_to_axi4.scala 167:60]
+  wire  _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 149:78]
+  wire  _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 149:124]
+  wire  _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 149:111]
+  wire  _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 149:149]
+  wire  _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 149:168]
+  wire  _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 149:156]
+  wire  _T_81 = ~_T_80; // @[ahb_to_axi4.scala 149:137]
+  wire  _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 149:135]
+  reg  buf_read_error; // @[ahb_to_axi4.scala 164:60]
+  wire  _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 149:181]
+  wire  _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 149:179]
   wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 166:60]
-  wire  _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 150:57]
-  wire  _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 150:79]
-  wire  _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 150:66]
-  wire  _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 151:26]
-  wire  _T_97 = ~_T_96; // @[ahb_to_axi4.scala 151:7]
-  reg  ahb_hwrite_q; // @[ahb_to_axi4.scala 168:65]
-  wire  _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 152:46]
-  wire  _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 152:26]
-  wire  _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 152:86]
-  wire  _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 152:115]
-  wire  _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 152:95]
-  wire  _T_105 = ~_T_104; // @[ahb_to_axi4.scala 152:66]
-  wire  _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 152:64]
-  wire  _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 151:47]
-  wire  _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 153:35]
-  wire  _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 152:126]
-  wire  _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 154:56]
-  wire  _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 154:35]
-  wire  _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 153:55]
-  wire  _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 155:56]
-  wire  _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 155:35]
-  wire  _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 154:61]
-  wire  _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 150:90]
-  wire  _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 155:63]
-  wire  _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 179:109]
-  wire  _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 179:107]
-  wire  _T_148 = io_ahb_in_hresp & _T_37; // @[ahb_to_axi4.scala 179:143]
-  wire  cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 179:124]
-  wire  _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 182:66]
-  wire  _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 182:110]
+  reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 169:60]
+  wire  _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 153:61]
+  wire  _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 153:83]
+  wire  _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 153:70]
+  wire  _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 154:26]
+  wire  _T_97 = ~_T_96; // @[ahb_to_axi4.scala 154:7]
+  reg  ahb_hwrite_q; // @[ahb_to_axi4.scala 171:65]
+  wire  _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 155:46]
+  wire  _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 155:26]
+  wire  _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 155:86]
+  wire  _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 155:115]
+  wire  _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 155:95]
+  wire  _T_105 = ~_T_104; // @[ahb_to_axi4.scala 155:66]
+  wire  _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 155:64]
+  wire  _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 154:47]
+  wire  _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 156:35]
+  wire  _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 155:126]
+  wire  _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 157:56]
+  wire  _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 157:35]
+  wire  _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 156:55]
+  wire  _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 158:56]
+  wire  _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 158:35]
+  wire  _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 157:61]
+  wire  _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 153:94]
+  wire  _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 158:63]
+  wire  _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 182:109]
+  wire  _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 182:107]
+  wire  _T_148 = io_ahb_sig_in_hresp & _T_37; // @[ahb_to_axi4.scala 182:147]
+  wire  cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 182:124]
+  wire  _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 185:66]
+  wire  _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 185:110]
   rvclkhdr rvclkhdr ( // @[lib.scala 327:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -81042,10 +81086,10 @@ module ahb_to_axi4(
     .io_en(rvclkhdr_5_io_en),
     .io_scan_mode(rvclkhdr_5_io_scan_mode)
   );
-  assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 199:27]
-  assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 214:27]
-  assign io_ahb_in_hready = io_ahb_in_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 146:34]
-  assign io_ahb_in_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 150:34]
+  assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 202:27]
+  assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 217:27]
+  assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 149:38]
+  assign io_ahb_sig_in_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 153:38]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
   assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
@@ -81160,7 +81204,7 @@ end // initial
     if (reset) begin
       ahb_haddr_q <= 32'h0;
     end else begin
-      ahb_haddr_q <= io_ahb_out_haddr;
+      ahb_haddr_q <= io_ahb_sig_out_haddr;
     end
   end
   always @(posedge ahb_clk or posedge reset) begin
@@ -81168,7 +81212,7 @@ end // initial
       buf_state <= 2'h0;
     end else if (buf_state_en) begin
       if (_T_6) begin
-        if (io_ahb_out_hwrite) begin
+        if (io_ahb_sig_out_hwrite) begin
           buf_state <= 2'h1;
         end else begin
           buf_state <= 2'h2;
@@ -81176,13 +81220,13 @@ end // initial
       end else if (_T_11) begin
         if (_T_16) begin
           buf_state <= 2'h0;
-        end else if (io_ahb_out_hwrite) begin
+        end else if (io_ahb_sig_out_hwrite) begin
           buf_state <= 2'h1;
         end else begin
           buf_state <= 2'h2;
         end
       end else if (_T_29) begin
-        if (io_ahb_in_hresp) begin
+        if (io_ahb_sig_in_hresp) begin
           buf_state <= 2'h0;
         end else begin
           buf_state <= 2'h3;
@@ -81210,21 +81254,21 @@ end // initial
     if (reset) begin
       ahb_hsize_q <= 3'h0;
     end else begin
-      ahb_hsize_q <= io_ahb_out_hsize;
+      ahb_hsize_q <= io_ahb_sig_out_hsize;
     end
   end
   always @(posedge ahb_clk or posedge reset) begin
     if (reset) begin
       ahb_hready_q <= 1'h0;
     end else begin
-      ahb_hready_q <= io_ahb_in_hready & io_ahb_hreadyin;
+      ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin;
     end
   end
   always @(posedge ahb_clk or posedge reset) begin
     if (reset) begin
       ahb_hresp_q <= 1'h0;
     end else begin
-      ahb_hresp_q <= io_ahb_in_hresp;
+      ahb_hresp_q <= io_ahb_sig_in_hresp;
     end
   end
   always @(posedge ahb_clk or posedge reset) begin
@@ -81244,14 +81288,14 @@ end // initial
     if (reset) begin
       ahb_htrans_q <= 2'h0;
     end else begin
-      ahb_htrans_q <= _T_88 & io_ahb_out_htrans;
+      ahb_htrans_q <= _T_88 & io_ahb_sig_out_htrans;
     end
   end
   always @(posedge ahb_addr_clk or posedge reset) begin
     if (reset) begin
       ahb_hwrite_q <= 1'h0;
     end else begin
-      ahb_hwrite_q <= io_ahb_out_hwrite;
+      ahb_hwrite_q <= io_ahb_sig_out_hwrite;
     end
   end
 endmodule
@@ -81346,6 +81390,8 @@ module quasar(
   input  [2:0]  io_dma_ahb_out_hsize,
   input  [1:0]  io_dma_ahb_out_htrans,
   input         io_dma_ahb_out_hwrite,
+  input         io_dma_hsel,
+  input         io_dma_hreadyin,
   input         io_dbg_rst_l,
   input  [30:0] io_rst_vec,
   input         io_nmi_int,
@@ -81417,8 +81463,6 @@ module quasar(
   output [77:0] io_iccm_wr_data,
   input  [63:0] io_iccm_rd_data,
   input  [77:0] io_iccm_rd_data_ecc,
-  input         io_dma_hsel,
-  input         io_dma_hreadyin,
   input         io_lsu_bus_clk_en,
   input         io_ifu_bus_clk_en,
   input         io_dbg_bus_clk_en,
@@ -81432,793 +81476,793 @@ module quasar(
   input         io_soft_int,
   input         io_scan_mode
 );
-  wire  ifu_clock; // @[quasar.scala 122:19]
-  wire  ifu_reset; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_flush_final; // @[quasar.scala 122:19]
-  wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 122:19]
-  wire  ifu_io_free_clk; // @[quasar.scala 122:19]
-  wire  ifu_io_active_clk; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 122:19]
-  wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 122:19]
-  wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 122:19]
-  wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 122:19]
-  wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 122:19]
-  wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 122:19]
-  wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 122:19]
-  wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 122:19]
-  wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 122:19]
-  wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 122:19]
-  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 122:19]
-  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 122:19]
-  wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 122:19]
-  wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_correction_state; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_wren; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_rden; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 122:19]
-  wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 122:19]
-  wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 122:19]
-  wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_rd_en; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 122:19]
-  wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 122:19]
-  wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 122:19]
-  wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_tag_perr; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_debug_rd_en; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_debug_wr_en; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_debug_tag_array; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 122:19]
-  wire  ifu_io_ic_sel_premux_data; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_ar_ready; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_ar_valid; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 122:19]
-  wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 122:19]
-  wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_r_valid; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 122:19]
-  wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_bus_clk_en; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:19]
-  wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:19]
-  wire  ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_dma_ecc_error; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_dma_rvalid; // @[quasar.scala 122:19]
-  wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 122:19]
-  wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_ready; // @[quasar.scala 122:19]
-  wire  ifu_io_iccm_dma_sb_error; // @[quasar.scala 122:19]
-  wire  ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 122:19]
-  wire  ifu_io_scan_mode; // @[quasar.scala 122:19]
-  wire  dec_clock; // @[quasar.scala 123:19]
-  wire  dec_reset; // @[quasar.scala 123:19]
-  wire  dec_io_free_clk; // @[quasar.scala 123:19]
-  wire  dec_io_active_clk; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_fastint_stall_any; // @[quasar.scala 123:19]
-  wire  dec_io_dec_pause_state_cg; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_rst_vec; // @[quasar.scala 123:19]
-  wire  dec_io_nmi_int; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_nmi_vec; // @[quasar.scala 123:19]
-  wire  dec_io_i_cpu_halt_req; // @[quasar.scala 123:19]
-  wire  dec_io_i_cpu_run_req; // @[quasar.scala 123:19]
-  wire  dec_io_o_cpu_halt_status; // @[quasar.scala 123:19]
-  wire  dec_io_o_cpu_halt_ack; // @[quasar.scala 123:19]
-  wire  dec_io_o_cpu_run_ack; // @[quasar.scala 123:19]
-  wire  dec_io_o_debug_mode_status; // @[quasar.scala 123:19]
-  wire [27:0] dec_io_core_id; // @[quasar.scala 123:19]
-  wire  dec_io_mpc_debug_halt_req; // @[quasar.scala 123:19]
-  wire  dec_io_mpc_debug_run_req; // @[quasar.scala 123:19]
-  wire  dec_io_mpc_reset_run_req; // @[quasar.scala 123:19]
-  wire  dec_io_mpc_debug_halt_ack; // @[quasar.scala 123:19]
-  wire  dec_io_mpc_debug_run_ack; // @[quasar.scala 123:19]
-  wire  dec_io_debug_brkpt_status; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 123:19]
-  wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_idle_any; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 123:19]
-  wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_exu_div_result; // @[quasar.scala 123:19]
-  wire  dec_io_exu_div_wren; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_load_stall_any; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_store_stall_any; // @[quasar.scala 123:19]
-  wire  dec_io_iccm_dma_sb_error; // @[quasar.scala 123:19]
-  wire  dec_io_exu_flush_final; // @[quasar.scala 123:19]
-  wire  dec_io_timer_int; // @[quasar.scala 123:19]
-  wire  dec_io_soft_int; // @[quasar.scala 123:19]
-  wire  dec_io_dbg_halt_req; // @[quasar.scala 123:19]
-  wire  dec_io_dbg_resume_req; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_dbg_halted; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_debug_mode; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_resume_ack; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dbg_cmd_done; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dbg_cmd_fail; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_0_select; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_0_store; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_0_load; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_1_select; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_1_store; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_1_load; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_2_select; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_2_store; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_2_load; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_3_select; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_3_store; // @[quasar.scala 123:19]
-  wire  dec_io_trigger_pkt_any_3_load; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 123:19]
-  wire  dec_io_exu_i0_br_way_r; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_valid; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_fast_int; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_by; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_half; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_word; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_load; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_store; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_unsign; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 123:19]
-  wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_perfcnt0; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_perfcnt1; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_perfcnt2; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_perfcnt3; // @[quasar.scala 123:19]
-  wire  dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 123:19]
-  wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 123:19]
-  wire  dec_io_scan_mode; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 123:19]
-  wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 123:19]
-  wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 123:19]
-  wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 123:19]
-  wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 123:19]
-  wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 123:19]
-  wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 123:19]
-  wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 123:19]
-  wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 123:19]
-  wire  dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 123:19]
-  wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 123:19]
-  wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 123:19]
-  wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 123:19]
-  wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 123:19]
-  wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 123:19]
-  wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 123:19]
-  wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 123:19]
-  wire  dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 123:19]
-  wire  dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 123:19]
-  wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 123:19]
-  wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 123:19]
-  wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 123:19]
-  wire  dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 123:19]
-  wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 123:19]
-  wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 123:19]
-  wire  dec_io_dec_pic_mhwakeup; // @[quasar.scala 123:19]
-  wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 123:19]
-  wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 123:19]
-  wire  dec_io_dec_pic_mexintpend; // @[quasar.scala 123:19]
-  wire  dbg_clock; // @[quasar.scala 124:19]
-  wire  dbg_reset; // @[quasar.scala 124:19]
-  wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_core_rst_l; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 124:19]
-  wire  dbg_io_core_dbg_cmd_done; // @[quasar.scala 124:19]
-  wire  dbg_io_core_dbg_cmd_fail; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_halt_req; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_resume_req; // @[quasar.scala 124:19]
-  wire  dbg_io_dec_tlu_debug_mode; // @[quasar.scala 124:19]
-  wire  dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 124:19]
-  wire  dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 124:19]
-  wire  dbg_io_dec_tlu_resume_ack; // @[quasar.scala 124:19]
-  wire  dbg_io_dmi_reg_en; // @[quasar.scala 124:19]
-  wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 124:19]
-  wire  dbg_io_dmi_reg_wr_en; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_aw_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_aw_valid; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 124:19]
-  wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 124:19]
-  wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_w_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_w_valid; // @[quasar.scala 124:19]
-  wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 124:19]
-  wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_b_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_b_valid; // @[quasar.scala 124:19]
-  wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_ar_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_ar_valid; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 124:19]
-  wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 124:19]
-  wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_r_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_sb_axi_r_valid; // @[quasar.scala 124:19]
-  wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 124:19]
-  wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19]
-  wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19]
-  wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19]
-  wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_bus_clk_en; // @[quasar.scala 124:19]
-  wire  dbg_io_dbg_rst_l; // @[quasar.scala 124:19]
-  wire  dbg_io_clk_override; // @[quasar.scala 124:19]
-  wire  dbg_io_scan_mode; // @[quasar.scala 124:19]
-  wire  exu_clock; // @[quasar.scala 125:19]
-  wire  exu_reset; // @[quasar.scala 125:19]
-  wire  exu_io_scan_mode; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 125:19]
-  wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 125:19]
-  wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 125:19]
-  wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 125:19]
-  wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 125:19]
-  wire  exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19]
-  wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19]
-  wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19]
-  wire  exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19]
-  wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 125:19]
-  wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 125:19]
-  wire  exu_io_exu_flush_final; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_exu_div_result; // @[quasar.scala 125:19]
-  wire  exu_io_exu_div_wren; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 125:19]
-  wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 125:19]
-  wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 125:19]
-  wire  lsu_clock; // @[quasar.scala 126:19]
-  wire  lsu_reset; // @[quasar.scala 126:19]
-  wire  lsu_io_clk_override; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 126:19]
-  wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 126:19]
-  wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 126:19]
-  wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_pic_picm_wren; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_pic_picm_rden; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_pic_picm_mken; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19]
-  wire  lsu_io_dccm_wren; // @[quasar.scala 126:19]
-  wire  lsu_io_dccm_rden; // @[quasar.scala 126:19]
-  wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 126:19]
-  wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 126:19]
-  wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 126:19]
-  wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 126:19]
-  wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 126:19]
-  wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 126:19]
-  wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 126:19]
-  wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_aw_ready; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_aw_valid; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_w_ready; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_w_valid; // @[quasar.scala 126:19]
-  wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 126:19]
-  wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_b_valid; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_ar_ready; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_ar_valid; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 126:19]
-  wire  lsu_io_axi_r_valid; // @[quasar.scala 126:19]
-  wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 126:19]
-  wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 126:19]
-  wire  lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 126:19]
-  wire  lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19]
-  wire  lsu_io_dec_tlu_force_halt; // @[quasar.scala 126:19]
-  wire  lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19]
-  wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_valid; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_by; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_half; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_word; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_load; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_store; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_unsign; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19]
-  wire  lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19]
-  wire  lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_load_stall_any; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_store_stall_any; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_fastint_stall_any; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_idle_any; // @[quasar.scala 126:19]
-  wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 126:19]
-  wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19]
-  wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19]
-  wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 126:19]
-  wire  lsu_io_lsu_bus_clk_en; // @[quasar.scala 126:19]
-  wire  lsu_io_scan_mode; // @[quasar.scala 126:19]
-  wire  lsu_io_free_clk; // @[quasar.scala 126:19]
-  wire  pic_ctrl_inst_clock; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_reset; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_scan_mode; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_free_clk; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_active_clk; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_clk_override; // @[quasar.scala 127:29]
-  wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 127:29]
-  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 127:29]
-  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 127:29]
-  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 127:29]
-  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 127:29]
-  wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 127:29]
-  wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 127:29]
-  wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 127:29]
-  wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 127:29]
-  wire  pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 127:29]
-  wire  dma_ctrl_clock; // @[quasar.scala 128:24]
-  wire  dma_ctrl_reset; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_free_clk; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_clk_override; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_scan_mode; // @[quasar.scala 128:24]
-  wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 128:24]
-  wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_iccm_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 128:24]
-  wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 128:24]
-  wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 128:24]
-  wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 128:24]
-  wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 128:24]
-  wire  dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 128:24]
-  wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 128:24]
-  wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 128:24]
+  wire  ifu_clock; // @[quasar.scala 125:19]
+  wire  ifu_reset; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_flush_final; // @[quasar.scala 125:19]
+  wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 125:19]
+  wire  ifu_io_free_clk; // @[quasar.scala 125:19]
+  wire  ifu_io_active_clk; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 125:19]
+  wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 125:19]
+  wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 125:19]
+  wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 125:19]
+  wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 125:19]
+  wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 125:19]
+  wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 125:19]
+  wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 125:19]
+  wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19]
+  wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19]
+  wire  ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19]
+  wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 125:19]
+  wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 125:19]
+  wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_correction_state; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_wren; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_rden; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 125:19]
+  wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 125:19]
+  wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 125:19]
+  wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_rd_en; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 125:19]
+  wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 125:19]
+  wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 125:19]
+  wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_tag_perr; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_debug_rd_en; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_debug_wr_en; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_debug_tag_array; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 125:19]
+  wire  ifu_io_ic_sel_premux_data; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_ar_ready; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_ar_valid; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 125:19]
+  wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 125:19]
+  wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_r_valid; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 125:19]
+  wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_bus_clk_en; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 125:19]
+  wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 125:19]
+  wire  ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_dma_ecc_error; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_dma_rvalid; // @[quasar.scala 125:19]
+  wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 125:19]
+  wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_ready; // @[quasar.scala 125:19]
+  wire  ifu_io_iccm_dma_sb_error; // @[quasar.scala 125:19]
+  wire  ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 125:19]
+  wire  ifu_io_scan_mode; // @[quasar.scala 125:19]
+  wire  dec_clock; // @[quasar.scala 126:19]
+  wire  dec_reset; // @[quasar.scala 126:19]
+  wire  dec_io_free_clk; // @[quasar.scala 126:19]
+  wire  dec_io_active_clk; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_fastint_stall_any; // @[quasar.scala 126:19]
+  wire  dec_io_dec_pause_state_cg; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_rst_vec; // @[quasar.scala 126:19]
+  wire  dec_io_nmi_int; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_nmi_vec; // @[quasar.scala 126:19]
+  wire  dec_io_i_cpu_halt_req; // @[quasar.scala 126:19]
+  wire  dec_io_i_cpu_run_req; // @[quasar.scala 126:19]
+  wire  dec_io_o_cpu_halt_status; // @[quasar.scala 126:19]
+  wire  dec_io_o_cpu_halt_ack; // @[quasar.scala 126:19]
+  wire  dec_io_o_cpu_run_ack; // @[quasar.scala 126:19]
+  wire  dec_io_o_debug_mode_status; // @[quasar.scala 126:19]
+  wire [27:0] dec_io_core_id; // @[quasar.scala 126:19]
+  wire  dec_io_mpc_debug_halt_req; // @[quasar.scala 126:19]
+  wire  dec_io_mpc_debug_run_req; // @[quasar.scala 126:19]
+  wire  dec_io_mpc_reset_run_req; // @[quasar.scala 126:19]
+  wire  dec_io_mpc_debug_halt_ack; // @[quasar.scala 126:19]
+  wire  dec_io_mpc_debug_run_ack; // @[quasar.scala 126:19]
+  wire  dec_io_debug_brkpt_status; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 126:19]
+  wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_idle_any; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19]
+  wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_exu_div_result; // @[quasar.scala 126:19]
+  wire  dec_io_exu_div_wren; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_load_stall_any; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_store_stall_any; // @[quasar.scala 126:19]
+  wire  dec_io_iccm_dma_sb_error; // @[quasar.scala 126:19]
+  wire  dec_io_exu_flush_final; // @[quasar.scala 126:19]
+  wire  dec_io_timer_int; // @[quasar.scala 126:19]
+  wire  dec_io_soft_int; // @[quasar.scala 126:19]
+  wire  dec_io_dbg_halt_req; // @[quasar.scala 126:19]
+  wire  dec_io_dbg_resume_req; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_dbg_halted; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_debug_mode; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_resume_ack; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dbg_cmd_done; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dbg_cmd_fail; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19]
+  wire  dec_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19]
+  wire  dec_io_exu_i0_br_way_r; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_valid; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_by; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_half; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_word; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_load; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_store; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_unsign; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19]
+  wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_perfcnt0; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_perfcnt1; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_perfcnt2; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_perfcnt3; // @[quasar.scala 126:19]
+  wire  dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 126:19]
+  wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 126:19]
+  wire  dec_io_scan_mode; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 126:19]
+  wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 126:19]
+  wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 126:19]
+  wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 126:19]
+  wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 126:19]
+  wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 126:19]
+  wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 126:19]
+  wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 126:19]
+  wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 126:19]
+  wire  dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 126:19]
+  wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 126:19]
+  wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 126:19]
+  wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 126:19]
+  wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 126:19]
+  wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 126:19]
+  wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 126:19]
+  wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 126:19]
+  wire  dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19]
+  wire  dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 126:19]
+  wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 126:19]
+  wire [31:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 126:19]
+  wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 126:19]
+  wire  dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 126:19]
+  wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 126:19]
+  wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 126:19]
+  wire  dec_io_dec_pic_mhwakeup; // @[quasar.scala 126:19]
+  wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 126:19]
+  wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 126:19]
+  wire  dec_io_dec_pic_mexintpend; // @[quasar.scala 126:19]
+  wire  dbg_clock; // @[quasar.scala 127:19]
+  wire  dbg_reset; // @[quasar.scala 127:19]
+  wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_core_rst_l; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 127:19]
+  wire  dbg_io_core_dbg_cmd_done; // @[quasar.scala 127:19]
+  wire  dbg_io_core_dbg_cmd_fail; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_halt_req; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_resume_req; // @[quasar.scala 127:19]
+  wire  dbg_io_dec_tlu_debug_mode; // @[quasar.scala 127:19]
+  wire  dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 127:19]
+  wire  dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 127:19]
+  wire  dbg_io_dec_tlu_resume_ack; // @[quasar.scala 127:19]
+  wire  dbg_io_dmi_reg_en; // @[quasar.scala 127:19]
+  wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 127:19]
+  wire  dbg_io_dmi_reg_wr_en; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_aw_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_aw_valid; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 127:19]
+  wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 127:19]
+  wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_w_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_w_valid; // @[quasar.scala 127:19]
+  wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 127:19]
+  wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_b_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_b_valid; // @[quasar.scala 127:19]
+  wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_ar_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_ar_valid; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 127:19]
+  wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 127:19]
+  wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_r_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_sb_axi_r_valid; // @[quasar.scala 127:19]
+  wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 127:19]
+  wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 127:19]
+  wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 127:19]
+  wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 127:19]
+  wire [31:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_bus_clk_en; // @[quasar.scala 127:19]
+  wire  dbg_io_dbg_rst_l; // @[quasar.scala 127:19]
+  wire  dbg_io_clk_override; // @[quasar.scala 127:19]
+  wire  dbg_io_scan_mode; // @[quasar.scala 127:19]
+  wire  exu_clock; // @[quasar.scala 128:19]
+  wire  exu_reset; // @[quasar.scala 128:19]
+  wire  exu_io_scan_mode; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 128:19]
+  wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 128:19]
+  wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 128:19]
+  wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 128:19]
+  wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 128:19]
+  wire  exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 128:19]
+  wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 128:19]
+  wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 128:19]
+  wire  exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 128:19]
+  wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 128:19]
+  wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 128:19]
+  wire  exu_io_exu_flush_final; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_exu_div_result; // @[quasar.scala 128:19]
+  wire  exu_io_exu_div_wren; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 128:19]
+  wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 128:19]
+  wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 128:19]
+  wire  lsu_clock; // @[quasar.scala 129:19]
+  wire  lsu_reset; // @[quasar.scala 129:19]
+  wire  lsu_io_clk_override; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 129:19]
+  wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 129:19]
+  wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 129:19]
+  wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_pic_picm_wren; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_pic_picm_rden; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_pic_picm_mken; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 129:19]
+  wire  lsu_io_dccm_wren; // @[quasar.scala 129:19]
+  wire  lsu_io_dccm_rden; // @[quasar.scala 129:19]
+  wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 129:19]
+  wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 129:19]
+  wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 129:19]
+  wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 129:19]
+  wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 129:19]
+  wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 129:19]
+  wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 129:19]
+  wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_aw_ready; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_aw_valid; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_w_ready; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_w_valid; // @[quasar.scala 129:19]
+  wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 129:19]
+  wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_b_valid; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_ar_ready; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_ar_valid; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 129:19]
+  wire  lsu_io_axi_r_valid; // @[quasar.scala 129:19]
+  wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 129:19]
+  wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 129:19]
+  wire  lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 129:19]
+  wire  lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 129:19]
+  wire  lsu_io_dec_tlu_force_halt; // @[quasar.scala 129:19]
+  wire  lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 129:19]
+  wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_valid; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_by; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_half; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_word; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_load; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_store; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_unsign; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 129:19]
+  wire  lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 129:19]
+  wire  lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_load_stall_any; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_store_stall_any; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_fastint_stall_any; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_idle_any; // @[quasar.scala 129:19]
+  wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 129:19]
+  wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 129:19]
+  wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 129:19]
+  wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 129:19]
+  wire  lsu_io_lsu_bus_clk_en; // @[quasar.scala 129:19]
+  wire  lsu_io_scan_mode; // @[quasar.scala 129:19]
+  wire  lsu_io_free_clk; // @[quasar.scala 129:19]
+  wire  pic_ctrl_inst_clock; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_reset; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_scan_mode; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_free_clk; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_active_clk; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_clk_override; // @[quasar.scala 130:29]
+  wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 130:29]
+  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 130:29]
+  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 130:29]
+  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 130:29]
+  wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 130:29]
+  wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 130:29]
+  wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 130:29]
+  wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 130:29]
+  wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 130:29]
+  wire  pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 130:29]
+  wire  dma_ctrl_clock; // @[quasar.scala 131:24]
+  wire  dma_ctrl_reset; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_free_clk; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_clk_override; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_scan_mode; // @[quasar.scala 131:24]
+  wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 131:24]
+  wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_iccm_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 131:24]
+  wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 131:24]
+  wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 131:24]
+  wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 131:24]
+  wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 131:24]
+  wire  dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 131:24]
+  wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 131:24]
+  wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 131:24]
   wire  rvclkhdr_io_l1clk; // @[lib.scala 327:22]
   wire  rvclkhdr_io_clk; // @[lib.scala 327:22]
   wire  rvclkhdr_io_en; // @[lib.scala 327:22]
@@ -82227,65 +82271,65 @@ module quasar(
   wire  rvclkhdr_1_io_clk; // @[lib.scala 327:22]
   wire  rvclkhdr_1_io_en; // @[lib.scala 327:22]
   wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 327:22]
-  wire  axi4_to_ahb_clock; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_reset; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_scan_mode; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_clk_override; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_bready; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_rready; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_awready; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_io_axi_wready; // @[quasar.scala 303:33]
-  wire  axi4_to_ahb_1_clock; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_reset; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_clk_override; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 330:33]
-  wire  axi4_to_ahb_2_clock; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_reset; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_clk_override; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 358:32]
-  wire  axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 358:32]
-  wire  ahb_to_axi4_clock; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_reset; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_scan_mode; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_axi_awready; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_axi_arready; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 385:33]
-  wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_ahb_in_hready; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_ahb_in_hresp; // @[quasar.scala 385:33]
-  wire [31:0] ahb_to_axi4_io_ahb_out_haddr; // @[quasar.scala 385:33]
-  wire [2:0] ahb_to_axi4_io_ahb_out_hsize; // @[quasar.scala 385:33]
-  wire [1:0] ahb_to_axi4_io_ahb_out_htrans; // @[quasar.scala 385:33]
-  wire  ahb_to_axi4_io_ahb_out_hwrite; // @[quasar.scala 385:33]
-  wire  _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 130:67]
-  wire  _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 130:70]
-  wire  _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 131:23]
-  wire  _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 131:50]
-  ifu ifu ( // @[quasar.scala 122:19]
+  wire  axi4_to_ahb_clock; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_reset; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_scan_mode; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_clk_override; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_bready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_rready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_awready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_io_axi_wready; // @[quasar.scala 306:33]
+  wire  axi4_to_ahb_1_clock; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_reset; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_clk_override; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 333:33]
+  wire  axi4_to_ahb_2_clock; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_reset; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_clk_override; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 361:32]
+  wire  axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 361:32]
+  wire  ahb_to_axi4_clock; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_reset; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_scan_mode; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_axi_awready; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_axi_arready; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 388:33]
+  wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_sig_in_hready; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 388:33]
+  wire [31:0] ahb_to_axi4_io_ahb_sig_out_haddr; // @[quasar.scala 388:33]
+  wire [2:0] ahb_to_axi4_io_ahb_sig_out_hsize; // @[quasar.scala 388:33]
+  wire [1:0] ahb_to_axi4_io_ahb_sig_out_htrans; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_sig_out_hwrite; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 388:33]
+  wire  ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 388:33]
+  wire  _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 133:67]
+  wire  _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 133:70]
+  wire  _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 134:23]
+  wire  _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 134:50]
+  ifu ifu ( // @[quasar.scala 125:19]
     .clock(ifu_clock),
     .reset(ifu_reset),
     .io_exu_flush_final(ifu_io_exu_flush_final),
@@ -82415,7 +82459,7 @@ module quasar(
     .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb),
     .io_scan_mode(ifu_io_scan_mode)
   );
-  dec dec ( // @[quasar.scala 123:19]
+  dec dec ( // @[quasar.scala 126:19]
     .clock(dec_clock),
     .reset(dec_reset),
     .io_free_clk(dec_io_free_clk),
@@ -82689,7 +82733,7 @@ module quasar(
     .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt),
     .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend)
   );
-  dbg dbg ( // @[quasar.scala 124:19]
+  dbg dbg ( // @[quasar.scala 127:19]
     .clock(dbg_clock),
     .reset(dbg_reset),
     .io_dbg_cmd_size(dbg_io_dbg_cmd_size),
@@ -82745,7 +82789,7 @@ module quasar(
     .io_clk_override(dbg_io_clk_override),
     .io_scan_mode(dbg_io_scan_mode)
   );
-  exu exu ( // @[quasar.scala 125:19]
+  exu exu ( // @[quasar.scala 128:19]
     .clock(exu_clock),
     .reset(exu_reset),
     .io_scan_mode(exu_io_scan_mode),
@@ -82850,7 +82894,7 @@ module quasar(
     .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d),
     .io_exu_flush_path_final(exu_io_exu_flush_path_final)
   );
-  lsu lsu ( // @[quasar.scala 126:19]
+  lsu lsu ( // @[quasar.scala 129:19]
     .clock(lsu_clock),
     .reset(lsu_reset),
     .io_clk_override(lsu_io_clk_override),
@@ -82989,7 +83033,7 @@ module quasar(
     .io_scan_mode(lsu_io_scan_mode),
     .io_free_clk(lsu_io_free_clk)
   );
-  pic_ctrl pic_ctrl_inst ( // @[quasar.scala 127:29]
+  pic_ctrl pic_ctrl_inst ( // @[quasar.scala 130:29]
     .clock(pic_ctrl_inst_clock),
     .reset(pic_ctrl_inst_reset),
     .io_scan_mode(pic_ctrl_inst_io_scan_mode),
@@ -83011,7 +83055,7 @@ module quasar(
     .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt),
     .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend)
   );
-  dma_ctrl dma_ctrl ( // @[quasar.scala 128:24]
+  dma_ctrl dma_ctrl ( // @[quasar.scala 131:24]
     .clock(dma_ctrl_clock),
     .reset(dma_ctrl_reset),
     .io_free_clk(dma_ctrl_io_free_clk),
@@ -83098,7 +83142,7 @@ module quasar(
     .io_en(rvclkhdr_1_io_en),
     .io_scan_mode(rvclkhdr_1_io_scan_mode)
   );
-  axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 303:33]
+  axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 306:33]
     .clock(axi4_to_ahb_clock),
     .reset(axi4_to_ahb_reset),
     .io_scan_mode(axi4_to_ahb_io_scan_mode),
@@ -83112,7 +83156,7 @@ module quasar(
     .io_axi_awready(axi4_to_ahb_io_axi_awready),
     .io_axi_wready(axi4_to_ahb_io_axi_wready)
   );
-  axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 330:33]
+  axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 333:33]
     .clock(axi4_to_ahb_1_clock),
     .reset(axi4_to_ahb_1_reset),
     .io_scan_mode(axi4_to_ahb_1_io_scan_mode),
@@ -83126,7 +83170,7 @@ module quasar(
     .io_axi_awready(axi4_to_ahb_1_io_axi_awready),
     .io_axi_wready(axi4_to_ahb_1_io_axi_wready)
   );
-  axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 358:32]
+  axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 361:32]
     .clock(axi4_to_ahb_2_clock),
     .reset(axi4_to_ahb_2_reset),
     .io_scan_mode(axi4_to_ahb_2_io_scan_mode),
@@ -83140,7 +83184,7 @@ module quasar(
     .io_axi_awready(axi4_to_ahb_2_io_axi_awready),
     .io_axi_wready(axi4_to_ahb_2_io_axi_wready)
   );
-  ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 385:33]
+  ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 388:33]
     .clock(ahb_to_axi4_clock),
     .reset(ahb_to_axi4_reset),
     .io_scan_mode(ahb_to_axi4_io_scan_mode),
@@ -83149,513 +83193,513 @@ module quasar(
     .io_axi_arready(ahb_to_axi4_io_axi_arready),
     .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid),
     .io_axi_rresp(ahb_to_axi4_io_axi_rresp),
-    .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel),
-    .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin),
     .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid),
     .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid),
-    .io_ahb_in_hready(ahb_to_axi4_io_ahb_in_hready),
-    .io_ahb_in_hresp(ahb_to_axi4_io_ahb_in_hresp),
-    .io_ahb_out_haddr(ahb_to_axi4_io_ahb_out_haddr),
-    .io_ahb_out_hsize(ahb_to_axi4_io_ahb_out_hsize),
-    .io_ahb_out_htrans(ahb_to_axi4_io_ahb_out_htrans),
-    .io_ahb_out_hwrite(ahb_to_axi4_io_ahb_out_hwrite)
+    .io_ahb_sig_in_hready(ahb_to_axi4_io_ahb_sig_in_hready),
+    .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp),
+    .io_ahb_sig_out_haddr(ahb_to_axi4_io_ahb_sig_out_haddr),
+    .io_ahb_sig_out_hsize(ahb_to_axi4_io_ahb_sig_out_hsize),
+    .io_ahb_sig_out_htrans(ahb_to_axi4_io_ahb_sig_out_htrans),
+    .io_ahb_sig_out_hwrite(ahb_to_axi4_io_ahb_sig_out_hwrite),
+    .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel),
+    .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin)
   );
-  assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 292:14]
-  assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 292:14]
-  assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 292:14]
-  assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 292:14]
-  assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 292:14]
-  assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 292:14]
-  assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 292:14]
-  assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 292:14]
-  assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 292:14]
-  assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 292:14]
-  assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 292:14]
-  assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 292:14]
-  assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 295:14]
-  assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 295:14]
-  assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 295:14]
-  assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 295:14]
-  assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 295:14]
-  assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 295:14]
-  assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 295:14]
-  assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 295:14]
-  assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 239:17]
-  assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 239:17]
-  assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 239:17]
-  assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 239:17]
-  assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 239:17]
-  assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 239:17]
-  assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 239:17]
-  assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 239:17]
-  assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 239:17]
-  assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 239:17]
-  assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 239:17]
-  assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 239:17]
-  assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 239:17]
-  assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 296:14]
-  assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 296:14]
-  assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 296:14]
-  assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 296:14]
-  assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 296:14]
-  assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 296:14]
-  assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 296:14]
-  assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 296:14]
-  assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 296:14]
-  assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 296:14]
-  assign io_core_rst_l = reset & _T_2; // @[quasar.scala 130:17]
-  assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 271:19]
-  assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 271:19]
-  assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 274:24]
-  assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 275:23]
-  assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 276:31]
-  assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 277:21]
-  assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 278:24]
-  assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 279:20]
-  assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 280:26]
-  assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 281:25]
-  assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 282:24]
-  assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 283:25]
-  assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 284:23]
-  assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 285:23]
-  assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 286:23]
-  assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 287:23]
-  assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 289:11]
-  assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 289:11]
-  assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 289:11]
-  assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 289:11]
-  assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 289:11]
-  assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 289:11]
-  assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 289:11]
-  assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 289:11]
-  assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 151:13]
-  assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 151:13]
-  assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 151:13]
-  assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 151:13]
-  assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 151:13]
-  assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 151:13]
-  assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 151:13]
-  assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 151:13]
-  assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 151:13]
-  assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 151:13]
-  assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 151:13]
-  assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 151:13]
-  assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 151:13]
-  assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 151:13]
-  assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 152:15]
-  assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 152:15]
-  assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 152:15]
-  assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 152:15]
-  assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 152:15]
-  assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 152:15]
-  assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 152:15]
+  assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 295:14]
+  assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 295:14]
+  assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 295:14]
+  assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 295:14]
+  assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 295:14]
+  assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 295:14]
+  assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 295:14]
+  assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 295:14]
+  assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 295:14]
+  assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 295:14]
+  assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 295:14]
+  assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 295:14]
+  assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 298:14]
+  assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 298:14]
+  assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 298:14]
+  assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 298:14]
+  assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 298:14]
+  assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 298:14]
+  assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 242:17]
+  assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 242:17]
+  assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 242:17]
+  assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 242:17]
+  assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 242:17]
+  assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 242:17]
+  assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 242:17]
+  assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 242:17]
+  assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 242:17]
+  assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 242:17]
+  assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 242:17]
+  assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 242:17]
+  assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 242:17]
+  assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 299:14]
+  assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 299:14]
+  assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 299:14]
+  assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 299:14]
+  assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 299:14]
+  assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 299:14]
+  assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 299:14]
+  assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 299:14]
+  assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 299:14]
+  assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 299:14]
+  assign io_core_rst_l = reset & _T_2; // @[quasar.scala 133:17]
+  assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 274:19]
+  assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 274:19]
+  assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 277:24]
+  assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 278:23]
+  assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 279:31]
+  assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 280:21]
+  assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 281:24]
+  assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 282:20]
+  assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 283:26]
+  assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 284:25]
+  assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 285:24]
+  assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 286:25]
+  assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 287:23]
+  assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 288:23]
+  assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 289:23]
+  assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 290:23]
+  assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 292:11]
+  assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 292:11]
+  assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 292:11]
+  assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 292:11]
+  assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 292:11]
+  assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 292:11]
+  assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 292:11]
+  assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 292:11]
+  assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 154:13]
+  assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 154:13]
+  assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 154:13]
+  assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 154:13]
+  assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 154:13]
+  assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 154:13]
+  assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 154:13]
+  assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 154:13]
+  assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 154:13]
+  assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 154:13]
+  assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 154:13]
+  assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 154:13]
+  assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 154:13]
+  assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 154:13]
+  assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 155:15]
+  assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 155:15]
+  assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 155:15]
+  assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 155:15]
+  assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 155:15]
+  assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 155:15]
+  assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 155:15]
   assign ifu_clock = clock;
-  assign ifu_reset = io_core_rst_l; // @[quasar.scala 141:13]
-  assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 146:26]
-  assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 147:31]
-  assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 143:19]
-  assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 144:21]
-  assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 139:18 quasar.scala 157:51]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 139:18 quasar.scala 157:51]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 139:18 quasar.scala 157:51]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 139:18 quasar.scala 157:51]
-  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 139:18]
-  assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 139:18]
-  assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 153:25 quasar.scala 155:43]
-  assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 153:25 quasar.scala 154:42]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 153:25]
-  assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 153:25]
-  assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 152:15]
-  assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 152:15]
-  assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 151:13]
-  assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 151:13]
-  assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 151:13]
-  assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 151:13]
-  assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 151:13]
-  assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 151:13]
-  assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 427:25]
-  assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 428:24]
-  assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 429:26]
-  assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 430:28]
-  assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 431:28]
-  assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 149:25]
-  assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 150:18]
-  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 150:18]
-  assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 156:33]
-  assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 142:20]
+  assign ifu_reset = io_core_rst_l; // @[quasar.scala 144:13]
+  assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 149:26]
+  assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 150:31]
+  assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 146:19]
+  assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 147:21]
+  assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 142:18 quasar.scala 160:51]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 142:18 quasar.scala 160:51]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 142:18 quasar.scala 160:51]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 142:18 quasar.scala 160:51]
+  assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 142:18]
+  assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 142:18]
+  assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 156:25 quasar.scala 158:43]
+  assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 156:25 quasar.scala 157:42]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 156:25]
+  assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 156:25]
+  assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 155:15]
+  assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 155:15]
+  assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 154:13]
+  assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 154:13]
+  assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 154:13]
+  assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 154:13]
+  assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 154:13]
+  assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 154:13]
+  assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 298:14 quasar.scala 430:25]
+  assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 298:14 quasar.scala 431:24]
+  assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 298:14 quasar.scala 432:26]
+  assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 298:14 quasar.scala 433:28]
+  assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 298:14 quasar.scala 434:28]
+  assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 152:25]
+  assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 153:18]
+  assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 153:18]
+  assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:33]
+  assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 145:20]
   assign dec_clock = clock;
-  assign dec_reset = io_core_rst_l; // @[quasar.scala 160:13]
-  assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 161:19]
-  assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 162:21]
-  assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 163:32]
-  assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 164:18]
-  assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 165:18]
-  assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 166:18]
-  assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 167:25]
-  assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 168:24]
-  assign dec_io_core_id = io_core_id; // @[quasar.scala 169:18]
-  assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 170:29]
-  assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 171:28]
-  assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 172:28]
-  assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 175:31]
-  assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 178:23]
-  assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 179:24]
-  assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 180:30]
-  assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 182:23]
-  assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 183:26]
-  assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 183:26]
-  assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 183:26]
-  assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 183:26]
-  assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 183:26]
-  assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 183:26]
-  assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 184:36]
-  assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 185:25]
-  assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 186:23]
-  assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 187:23]
-  assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 188:28]
-  assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 189:29]
-  assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 190:30]
-  assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 191:28]
-  assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 192:26]
-  assign dec_io_timer_int = io_timer_int; // @[quasar.scala 198:20]
-  assign dec_io_soft_int = io_soft_int; // @[quasar.scala 194:19]
-  assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 195:23]
-  assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 196:25]
-  assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 197:26]
-  assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 199:20]
-  assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 139:18]
-  assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 139:18]
-  assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 202:18]
-  assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 202:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 173:18]
-  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 173:18]
-  assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 174:18]
-  assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 174:18]
-  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 181:18]
-  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 181:18]
-  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 181:18]
-  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 181:18]
-  assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 181:18]
-  assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 176:18]
-  assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 176:18]
-  assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 269:28]
-  assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 269:28]
-  assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 269:28]
-  assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 269:28]
+  assign dec_reset = io_core_rst_l; // @[quasar.scala 163:13]
+  assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 164:19]
+  assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 165:21]
+  assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 166:32]
+  assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 167:18]
+  assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 168:18]
+  assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 169:18]
+  assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 170:25]
+  assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 171:24]
+  assign dec_io_core_id = io_core_id; // @[quasar.scala 172:18]
+  assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 173:29]
+  assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 174:28]
+  assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 175:28]
+  assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 178:31]
+  assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 181:23]
+  assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 182:24]
+  assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 183:30]
+  assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 185:23]
+  assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 186:26]
+  assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 186:26]
+  assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 186:26]
+  assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 186:26]
+  assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 186:26]
+  assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 186:26]
+  assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 187:36]
+  assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 188:25]
+  assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 189:23]
+  assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 190:23]
+  assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 191:28]
+  assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 192:29]
+  assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 193:30]
+  assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 194:28]
+  assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 195:26]
+  assign dec_io_timer_int = io_timer_int; // @[quasar.scala 201:20]
+  assign dec_io_soft_int = io_soft_int; // @[quasar.scala 197:19]
+  assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 198:23]
+  assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 199:25]
+  assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 200:26]
+  assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 202:20]
+  assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 142:18]
+  assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 142:18]
+  assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 205:18]
+  assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 205:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 176:18]
+  assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 176:18]
+  assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 177:18]
+  assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 177:18]
+  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 184:18]
+  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 184:18]
+  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 184:18]
+  assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 184:18]
+  assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 184:18]
+  assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 179:18]
+  assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 179:18]
+  assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 272:28]
+  assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 272:28]
+  assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 272:28]
+  assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 272:28]
   assign dbg_clock = clock;
-  assign dbg_reset = io_core_rst_l; // @[quasar.scala 227:13]
-  assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 228:26]
-  assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 229:28]
-  assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 230:28]
-  assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 231:29]
-  assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 232:29]
-  assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 233:34]
-  assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 234:29]
-  assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 235:21]
-  assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 236:23]
-  assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 237:24]
-  assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 238:24]
-  assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 239:17 quasar.scala 434:28]
-  assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 239:17 quasar.scala 435:27]
-  assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 239:17 quasar.scala 436:27]
-  assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 239:17 quasar.scala 437:31]
-  assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 239:17 quasar.scala 438:28]
-  assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 239:17 quasar.scala 439:27]
-  assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 239:17 quasar.scala 441:31]
-  assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 239:17 quasar.scala 442:31]
-  assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 253:26]
-  assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 240:25]
-  assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 241:20]
-  assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 242:23]
-  assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 243:20]
+  assign dbg_reset = io_core_rst_l; // @[quasar.scala 230:13]
+  assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 231:26]
+  assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 232:28]
+  assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 233:28]
+  assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 234:29]
+  assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 235:29]
+  assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 236:34]
+  assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 237:29]
+  assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 238:21]
+  assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 239:23]
+  assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 240:24]
+  assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 241:24]
+  assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 242:17 quasar.scala 437:28]
+  assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 242:17 quasar.scala 438:27]
+  assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 242:17 quasar.scala 439:27]
+  assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 242:17 quasar.scala 440:31]
+  assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 242:17 quasar.scala 441:28]
+  assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 242:17 quasar.scala 442:27]
+  assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 242:17 quasar.scala 444:31]
+  assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 242:17 quasar.scala 445:31]
+  assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 256:26]
+  assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 243:25]
+  assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 244:20]
+  assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 245:23]
+  assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 246:20]
   assign exu_clock = clock;
-  assign exu_reset = io_core_rst_l; // @[quasar.scala 203:13]
-  assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 204:20]
-  assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 202:18]
-  assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 202:18]
-  assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 205:25]
+  assign exu_reset = io_core_rst_l; // @[quasar.scala 206:13]
+  assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 207:20]
+  assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 205:18]
+  assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 205:18]
+  assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 208:25]
   assign lsu_clock = clock;
-  assign lsu_reset = io_core_rst_l; // @[quasar.scala 208:13]
-  assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 209:23]
-  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 222:18]
-  assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 268:28]
-  assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 214:18]
-  assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 214:18]
-  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 173:18]
-  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 173:18]
-  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 173:18]
-  assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 289:11]
-  assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 289:11]
-  assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 292:14 quasar.scala 413:25]
-  assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 292:14 quasar.scala 414:24]
-  assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 292:14 quasar.scala 415:24]
-  assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 292:14 quasar.scala 416:28]
-  assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 292:14 quasar.scala 417:26]
-  assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 292:14 quasar.scala 418:25]
-  assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 292:14 quasar.scala 419:24]
-  assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 292:14 quasar.scala 420:26]
-  assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 292:14 quasar.scala 421:28]
-  assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 292:14 quasar.scala 422:28]
-  assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 210:32]
-  assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 211:35]
-  assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 212:29]
-  assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 213:35]
-  assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 215:27]
-  assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 216:16]
-  assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 216:16]
-  assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 219:26]
-  assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 219:26]
-  assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 217:30]
-  assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 218:26]
-  assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 221:25]
-  assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 223:20]
-  assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 224:19]
+  assign lsu_reset = io_core_rst_l; // @[quasar.scala 211:13]
+  assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 212:23]
+  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 225:18]
+  assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 271:28]
+  assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 217:18]
+  assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 217:18]
+  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 176:18]
+  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 176:18]
+  assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 176:18]
+  assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 292:11]
+  assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 292:11]
+  assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 295:14 quasar.scala 416:25]
+  assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 295:14 quasar.scala 417:24]
+  assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 295:14 quasar.scala 418:24]
+  assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 295:14 quasar.scala 419:28]
+  assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 295:14 quasar.scala 420:26]
+  assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 295:14 quasar.scala 421:25]
+  assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 295:14 quasar.scala 422:24]
+  assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 295:14 quasar.scala 423:26]
+  assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 295:14 quasar.scala 424:28]
+  assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 295:14 quasar.scala 425:28]
+  assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 213:32]
+  assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 214:35]
+  assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 215:29]
+  assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 216:35]
+  assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 218:27]
+  assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 219:16]
+  assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 219:16]
+  assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 222:26]
+  assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 222:26]
+  assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 220:30]
+  assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 221:26]
+  assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 224:25]
+  assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 226:20]
+  assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 227:19]
   assign pic_ctrl_inst_clock = clock;
-  assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 263:23]
-  assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 262:30]
-  assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 264:29]
-  assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 265:31]
-  assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 266:33]
-  assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 267:34]
-  assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 268:28]
-  assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 269:28]
-  assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 269:28]
+  assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 266:23]
+  assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 265:30]
+  assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 267:29]
+  assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 268:31]
+  assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 269:33]
+  assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 270:34]
+  assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 271:28]
+  assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 272:28]
+  assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 272:28]
   assign dma_ctrl_clock = clock;
-  assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 247:18]
-  assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 248:24]
-  assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 249:30]
-  assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 250:28]
-  assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 251:25]
-  assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 254:28]
-  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 252:23]
-  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 252:23]
-  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 252:23]
-  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 252:23]
-  assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 252:23]
-  assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 253:26]
-  assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 176:18]
-  assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 255:31]
-  assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 259:34]
-  assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 256:29]
-  assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 257:30]
-  assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 258:26]
-  assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 296:14 quasar.scala 444:34]
-  assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 296:14 quasar.scala 445:36]
-  assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 296:14 quasar.scala 446:38]
-  assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 296:14 quasar.scala 447:38]
-  assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 296:14 quasar.scala 448:33]
-  assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 296:14 quasar.scala 449:37]
-  assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 296:14 quasar.scala 450:37]
-  assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 296:14 quasar.scala 451:33]
-  assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 296:14 quasar.scala 452:34]
-  assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 296:14 quasar.scala 453:36]
-  assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 296:14 quasar.scala 454:38]
-  assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 296:14 quasar.scala 455:38]
-  assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 296:14 quasar.scala 456:33]
-  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 222:18]
-  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 222:18]
-  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 222:18]
-  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 222:18]
-  assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 222:18]
+  assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 250:18]
+  assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 251:24]
+  assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 252:30]
+  assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 253:28]
+  assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 254:25]
+  assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 257:28]
+  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 255:23]
+  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 255:23]
+  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 255:23]
+  assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 255:23]
+  assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 255:23]
+  assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 256:26]
+  assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 179:18]
+  assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 258:31]
+  assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 262:34]
+  assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 259:29]
+  assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 260:30]
+  assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 261:26]
+  assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 299:14 quasar.scala 447:34]
+  assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 299:14 quasar.scala 448:36]
+  assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 299:14 quasar.scala 449:38]
+  assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 299:14 quasar.scala 450:38]
+  assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 299:14 quasar.scala 451:33]
+  assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 299:14 quasar.scala 452:37]
+  assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 299:14 quasar.scala 453:37]
+  assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 299:14 quasar.scala 454:33]
+  assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 299:14 quasar.scala 455:34]
+  assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 299:14 quasar.scala 456:36]
+  assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 299:14 quasar.scala 457:38]
+  assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 299:14 quasar.scala 458:38]
+  assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 299:14 quasar.scala 459:33]
+  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 225:18]
+  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 225:18]
+  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 225:18]
+  assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 225:18]
+  assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 225:18]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
   assign rvclkhdr_io_en = 1'h1; // @[lib.scala 329:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
@@ -83664,48 +83708,48 @@ module quasar(
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
   assign axi4_to_ahb_clock = clock;
   assign axi4_to_ahb_reset = reset;
-  assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 305:34]
-  assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 306:35]
-  assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 307:37]
-  assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 304:36]
-  assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 313:35]
-  assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 317:35]
-  assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 319:36]
-  assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 325:35]
+  assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 308:34]
+  assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 309:35]
+  assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 310:37]
+  assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 307:36]
+  assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 316:35]
+  assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 320:35]
+  assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 322:36]
+  assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 328:35]
   assign axi4_to_ahb_1_clock = clock;
   assign axi4_to_ahb_1_reset = reset;
-  assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 332:34]
-  assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 333:35]
-  assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 334:37]
-  assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 331:36]
-  assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 340:35]
-  assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 344:35]
-  assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 346:36]
-  assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 352:35]
+  assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 335:34]
+  assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 336:35]
+  assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 337:37]
+  assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 334:36]
+  assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 343:35]
+  assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 347:35]
+  assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 349:36]
+  assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 355:35]
   assign axi4_to_ahb_2_clock = clock;
   assign axi4_to_ahb_2_reset = reset;
-  assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 360:33]
-  assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 361:34]
-  assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 362:36]
-  assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 359:35]
-  assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 368:34]
-  assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 372:34]
-  assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 374:35]
-  assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 380:34]
+  assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 363:33]
+  assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 364:34]
+  assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 365:36]
+  assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 362:35]
+  assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 371:34]
+  assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 375:34]
+  assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 377:35]
+  assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 383:34]
   assign ahb_to_axi4_clock = clock;
   assign ahb_to_axi4_reset = reset;
-  assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 386:34]
-  assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 387:35]
-  assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 389:36]
-  assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 396:36]
-  assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 397:35]
-  assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 400:34]
-  assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 411:33]
-  assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 412:37]
-  assign ahb_to_axi4_io_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar.scala 487:16]
-  assign ahb_to_axi4_io_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar.scala 487:16]
-  assign ahb_to_axi4_io_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar.scala 487:16]
-  assign ahb_to_axi4_io_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar.scala 487:16]
+  assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 389:34]
+  assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 390:35]
+  assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 392:36]
+  assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 399:36]
+  assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 400:35]
+  assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 403:34]
+  assign ahb_to_axi4_io_ahb_sig_out_haddr = io_dma_ahb_out_haddr; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_hsize = io_dma_ahb_out_hsize; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_htrans = io_dma_ahb_out_htrans; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_sig_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar.scala 490:16]
+  assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 414:33]
+  assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 415:37]
 endmodule
 module quasar_wrapper(
   input         clock,
@@ -83871,7 +83915,6 @@ module quasar_wrapper(
   output [63:0] io_dma_axi_r_bits_data,
   output [1:0]  io_dma_axi_r_bits_resp,
   output        io_dma_axi_r_bits_last,
-  input         io_dma_hsel,
   output [63:0] io_dma_ahb_in_hrdata,
   output        io_dma_ahb_in_hready,
   output        io_dma_ahb_in_hresp,
@@ -83883,6 +83926,7 @@ module quasar_wrapper(
   input  [1:0]  io_dma_ahb_out_htrans,
   input         io_dma_ahb_out_hwrite,
   input  [63:0] io_dma_ahb_out_hwdata,
+  input         io_dma_hsel,
   input         io_dma_hreadyin,
   input         io_lsu_bus_clk_en,
   input         io_ifu_bus_clk_en,
@@ -83923,243 +83967,243 @@ module quasar_wrapper(
   output [31:0] io_rv_trace_pkt_rv_i_tval_ip,
   input         io_scan_mode
 );
-  wire  mem_clk; // @[quasar_wrapper.scala 79:19]
-  wire  mem_rst_l; // @[quasar_wrapper.scala 79:19]
-  wire  mem_dccm_clk_override; // @[quasar_wrapper.scala 79:19]
-  wire  mem_icm_clk_override; // @[quasar_wrapper.scala 79:19]
-  wire  mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 79:19]
-  wire  mem_dccm_wren; // @[quasar_wrapper.scala 79:19]
-  wire  mem_dccm_rden; // @[quasar_wrapper.scala 79:19]
-  wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 79:19]
-  wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 79:19]
-  wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 79:19]
-  wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 79:19]
-  wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 79:19]
-  wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 79:19]
-  wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 79:19]
-  wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 79:19]
-  wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 79:19]
-  wire  mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 79:19]
-  wire  mem_iccm_correction_state; // @[quasar_wrapper.scala 79:19]
-  wire  mem_iccm_wren; // @[quasar_wrapper.scala 79:19]
-  wire  mem_iccm_rden; // @[quasar_wrapper.scala 79:19]
-  wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 79:19]
-  wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 79:19]
-  wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 79:19]
-  wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 79:19]
-  wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_rd_en; // @[quasar_wrapper.scala 79:19]
-  wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 79:19]
-  wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 79:19]
-  wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 79:19]
-  wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 79:19]
-  wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 79:19]
-  wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 79:19]
-  wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_tag_perr; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_debug_rd_en; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_debug_wr_en; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_debug_tag_array; // @[quasar_wrapper.scala 79:19]
-  wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 79:19]
-  wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 79:19]
-  wire  mem_ic_sel_premux_data; // @[quasar_wrapper.scala 79:19]
-  wire  mem_scan_mode; // @[quasar_wrapper.scala 79:19]
-  wire  dmi_wrapper_trst_n; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_tck; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_tms; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_tdi; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_tdo; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_core_clk; // @[quasar_wrapper.scala 80:27]
-  wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 80:27]
-  wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 80:27]
-  wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 80:27]
-  wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_reg_en; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:27]
-  wire  dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 80:27]
-  wire  swerv_clock; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_reset; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 81:21]
-  wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_nmi_int; // @[quasar_wrapper.scala 81:21]
-  wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_core_rst_l; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 81:21]
-  wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_icm_clk_override; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 81:21]
-  wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dccm_wren; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dccm_rden; // @[quasar_wrapper.scala 81:21]
-  wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 81:21]
-  wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 81:21]
-  wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 81:21]
-  wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 81:21]
-  wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 81:21]
-  wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 81:21]
-  wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 81:21]
-  wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 81:21]
-  wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_rd_en; // @[quasar_wrapper.scala 81:21]
-  wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 81:21]
-  wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 81:21]
-  wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 81:21]
-  wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 81:21]
-  wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 81:21]
-  wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 81:21]
-  wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 81:21]
-  wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_iccm_wren; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_iccm_rden; // @[quasar_wrapper.scala 81:21]
-  wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 81:21]
-  wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 81:21]
-  wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 81:21]
-  wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_hsel; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 81:21]
-  wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 81:21]
-  wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 81:21]
-  wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_timer_int; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_soft_int; // @[quasar_wrapper.scala 81:21]
-  wire  swerv_io_scan_mode; // @[quasar_wrapper.scala 81:21]
-  mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 79:19]
+  wire  mem_clk; // @[quasar_wrapper.scala 82:19]
+  wire  mem_rst_l; // @[quasar_wrapper.scala 82:19]
+  wire  mem_dccm_clk_override; // @[quasar_wrapper.scala 82:19]
+  wire  mem_icm_clk_override; // @[quasar_wrapper.scala 82:19]
+  wire  mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 82:19]
+  wire  mem_dccm_wren; // @[quasar_wrapper.scala 82:19]
+  wire  mem_dccm_rden; // @[quasar_wrapper.scala 82:19]
+  wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 82:19]
+  wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 82:19]
+  wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 82:19]
+  wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 82:19]
+  wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 82:19]
+  wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 82:19]
+  wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 82:19]
+  wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 82:19]
+  wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 82:19]
+  wire  mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 82:19]
+  wire  mem_iccm_correction_state; // @[quasar_wrapper.scala 82:19]
+  wire  mem_iccm_wren; // @[quasar_wrapper.scala 82:19]
+  wire  mem_iccm_rden; // @[quasar_wrapper.scala 82:19]
+  wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 82:19]
+  wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 82:19]
+  wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 82:19]
+  wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 82:19]
+  wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_rd_en; // @[quasar_wrapper.scala 82:19]
+  wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 82:19]
+  wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 82:19]
+  wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 82:19]
+  wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 82:19]
+  wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 82:19]
+  wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 82:19]
+  wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_tag_perr; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_debug_rd_en; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_debug_wr_en; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_debug_tag_array; // @[quasar_wrapper.scala 82:19]
+  wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 82:19]
+  wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 82:19]
+  wire  mem_ic_sel_premux_data; // @[quasar_wrapper.scala 82:19]
+  wire  mem_scan_mode; // @[quasar_wrapper.scala 82:19]
+  wire  dmi_wrapper_trst_n; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_tck; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_tms; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_tdi; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_tdo; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_core_clk; // @[quasar_wrapper.scala 83:27]
+  wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 83:27]
+  wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 83:27]
+  wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 83:27]
+  wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_reg_en; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 83:27]
+  wire  dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 83:27]
+  wire  swerv_clock; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_reset; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_hsel; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 84:21]
+  wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_nmi_int; // @[quasar_wrapper.scala 84:21]
+  wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_core_rst_l; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 84:21]
+  wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_icm_clk_override; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 84:21]
+  wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dccm_wren; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dccm_rden; // @[quasar_wrapper.scala 84:21]
+  wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 84:21]
+  wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 84:21]
+  wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 84:21]
+  wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 84:21]
+  wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 84:21]
+  wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 84:21]
+  wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 84:21]
+  wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 84:21]
+  wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_rd_en; // @[quasar_wrapper.scala 84:21]
+  wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 84:21]
+  wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 84:21]
+  wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 84:21]
+  wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 84:21]
+  wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 84:21]
+  wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 84:21]
+  wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 84:21]
+  wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_iccm_wren; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_iccm_rden; // @[quasar_wrapper.scala 84:21]
+  wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 84:21]
+  wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 84:21]
+  wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 84:21]
+  wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 84:21]
+  wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 84:21]
+  wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 84:21]
+  wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_timer_int; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_soft_int; // @[quasar_wrapper.scala 84:21]
+  wire  swerv_io_scan_mode; // @[quasar_wrapper.scala 84:21]
+  mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 82:19]
     .clk(mem_clk),
     .rst_l(mem_rst_l),
     .dccm_clk_override(mem_dccm_clk_override),
@@ -84207,7 +84251,7 @@ module quasar_wrapper(
     .ic_sel_premux_data(mem_ic_sel_premux_data),
     .scan_mode(mem_scan_mode)
   );
-  dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 80:27]
+  dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 83:27]
     .trst_n(dmi_wrapper_trst_n),
     .tck(dmi_wrapper_tck),
     .tms(dmi_wrapper_tms),
@@ -84224,7 +84268,7 @@ module quasar_wrapper(
     .reg_wr_en(dmi_wrapper_reg_wr_en),
     .dmi_hard_reset(dmi_wrapper_dmi_hard_reset)
   );
-  quasar swerv ( // @[quasar_wrapper.scala 81:21]
+  quasar swerv ( // @[quasar_wrapper.scala 84:21]
     .clock(swerv_clock),
     .reset(swerv_reset),
     .io_lsu_axi_aw_ready(swerv_io_lsu_axi_aw_ready),
@@ -84315,6 +84359,8 @@ module quasar_wrapper(
     .io_dma_ahb_out_hsize(swerv_io_dma_ahb_out_hsize),
     .io_dma_ahb_out_htrans(swerv_io_dma_ahb_out_htrans),
     .io_dma_ahb_out_hwrite(swerv_io_dma_ahb_out_hwrite),
+    .io_dma_hsel(swerv_io_dma_hsel),
+    .io_dma_hreadyin(swerv_io_dma_hreadyin),
     .io_dbg_rst_l(swerv_io_dbg_rst_l),
     .io_rst_vec(swerv_io_rst_vec),
     .io_nmi_int(swerv_io_nmi_int),
@@ -84386,8 +84432,6 @@ module quasar_wrapper(
     .io_iccm_wr_data(swerv_io_iccm_wr_data),
     .io_iccm_rd_data(swerv_io_iccm_rd_data),
     .io_iccm_rd_data_ecc(swerv_io_iccm_rd_data_ecc),
-    .io_dma_hsel(swerv_io_dma_hsel),
-    .io_dma_hreadyin(swerv_io_dma_hreadyin),
     .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en),
     .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en),
     .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en),
@@ -84401,240 +84445,240 @@ module quasar_wrapper(
     .io_soft_int(swerv_io_soft_int),
     .io_scan_mode(swerv_io_scan_mode)
   );
-  assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:20]
-  assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:20]
-  assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20]
-  assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 147:20]
-  assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:19]
-  assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 150:19]
-  assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 154:20]
-  assign io_dma_ahb_in_hrdata = 64'h0; // @[quasar_wrapper.scala 115:19]
-  assign io_dma_ahb_in_hready = 1'h0; // @[quasar_wrapper.scala 115:19]
-  assign io_dma_ahb_in_hresp = 1'h0; // @[quasar_wrapper.scala 115:19]
-  assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 208:23]
-  assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 209:23]
-  assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 210:23]
-  assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 211:23]
-  assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 97:15]
-  assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 204:25]
-  assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 205:24]
-  assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 206:25]
-  assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 199:21]
-  assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 200:24]
-  assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 202:26]
-  assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 201:20]
-  assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 196:19]
-  assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 196:19]
-  assign mem_clk = clock; // @[quasar_wrapper.scala 105:14]
-  assign mem_rst_l = reset; // @[quasar_wrapper.scala 104:16]
-  assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 100:28]
-  assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 101:27]
-  assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 102:35]
-  assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 103:15]
-  assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 103:15]
-  assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 110:17]
-  assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 110:17]
-  assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 109:15]
-  assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 109:15]
-  assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 106:20]
-  assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 82:25]
-  assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 83:22]
-  assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 84:22]
-  assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 85:22]
-  assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 91:29]
-  assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 86:27]
-  assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 87:26]
-  assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 88:26]
+  assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 147:20]
+  assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 147:20]
+  assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 150:20]
+  assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 150:20]
+  assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 153:19]
+  assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 153:19]
+  assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 157:20]
+  assign io_dma_ahb_in_hrdata = 64'h0; // @[quasar_wrapper.scala 118:19]
+  assign io_dma_ahb_in_hready = 1'h0; // @[quasar_wrapper.scala 118:19]
+  assign io_dma_ahb_in_hresp = 1'h0; // @[quasar_wrapper.scala 118:19]
+  assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 211:23]
+  assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 212:23]
+  assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 213:23]
+  assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 214:23]
+  assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 100:15]
+  assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 207:25]
+  assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 208:24]
+  assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 209:25]
+  assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 202:21]
+  assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 203:24]
+  assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 205:26]
+  assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 204:20]
+  assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 199:19]
+  assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 199:19]
+  assign mem_clk = clock; // @[quasar_wrapper.scala 108:14]
+  assign mem_rst_l = reset; // @[quasar_wrapper.scala 107:16]
+  assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 103:28]
+  assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 104:27]
+  assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 105:35]
+  assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 106:15]
+  assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 106:15]
+  assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 113:17]
+  assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 113:17]
+  assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 112:15]
+  assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 112:15]
+  assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 109:20]
+  assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 85:25]
+  assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 86:22]
+  assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 87:22]
+  assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 88:22]
+  assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 94:29]
+  assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 89:27]
+  assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 90:26]
+  assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 91:26]
   assign swerv_clock = clock;
   assign swerv_reset = reset;
-  assign swerv_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 144:20]
-  assign swerv_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 147:20]
-  assign swerv_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 147:20]
-  assign swerv_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 147:20]
-  assign swerv_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 147:20]
-  assign swerv_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 147:20]
-  assign swerv_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 150:19]
-  assign swerv_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 154:20]
-  assign swerv_io_dma_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 158:24]
-  assign swerv_io_dma_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 158:24]
-  assign swerv_io_dma_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 158:24]
-  assign swerv_io_dma_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 158:24]
-  assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 108:22 quasar_wrapper.scala 127:22]
-  assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 128:20]
-  assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 129:20]
-  assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 130:20]
-  assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 133:27]
-  assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 134:26]
-  assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 135:20]
-  assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 138:31]
-  assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 139:30]
-  assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 140:30]
-  assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 103:15]
-  assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 103:15]
-  assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 109:15]
-  assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 110:17]
-  assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 110:17]
-  assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 157:21]
-  assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 167:25]
-  assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 185:27]
-  assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 186:27]
-  assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 187:27]
-  assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 188:27]
-  assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 94:23]
-  assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 93:25]
-  assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 95:26]
-  assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 92:26]
-  assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 192:26]
-  assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 190:22]
-  assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 191:21]
-  assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 125:22]
+  assign swerv_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 147:20]
+  assign swerv_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 150:20]
+  assign swerv_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 150:20]
+  assign swerv_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 150:20]
+  assign swerv_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 150:20]
+  assign swerv_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 150:20]
+  assign swerv_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 153:19]
+  assign swerv_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 157:20]
+  assign swerv_io_dma_ahb_out_haddr = io_dma_ahb_out_haddr; // @[quasar_wrapper.scala 161:24]
+  assign swerv_io_dma_ahb_out_hsize = io_dma_ahb_out_hsize; // @[quasar_wrapper.scala 161:24]
+  assign swerv_io_dma_ahb_out_htrans = io_dma_ahb_out_htrans; // @[quasar_wrapper.scala 161:24]
+  assign swerv_io_dma_ahb_out_hwrite = io_dma_ahb_out_hwrite; // @[quasar_wrapper.scala 161:24]
+  assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 160:21]
+  assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 170:25]
+  assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 111:22 quasar_wrapper.scala 130:22]
+  assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 131:20]
+  assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 132:20]
+  assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 133:20]
+  assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 136:27]
+  assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 137:26]
+  assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 138:20]
+  assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 141:31]
+  assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 142:30]
+  assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 143:30]
+  assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 106:15]
+  assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 106:15]
+  assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 112:15]
+  assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 113:17]
+  assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 113:17]
+  assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 188:27]
+  assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 189:27]
+  assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 190:27]
+  assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 191:27]
+  assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 97:23]
+  assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 96:25]
+  assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 98:26]
+  assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 95:26]
+  assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 195:26]
+  assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 193:22]
+  assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 194:21]
+  assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 128:22]
 endmodule
diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala
index 84b4c230..80b5fbca 100644
--- a/src/main/scala/dbg/dbg.scala
+++ b/src/main/scala/dbg/dbg.scala
@@ -311,7 +311,7 @@ class dbg extends Module with lib with RequireAsyncReset {
     Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
     Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
     Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
-0
+  0
   dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) {
     RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
   } // dbg_state_reg
@@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_write     := io.dbg_dec.dbg_ib.dbg_cmd_write
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
+object dgb extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
+}
\ No newline at end of file
diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala
index 14fffb3a..526f1c24 100644
--- a/src/main/scala/dec/dec_decode_ctl.scala
+++ b/src/main/scala/dec/dec_decode_ctl.scala
@@ -10,263 +10,257 @@ import lsu._
 
 class dec_decode_ctl extends Module with lib with RequireAsyncReset{
   val io = IO(new Bundle{
-    val decode_exu = Flipped(new decode_exu)
-    val dec_alu = Flipped(new dec_alu)
-    val dec_div = Flipped(new dec_div)
-    val dctl_busbuff = Flipped(new dctl_busbuff())
-    val dctl_dma = new dctl_dma
-    val dec_tlu_flush_extint          = Input(Bool())
-    val dec_tlu_force_halt            = Input(Bool()) // invalidate nonblock load cam on a force halt event
-    val dec_i0_inst_wb1               = Output(UInt(32.W))      // 32b instruction at wb+1 for trace encoder
-    val dec_i0_pc_wb1                 = Output(UInt(31.W))      // 31b pc at wb+1 for trace encoder
-    val dec_i0_trigger_match_d        = Input(UInt(4.W))         // i0 decode trigger matches
-    val dec_tlu_wr_pause_r         =   Input(Bool())           // pause instruction at r
-    val dec_tlu_pipelining_disable =   Input(Bool())           // pipeline disable - presync, i0 decode only
-    val lsu_trigger_match_m        =   Input(UInt(4.W))     // lsu trigger matches
-    val lsu_pmu_misaligned_m       =   Input(Bool())            // perf mon: load/store misalign
-    val dec_tlu_debug_stall        =   Input(Bool())            // debug stall decode
-    val dec_tlu_flush_leak_one_r   =   Input(Bool())            // leak1 instruction
-    val dec_debug_fence_d          =   Input(Bool())            // debug fence instruction
-    val dec_i0_icaf_d              =   Input(Bool())            // icache access fault
-    val dec_i0_icaf_f1_d           =   Input(Bool())            // i0 instruction access fault at decode for f1 fetch group
-    val dec_i0_icaf_type_d         =   Input(UInt(2.W))      // i0 instruction access fault type
-    val dec_i0_dbecc_d             =   Input(Bool())            // icache/iccm double-bit error
-    val dec_i0_brp                 =   Flipped(Valid(new br_pkt_t))          // branch packet
-    val dec_i0_bp_index            =   Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))    // i0 branch index
-    val dec_i0_bp_fghr             =   Input(UInt(BHT_GHR_SIZE.W))   // BP FGHR
-    val dec_i0_bp_btag             =   Input(UInt(BTB_BTAG_SIZE.W))   // BP tag
-    val dec_i0_pc_d                =   Input(UInt(31.W))    // pc
-    val lsu_idle_any               =   Input(Bool())        // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
-    val lsu_load_stall_any         =   Input(Bool())              // stall any load at decode
-    val lsu_store_stall_any        =   Input(Bool())              // stall any store at decode6
-    val exu_div_wren               =   Input(Bool())           // nonblocking divide write enable to GPR.
-    val dec_tlu_i0_kill_writeb_wb  =   Input(Bool())           // I0 is flushed, don't writeback any results to arch state
-    val dec_tlu_flush_lower_wb     =   Input(Bool())           // trap lower flush
-    val dec_tlu_i0_kill_writeb_r   =   Input(Bool())           // I0 is flushed, don't writeback any results to arch state
-    val dec_tlu_flush_lower_r      =   Input(Bool())           // trap lower flush
-    val dec_tlu_flush_pause_r      =   Input(Bool())           // don't clear pause state on initial lower flush
-    val dec_tlu_presync_d          =   Input(Bool())           // CSR read needs to be presync'd
-    val dec_tlu_postsync_d         =   Input(Bool())           // CSR ops that need to be postsync'd
-    val dec_i0_pc4_d               =   Input(Bool())           // inst is 4B inst else 2B
-    val dec_csr_rddata_d           =   Input(UInt(32.W)) // csr read data at wb
-    val dec_csr_legal_d            =   Input(Bool())           // csr indicates legal operation
-    val lsu_result_m               =   Input(UInt(32.W))    // load result
-    val lsu_result_corr_r          =   Input(UInt(32.W))   // load result - corrected data for writing gpr's, not for bypassing
-    val exu_flush_final            =   Input(Bool())           // lower flush or i0 flush at X or D
-    val dec_i0_instr_d             =   Input(UInt(32.W))    // inst at decode
-    val dec_ib0_valid_d            =   Input(Bool())          // inst valid at decode
-    val free_clk                   =   Input(Clock())
-    val active_clk                 =   Input(Clock())              // clk except for halt / pause
-    val clk_override               =   Input(Bool())              // test stuff
-    val dec_i0_rs1_d               =   Output(UInt(5.W))    // rs1 logical source
-    val dec_i0_rs2_d               =   Output(UInt(5.W))
-    val dec_i0_waddr_r             =   Output(UInt(5.W))   // i0 logical source to write to gpr's
-    val dec_i0_wen_r               =   Output(Bool())   // i0 write enable
-    val dec_i0_wdata_r             =   Output(UInt(32.W))   // i0 write data
-    val lsu_p                      =   Valid(new lsu_pkt_t) // load/store packet
-    val div_waddr_wb               =   Output(UInt(5.W)) // DIV write address to GPR
-    val dec_lsu_valid_raw_d        =   Output(Bool())
-    val dec_lsu_offset_d           =   Output(UInt(12.W))
-    val dec_csr_wen_unq_d          =   Output(Bool())   // valid csr with write - for csr legal
-    val dec_csr_any_unq_d          =   Output(Bool())   // valid csr - for csr legal
-    val dec_csr_rdaddr_d           =   Output(UInt(12.W))   // read address for csr
-    val dec_csr_wen_r              =   Output(Bool())   // csr write enable at r
-    val dec_csr_wraddr_r           =   Output(UInt(12.W))   // write address for csr
-    val dec_csr_wrdata_r           =   Output(UInt(32.W))   // csr write data at r
-    val dec_csr_stall_int_ff       =   Output(Bool())   // csr is mie/mstatus
-    val dec_tlu_i0_valid_r         =   Output(Bool())   // i0 valid inst at c
-    val dec_tlu_packet_r           =   Output(new trap_pkt_t)   // trap packet
-    val dec_tlu_i0_pc_r            =   Output(UInt(31.W))   // i0 trap pc
-    val dec_illegal_inst           =   Output(UInt(32.W))   // illegal inst
-    val dec_pmu_instr_decoded      =   Output(Bool())    // number of instructions decode this cycle encoded
-    val dec_pmu_decode_stall       =   Output(Bool())    // decode is stalled
-    val dec_pmu_presync_stall      =   Output(Bool())    // decode has presync stall
-    val dec_pmu_postsync_stall     =   Output(Bool())    // decode has postsync stall
-    val dec_nonblock_load_wen      =   Output(Bool())    // write enable for nonblock load
-    val dec_nonblock_load_waddr    =   Output(UInt(5.W))    // logical write addr for nonblock load
-    val dec_pause_state            =   Output(Bool())    // core in pause state
-    val dec_pause_state_cg         =   Output(Bool())    // pause state for clock-gating
-    val dec_div_active             =   Output(Bool())    // non-block divide is active
-    val scan_mode                  =   Input(Bool())
-
-    val dec_aln = Flipped(new aln_dec)
-    val dbg_dctl = new dbg_dctl()
+    val decode_exu                    =   Flipped(new decode_exu)     //connection with exu top
+    val dec_alu                       =   Flipped(new dec_alu)        //connection with alu
+    val dec_div                       =   Flipped(new dec_div)        //connection with divider
+    val dctl_busbuff                  =   Flipped(new dctl_busbuff()) //connection with bus buffer
+    val dctl_dma                      =   new dctl_dma                //connection with dma
+    val dec_aln                       =   Flipped(new aln_dec)        //connection with aligner
+    val dbg_dctl                      =   new dbg_dctl()              //connection with dbg
+    val dec_tlu_flush_extint          =   Input(Bool())
+    val dec_tlu_force_halt            =   Input(Bool()) // invalidate nonblock load cam on a force halt event
+    val dec_i0_inst_wb1               =   Output(UInt(32.W))      // 32b instruction at wb+1 for trace encoder
+    val dec_i0_pc_wb1                 =   Output(UInt(31.W))      // 31b pc at wb+1 for trace encoder
+    val dec_i0_trigger_match_d        =   Input(UInt(4.W))         // i0 decode trigger matches
+    val dec_tlu_wr_pause_r            =   Input(Bool())           // pause instruction at r
+    val dec_tlu_pipelining_disable    =   Input(Bool())           // pipeline disable - presync, i0 decode only
+    val lsu_trigger_match_m           =   Input(UInt(4.W))     // lsu trigger matches
+    val lsu_pmu_misaligned_m          =   Input(Bool())            // perf mon: load/store misalign
+    val dec_tlu_debug_stall           =   Input(Bool())            // debug stall decode
+    val dec_tlu_flush_leak_one_r      =   Input(Bool())            // leak1 instruction
+    val dec_debug_fence_d             =   Input(Bool())            // debug fence instruction
+    val dec_i0_icaf_d                 =   Input(Bool())            // icache access fault
+    val dec_i0_icaf_f1_d              =   Input(Bool())            // i0 instruction access fault at decode for f1 fetch group
+    val dec_i0_icaf_type_d            =   Input(UInt(2.W))      // i0 instruction access fault type
+    val dec_i0_dbecc_d                =   Input(Bool())            // icache/iccm double-bit error
+    val dec_i0_brp                    =   Flipped(Valid(new br_pkt_t))          // branch packet
+    val dec_i0_bp_index               =   Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))    // i0 branch index
+    val dec_i0_bp_fghr                =   Input(UInt(BHT_GHR_SIZE.W))   // BP FGHR
+    val dec_i0_bp_btag                =   Input(UInt(BTB_BTAG_SIZE.W))   // BP tag
+    val dec_i0_pc_d                   =   Input(UInt(31.W))    // pc
+    val lsu_idle_any                  =   Input(Bool())        // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
+    val lsu_load_stall_any            =   Input(Bool())              // stall any load at decode
+    val lsu_store_stall_any           =   Input(Bool())              // stall any store at decode6
+    val exu_div_wren                  =   Input(Bool())           // nonblocking divide write enable to GPR.
+    val dec_tlu_i0_kill_writeb_wb     =   Input(Bool())           // I0 is flushed, don't writeback any results to arch state
+    val dec_tlu_flush_lower_wb        =   Input(Bool())           // trap lower flush
+    val dec_tlu_i0_kill_writeb_r      =   Input(Bool())           // I0 is flushed, don't writeback any results to arch state
+    val dec_tlu_flush_lower_r         =   Input(Bool())           // trap lower flush
+    val dec_tlu_flush_pause_r         =   Input(Bool())           // don't clear pause state on initial lower flush
+    val dec_tlu_presync_d             =   Input(Bool())           // CSR read needs to be presync'd
+    val dec_tlu_postsync_d            =   Input(Bool())           // CSR ops that need to be postsync'd
+    val dec_i0_pc4_d                  =   Input(Bool())           // inst is 4B inst else 2B
+    val dec_csr_rddata_d              =   Input(UInt(32.W)) // csr read data at wb
+    val dec_csr_legal_d               =   Input(Bool())           // csr indicates legal operation
+    val lsu_result_m                  =   Input(UInt(32.W))    // load result
+    val lsu_result_corr_r             =   Input(UInt(32.W))   // load result - corrected data for writing gpr's, not for bypassing
+    val exu_flush_final               =   Input(Bool())           // lower flush or i0 flush at X or D
+    val dec_i0_instr_d                =   Input(UInt(32.W))    // inst at decode
+    val dec_ib0_valid_d               =   Input(Bool())          // inst valid at decode
+    val free_clk                      =   Input(Clock())
+    val active_clk                    =   Input(Clock())              // clk except for halt / pause
+    val clk_override                  =   Input(Bool())              // test stuff
+    val dec_i0_rs1_d                  =   Output(UInt(5.W))    // rs1 logical source
+    val dec_i0_rs2_d                  =   Output(UInt(5.W))
+    val dec_i0_waddr_r                =   Output(UInt(5.W))   // i0 logical source to write to gpr's
+    val dec_i0_wen_r                  =   Output(Bool())   // i0 write enable
+    val dec_i0_wdata_r                =   Output(UInt(32.W))   // i0 write data
+    val lsu_p                         =   Valid(new lsu_pkt_t) // load/store packet
+    val div_waddr_wb                  =   Output(UInt(5.W)) // DIV write address to GPR
+    val dec_lsu_valid_raw_d           =   Output(Bool())
+    val dec_lsu_offset_d              =   Output(UInt(12.W))
+    val dec_csr_wen_unq_d             =   Output(Bool())   // valid csr with write - for csr legal
+    val dec_csr_any_unq_d             =   Output(Bool())   // valid csr - for csr legal
+    val dec_csr_rdaddr_d              =   Output(UInt(12.W))   // read address for csr
+    val dec_csr_wen_r                 =   Output(Bool())   // csr write enable at r
+    val dec_csr_wraddr_r              =   Output(UInt(12.W))   // write address for csr
+    val dec_csr_wrdata_r              =   Output(UInt(32.W))   // csr write data at r
+    val dec_csr_stall_int_ff          =   Output(Bool())   // csr is mie/mstatus
+    val dec_tlu_i0_valid_r            =   Output(Bool())   // i0 valid inst at c
+    val dec_tlu_packet_r              =   Output(new trap_pkt_t)   // trap packet
+    val dec_tlu_i0_pc_r               =   Output(UInt(31.W))   // i0 trap pc
+    val dec_illegal_inst              =   Output(UInt(32.W))   // illegal inst
+    val dec_pmu_instr_decoded         =   Output(Bool())    // number of instructions decode this cycle encoded
+    val dec_pmu_decode_stall          =   Output(Bool())    // decode is stalled
+    val dec_pmu_presync_stall         =   Output(Bool())    // decode has presync stall
+    val dec_pmu_postsync_stall        =   Output(Bool())    // decode has postsync stall
+    val dec_nonblock_load_wen         =   Output(Bool())    // write enable for nonblock load
+    val dec_nonblock_load_waddr       =   Output(UInt(5.W))    // logical write addr for nonblock load
+    val dec_pause_state               =   Output(Bool())    // core in pause state
+    val dec_pause_state_cg            =   Output(Bool())    // pause state for clock-gating
+    val dec_div_active                =   Output(Bool())    // non-block divide is active
+    val scan_mode                     =   Input(Bool())
 })
-  /////////////////////////////////////////////////////////////////////////////////////////
-//  //packets zero initialization
-  io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p)
+  //packets zero initialization
+  io.decode_exu.mul_p   := 0.U.asTypeOf(io.decode_exu.mul_p)
   // Vals defined
-  val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
-  val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
-  val i0r = Wire(new reg_pkt_t)
-  val d_t = Wire(new trap_pkt_t)
-  val x_t = Wire(new trap_pkt_t)
-  val x_t_in = Wire(new trap_pkt_t)
-  val r_t = Wire(new trap_pkt_t)
-  val r_t_in    = Wire(new trap_pkt_t)
-  val d_d = Wire(Valid(new dest_pkt_t))
-  val x_d = Wire(Valid(new dest_pkt_t))
-  val r_d = Wire(Valid(new dest_pkt_t))
-  val r_d_in = Wire(Valid(new dest_pkt_t))
-  val wbd = Wire(Valid(new dest_pkt_t))
-  val i0_d_c = Wire(new class_pkt_t)
-  val i0_rs1_class_d = Wire(new class_pkt_t)
-  val i0_rs2_class_d = Wire(new class_pkt_t)
-  val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
-  val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
-  val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
-  val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
-  val cam_write=WireInit(UInt(1.W), 0.U)
-  val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
-  val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
-  val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
-  val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
-  val cam_in  =Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
-  //val i0_temp = Wire(new inst_pkt_t)
-  val i0_dp= Wire(new dec_pkt_t)
-  val i0_dp_raw= Wire(new dec_pkt_t)
-  val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
-  val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
-  val illegal_lockout = WireInit(UInt(1.W), 0.U)
-  val postsync_stall = WireInit(UInt(1.W), 0.U)
-  val ps_stall_in = WireInit(UInt(1.W), 0.U)
-  val i0_pipe_en = WireInit(UInt(4.W), 0.U)
-  val i0_load_block_d = WireInit(UInt(1.W), 0.U)
-  val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U)
-  val store_data_bypass_d = WireInit(UInt(1.W), 0.U)
-  val store_data_bypass_m = WireInit(UInt(1.W), 0.U)
-  val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U)
-  val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U)
-  val leak1_i1_stall = WireInit(UInt(1.W), 0.U)
-  val leak1_i0_stall = WireInit(UInt(1.W), 0.U)
-  val pause_state = WireInit(Bool(), 0.B)
-  val flush_final_r =  WireInit(UInt(1.W), 0.U)
-  val illegal_lockout_in = WireInit(UInt(1.W), 0.U)
-  val lsu_idle = WireInit(Bool(), 0.B)
-  val pause_state_in =  WireInit(Bool(), 0.B)
-  val leak1_mode = WireInit(UInt(1.W), 0.U)
-  val  i0_pcall = WireInit(UInt(1.W), 0.U)
-  val  i0_pja = WireInit(UInt(1.W), 0.U)
-  val i0_pret = WireInit(UInt(1.W), 0.U)
-  val i0_legal_decode_d = WireInit(UInt(1.W), 0.U)
-  val  i0_pcall_raw = WireInit(UInt(1.W), 0.U)
-  val  i0_pja_raw = WireInit(UInt(1.W), 0.U)
-  val i0_pret_raw = WireInit(UInt(1.W), 0.U)
-  val i0_br_offset = WireInit(UInt(12.W), 0.U)
-  val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U)
-  val i0_jal = WireInit(UInt(1.W), 0.U)
-  val i0_wen_r = WireInit(UInt(1.W), 0.U)
-  val i0_x_ctl_en    = WireInit(UInt(1.W), 0.U)
-  val i0_r_ctl_en    = WireInit(UInt(1.W), 0.U)
-  val i0_wb_ctl_en   = WireInit(UInt(1.W), 0.U)
-  val i0_x_data_en   = WireInit(UInt(1.W), 0.U)
-  val i0_r_data_en   = WireInit(UInt(1.W), 0.U)
-  val i0_wb_data_en  = WireInit(UInt(1.W), 0.U)
-  val i0_wb1_data_en = WireInit(UInt(1.W), 0.U)
-  val  i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U)
-  val csr_ren_qual_d = WireInit(Bool(), 0.B)
-  val lsu_decode_d = WireInit(UInt(1.W), 0.U)
-  val mul_decode_d = WireInit(UInt(1.W), 0.U)
-  val div_decode_d = WireInit(UInt(1.W), 0.U)
-  val write_csr_data = WireInit(UInt(32.W),0.U)
-  val i0_result_corr_r = WireInit(UInt(32.W),0.U)
-  val presync_stall = WireInit(UInt(1.W), 0.U)
-  val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U)
-  val debug_fence = WireInit(Bool(), 0.B)
-  val i0_immed_d = WireInit(UInt(32.W), 0.U)
-  val i0_result_x = WireInit(UInt(32.W), 0.U)
-  val i0_result_r = WireInit(UInt(32.W), 0.U)
+  val leak1_i1_stall_in       = WireInit(UInt(1.W), 0.U)
+  val leak1_i0_stall_in       = WireInit(UInt(1.W), 0.U)
+  val i0r                     = Wire(new reg_pkt_t)
+  val d_t                     = Wire(new trap_pkt_t)
+  val x_t                     = Wire(new trap_pkt_t)
+  val x_t_in                  = Wire(new trap_pkt_t)
+  val r_t                     = Wire(new trap_pkt_t)
+  val r_t_in                  = Wire(new trap_pkt_t)
+  val d_d                     = Wire(Valid(new dest_pkt_t))
+  val x_d                     = Wire(Valid(new dest_pkt_t))
+  val r_d                     = Wire(Valid(new dest_pkt_t))
+  val r_d_in                  = Wire(Valid(new dest_pkt_t))
+  val wbd                     = Wire(Valid(new dest_pkt_t))
+  val i0_d_c                  = Wire(new class_pkt_t)
+  val i0_rs1_class_d          = Wire(new class_pkt_t)
+  val i0_rs2_class_d          = Wire(new class_pkt_t)
+  val i0_rs1_depth_d          = WireInit(UInt(2.W),0.U)
+  val i0_rs2_depth_d          = WireInit(UInt(2.W),0.U)
+  val cam_wen                 = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
+  val cam                     = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
+  val cam_write               = WireInit(UInt(1.W), 0.U)
+  val cam_inv_reset_val       = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
+  val cam_data_reset_val      = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
+  val nonblock_load_write     = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
+  val cam_raw                 = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
+  val cam_in                  = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t)))
+  val i0_dp                   = Wire(new dec_pkt_t)
+  val i0_dp_raw               = Wire(new dec_pkt_t)
+  val i0_rs1bypass            = WireInit(UInt(3.W), 0.U)
+  val i0_rs2bypass            = WireInit(UInt(3.W), 0.U)
+  val illegal_lockout         = WireInit(UInt(1.W), 0.U)
+  val postsync_stall          = WireInit(UInt(1.W), 0.U)
+  val ps_stall_in             = WireInit(UInt(1.W), 0.U)
+  val i0_pipe_en              = WireInit(UInt(4.W), 0.U)
+  val i0_load_block_d         = WireInit(UInt(1.W), 0.U)
+  val load_ldst_bypass_d      = WireInit(UInt(1.W), 0.U)
+  val store_data_bypass_d     = WireInit(UInt(1.W), 0.U)
+  val store_data_bypass_m     = WireInit(UInt(1.W), 0.U)
+  val tlu_wr_pause_r1         = WireInit(UInt(1.W), 0.U)
+  val tlu_wr_pause_r2         = WireInit(UInt(1.W), 0.U)
+  val leak1_i1_stall          = WireInit(UInt(1.W), 0.U)
+  val leak1_i0_stall          = WireInit(UInt(1.W), 0.U)
+  val pause_state             = WireInit(Bool(), 0.B)
+  val flush_final_r           = WireInit(UInt(1.W), 0.U)
+  val illegal_lockout_in      = WireInit(UInt(1.W), 0.U)
+  val lsu_idle                = WireInit(Bool(), 0.B)
+  val pause_state_in          = WireInit(Bool(), 0.B)
+  val leak1_mode              = WireInit(UInt(1.W), 0.U)
+  val  i0_pcall               = WireInit(UInt(1.W), 0.U)
+  val  i0_pja                 = WireInit(UInt(1.W), 0.U)
+  val i0_pret                 = WireInit(UInt(1.W), 0.U)
+  val i0_legal_decode_d       = WireInit(UInt(1.W), 0.U)
+  val  i0_pcall_raw           = WireInit(UInt(1.W), 0.U)
+  val  i0_pja_raw             = WireInit(UInt(1.W), 0.U)
+  val i0_pret_raw             = WireInit(UInt(1.W), 0.U)
+  val i0_br_offset            = WireInit(UInt(12.W), 0.U)
+  val i0_csr_write_only_d     = WireInit(UInt(1.W), 0.U)
+  val i0_jal                  = WireInit(UInt(1.W), 0.U)
+  val i0_wen_r                = WireInit(UInt(1.W), 0.U)
+  val i0_x_ctl_en             = WireInit(UInt(1.W), 0.U)
+  val i0_r_ctl_en             = WireInit(UInt(1.W), 0.U)
+  val i0_wb_ctl_en            = WireInit(UInt(1.W), 0.U)
+  val i0_x_data_en            = WireInit(UInt(1.W), 0.U)
+  val i0_r_data_en            = WireInit(UInt(1.W), 0.U)
+  val i0_wb_data_en           = WireInit(UInt(1.W), 0.U)
+  val i0_wb1_data_en          = WireInit(UInt(1.W), 0.U)
+  val i0_nonblock_load_stall  = WireInit(UInt(1.W), 0.U)
+  val csr_ren_qual_d          = WireInit(Bool(), 0.B)
+  val lsu_decode_d            = WireInit(UInt(1.W), 0.U)
+  val mul_decode_d            = WireInit(UInt(1.W), 0.U)
+  val div_decode_d            = WireInit(UInt(1.W), 0.U)
+  val write_csr_data          = WireInit(UInt(32.W),0.U)
+  val i0_result_corr_r        = WireInit(UInt(32.W),0.U)
+  val presync_stall           = WireInit(UInt(1.W), 0.U)
+  val i0_nonblock_div_stall   = WireInit(UInt(1.W), 0.U)
+  val debug_fence             = WireInit(Bool(), 0.B)
+  val i0_immed_d              = WireInit(UInt(32.W), 0.U)
+  val i0_result_x             = WireInit(UInt(32.W), 0.U)
+  val i0_result_r             = WireInit(UInt(32.W), 0.U)
   //////////////////////////////////////////////////////////////////////
   // Start - Data gating {{
-  val data_gate_en     = (io.dec_tlu_wr_pause_r   ^  tlu_wr_pause_r1  ) |   // replaces free_clk
-    (tlu_wr_pause_r1           ^  tlu_wr_pause_r2    ) |   // replaces free_clk
-    (io.dec_tlu_flush_extint   ^  io.decode_exu.dec_extint_stall) |
-    (leak1_i1_stall_in         ^  leak1_i1_stall     ) |   // replaces free_clk
-    (leak1_i0_stall_in         ^  leak1_i0_stall     ) |   // replaces free_clk
-    (pause_state_in            ^  pause_state        ) |   // replaces free_clk
-    (ps_stall_in               ^  postsync_stall     ) |   // replaces free_clk
-    (io.exu_flush_final        ^  flush_final_r      ) |   // replaces free_clk
-    (illegal_lockout_in        ^  illegal_lockout    )     // replaces active_clk
+  val data_gate_en     =  (io.dec_tlu_wr_pause_r     ^  tlu_wr_pause_r1               ) |   // replaces free_clk
+                          (tlu_wr_pause_r1           ^  tlu_wr_pause_r2               ) |   // replaces free_clk
+                          (io.dec_tlu_flush_extint   ^  io.decode_exu.dec_extint_stall) |
+                          (leak1_i1_stall_in         ^  leak1_i1_stall                ) |   // replaces free_clk
+                          (leak1_i0_stall_in         ^  leak1_i0_stall                ) |   // replaces free_clk
+                          (pause_state_in            ^  pause_state                   ) |   // replaces free_clk
+                          (ps_stall_in               ^  postsync_stall                ) |   // replaces free_clk
+                          (io.exu_flush_final        ^  flush_final_r                 ) |   // replaces free_clk
+                          (illegal_lockout_in        ^  illegal_lockout               )     // replaces active_clk
 
 
-  val data_gate_clk= rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
+  val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode)
+  // End  - Data gating
 
-  // End  - Data gating }}
-
-  val i0_brp_valid                   = io.dec_i0_brp.valid & !leak1_mode
-  io.decode_exu.dec_i0_predict_p_d.bits.misp         :=0.U
-  io.decode_exu.dec_i0_predict_p_d.bits.ataken       :=0.U
-  io.decode_exu.dec_i0_predict_p_d.bits.boffset      :=0.U
-  io.decode_exu.dec_i0_predict_p_d.bits.pcall        :=  i0_pcall  // don't mark as pcall if branch error
-  io.decode_exu.dec_i0_predict_p_d.bits.pja          :=  i0_pja
-  io.decode_exu.dec_i0_predict_p_d.bits.pret         :=  i0_pret
-  io.decode_exu.dec_i0_predict_p_d.bits.prett        :=  io.dec_i0_brp.bits.prett
-  io.decode_exu.dec_i0_predict_p_d.bits.pc4          :=  io.dec_i0_pc4_d
-  io.decode_exu.dec_i0_predict_p_d.bits.hist         :=  io.dec_i0_brp.bits.hist
-  io.decode_exu.dec_i0_predict_p_d.valid        :=  i0_brp_valid & i0_legal_decode_d
-  val i0_notbr_error                 =  i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
+  val i0_brp_valid                                     = io.dec_i0_brp.valid & !leak1_mode
+  io.decode_exu.dec_i0_predict_p_d.bits.misp          := 0.U
+  io.decode_exu.dec_i0_predict_p_d.bits.ataken        := 0.U
+  io.decode_exu.dec_i0_predict_p_d.bits.boffset       := 0.U
+  io.decode_exu.dec_i0_predict_p_d.bits.pcall         := i0_pcall  // don't mark as pcall if branch error
+  io.decode_exu.dec_i0_predict_p_d.bits.pja           := i0_pja
+  io.decode_exu.dec_i0_predict_p_d.bits.pret          := i0_pret
+  io.decode_exu.dec_i0_predict_p_d.bits.prett         := io.dec_i0_brp.bits.prett
+  io.decode_exu.dec_i0_predict_p_d.bits.pc4           := io.dec_i0_pc4_d
+  io.decode_exu.dec_i0_predict_p_d.bits.hist          := io.dec_i0_brp.bits.hist
+  io.decode_exu.dec_i0_predict_p_d.valid              := i0_brp_valid & i0_legal_decode_d
+  val i0_notbr_error                                   = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
 
   // no toffset error for a pret
-  val i0_br_toffset_error     =  i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
-  val i0_ret_error            =  i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
-  val i0_br_error             =  io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
-  io.decode_exu.dec_i0_predict_p_d.bits.br_error                  :=  i0_br_error & i0_legal_decode_d & !leak1_mode
-  io.decode_exu.dec_i0_predict_p_d.bits.br_start_error            :=  io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
-  io.decode_exu.i0_predict_index_d        :=  io.dec_i0_bp_index
-  io.decode_exu.i0_predict_btag_d         :=  io.dec_i0_bp_btag
-  val i0_br_error_all          = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
-  io.decode_exu.dec_i0_predict_p_d.bits.toffset            :=  i0_br_offset
-  io.decode_exu.i0_predict_fghr_d         :=  io.dec_i0_bp_fghr
-  io.decode_exu.dec_i0_predict_p_d.bits.way                       :=  io.dec_i0_brp.bits.way
+  val i0_br_toffset_error                              =  i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
+  val i0_ret_error                                     =  i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
+  val i0_br_error                                      =  io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
+  io.decode_exu.dec_i0_predict_p_d.bits.br_error       :=  i0_br_error & i0_legal_decode_d & !leak1_mode
+  io.decode_exu.dec_i0_predict_p_d.bits.br_start_error :=  io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
+  io.decode_exu.i0_predict_index_d                     :=  io.dec_i0_bp_index
+  io.decode_exu.i0_predict_btag_d                      :=  io.dec_i0_bp_btag
+  val i0_br_error_all                                   = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
+  io.decode_exu.dec_i0_predict_p_d.bits.toffset        :=  i0_br_offset
+  io.decode_exu.i0_predict_fghr_d                      :=  io.dec_i0_bp_fghr
+  io.decode_exu.dec_i0_predict_p_d.bits.way            :=  io.dec_i0_brp.bits.way
   //   end
 
   // on br error turn anything into a nop
   // on i0 instruction fetch access fault turn anything into a nop
   // nop =>   alu rs1 imm12 rd lor
-  val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
-
-  val i0_instr_error = i0_icaf_d;
-  i0_dp := i0_dp_raw
+  val i0_icaf_d        = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
+  val i0_instr_error   = i0_icaf_d;
+  i0_dp               := i0_dp_raw
   when((i0_br_error_all | i0_instr_error).asBool){
-    i0_dp          := 0.U.asTypeOf(i0_dp)
-    i0_dp.alu      := 1.B
-    i0_dp.rs1      := 1.B
-    i0_dp.rs2      := 1.B
-    i0_dp.lor      := 1.B
-    i0_dp.legal    := 1.B
-    i0_dp.postsync := 1.B
+    i0_dp             := 0.U.asTypeOf(i0_dp)
+    i0_dp.alu         := 1.B
+    i0_dp.rs1         := 1.B
+    i0_dp.rs2         := 1.B
+    i0_dp.lor         := 1.B
+    i0_dp.legal       := 1.B
+    i0_dp.postsync    := 1.B
   }
 
-  val i0 = io.dec_i0_instr_d
+  val i0                            = io.dec_i0_instr_d
   io.decode_exu.dec_i0_select_pc_d := i0_dp.pc
 
   // branches that can be predicted
-  val i0_predict_br    =  i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
-
-  val i0_predict_nt    = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
-  val i0_predict_t     =  (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
-  val i0_ap_pc2  = !io.dec_i0_pc4_d
-  val i0_ap_pc4  =  io.dec_i0_pc4_d
+  val i0_predict_br                  =  i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
+  val i0_predict_nt                  = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
+  val i0_predict_t                   =  (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
+  val i0_ap_pc2                      = !io.dec_i0_pc4_d
+  val i0_ap_pc4                      =  io.dec_i0_pc4_d
   io.decode_exu.i0_ap.predict_nt    := i0_predict_nt
   io.decode_exu.i0_ap.predict_t     := i0_predict_t
 
-  io.decode_exu.i0_ap.add     :=  i0_dp.add
-  io.decode_exu.i0_ap.sub     :=  i0_dp.sub
-  io.decode_exu.i0_ap.land    :=  i0_dp.land
-  io.decode_exu.i0_ap.lor     :=  i0_dp.lor
-  io.decode_exu.i0_ap.lxor    :=  i0_dp.lxor
-  io.decode_exu.i0_ap.sll     :=  i0_dp.sll
-  io.decode_exu.i0_ap.srl     :=  i0_dp.srl
-  io.decode_exu.i0_ap.sra     :=  i0_dp.sra
-  io.decode_exu.i0_ap.slt     :=  i0_dp.slt
-  io.decode_exu.i0_ap.unsign  :=  i0_dp.unsign
-  io.decode_exu.i0_ap.beq     :=  i0_dp.beq
-  io.decode_exu.i0_ap.bne     :=  i0_dp.bne
-  io.decode_exu.i0_ap.blt     :=  i0_dp.blt
-  io.decode_exu.i0_ap.bge     :=  i0_dp.bge
-  io.decode_exu.i0_ap.csr_write :=  i0_csr_write_only_d
-  io.decode_exu.i0_ap.csr_imm   :=  i0_dp.csr_imm
-  io.decode_exu.i0_ap.jal       :=  i0_jal
+  io.decode_exu.i0_ap.add           :=  i0_dp.add
+  io.decode_exu.i0_ap.sub           :=  i0_dp.sub
+  io.decode_exu.i0_ap.land          :=  i0_dp.land
+  io.decode_exu.i0_ap.lor           :=  i0_dp.lor
+  io.decode_exu.i0_ap.lxor          :=  i0_dp.lxor
+  io.decode_exu.i0_ap.sll           :=  i0_dp.sll
+  io.decode_exu.i0_ap.srl           :=  i0_dp.srl
+  io.decode_exu.i0_ap.sra           :=  i0_dp.sra
+  io.decode_exu.i0_ap.slt           :=  i0_dp.slt
+  io.decode_exu.i0_ap.unsign        :=  i0_dp.unsign
+  io.decode_exu.i0_ap.beq           :=  i0_dp.beq
+  io.decode_exu.i0_ap.bne           :=  i0_dp.bne
+  io.decode_exu.i0_ap.blt           :=  i0_dp.blt
+  io.decode_exu.i0_ap.bge           :=  i0_dp.bge
+  io.decode_exu.i0_ap.csr_write     :=  i0_csr_write_only_d
+  io.decode_exu.i0_ap.csr_imm       :=  i0_dp.csr_imm
+  io.decode_exu.i0_ap.jal           :=  i0_jal
    
   // non block load cam logic
   // val found=Wire(UInt(1.W))
diff --git a/src/main/scala/exu/exu_alu_ctl.scala b/src/main/scala/exu/exu_alu_ctl.scala
index f15575c2..da24a9ac 100644
--- a/src/main/scala/exu/exu_alu_ctl.scala
+++ b/src/main/scala/exu/exu_alu_ctl.scala
@@ -109,7 +109,6 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
   val target_mispredict   =  io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
 
   io.flush_upper_out     :=   (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x   & !io.dec_tlu_flush_lower_r
-  //there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
   io.flush_final_out     := ( (io.i0_ap.jal | cond_mispredict | target_mispredict) & io.dec_alu.dec_i0_alu_decode_d & !io.flush_upper_x ) |  io.dec_tlu_flush_lower_r
   //there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
 
diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala
index 46baf82a..1cc4faaa 100644
--- a/src/main/scala/include/bundle.scala
+++ b/src/main/scala/include/bundle.scala
@@ -58,12 +58,10 @@ class ahb_out extends Bundle{
   val htrans        = Output(UInt(2.W))
   val hwrite        = Output(Bool()) // ahb bus write
   val hwdata        = Output(UInt(64.W)) // [63:0]  // ahb bus write data
-
-
 }
 class ahb_channel extends Bundle{
-  val in = Input(new ahb_in)
-  val out = Output(new ahb_out)
+  val in  = new ahb_in
+  val out = new ahb_out
 }
 class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{
   val aw = Decoupled(new write_addr(BUS_TAG))
diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala
index 63a820b7..22f74d34 100644
--- a/src/main/scala/lib/ahb_to_axi4.scala
+++ b/src/main/scala/lib/ahb_to_axi4.scala
@@ -28,8 +28,8 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
     //    val ahb_htrans      = Input(UInt(2.W)) // Transaction type (possible values 0          =2 only right now)
     //    val ahb_hwrite      = Input(Bool()) // ahb bus write
     //    val ahb_hwdata      = Input(UInt(64.W)) // ahb bus write data
-    val ahb_hsel        = Input(Bool()) // this slave was selected
-    val ahb_hreadyin    = Input(Bool()) // previous hready was accepted or not
+//    val ahb_hsel        = Input(Bool()) // this slave was selected
+//    val ahb_hreadyin    = Input(Bool()) // previous hready was accepted or not
     // outputs
     val axi_awvalid     = Output(Bool())
     val axi_awid        = Output(UInt(TAG.W))
@@ -51,7 +51,10 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
     val axi_arlen       = Output(UInt(8.W))
     val axi_arburst     = Output(UInt(2.W))
     val axi_rready      = Output(Bool())
-    val ahb             = Flipped(new ahb_channel())
+    val ahb = new Bundle{
+      val sig = Flipped(new ahb_channel())
+      val hsel = Input(Bool())
+      val hreadyin = Input(Bool())}
     //    val ahb_hrdata      = Output(UInt(64.W)) // ahb bus read data
     //    val ahb_hreadyout   = Output(Bool()) // slave ready to accept transaction
     //    val ahb_hresp       = Output(Bool()) // slave response (high indicates erro)
@@ -115,18 +118,18 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
   switch(buf_state) {
 
     is(idle) {
-      buf_nxtstate := Mux(io.ahb.out.hwrite, wr, rd)
-      buf_state_en := ahb_hready & io.ahb.out.htrans(1) & io.ahb_hsel // only transition on a valid hrtans
+      buf_nxtstate := Mux(io.ahb.sig.out.hwrite, wr, rd)
+      buf_state_en := ahb_hready & io.ahb.sig.out.htrans(1) & io.ahb.hsel // only transition on a valid hrtans
     }
     is(wr) { // Write command recieved last cycle
-      buf_nxtstate := Mux((io.ahb.in.hresp | (io.ahb.out.htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb.out.hwrite, wr, rd))
-      buf_state_en := (!cmdbuf_full | io.ahb.in.hresp)
-      cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.in.hresp | ((io.ahb.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
+      buf_nxtstate := Mux((io.ahb.sig.in.hresp | (io.ahb.sig.out.htrans(1, 0) === "b0".U) | !io.ahb.hsel).asBool, idle, Mux(io.ahb.sig.out.hwrite, wr, rd))
+      buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp)
+      cmdbuf_wr_en := !cmdbuf_full & !(io.ahb.sig.in.hresp | ((io.ahb.sig.out.htrans(1, 0) === "b01".U(2.W)) & io.ahb.hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
     }
     is(rd) { // Read command recieved last cycle.
-      buf_nxtstate := Mux(io.ahb.in.hresp, idle, pend) // If error go to idle, else wait for read data
-      buf_state_en := (!cmdbuf_full | io.ahb.in.hresp) // only when command can go, or if its an error
-      cmdbuf_wr_en := !io.ahb.in.hresp & !cmdbuf_full // send command only when no error
+      buf_nxtstate := Mux(io.ahb.sig.in.hresp, idle, pend) // If error go to idle, else wait for read data
+      buf_state_en := (!cmdbuf_full | io.ahb.sig.in.hresp) // only when command can go, or if its an error
+      cmdbuf_wr_en := !io.ahb.sig.in.hresp & !cmdbuf_full // send command only when no error
     }
     is(pend) { // Read Command has been sent. Waiting on Data.
       buf_nxtstate := idle // go back for next command and present data next cycle
@@ -143,11 +146,11 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
     (Fill(8,ahb_hsize_q(2,0) === 3.U)  &  255.U)
 
   // AHB signals
-  io.ahb.in.hready               := Mux(io.ahb.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend)  & !buf_read_error))
-  ahb_hready                  := io.ahb.in.hready & io.ahb_hreadyin
-  ahb_htrans_in               := Fill(2,io.ahb_hsel) & io.ahb.out.htrans(1,0)
-  io.ahb.in.hrdata               := buf_rdata(63,0)
-  io.ahb.in.hresp                := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle)  &
+  io.ahb.sig.in.hready               := Mux(io.ahb.sig.in.hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend)  & !buf_read_error))
+  ahb_hready                  := io.ahb.sig.in.hready & io.ahb.hreadyin
+  ahb_htrans_in               := Fill(2,io.ahb.hsel) & io.ahb.sig.out.htrans(1,0)
+  io.ahb.sig.in.hrdata               := buf_rdata(63,0)
+  io.ahb.sig.in.hresp                := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle)  &
     ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) |                                                                                   // request not for ICCM or DCCM
       ((ahb_addr_in_iccm | (ahb_addr_in_dccm &  ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) |    // ICCM Rd/Wr OR DCCM Wr not the right size
       ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0))   |                                                                             // HW size but unaligned
@@ -161,22 +164,22 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
   buf_read_error              := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
 
   // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
-  ahb_hresp_q                 := withClock(ahb_clk){RegNext(io.ahb.in.hresp,0.U)}
+  ahb_hresp_q                 := withClock(ahb_clk){RegNext(io.ahb.sig.in.hresp,0.U)}
   ahb_hready_q                := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
   ahb_htrans_q                := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
-  ahb_hsize_q                 := withClock(ahb_addr_clk){RegNext(io.ahb.out.hsize,0.U)}
-  ahb_hwrite_q                := withClock(ahb_addr_clk){RegNext(io.ahb.out.hwrite,0.U)}
-  ahb_haddr_q                 := withClock(ahb_addr_clk){RegNext(io.ahb.out.haddr,0.U)}
+  ahb_hsize_q                 := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hsize,0.U)}
+  ahb_hwrite_q                := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hwrite,0.U)}
+  ahb_haddr_q                 := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.haddr,0.U)}
 
   // Clock header logic
-  ahb_bus_addr_clk_en         := io.bus_clk_en & (ahb_hready & io.ahb.out.htrans(1))
+  ahb_bus_addr_clk_en         := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
   buf_rdata_clk_en            := io.bus_clk_en & buf_rdata_en;
 
   ahb_clk                     := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
   ahb_addr_clk                := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
   buf_rdata_clk               := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
 
-  cmdbuf_rst                  := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.in.hresp & !cmdbuf_write)
+  cmdbuf_rst                  := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
   cmdbuf_full                 := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
   //rvdffsc
   cmdbuf_vld                  := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
@@ -193,7 +196,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
 
   //rvdffe
   cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
-  cmdbuf_wdata := rvdffe(io.ahb.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
+  cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
 
   // AXI Write Command Channel
   io.axi_awvalid          := cmdbuf_vld & cmdbuf_write
diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala
index 00235400..ddf61671 100644
--- a/src/main/scala/quasar.scala
+++ b/src/main/scala/quasar.scala
@@ -17,7 +17,10 @@ class quasar_bundle extends Bundle with  lib{
   val ahb = new ahb_channel
   val lsu_ahb = new ahb_channel
   val sb_ahb = new ahb_channel
-  val dma_ahb = Flipped(new ahb_channel)
+  val dma = new Bundle{
+    val ahb= Flipped(new ahb_channel())
+    val hsel = Input(Bool())
+    val hreadyin = Input(Bool())}
 
   val dbg_rst_l = Input(AsyncReset())
   val rst_vec = Input(UInt(31.W))
@@ -88,7 +91,7 @@ class quasar_bundle extends Bundle with  lib{
   //  val sb_hresp = Input(Bool())
   //
   //  // DMA slave
-  val dma_hsel = Input(Bool())
+//  dma_hsel = Input(Bool())
   //  val dma_haddr = Input(UInt(32.W))
   //  val dma_hburst = Input(UInt(3.W))
   //  val dma_hmastlock = Input(Bool())
@@ -97,7 +100,7 @@ class quasar_bundle extends Bundle with  lib{
   //  val dma_htrans = Input(UInt(2.W))
   //  val dma_hwrite = Input(Bool())
   //  val dma_hwdata = Input(UInt(64.W))
-  val dma_hreadyin = Input(Bool())
+//  val dma_hreadyin = Input(Bool())
   //  val dma_hrdata = Output(UInt(64.W))
   //  val dma_hreadyout = Output(Bool())
   //  val dma_hresp = Output(Bool())
@@ -408,8 +411,8 @@ class quasar extends Module with RequireAsyncReset with lib {
     //    dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans
     //    dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite
     //    dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata
-    dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel
-    dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin
+    dma_ahb_to_axi4.io.ahb.hsel := io.dma.hsel
+    dma_ahb_to_axi4.io.ahb.hreadyin := io.dma.hreadyin
     lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
     lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
     lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
@@ -484,7 +487,7 @@ class quasar extends Module with RequireAsyncReset with lib {
     //    io.sb_hwrite := sb_axi4_to_ahb.io.ahb_hwrite
     //    io.sb_hwdata := sb_axi4_to_ahb.io.ahb_hwdata
 
-    io.dma_ahb <> dma_ahb_to_axi4.io.ahb
+    io.dma.ahb <> dma_ahb_to_axi4.io.ahb.sig
     //    io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
     //    io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
     //    io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
@@ -522,7 +525,7 @@ class quasar extends Module with RequireAsyncReset with lib {
       //        io.sb_hwrite := 0.U
       //        io.sb_hwdata := 0.U
 
-      io.dma_ahb.in <> 0.U.asTypeOf(io.dma_ahb.in)
+      io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in)
       //        io.dma_hrdata := 0.U
       //        io.dma_hreadyout := 0.U
       //        io.dma_hresp := 0.U
diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala
index 4510af97..c167dd58 100644
--- a/src/main/scala/quasar_wrapper.scala
+++ b/src/main/scala/quasar_wrapper.scala
@@ -19,8 +19,11 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
 
     // DMA slave
-    val dma_hsel = Input(Bool())
-    val dma_ahb = Flipped(new ahb_channel())
+
+    val dma = new Bundle{
+      val ahb= Flipped(new ahb_channel())
+      val hsel = Input(Bool())
+      val hreadyin = Input(Bool())}
     //    val dma_haddr = Input(UInt(32.W))
     //    val dma_hburst = Input(UInt(3.W))
     //    val dma_hmastlock = Input(Bool())
@@ -29,7 +32,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     //    val dma_htrans = Input(UInt(2.W))
     //    val dma_hwrite = Input(Bool())
     //    val dma_hwdata = Input(UInt(64.W))
-    val dma_hreadyin = Input(Bool())
+
     //    val dma_hrdata = Output(UInt(64.W))
     //    val dma_hreadyout = Output(Bool())
     //    val dma_hresp = Output(Bool())
@@ -112,7 +115,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   swerv.io.ahb.in      <> 0.U.asTypeOf(swerv.io.ahb.in)
   swerv.io.lsu_ahb.in  <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
   swerv.io.sb_ahb.in   <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
-  io.dma_ahb.in   <> 0.U.asTypeOf(io.dma_ahb.in)
+  io.dma.ahb.in   <> 0.U.asTypeOf(io.dma.ahb.in)
   //  swerv.io.sb_hready := 0.U
   //  swerv.io.hrdata := 0.U
   //  swerv.io.sb_hresp := 0.U
@@ -154,8 +157,8 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   swerv.io.dma_axi <> io.dma_axi
 
   // DMA Slave
-  swerv.io.dma_hsel := io.dma_hsel
-  swerv.io.dma_ahb.out <> io.dma_ahb.out
+  swerv.io.dma.hsel := io.dma.hsel
+  swerv.io.dma.ahb.out <> io.dma.ahb.out
   //  swerv.io.dma_haddr := io.dma_haddr
   //  swerv.io.dma_hburst := io.dma_hburst
   //  swerv.io.dma_hmastlock := io.dma_hmastlock
@@ -164,7 +167,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   //  swerv.io.dma_htrans := io.dma_htrans
   //  swerv.io.dma_hwrite := io.dma_hwrite
   //  swerv.io.dma_hwdata := io.dma_hwdata
-  swerv.io.dma_hreadyin := io.dma_hreadyin
+  swerv.io.dma.hreadyin := io.dma.hreadyin
 
   swerv.io.lsu_bus_clk_en
   swerv.io.ifu_bus_clk_en
diff --git a/target/.history b/target/.history
index e8557d91..7098462e 100644
--- a/target/.history
+++ b/target/.history
@@ -4,3 +4,4 @@
 ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
 ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
 ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
+;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
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diff --git a/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous b/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous
index 2a283a39..8a3823fa 100644
--- a/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous
+++ b/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous
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\ No newline at end of file
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\ No newline at end of file
diff --git a/target/streams/_global/_global/checkBuildSources/_global/streams/out b/target/streams/_global/_global/checkBuildSources/_global/streams/out
index 24ce6f61..6c981659 100644
--- a/target/streams/_global/_global/checkBuildSources/_global/streams/out
+++ b/target/streams/_global/_global/checkBuildSources/_global/streams/out
@@ -1 +1 @@
-[0m[[0m[0mdebug[0m] [0m[0mChecking for meta build source updates[0m
+[debug] Checking for meta build source updates
diff --git a/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
index bd541622..6b9a0fb5 100644
--- a/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
+++ b/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
@@ -1 +1 @@
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\ No newline at end of file
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diff --git a/target/streams/_global/updateClassifiers/_global/streams/out b/target/streams/_global/updateClassifiers/_global/streams/out
index 022f958b..a047fedb 100644
--- a/target/streams/_global/updateClassifiers/_global/streams/out
+++ b/target/streams/_global/updateClassifiers/_global/streams/out
@@ -1,4 +1,4 @@
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+[warn] paradise_2.12.10-2.1.0-sources.jar no longer exists at /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0-sources.jar
 [debug] "not up to date. inChanged = false, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/"), "quasar")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/"), "quasar")
+[debug] Updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/"), "quasar")...
+[debug] Done updating ProjectRef(uri("file:/home/abdulhameed.akram/Music/Quasar/"), "quasar")
diff --git a/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output b/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output
index c112785a..b31e3edd 100644
--- a/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output
+++ b/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output
@@ -1 +1 @@
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diff --git a/target/streams/compile/externalDependencyClasspath/_global/streams/export b/target/streams/compile/externalDependencyClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/compile/externalDependencyClasspath/_global/streams/export
+++ b/target/streams/compile/externalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
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+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
diff --git a/target/streams/compile/managedClasspath/_global/streams/export b/target/streams/compile/managedClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/compile/managedClasspath/_global/streams/export
+++ b/target/streams/compile/managedClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
diff --git a/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/target/streams/runtime/externalDependencyClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/runtime/externalDependencyClasspath/_global/streams/export
+++ b/target/streams/runtime/externalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
diff --git a/target/streams/runtime/managedClasspath/_global/streams/export b/target/streams/runtime/managedClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/runtime/managedClasspath/_global/streams/export
+++ b/target/streams/runtime/managedClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
diff --git a/target/streams/test/externalDependencyClasspath/_global/streams/export b/target/streams/test/externalDependencyClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/test/externalDependencyClasspath/_global/streams/export
+++ b/target/streams/test/externalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
diff --git a/target/streams/test/managedClasspath/_global/streams/export b/target/streams/test/managedClasspath/_global/streams/export
index 414eb951..58921df4 100644
--- a/target/streams/test/managedClasspath/_global/streams/export
+++ b/target/streams/test/managedClasspath/_global/streams/export
@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
