diff --git a/design/src/main/scala/lsu/lsu_lsc_ctl.scala b/design/src/main/scala/lsu/lsu_lsc_ctl.scala
index b1f8cf5e..f1bba33d 100644
--- a/design/src/main/scala/lsu/lsu_lsc_ctl.scala
+++ b/design/src/main/scala/lsu/lsu_lsc_ctl.scala
@@ -255,7 +255,7 @@ class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
   }
 
   else  {
-    lsu_ld_datafn_m       := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m)
+    lsu_ld_datafn_m       := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m)
     lsu_ld_datafn_corr_r  := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
     io.lsu_result_m       := ((Fill(32,io.lsu_pkt_m.bits.unsign  & io.lsu_pkt_m.bits.by))    & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
       ((Fill(32,io.lsu_pkt_m.bits.unsign  & io.lsu_pkt_m.bits.half))  & Cat(0.U(16.W),lsu_ld_datafn_m(15,0)))    |