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​laraibkhan119 2020-09-24 12:28:55 +05:00
parent 4a560e881a
commit 2a2474ca44
127 changed files with 4760 additions and 1858 deletions
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111
el2_lsu_stbuf.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_lo_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_stbuf_full_any",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_dec_lsu_valid_raw_d",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_d",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_d",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_reqvld_any",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_m_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_ldst_stbuf_reqvld_r",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_commit_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwddata_lo_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwddata_hi_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_lo_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_data_hi_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_store",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dma",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_valid",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_store_stbuf_reqvld_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_r",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_dword",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_word",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_by",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_lsu_pkt_r_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_stbuf|el2_lsu_stbuf>io_stbuf_fwdbyteen_hi_m",
"sources":[
"~el2_lsu_stbuf|el2_lsu_stbuf>io_addr_in_dccm_m",
"~el2_lsu_stbuf|el2_lsu_stbuf>io_end_addr_m"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_stbuf"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1535
el2_lsu_stbuf.fir Normal file
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878
el2_lsu_stbuf.v Normal file
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module el2_lsu_stbuf(
input clock,
input reset,
input io_lsu_c1_m_clk,
input io_lsu_c1_r_clk,
input io_lsu_stbuf_c1_clk,
input io_lsu_free_c2_clk,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input io_lsu_pkt_r_fast_int,
input io_lsu_pkt_r_by,
input io_lsu_pkt_r_half,
input io_lsu_pkt_r_word,
input io_lsu_pkt_r_dword,
input io_lsu_pkt_r_load,
input io_lsu_pkt_r_store,
input io_lsu_pkt_r_unsign,
input io_lsu_pkt_r_dma,
input io_lsu_pkt_r_store_data_bypass_d,
input io_lsu_pkt_r_load_ldst_bypass_d,
input io_lsu_pkt_r_store_data_bypass_m,
input io_lsu_pkt_r_valid,
input io_store_stbuf_reqvld_r,
input io_lsu_commit_r,
input io_dec_lsu_valid_raw_d,
input [31:0] io_store_data_hi_r,
input [31:0] io_store_data_lo_r,
input [31:0] io_store_datafn_hi_r,
input [31:0] io_store_datafn_lo_r,
input io_lsu_stbuf_commit_any,
input [15:0] io_lsu_addr_d,
input [31:0] io_lsu_addr_m,
input [31:0] io_lsu_addr_r,
input [15:0] io_end_addr_d,
input [31:0] io_end_addr_m,
input [31:0] io_end_addr_r,
input io_addr_in_dccm_m,
input io_addr_in_dccm_r,
input io_lsu_cmpen_m,
input io_scan_mode,
output io_stbuf_reqvld_any,
output io_stbuf_reqvld_flushed_any,
output [15:0] io_stbuf_addr_any,
output [31:0] io_stbuf_data_any,
output io_lsu_stbuf_full_any,
output io_lsu_stbuf_empty_any,
output io_ldst_stbuf_reqvld_r,
output [31:0] io_stbuf_fwddata_hi_m,
output [31:0] io_stbuf_fwddata_lo_m,
output [3:0] io_stbuf_fwdbyteen_hi_m,
output [3:0] io_stbuf_fwdbyteen_lo_m
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [31:0] _RAND_18;
reg [31:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
wire [7:0] _T_1 = io_lsu_pkt_r_by ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_2 = _T_1 & 8'h1; // @[el2_lsu_stbuf.scala 108:49]
wire [7:0] _T_4 = io_lsu_pkt_r_half ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_5 = _T_4 & 8'h3; // @[el2_lsu_stbuf.scala 109:32]
wire [7:0] _T_6 = _T_2 | _T_5; // @[el2_lsu_stbuf.scala 108:65]
wire [7:0] _T_8 = io_lsu_pkt_r_word ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_9 = _T_8 & 8'hf; // @[el2_lsu_stbuf.scala 110:32]
wire [7:0] _T_10 = _T_6 | _T_9; // @[el2_lsu_stbuf.scala 109:48]
wire [7:0] _T_12 = io_lsu_pkt_r_dword ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] ldst_byteen_r = _T_10 | _T_12; // @[el2_lsu_stbuf.scala 110:48]
wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 112:40]
reg ldst_dual_r; // @[el2_lsu_stbuf.scala 161:53]
wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 113:41]
wire [10:0] _GEN_38 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 115:40]
wire [10:0] _T_17 = _GEN_38 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 115:40]
wire [7:0] store_byteen_ext_r = _T_17[7:0]; // @[el2_lsu_stbuf.scala 115:23]
wire [3:0] _T_20 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_20; // @[el2_lsu_stbuf.scala 116:53]
wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_20; // @[el2_lsu_stbuf.scala 117:53]
reg [1:0] RdPtr; // @[Reg.scala 27:20]
wire [1:0] NxtRdPtr = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 118:27]
reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20]
wire _T_30 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121]
reg stbuf_vld_0; // @[Reg.scala 27:20]
wire _T_31 = _T_30 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 124:181]
reg stbuf_dma_kill_0; // @[Reg.scala 27:20]
wire _T_32 = ~stbuf_dma_kill_0; // @[el2_lsu_stbuf.scala 124:198]
wire _T_33 = _T_31 & _T_32; // @[el2_lsu_stbuf.scala 124:196]
wire _T_184 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 132:78]
reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20]
wire _T_39 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121]
reg stbuf_vld_1; // @[Reg.scala 27:20]
wire _T_40 = _T_39 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 124:181]
reg stbuf_dma_kill_1; // @[Reg.scala 27:20]
wire _T_41 = ~stbuf_dma_kill_1; // @[el2_lsu_stbuf.scala 124:198]
wire _T_42 = _T_40 & _T_41; // @[el2_lsu_stbuf.scala 124:196]
reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20]
wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121]
reg stbuf_vld_2; // @[Reg.scala 27:20]
wire _T_49 = _T_48 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 124:181]
reg stbuf_dma_kill_2; // @[Reg.scala 27:20]
wire _T_50 = ~stbuf_dma_kill_2; // @[el2_lsu_stbuf.scala 124:198]
wire _T_51 = _T_49 & _T_50; // @[el2_lsu_stbuf.scala 124:196]
reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20]
wire _T_57 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121]
reg stbuf_vld_3; // @[Reg.scala 27:20]
wire _T_58 = _T_57 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 124:181]
reg stbuf_dma_kill_3; // @[Reg.scala 27:20]
wire _T_59 = ~stbuf_dma_kill_3; // @[el2_lsu_stbuf.scala 124:198]
wire _T_60 = _T_58 & _T_59; // @[el2_lsu_stbuf.scala 124:196]
wire [3:0] store_matchvec_lo_r = {_T_60,_T_51,_T_42,_T_33}; // @[Cat.scala 29:58]
wire _T_68 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121]
wire _T_69 = _T_68 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 125:181]
wire _T_71 = _T_69 & _T_32; // @[el2_lsu_stbuf.scala 125:196]
wire _T_72 = _T_71 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217]
wire _T_78 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121]
wire _T_79 = _T_78 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 125:181]
wire _T_81 = _T_79 & _T_41; // @[el2_lsu_stbuf.scala 125:196]
wire _T_82 = _T_81 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217]
wire _T_88 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121]
wire _T_89 = _T_88 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 125:181]
wire _T_91 = _T_89 & _T_50; // @[el2_lsu_stbuf.scala 125:196]
wire _T_92 = _T_91 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217]
wire _T_98 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121]
wire _T_99 = _T_98 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 125:181]
wire _T_101 = _T_99 & _T_59; // @[el2_lsu_stbuf.scala 125:196]
wire _T_102 = _T_101 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217]
wire [3:0] store_matchvec_hi_r = {_T_102,_T_92,_T_82,_T_72}; // @[Cat.scala 29:58]
wire _T_124 = store_matchvec_lo_r[0] | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 131:126]
wire _T_141 = store_matchvec_lo_r[1] | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 131:126]
wire _T_158 = store_matchvec_lo_r[2] | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 131:126]
wire _T_175 = store_matchvec_lo_r[3] | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 131:126]
wire [3:0] stbuf_wr_en = {_T_175,_T_158,_T_141,_T_124}; // @[Cat.scala 29:58]
wire [3:0] sel_lo = {store_matchvec_lo_r[3],store_matchvec_lo_r[2],store_matchvec_lo_r[1],store_matchvec_lo_r[0]}; // @[Cat.scala 29:58]
wire [31:0] _T_220 = sel_lo[0] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57]
wire [31:0] _T_222 = sel_lo[1] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57]
wire [31:0] _T_224 = sel_lo[2] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57]
wire [31:0] _T_226 = sel_lo[3] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57]
reg [3:0] stbuf_byteen_0; // @[Reg.scala 27:20]
wire [3:0] _T_228 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87]
wire [3:0] _T_229 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124]
reg [3:0] stbuf_byteen_1; // @[Reg.scala 27:20]
wire [3:0] _T_232 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87]
wire [3:0] _T_233 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124]
reg [3:0] stbuf_byteen_2; // @[Reg.scala 27:20]
wire [3:0] _T_236 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87]
wire [3:0] _T_237 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124]
reg [3:0] stbuf_byteen_3; // @[Reg.scala 27:20]
wire [3:0] _T_240 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87]
wire [3:0] _T_241 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124]
wire _T_245 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 138:68]
wire _T_247 = _T_245 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88]
reg [31:0] stbuf_data_0; // @[Reg.scala 27:20]
wire [7:0] _T_250 = _T_247 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 138:67]
wire _T_254 = _T_245 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31]
wire [7:0] _T_257 = _T_254 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 139:10]
wire [7:0] datain1_3 = sel_lo[0] ? _T_250 : _T_257; // @[el2_lsu_stbuf.scala 138:52]
wire _T_261 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 138:68]
wire _T_263 = _T_261 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88]
reg [31:0] stbuf_data_1; // @[Reg.scala 27:20]
wire [7:0] _T_266 = _T_263 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 138:67]
wire _T_270 = _T_261 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31]
wire [7:0] _T_273 = _T_270 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 139:10]
wire [7:0] datain1_2 = sel_lo[1] ? _T_266 : _T_273; // @[el2_lsu_stbuf.scala 138:52]
wire _T_277 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 138:68]
wire _T_279 = _T_277 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88]
reg [31:0] stbuf_data_2; // @[Reg.scala 27:20]
wire [7:0] _T_282 = _T_279 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 138:67]
wire _T_286 = _T_277 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31]
wire [7:0] _T_289 = _T_286 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 139:10]
wire [7:0] datain1_1 = sel_lo[2] ? _T_282 : _T_289; // @[el2_lsu_stbuf.scala 138:52]
wire _T_293 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 138:68]
wire _T_295 = _T_293 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88]
reg [31:0] stbuf_data_3; // @[Reg.scala 27:20]
wire [7:0] _T_298 = _T_295 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 138:67]
wire _T_302 = _T_293 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31]
wire [7:0] _T_305 = _T_302 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 139:10]
wire [7:0] datain1_0 = sel_lo[3] ? _T_298 : _T_305; // @[el2_lsu_stbuf.scala 138:52]
wire _T_309 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 141:69]
wire _T_311 = _T_309 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89]
wire [7:0] _T_314 = _T_311 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 141:68]
wire _T_318 = _T_309 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31]
wire [7:0] _T_321 = _T_318 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 142:10]
wire [7:0] datain2_3 = sel_lo[0] ? _T_314 : _T_321; // @[el2_lsu_stbuf.scala 141:53]
wire _T_325 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 141:69]
wire _T_327 = _T_325 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89]
wire [7:0] _T_330 = _T_327 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 141:68]
wire _T_334 = _T_325 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31]
wire [7:0] _T_337 = _T_334 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 142:10]
wire [7:0] datain2_2 = sel_lo[1] ? _T_330 : _T_337; // @[el2_lsu_stbuf.scala 141:53]
wire _T_341 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 141:69]
wire _T_343 = _T_341 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89]
wire [7:0] _T_346 = _T_343 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 141:68]
wire _T_350 = _T_341 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31]
wire [7:0] _T_353 = _T_350 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 142:10]
wire [7:0] datain2_1 = sel_lo[2] ? _T_346 : _T_353; // @[el2_lsu_stbuf.scala 141:53]
wire _T_357 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 141:69]
wire _T_359 = _T_357 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89]
wire [7:0] _T_362 = _T_359 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 141:68]
wire _T_366 = _T_357 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31]
wire [7:0] _T_369 = _T_366 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 142:10]
wire [7:0] datain2_0 = sel_lo[3] ? _T_362 : _T_369; // @[el2_lsu_stbuf.scala 141:53]
wire _T_373 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 144:69]
wire _T_375 = _T_373 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89]
wire [7:0] _T_378 = _T_375 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 144:68]
wire _T_382 = _T_373 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31]
wire [7:0] _T_385 = _T_382 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 145:10]
wire [7:0] datain3_3 = sel_lo[0] ? _T_378 : _T_385; // @[el2_lsu_stbuf.scala 144:53]
wire _T_389 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 144:69]
wire _T_391 = _T_389 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89]
wire [7:0] _T_394 = _T_391 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 144:68]
wire _T_398 = _T_389 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31]
wire [7:0] _T_401 = _T_398 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 145:10]
wire [7:0] datain3_2 = sel_lo[1] ? _T_394 : _T_401; // @[el2_lsu_stbuf.scala 144:53]
wire _T_405 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 144:69]
wire _T_407 = _T_405 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89]
wire [7:0] _T_410 = _T_407 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 144:68]
wire _T_414 = _T_405 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31]
wire [7:0] _T_417 = _T_414 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 145:10]
wire [7:0] datain3_1 = sel_lo[2] ? _T_410 : _T_417; // @[el2_lsu_stbuf.scala 144:53]
wire _T_421 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 144:69]
wire _T_423 = _T_421 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89]
wire [7:0] _T_426 = _T_423 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 144:68]
wire _T_430 = _T_421 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31]
wire [7:0] _T_433 = _T_430 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 145:10]
wire [7:0] datain3_0 = sel_lo[3] ? _T_426 : _T_433; // @[el2_lsu_stbuf.scala 144:53]
wire _T_437 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 147:69]
wire _T_439 = _T_437 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89]
wire [7:0] _T_442 = _T_439 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 147:68]
wire _T_446 = _T_437 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31]
wire [7:0] _T_449 = _T_446 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 148:10]
wire [7:0] datain4_3 = sel_lo[0] ? _T_442 : _T_449; // @[el2_lsu_stbuf.scala 147:53]
wire _T_453 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 147:69]
wire _T_455 = _T_453 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89]
wire [7:0] _T_458 = _T_455 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 147:68]
wire _T_462 = _T_453 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31]
wire [7:0] _T_465 = _T_462 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 148:10]
wire [7:0] datain4_2 = sel_lo[1] ? _T_458 : _T_465; // @[el2_lsu_stbuf.scala 147:53]
wire _T_469 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 147:69]
wire _T_471 = _T_469 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89]
wire [7:0] _T_474 = _T_471 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 147:68]
wire _T_478 = _T_469 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31]
wire [7:0] _T_481 = _T_478 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 148:10]
wire [7:0] datain4_1 = sel_lo[2] ? _T_474 : _T_481; // @[el2_lsu_stbuf.scala 147:53]
wire _T_485 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 147:69]
wire _T_487 = _T_485 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89]
wire [7:0] _T_490 = _T_487 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 147:68]
wire _T_494 = _T_485 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31]
wire [7:0] _T_497 = _T_494 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 148:10]
wire [7:0] datain4_0 = sel_lo[3] ? _T_490 : _T_497; // @[el2_lsu_stbuf.scala 147:53]
wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58]
wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58]
wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58]
wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58]
wire _GEN_0 = stbuf_wr_en[0] | stbuf_vld_0; // @[Reg.scala 28:19]
wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 187:17]
wire _T_681 = stbuf_addr_3[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116]
wire _T_682 = _T_681 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 193:175]
wire _T_684 = _T_682 & _T_59; // @[el2_lsu_stbuf.scala 193:190]
wire _T_685 = _T_684 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211]
wire _T_674 = stbuf_addr_2[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116]
wire _T_675 = _T_674 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 193:175]
wire _T_677 = _T_675 & _T_50; // @[el2_lsu_stbuf.scala 193:190]
wire _T_678 = _T_677 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211]
wire _T_667 = stbuf_addr_1[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116]
wire _T_668 = _T_667 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 193:175]
wire _T_670 = _T_668 & _T_41; // @[el2_lsu_stbuf.scala 193:190]
wire _T_671 = _T_670 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211]
wire _T_660 = stbuf_addr_0[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116]
wire _T_661 = _T_660 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 193:175]
wire _T_663 = _T_661 & _T_32; // @[el2_lsu_stbuf.scala 193:190]
wire _T_664 = _T_663 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211]
wire [3:0] stbuf_match_hi = {_T_685,_T_678,_T_671,_T_664}; // @[Cat.scala 29:58]
wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 190:18]
wire _T_711 = stbuf_addr_3[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116]
wire _T_712 = _T_711 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 194:175]
wire _T_714 = _T_712 & _T_59; // @[el2_lsu_stbuf.scala 194:190]
wire _T_715 = _T_714 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211]
wire _T_704 = stbuf_addr_2[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116]
wire _T_705 = _T_704 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 194:175]
wire _T_707 = _T_705 & _T_50; // @[el2_lsu_stbuf.scala 194:190]
wire _T_708 = _T_707 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211]
wire _T_697 = stbuf_addr_1[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116]
wire _T_698 = _T_697 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 194:175]
wire _T_700 = _T_698 & _T_41; // @[el2_lsu_stbuf.scala 194:190]
wire _T_701 = _T_700 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211]
wire _T_690 = stbuf_addr_0[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116]
wire _T_691 = _T_690 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 194:175]
wire _T_693 = _T_691 & _T_32; // @[el2_lsu_stbuf.scala 194:190]
wire _T_694 = _T_693 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211]
wire [3:0] stbuf_match_lo = {_T_715,_T_708,_T_701,_T_694}; // @[Cat.scala 29:58]
wire _T_738 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 195:79]
wire _T_739 = _T_738 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100]
wire _T_740 = _T_739 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121]
wire _T_741 = _T_740 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140]
wire _T_732 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 195:79]
wire _T_733 = _T_732 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100]
wire _T_734 = _T_733 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121]
wire _T_735 = _T_734 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140]
wire _T_726 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 195:79]
wire _T_727 = _T_726 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100]
wire _T_728 = _T_727 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121]
wire _T_729 = _T_728 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140]
wire _T_720 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 195:79]
wire _T_721 = _T_720 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100]
wire _T_722 = _T_721 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121]
wire _T_723 = _T_722 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140]
wire [3:0] stbuf_dma_kill_en = {_T_741,_T_735,_T_729,_T_723}; // @[Cat.scala 29:58]
wire _GEN_1 = stbuf_dma_kill_en[0] | stbuf_dma_kill_0; // @[Reg.scala 28:19]
wire [15:0] stbuf_addrin_0 = _T_226[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17]
wire _GEN_5 = stbuf_wr_en[1] | stbuf_vld_1; // @[Reg.scala 28:19]
wire _GEN_6 = stbuf_dma_kill_en[1] | stbuf_dma_kill_1; // @[Reg.scala 28:19]
wire [15:0] stbuf_addrin_1 = _T_224[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17]
wire _GEN_10 = stbuf_wr_en[2] | stbuf_vld_2; // @[Reg.scala 28:19]
wire _GEN_11 = stbuf_dma_kill_en[2] | stbuf_dma_kill_2; // @[Reg.scala 28:19]
wire [15:0] stbuf_addrin_2 = _T_222[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17]
wire _GEN_15 = stbuf_wr_en[3] | stbuf_vld_3; // @[Reg.scala 28:19]
wire _GEN_16 = stbuf_dma_kill_en[3] | stbuf_dma_kill_3; // @[Reg.scala 28:19]
wire [15:0] stbuf_addrin_3 = _T_220[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17]
reg ldst_dual_m; // @[el2_lsu_stbuf.scala 160:53]
wire _GEN_21 = 2'h1 == RdPtr ? stbuf_vld_1 : stbuf_vld_0; // @[el2_lsu_stbuf.scala 164:52]
wire _GEN_22 = 2'h2 == RdPtr ? stbuf_vld_2 : _GEN_21; // @[el2_lsu_stbuf.scala 164:52]
wire _GEN_23 = 2'h3 == RdPtr ? stbuf_vld_3 : _GEN_22; // @[el2_lsu_stbuf.scala 164:52]
wire _GEN_25 = 2'h1 == RdPtr ? stbuf_dma_kill_1 : stbuf_dma_kill_0; // @[el2_lsu_stbuf.scala 164:52]
wire _GEN_26 = 2'h2 == RdPtr ? stbuf_dma_kill_2 : _GEN_25; // @[el2_lsu_stbuf.scala 164:52]
wire _GEN_27 = 2'h3 == RdPtr ? stbuf_dma_kill_3 : _GEN_26; // @[el2_lsu_stbuf.scala 164:52]
wire _T_602 = ~_GEN_27; // @[el2_lsu_stbuf.scala 165:47]
wire _T_603 = _GEN_23 & _T_602; // @[el2_lsu_stbuf.scala 165:45]
wire _T_604 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 165:91]
wire _T_605 = ~_T_604; // @[el2_lsu_stbuf.scala 165:72]
wire [15:0] _GEN_29 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 166:23]
wire [15:0] _GEN_30 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_29; // @[el2_lsu_stbuf.scala 166:23]
wire [31:0] _GEN_33 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 167:23]
wire [31:0] _GEN_34 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_33; // @[el2_lsu_stbuf.scala 167:23]
wire [3:0] _T_622 = {3'h0,stbuf_vld_0}; // @[Cat.scala 29:58]
wire [3:0] _T_623 = {3'h0,stbuf_vld_1}; // @[Cat.scala 29:58]
wire [3:0] _T_624 = {3'h0,stbuf_vld_2}; // @[Cat.scala 29:58]
wire [3:0] _T_625 = {3'h0,stbuf_vld_3}; // @[Cat.scala 29:58]
wire [3:0] _T_628 = _T_622 + _T_623; // @[el2_lsu_stbuf.scala 175:102]
wire [3:0] _T_630 = _T_628 + _T_624; // @[el2_lsu_stbuf.scala 175:102]
wire [3:0] stbuf_numvld_any = _T_630 + _T_625; // @[el2_lsu_stbuf.scala 175:102]
wire _T_632 = io_lsu_pkt_m_valid & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 176:40]
wire _T_633 = _T_632 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 176:61]
wire _T_634 = ~io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 176:83]
wire isdccmst_m = _T_633 & _T_634; // @[el2_lsu_stbuf.scala 176:81]
wire _T_635 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 177:40]
wire _T_636 = _T_635 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 177:61]
wire _T_637 = ~io_lsu_pkt_r_dma; // @[el2_lsu_stbuf.scala 177:83]
wire isdccmst_r = _T_636 & _T_637; // @[el2_lsu_stbuf.scala 177:81]
wire [1:0] _T_638 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58]
wire _T_639 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 179:63]
wire [2:0] _GEN_39 = {{1'd0}, _T_638}; // @[el2_lsu_stbuf.scala 179:48]
wire [2:0] _T_640 = _GEN_39 << _T_639; // @[el2_lsu_stbuf.scala 179:48]
wire [1:0] _T_641 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58]
wire _T_642 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 180:63]
wire [2:0] _GEN_40 = {{1'd0}, _T_641}; // @[el2_lsu_stbuf.scala 180:48]
wire [2:0] _T_643 = _GEN_40 << _T_642; // @[el2_lsu_stbuf.scala 180:48]
wire [1:0] stbuf_specvld_m = _T_640[1:0]; // @[el2_lsu_stbuf.scala 179:20]
wire [3:0] _T_644 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58]
wire [3:0] _T_646 = stbuf_numvld_any + _T_644; // @[el2_lsu_stbuf.scala 181:45]
wire [1:0] stbuf_specvld_r = _T_643[1:0]; // @[el2_lsu_stbuf.scala 180:20]
wire [3:0] _T_647 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58]
wire [3:0] stbuf_specvld_any = _T_646 + _T_647; // @[el2_lsu_stbuf.scala 181:79]
wire _T_649 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 183:35]
wire _T_650 = _T_649 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 183:48]
wire _T_652 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 183:99]
wire _T_653 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 183:138]
wire _T_747 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_748 = _T_747 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138]
wire _T_751 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_752 = _T_751 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138]
wire _T_755 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_756 = _T_755 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138]
wire _T_759 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_760 = _T_759 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138]
wire [3:0] stbuf_fwdbyteenvec_hi_0 = {_T_760,_T_756,_T_752,_T_748}; // @[Cat.scala 29:58]
wire _T_765 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_766 = _T_765 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138]
wire _T_769 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_770 = _T_769 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138]
wire _T_773 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_774 = _T_773 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138]
wire _T_777 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_778 = _T_777 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138]
wire [3:0] stbuf_fwdbyteenvec_hi_1 = {_T_778,_T_774,_T_770,_T_766}; // @[Cat.scala 29:58]
wire _T_783 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_784 = _T_783 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138]
wire _T_787 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_788 = _T_787 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138]
wire _T_791 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_792 = _T_791 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138]
wire _T_795 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_796 = _T_795 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138]
wire [3:0] stbuf_fwdbyteenvec_hi_2 = {_T_796,_T_792,_T_788,_T_784}; // @[Cat.scala 29:58]
wire _T_801 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_802 = _T_801 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138]
wire _T_805 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_806 = _T_805 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138]
wire _T_809 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_810 = _T_809 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138]
wire _T_813 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 198:117]
wire _T_814 = _T_813 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138]
wire [3:0] stbuf_fwdbyteenvec_hi_3 = {_T_814,_T_810,_T_806,_T_802}; // @[Cat.scala 29:58]
wire _T_819 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_820 = _T_819 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138]
wire _T_823 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_824 = _T_823 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138]
wire _T_827 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_828 = _T_827 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138]
wire _T_831 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_832 = _T_831 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138]
wire [3:0] stbuf_fwdbyteenvec_lo_0 = {_T_832,_T_828,_T_824,_T_820}; // @[Cat.scala 29:58]
wire _T_837 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_838 = _T_837 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138]
wire _T_841 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_842 = _T_841 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138]
wire _T_845 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_846 = _T_845 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138]
wire _T_849 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_850 = _T_849 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138]
wire [3:0] stbuf_fwdbyteenvec_lo_1 = {_T_850,_T_846,_T_842,_T_838}; // @[Cat.scala 29:58]
wire _T_855 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_856 = _T_855 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138]
wire _T_859 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_860 = _T_859 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138]
wire _T_863 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_864 = _T_863 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138]
wire _T_867 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_868 = _T_867 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138]
wire [3:0] stbuf_fwdbyteenvec_lo_2 = {_T_868,_T_864,_T_860,_T_856}; // @[Cat.scala 29:58]
wire _T_873 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_874 = _T_873 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138]
wire _T_877 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_878 = _T_877 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138]
wire _T_881 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_882 = _T_881 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138]
wire _T_885 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 199:117]
wire _T_886 = _T_885 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138]
wire [3:0] stbuf_fwdbyteenvec_lo_3 = {_T_886,_T_882,_T_878,_T_874}; // @[Cat.scala 29:58]
wire _T_893 = stbuf_fwdbyteenvec_hi_0[3] | stbuf_fwdbyteenvec_hi_0[2]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_894 = _T_893 | stbuf_fwdbyteenvec_hi_0[1]; // @[el2_lsu_stbuf.scala 200:156]
wire stbuf_fwdbyteen_hi_pre_m_0 = _T_894 | stbuf_fwdbyteenvec_hi_0[0]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_899 = stbuf_fwdbyteenvec_hi_1[3] | stbuf_fwdbyteenvec_hi_1[2]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_900 = _T_899 | stbuf_fwdbyteenvec_hi_1[1]; // @[el2_lsu_stbuf.scala 200:156]
wire stbuf_fwdbyteen_hi_pre_m_1 = _T_900 | stbuf_fwdbyteenvec_hi_1[0]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_905 = stbuf_fwdbyteenvec_hi_2[3] | stbuf_fwdbyteenvec_hi_2[2]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_906 = _T_905 | stbuf_fwdbyteenvec_hi_2[1]; // @[el2_lsu_stbuf.scala 200:156]
wire stbuf_fwdbyteen_hi_pre_m_2 = _T_906 | stbuf_fwdbyteenvec_hi_2[0]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_911 = stbuf_fwdbyteenvec_hi_3[3] | stbuf_fwdbyteenvec_hi_3[2]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_912 = _T_911 | stbuf_fwdbyteenvec_hi_3[1]; // @[el2_lsu_stbuf.scala 200:156]
wire stbuf_fwdbyteen_hi_pre_m_3 = _T_912 | stbuf_fwdbyteenvec_hi_3[0]; // @[el2_lsu_stbuf.scala 200:156]
wire _T_917 = stbuf_fwdbyteenvec_lo_0[3] | stbuf_fwdbyteenvec_lo_0[2]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_918 = _T_917 | stbuf_fwdbyteenvec_lo_0[1]; // @[el2_lsu_stbuf.scala 201:156]
wire stbuf_fwdbyteen_lo_pre_m_0 = _T_918 | stbuf_fwdbyteenvec_lo_0[0]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_923 = stbuf_fwdbyteenvec_lo_1[3] | stbuf_fwdbyteenvec_lo_1[2]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_924 = _T_923 | stbuf_fwdbyteenvec_lo_1[1]; // @[el2_lsu_stbuf.scala 201:156]
wire stbuf_fwdbyteen_lo_pre_m_1 = _T_924 | stbuf_fwdbyteenvec_lo_1[0]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_929 = stbuf_fwdbyteenvec_lo_2[3] | stbuf_fwdbyteenvec_lo_2[2]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_930 = _T_929 | stbuf_fwdbyteenvec_lo_2[1]; // @[el2_lsu_stbuf.scala 201:156]
wire stbuf_fwdbyteen_lo_pre_m_2 = _T_930 | stbuf_fwdbyteenvec_lo_2[0]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_935 = stbuf_fwdbyteenvec_lo_3[3] | stbuf_fwdbyteenvec_lo_3[2]; // @[el2_lsu_stbuf.scala 201:156]
wire _T_936 = _T_935 | stbuf_fwdbyteenvec_lo_3[1]; // @[el2_lsu_stbuf.scala 201:156]
wire stbuf_fwdbyteen_lo_pre_m_3 = _T_936 | stbuf_fwdbyteenvec_lo_3[0]; // @[el2_lsu_stbuf.scala 201:156]
wire [31:0] _T_939 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_940 = _T_939 & stbuf_data_0; // @[el2_lsu_stbuf.scala 203:98]
wire [31:0] _T_943 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_944 = _T_943 & stbuf_data_1; // @[el2_lsu_stbuf.scala 203:98]
wire [31:0] _T_947 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_948 = _T_947 & stbuf_data_2; // @[el2_lsu_stbuf.scala 203:98]
wire [31:0] _T_951 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_952 = _T_951 & stbuf_data_3; // @[el2_lsu_stbuf.scala 203:98]
wire [31:0] _T_954 = _T_940 | _T_944; // @[el2_lsu_stbuf.scala 203:123]
wire [31:0] _T_955 = _T_954 | _T_948; // @[el2_lsu_stbuf.scala 203:123]
wire [31:0] stbuf_fwddata_hi_pre_m = _T_955 | _T_952; // @[el2_lsu_stbuf.scala 203:123]
wire [31:0] _T_958 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_959 = _T_958 & stbuf_data_0; // @[el2_lsu_stbuf.scala 204:98]
wire [31:0] _T_962 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_963 = _T_962 & stbuf_data_1; // @[el2_lsu_stbuf.scala 204:98]
wire [31:0] _T_966 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_967 = _T_966 & stbuf_data_2; // @[el2_lsu_stbuf.scala 204:98]
wire [31:0] _T_970 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_971 = _T_970 & stbuf_data_3; // @[el2_lsu_stbuf.scala 204:98]
wire [31:0] _T_973 = _T_959 | _T_963; // @[el2_lsu_stbuf.scala 204:123]
wire [31:0] _T_974 = _T_973 | _T_967; // @[el2_lsu_stbuf.scala 204:123]
wire [31:0] stbuf_fwddata_lo_pre_m = _T_974 | _T_971; // @[el2_lsu_stbuf.scala 204:123]
wire _T_979 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 210:50]
wire _T_980 = _T_979 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 210:75]
wire _T_981 = _T_980 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 210:96]
wire ld_addr_rhit_lo_lo = _T_981 & _T_637; // @[el2_lsu_stbuf.scala 210:117]
wire _T_985 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 211:50]
wire _T_986 = _T_985 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 211:75]
wire _T_987 = _T_986 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 211:96]
wire ld_addr_rhit_lo_hi = _T_987 & _T_637; // @[el2_lsu_stbuf.scala 211:117]
wire _T_991 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 212:50]
wire _T_992 = _T_991 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 212:75]
wire _T_993 = _T_992 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 212:96]
wire _T_995 = _T_993 & _T_637; // @[el2_lsu_stbuf.scala 212:117]
wire ld_addr_rhit_hi_lo = _T_995 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 212:137]
wire _T_998 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 213:50]
wire _T_999 = _T_998 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 213:75]
wire _T_1000 = _T_999 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 213:96]
wire _T_1002 = _T_1000 & _T_637; // @[el2_lsu_stbuf.scala 213:117]
wire ld_addr_rhit_hi_hi = _T_1002 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 213:137]
wire _T_1004 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 215:80]
wire _T_1006 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 215:80]
wire _T_1008 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 215:80]
wire _T_1010 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 215:80]
wire [3:0] _T_1013 = {_T_1010,_T_1008,_T_1006,_T_1004}; // @[Cat.scala 29:58]
wire _T_1015 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 216:80]
wire _T_1017 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 216:80]
wire _T_1019 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 216:80]
wire _T_1021 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 216:80]
wire [3:0] _T_1024 = {_T_1021,_T_1019,_T_1017,_T_1015}; // @[Cat.scala 29:58]
wire _T_1026 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 217:80]
wire _T_1028 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 217:80]
wire _T_1030 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 217:80]
wire _T_1032 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 217:80]
wire [3:0] _T_1035 = {_T_1032,_T_1030,_T_1028,_T_1026}; // @[Cat.scala 29:58]
wire _T_1037 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 218:80]
wire _T_1039 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 218:80]
wire _T_1041 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 218:80]
wire _T_1043 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 218:80]
wire [3:0] _T_1046 = {_T_1043,_T_1041,_T_1039,_T_1037}; // @[Cat.scala 29:58]
wire [31:0] ld_byte_rhit_hi_lo = {{28'd0}, _T_1035}; // @[el2_lsu_stbuf.scala 217:23]
wire [31:0] ld_byte_rhit_lo_lo = {{28'd0}, _T_1013}; // @[el2_lsu_stbuf.scala 215:23]
wire [31:0] _GEN_42 = {{31'd0}, ld_byte_rhit_hi_lo[0]}; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _T_1048 = ld_byte_rhit_lo_lo | _GEN_42; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _GEN_43 = {{31'd0}, ld_byte_rhit_hi_lo[1]}; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _T_1050 = ld_byte_rhit_lo_lo | _GEN_43; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _GEN_44 = {{31'd0}, ld_byte_rhit_hi_lo[2]}; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _T_1052 = ld_byte_rhit_lo_lo | _GEN_44; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _GEN_45 = {{31'd0}, ld_byte_rhit_hi_lo[3]}; // @[el2_lsu_stbuf.scala 220:77]
wire [31:0] _T_1054 = ld_byte_rhit_lo_lo | _GEN_45; // @[el2_lsu_stbuf.scala 220:77]
wire [127:0] _T_1057 = {_T_1054,_T_1052,_T_1050,_T_1048}; // @[Cat.scala 29:58]
wire [31:0] ld_byte_rhit_hi_hi = {{28'd0}, _T_1046}; // @[el2_lsu_stbuf.scala 218:23]
wire [31:0] ld_byte_rhit_lo_hi = {{28'd0}, _T_1024}; // @[el2_lsu_stbuf.scala 216:23]
wire [31:0] _GEN_46 = {{31'd0}, ld_byte_rhit_hi_hi[0]}; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _T_1059 = ld_byte_rhit_lo_hi | _GEN_46; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _GEN_47 = {{31'd0}, ld_byte_rhit_hi_hi[1]}; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _T_1061 = ld_byte_rhit_lo_hi | _GEN_47; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _GEN_48 = {{31'd0}, ld_byte_rhit_hi_hi[2]}; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _T_1063 = ld_byte_rhit_lo_hi | _GEN_48; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _GEN_49 = {{31'd0}, ld_byte_rhit_hi_hi[3]}; // @[el2_lsu_stbuf.scala 221:77]
wire [31:0] _T_1065 = ld_byte_rhit_lo_hi | _GEN_49; // @[el2_lsu_stbuf.scala 221:77]
wire [127:0] _T_1068 = {_T_1065,_T_1063,_T_1061,_T_1059}; // @[Cat.scala 29:58]
wire [7:0] _T_1071 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1073 = _T_1071 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 223:54]
wire [7:0] _T_1076 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1078 = _T_1076 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 223:115]
wire [7:0] fwdpipe1_lo = _T_1073 | _T_1078; // @[el2_lsu_stbuf.scala 223:81]
wire [7:0] _T_1081 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1083 = _T_1081 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 224:54]
wire [7:0] _T_1086 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1088 = _T_1086 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 224:116]
wire [7:0] fwdpipe2_lo = _T_1083 | _T_1088; // @[el2_lsu_stbuf.scala 224:82]
wire [7:0] _T_1091 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1093 = _T_1091 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 225:54]
wire [7:0] _T_1096 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1098 = _T_1096 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 225:117]
wire [7:0] fwdpipe3_lo = _T_1093 | _T_1098; // @[el2_lsu_stbuf.scala 225:83]
wire [7:0] _T_1101 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1103 = _T_1101 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 226:54]
wire [7:0] _T_1106 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [23:0] _GEN_50 = {{16'd0}, _T_1106}; // @[el2_lsu_stbuf.scala 226:117]
wire [23:0] _T_1108 = _GEN_50 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 226:117]
wire [23:0] _GEN_51 = {{16'd0}, _T_1103}; // @[el2_lsu_stbuf.scala 226:83]
wire [23:0] fwdpipe4_lo = _GEN_51 | _T_1108; // @[el2_lsu_stbuf.scala 226:83]
wire [47:0] _T_1111 = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58]
wire [7:0] _T_1114 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1116 = _T_1114 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 229:54]
wire [7:0] _T_1119 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1121 = _T_1119 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 229:115]
wire [7:0] fwdpipe1_hi = _T_1116 | _T_1121; // @[el2_lsu_stbuf.scala 229:81]
wire [7:0] _T_1124 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1126 = _T_1124 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 230:54]
wire [7:0] _T_1129 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1131 = _T_1129 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 230:116]
wire [7:0] fwdpipe2_hi = _T_1126 | _T_1131; // @[el2_lsu_stbuf.scala 230:82]
wire [7:0] _T_1134 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1136 = _T_1134 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 231:54]
wire [7:0] _T_1139 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1141 = _T_1139 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 231:117]
wire [7:0] fwdpipe3_hi = _T_1136 | _T_1141; // @[el2_lsu_stbuf.scala 231:83]
wire [7:0] _T_1144 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_1146 = _T_1144 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 232:54]
wire [7:0] _T_1149 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [23:0] _GEN_52 = {{16'd0}, _T_1149}; // @[el2_lsu_stbuf.scala 232:117]
wire [23:0] _T_1151 = _GEN_52 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 232:117]
wire [23:0] _GEN_53 = {{16'd0}, _T_1146}; // @[el2_lsu_stbuf.scala 232:83]
wire [23:0] fwdpipe4_hi = _GEN_53 | _T_1151; // @[el2_lsu_stbuf.scala 232:83]
wire [47:0] _T_1154 = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58]
wire [2:0] _T_1164 = {stbuf_fwdbyteen_hi_pre_m_3,stbuf_fwdbyteen_hi_pre_m_2,stbuf_fwdbyteen_hi_pre_m_1}; // @[Cat.scala 29:58]
wire [2:0] _T_1175 = {stbuf_fwdbyteen_lo_pre_m_3,stbuf_fwdbyteen_lo_pre_m_2,stbuf_fwdbyteen_lo_pre_m_1}; // @[Cat.scala 29:58]
wire [3:0] ld_byte_rhit_lo = _T_1057[3:0]; // @[el2_lsu_stbuf.scala 220:20]
wire [31:0] ld_fwddata_rpipe_lo = _T_1111[31:0]; // @[el2_lsu_stbuf.scala 227:24]
wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 239:31]
wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 240:31]
wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 241:31]
wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 242:31]
wire [15:0] _T_1189 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58]
wire [15:0] _T_1190 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58]
wire [3:0] ld_byte_rhit_hi = _T_1068[3:0]; // @[el2_lsu_stbuf.scala 221:20]
wire [31:0] ld_fwddata_rpipe_hi = _T_1154[31:0]; // @[el2_lsu_stbuf.scala 233:24]
wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 245:31]
wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 246:31]
wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 247:31]
wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 248:31]
wire [15:0] _T_1204 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
wire [15:0] _T_1205 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
assign io_stbuf_reqvld_any = _T_603 & _T_605; // @[el2_lsu_stbuf.scala 50:47 el2_lsu_stbuf.scala 165:25]
assign io_stbuf_reqvld_flushed_any = _GEN_23 & _GEN_27; // @[el2_lsu_stbuf.scala 51:36 el2_lsu_stbuf.scala 164:32]
assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_30; // @[el2_lsu_stbuf.scala 52:35 el2_lsu_stbuf.scala 166:23]
assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_34; // @[el2_lsu_stbuf.scala 53:35 el2_lsu_stbuf.scala 167:23]
assign io_lsu_stbuf_full_any = _T_650 ? _T_652 : _T_653; // @[el2_lsu_stbuf.scala 54:43 el2_lsu_stbuf.scala 183:27]
assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 55:43 el2_lsu_stbuf.scala 184:27]
assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 122:27]
assign io_stbuf_fwddata_hi_m = {_T_1205,_T_1204}; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 249:26]
assign io_stbuf_fwddata_lo_m = {_T_1190,_T_1189}; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 243:26]
assign io_stbuf_fwdbyteen_hi_m = {_T_1164,stbuf_fwdbyteen_hi_pre_m_0}; // @[el2_lsu_stbuf.scala 59:37 el2_lsu_stbuf.scala 235:28]
assign io_stbuf_fwdbyteen_lo_m = {_T_1175,stbuf_fwdbyteen_lo_pre_m_0}; // @[el2_lsu_stbuf.scala 60:37 el2_lsu_stbuf.scala 236:28]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
ldst_dual_r = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
RdPtr = _RAND_1[1:0];
_RAND_2 = {1{`RANDOM}};
stbuf_addr_0 = _RAND_2[15:0];
_RAND_3 = {1{`RANDOM}};
stbuf_vld_0 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
stbuf_dma_kill_0 = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
stbuf_addr_1 = _RAND_5[15:0];
_RAND_6 = {1{`RANDOM}};
stbuf_vld_1 = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
stbuf_dma_kill_1 = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
stbuf_addr_2 = _RAND_8[15:0];
_RAND_9 = {1{`RANDOM}};
stbuf_vld_2 = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
stbuf_dma_kill_2 = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}};
stbuf_addr_3 = _RAND_11[15:0];
_RAND_12 = {1{`RANDOM}};
stbuf_vld_3 = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
stbuf_dma_kill_3 = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
stbuf_byteen_0 = _RAND_14[3:0];
_RAND_15 = {1{`RANDOM}};
stbuf_byteen_1 = _RAND_15[3:0];
_RAND_16 = {1{`RANDOM}};
stbuf_byteen_2 = _RAND_16[3:0];
_RAND_17 = {1{`RANDOM}};
stbuf_byteen_3 = _RAND_17[3:0];
_RAND_18 = {1{`RANDOM}};
stbuf_data_0 = _RAND_18[31:0];
_RAND_19 = {1{`RANDOM}};
stbuf_data_1 = _RAND_19[31:0];
_RAND_20 = {1{`RANDOM}};
stbuf_data_2 = _RAND_20[31:0];
_RAND_21 = {1{`RANDOM}};
stbuf_data_3 = _RAND_21[31:0];
_RAND_22 = {1{`RANDOM}};
ldst_dual_m = _RAND_22[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_lsu_c1_r_clk) begin
if (reset) begin
ldst_dual_r <= 1'h0;
end else begin
ldst_dual_r <= ldst_dual_m;
end
end
always @(posedge io_lsu_stbuf_c1_clk) begin
if (reset) begin
RdPtr <= 2'h0;
end else if (_T_184) begin
RdPtr <= NxtRdPtr;
end
if (reset) begin
stbuf_byteen_0 <= 4'h0;
end else if (stbuf_wr_en[0]) begin
if (sel_lo[3]) begin
stbuf_byteen_0 <= _T_240;
end else begin
stbuf_byteen_0 <= _T_241;
end
end
if (reset) begin
stbuf_byteen_1 <= 4'h0;
end else if (stbuf_wr_en[1]) begin
if (sel_lo[2]) begin
stbuf_byteen_1 <= _T_236;
end else begin
stbuf_byteen_1 <= _T_237;
end
end
if (reset) begin
stbuf_byteen_2 <= 4'h0;
end else if (stbuf_wr_en[2]) begin
if (sel_lo[1]) begin
stbuf_byteen_2 <= _T_232;
end else begin
stbuf_byteen_2 <= _T_233;
end
end
if (reset) begin
stbuf_byteen_3 <= 4'h0;
end else if (stbuf_wr_en[3]) begin
if (sel_lo[0]) begin
stbuf_byteen_3 <= _T_228;
end else begin
stbuf_byteen_3 <= _T_229;
end
end
end
always @(posedge clock) begin
if (reset) begin
stbuf_addr_0 <= 16'h0;
end else if (stbuf_wr_en[0]) begin
stbuf_addr_0 <= stbuf_addrin_0;
end
if (reset) begin
stbuf_addr_1 <= 16'h0;
end else if (stbuf_wr_en[1]) begin
stbuf_addr_1 <= stbuf_addrin_1;
end
if (reset) begin
stbuf_addr_2 <= 16'h0;
end else if (stbuf_wr_en[2]) begin
stbuf_addr_2 <= stbuf_addrin_2;
end
if (reset) begin
stbuf_addr_3 <= 16'h0;
end else if (stbuf_wr_en[3]) begin
stbuf_addr_3 <= stbuf_addrin_3;
end
if (reset) begin
stbuf_data_0 <= 32'h0;
end else if (stbuf_wr_en[0]) begin
stbuf_data_0 <= stbuf_datain_0;
end
if (reset) begin
stbuf_data_1 <= 32'h0;
end else if (stbuf_wr_en[1]) begin
stbuf_data_1 <= stbuf_datain_1;
end
if (reset) begin
stbuf_data_2 <= 32'h0;
end else if (stbuf_wr_en[2]) begin
stbuf_data_2 <= stbuf_datain_2;
end
if (reset) begin
stbuf_data_3 <= 32'h0;
end else if (stbuf_wr_en[3]) begin
stbuf_data_3 <= stbuf_datain_3;
end
end
always @(posedge io_lsu_free_c2_clk) begin
if (reset) begin
stbuf_vld_0 <= 1'h0;
end else begin
stbuf_vld_0 <= _GEN_0;
end
if (reset) begin
stbuf_dma_kill_0 <= 1'h0;
end else begin
stbuf_dma_kill_0 <= _GEN_1;
end
if (reset) begin
stbuf_vld_1 <= 1'h0;
end else begin
stbuf_vld_1 <= _GEN_5;
end
if (reset) begin
stbuf_dma_kill_1 <= 1'h0;
end else begin
stbuf_dma_kill_1 <= _GEN_6;
end
if (reset) begin
stbuf_vld_2 <= 1'h0;
end else begin
stbuf_vld_2 <= _GEN_10;
end
if (reset) begin
stbuf_dma_kill_2 <= 1'h0;
end else begin
stbuf_dma_kill_2 <= _GEN_11;
end
if (reset) begin
stbuf_vld_3 <= 1'h0;
end else begin
stbuf_vld_3 <= _GEN_15;
end
if (reset) begin
stbuf_dma_kill_3 <= 1'h0;
end else begin
stbuf_dma_kill_3 <= _GEN_16;
end
end
always @(posedge io_lsu_c1_m_clk) begin
if (reset) begin
ldst_dual_m <= 1'h0;
end else begin
ldst_dual_m <= ldst_dual_d;
end
end
endmodule

52
el2_lsu_trigger.anno.json Normal file
View File

@ -0,0 +1,52 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_trigger_match_m",
"sources":[
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_valid",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_dma",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_store",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_load",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_select",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_tdata2",
"~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_addr_m",
"~el2_lsu_trigger|el2_lsu_trigger>io_store_data_m",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_word",
"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_half"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_lsu_trigger"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1263
el2_lsu_trigger.fir Normal file
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655
el2_lsu_trigger.v Normal file
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@ -0,0 +1,655 @@
module el2_lsu_trigger(
input clock,
input reset,
input io_trigger_pkt_any_0_select,
input io_trigger_pkt_any_0_match_,
input io_trigger_pkt_any_0_store,
input io_trigger_pkt_any_0_load,
input io_trigger_pkt_any_0_execute,
input io_trigger_pkt_any_0_m,
input [31:0] io_trigger_pkt_any_0_tdata2,
input io_trigger_pkt_any_1_select,
input io_trigger_pkt_any_1_match_,
input io_trigger_pkt_any_1_store,
input io_trigger_pkt_any_1_load,
input io_trigger_pkt_any_1_execute,
input io_trigger_pkt_any_1_m,
input [31:0] io_trigger_pkt_any_1_tdata2,
input io_trigger_pkt_any_2_select,
input io_trigger_pkt_any_2_match_,
input io_trigger_pkt_any_2_store,
input io_trigger_pkt_any_2_load,
input io_trigger_pkt_any_2_execute,
input io_trigger_pkt_any_2_m,
input [31:0] io_trigger_pkt_any_2_tdata2,
input io_trigger_pkt_any_3_select,
input io_trigger_pkt_any_3_match_,
input io_trigger_pkt_any_3_store,
input io_trigger_pkt_any_3_load,
input io_trigger_pkt_any_3_execute,
input io_trigger_pkt_any_3_m,
input [31:0] io_trigger_pkt_any_3_tdata2,
input io_lsu_pkt_m_fast_int,
input io_lsu_pkt_m_by,
input io_lsu_pkt_m_half,
input io_lsu_pkt_m_word,
input io_lsu_pkt_m_dword,
input io_lsu_pkt_m_load,
input io_lsu_pkt_m_store,
input io_lsu_pkt_m_unsign,
input io_lsu_pkt_m_dma,
input io_lsu_pkt_m_store_data_bypass_d,
input io_lsu_pkt_m_load_ldst_bypass_d,
input io_lsu_pkt_m_store_data_bypass_m,
input io_lsu_pkt_m_valid,
input [31:0] io_lsu_addr_m,
input [31:0] io_store_data_m,
output [3:0] io_lsu_trigger_match_m
);
wire [15:0] _T_1 = io_lsu_pkt_m_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 18:61]
wire _T_4 = io_lsu_pkt_m_half | io_lsu_pkt_m_word; // @[el2_lsu_trigger.scala 18:114]
wire [7:0] _T_6 = _T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 18:136]
wire [31:0] store_data_trigger_m = {_T_3,_T_8,io_store_data_m[7:0]}; // @[Cat.scala 29:58]
wire _T_11 = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 20:57]
wire [31:0] _T_13 = _T_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_14 = _T_13 & io_lsu_addr_m; // @[el2_lsu_trigger.scala 20:88]
wire [31:0] _T_16 = io_trigger_pkt_any_0_select ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _GEN_0 = {{31'd0}, io_trigger_pkt_any_0_store}; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_17 = _T_16 & _GEN_0; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_18 = _T_17 & store_data_trigger_m; // @[el2_lsu_trigger.scala 20:179]
wire [31:0] lsu_match_data_0 = _T_14 | _T_18; // @[el2_lsu_trigger.scala 20:105]
wire _T_20 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 20:57]
wire [31:0] _T_22 = _T_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_23 = _T_22 & io_lsu_addr_m; // @[el2_lsu_trigger.scala 20:88]
wire [31:0] _T_25 = io_trigger_pkt_any_1_select ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _GEN_1 = {{31'd0}, io_trigger_pkt_any_1_store}; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_26 = _T_25 & _GEN_1; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_27 = _T_26 & store_data_trigger_m; // @[el2_lsu_trigger.scala 20:179]
wire [31:0] lsu_match_data_1 = _T_23 | _T_27; // @[el2_lsu_trigger.scala 20:105]
wire _T_29 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 20:57]
wire [31:0] _T_31 = _T_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_32 = _T_31 & io_lsu_addr_m; // @[el2_lsu_trigger.scala 20:88]
wire [31:0] _T_34 = io_trigger_pkt_any_2_select ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _GEN_2 = {{31'd0}, io_trigger_pkt_any_2_store}; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_35 = _T_34 & _GEN_2; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_36 = _T_35 & store_data_trigger_m; // @[el2_lsu_trigger.scala 20:179]
wire [31:0] lsu_match_data_2 = _T_32 | _T_36; // @[el2_lsu_trigger.scala 20:105]
wire _T_38 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 20:57]
wire [31:0] _T_40 = _T_38 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_41 = _T_40 & io_lsu_addr_m; // @[el2_lsu_trigger.scala 20:88]
wire [31:0] _T_43 = io_trigger_pkt_any_3_select ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _GEN_3 = {{31'd0}, io_trigger_pkt_any_3_store}; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_44 = _T_43 & _GEN_3; // @[el2_lsu_trigger.scala 20:148]
wire [31:0] _T_45 = _T_44 & store_data_trigger_m; // @[el2_lsu_trigger.scala 20:179]
wire [31:0] lsu_match_data_3 = _T_41 | _T_45; // @[el2_lsu_trigger.scala 20:105]
wire _T_48 = ~io_lsu_pkt_m_dma; // @[el2_lsu_trigger.scala 21:71]
wire _T_49 = io_lsu_pkt_m_valid & _T_48; // @[el2_lsu_trigger.scala 21:69]
wire _T_50 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 21:120]
wire _T_51 = _T_49 & _T_50; // @[el2_lsu_trigger.scala 21:89]
wire _T_52 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 22:33]
wire _T_54 = _T_52 & _T_11; // @[el2_lsu_trigger.scala 22:53]
wire _T_57 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 194:45]
wire _T_58 = ~_T_57; // @[el2_lib.scala 194:39]
wire _T_59 = io_trigger_pkt_any_0_match_ & _T_58; // @[el2_lib.scala 194:37]
wire _T_62 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 195:52]
wire _T_63 = _T_59 | _T_62; // @[el2_lib.scala 195:41]
wire _T_65 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_66 = _T_65 & _T_59; // @[el2_lib.scala 197:43]
wire _T_69 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 197:80]
wire _T_70 = _T_66 | _T_69; // @[el2_lib.scala 197:25]
wire _T_72 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_73 = _T_72 & _T_59; // @[el2_lib.scala 197:43]
wire _T_76 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 197:80]
wire _T_77 = _T_73 | _T_76; // @[el2_lib.scala 197:25]
wire _T_79 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_80 = _T_79 & _T_59; // @[el2_lib.scala 197:43]
wire _T_83 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 197:80]
wire _T_84 = _T_80 | _T_83; // @[el2_lib.scala 197:25]
wire _T_86 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_87 = _T_86 & _T_59; // @[el2_lib.scala 197:43]
wire _T_90 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 197:80]
wire _T_91 = _T_87 | _T_90; // @[el2_lib.scala 197:25]
wire _T_93 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_94 = _T_93 & _T_59; // @[el2_lib.scala 197:43]
wire _T_97 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 197:80]
wire _T_98 = _T_94 | _T_97; // @[el2_lib.scala 197:25]
wire _T_100 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_101 = _T_100 & _T_59; // @[el2_lib.scala 197:43]
wire _T_104 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 197:80]
wire _T_105 = _T_101 | _T_104; // @[el2_lib.scala 197:25]
wire _T_107 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_108 = _T_107 & _T_59; // @[el2_lib.scala 197:43]
wire _T_111 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 197:80]
wire _T_112 = _T_108 | _T_111; // @[el2_lib.scala 197:25]
wire _T_114 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_115 = _T_114 & _T_59; // @[el2_lib.scala 197:43]
wire _T_118 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 197:80]
wire _T_119 = _T_115 | _T_118; // @[el2_lib.scala 197:25]
wire _T_121 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_122 = _T_121 & _T_59; // @[el2_lib.scala 197:43]
wire _T_125 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 197:80]
wire _T_126 = _T_122 | _T_125; // @[el2_lib.scala 197:25]
wire _T_128 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_129 = _T_128 & _T_59; // @[el2_lib.scala 197:43]
wire _T_132 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 197:80]
wire _T_133 = _T_129 | _T_132; // @[el2_lib.scala 197:25]
wire _T_135 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_136 = _T_135 & _T_59; // @[el2_lib.scala 197:43]
wire _T_139 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 197:80]
wire _T_140 = _T_136 | _T_139; // @[el2_lib.scala 197:25]
wire _T_142 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_143 = _T_142 & _T_59; // @[el2_lib.scala 197:43]
wire _T_146 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 197:80]
wire _T_147 = _T_143 | _T_146; // @[el2_lib.scala 197:25]
wire _T_149 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_150 = _T_149 & _T_59; // @[el2_lib.scala 197:43]
wire _T_153 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 197:80]
wire _T_154 = _T_150 | _T_153; // @[el2_lib.scala 197:25]
wire _T_156 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_157 = _T_156 & _T_59; // @[el2_lib.scala 197:43]
wire _T_160 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 197:80]
wire _T_161 = _T_157 | _T_160; // @[el2_lib.scala 197:25]
wire _T_163 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_164 = _T_163 & _T_59; // @[el2_lib.scala 197:43]
wire _T_167 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 197:80]
wire _T_168 = _T_164 | _T_167; // @[el2_lib.scala 197:25]
wire _T_170 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_171 = _T_170 & _T_59; // @[el2_lib.scala 197:43]
wire _T_174 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 197:80]
wire _T_175 = _T_171 | _T_174; // @[el2_lib.scala 197:25]
wire _T_177 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_178 = _T_177 & _T_59; // @[el2_lib.scala 197:43]
wire _T_181 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 197:80]
wire _T_182 = _T_178 | _T_181; // @[el2_lib.scala 197:25]
wire _T_184 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_185 = _T_184 & _T_59; // @[el2_lib.scala 197:43]
wire _T_188 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 197:80]
wire _T_189 = _T_185 | _T_188; // @[el2_lib.scala 197:25]
wire _T_191 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_192 = _T_191 & _T_59; // @[el2_lib.scala 197:43]
wire _T_195 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 197:80]
wire _T_196 = _T_192 | _T_195; // @[el2_lib.scala 197:25]
wire _T_198 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_199 = _T_198 & _T_59; // @[el2_lib.scala 197:43]
wire _T_202 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 197:80]
wire _T_203 = _T_199 | _T_202; // @[el2_lib.scala 197:25]
wire _T_205 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_206 = _T_205 & _T_59; // @[el2_lib.scala 197:43]
wire _T_209 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 197:80]
wire _T_210 = _T_206 | _T_209; // @[el2_lib.scala 197:25]
wire _T_212 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_213 = _T_212 & _T_59; // @[el2_lib.scala 197:43]
wire _T_216 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 197:80]
wire _T_217 = _T_213 | _T_216; // @[el2_lib.scala 197:25]
wire _T_219 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_220 = _T_219 & _T_59; // @[el2_lib.scala 197:43]
wire _T_223 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 197:80]
wire _T_224 = _T_220 | _T_223; // @[el2_lib.scala 197:25]
wire _T_226 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_227 = _T_226 & _T_59; // @[el2_lib.scala 197:43]
wire _T_230 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 197:80]
wire _T_231 = _T_227 | _T_230; // @[el2_lib.scala 197:25]
wire _T_233 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_234 = _T_233 & _T_59; // @[el2_lib.scala 197:43]
wire _T_237 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 197:80]
wire _T_238 = _T_234 | _T_237; // @[el2_lib.scala 197:25]
wire _T_240 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_241 = _T_240 & _T_59; // @[el2_lib.scala 197:43]
wire _T_244 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 197:80]
wire _T_245 = _T_241 | _T_244; // @[el2_lib.scala 197:25]
wire _T_247 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_248 = _T_247 & _T_59; // @[el2_lib.scala 197:43]
wire _T_251 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 197:80]
wire _T_252 = _T_248 | _T_251; // @[el2_lib.scala 197:25]
wire _T_254 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_255 = _T_254 & _T_59; // @[el2_lib.scala 197:43]
wire _T_258 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 197:80]
wire _T_259 = _T_255 | _T_258; // @[el2_lib.scala 197:25]
wire _T_261 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_262 = _T_261 & _T_59; // @[el2_lib.scala 197:43]
wire _T_265 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 197:80]
wire _T_266 = _T_262 | _T_265; // @[el2_lib.scala 197:25]
wire _T_268 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_269 = _T_268 & _T_59; // @[el2_lib.scala 197:43]
wire _T_272 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 197:80]
wire _T_273 = _T_269 | _T_272; // @[el2_lib.scala 197:25]
wire _T_275 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_276 = _T_275 & _T_59; // @[el2_lib.scala 197:43]
wire _T_279 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 197:80]
wire _T_280 = _T_276 | _T_279; // @[el2_lib.scala 197:25]
wire [7:0] _T_287 = {_T_112,_T_105,_T_98,_T_91,_T_84,_T_77,_T_70,_T_63}; // @[el2_lib.scala 198:14]
wire [15:0] _T_295 = {_T_168,_T_161,_T_154,_T_147,_T_140,_T_133,_T_126,_T_119,_T_287}; // @[el2_lib.scala 198:14]
wire [7:0] _T_302 = {_T_224,_T_217,_T_210,_T_203,_T_196,_T_189,_T_182,_T_175}; // @[el2_lib.scala 198:14]
wire [31:0] _T_311 = {_T_280,_T_273,_T_266,_T_259,_T_252,_T_245,_T_238,_T_231,_T_302,_T_295}; // @[el2_lib.scala 198:14]
wire [31:0] _GEN_4 = {{31'd0}, _T_54}; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _T_312 = _GEN_4 & _T_311; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _GEN_5 = {{31'd0}, _T_51}; // @[el2_lsu_trigger.scala 21:141]
wire [31:0] _T_313 = _GEN_5 | _T_312; // @[el2_lsu_trigger.scala 21:141]
wire _T_316 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 21:120]
wire _T_317 = _T_49 & _T_316; // @[el2_lsu_trigger.scala 21:89]
wire _T_318 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 22:33]
wire _T_320 = _T_318 & _T_20; // @[el2_lsu_trigger.scala 22:53]
wire _T_323 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 194:45]
wire _T_324 = ~_T_323; // @[el2_lib.scala 194:39]
wire _T_325 = io_trigger_pkt_any_1_match_ & _T_324; // @[el2_lib.scala 194:37]
wire _T_328 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 195:52]
wire _T_329 = _T_325 | _T_328; // @[el2_lib.scala 195:41]
wire _T_331 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_332 = _T_331 & _T_325; // @[el2_lib.scala 197:43]
wire _T_335 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 197:80]
wire _T_336 = _T_332 | _T_335; // @[el2_lib.scala 197:25]
wire _T_338 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_339 = _T_338 & _T_325; // @[el2_lib.scala 197:43]
wire _T_342 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 197:80]
wire _T_343 = _T_339 | _T_342; // @[el2_lib.scala 197:25]
wire _T_345 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_346 = _T_345 & _T_325; // @[el2_lib.scala 197:43]
wire _T_349 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 197:80]
wire _T_350 = _T_346 | _T_349; // @[el2_lib.scala 197:25]
wire _T_352 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_353 = _T_352 & _T_325; // @[el2_lib.scala 197:43]
wire _T_356 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 197:80]
wire _T_357 = _T_353 | _T_356; // @[el2_lib.scala 197:25]
wire _T_359 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_360 = _T_359 & _T_325; // @[el2_lib.scala 197:43]
wire _T_363 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 197:80]
wire _T_364 = _T_360 | _T_363; // @[el2_lib.scala 197:25]
wire _T_366 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_367 = _T_366 & _T_325; // @[el2_lib.scala 197:43]
wire _T_370 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 197:80]
wire _T_371 = _T_367 | _T_370; // @[el2_lib.scala 197:25]
wire _T_373 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_374 = _T_373 & _T_325; // @[el2_lib.scala 197:43]
wire _T_377 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 197:80]
wire _T_378 = _T_374 | _T_377; // @[el2_lib.scala 197:25]
wire _T_380 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_381 = _T_380 & _T_325; // @[el2_lib.scala 197:43]
wire _T_384 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 197:80]
wire _T_385 = _T_381 | _T_384; // @[el2_lib.scala 197:25]
wire _T_387 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_388 = _T_387 & _T_325; // @[el2_lib.scala 197:43]
wire _T_391 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 197:80]
wire _T_392 = _T_388 | _T_391; // @[el2_lib.scala 197:25]
wire _T_394 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_395 = _T_394 & _T_325; // @[el2_lib.scala 197:43]
wire _T_398 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 197:80]
wire _T_399 = _T_395 | _T_398; // @[el2_lib.scala 197:25]
wire _T_401 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_402 = _T_401 & _T_325; // @[el2_lib.scala 197:43]
wire _T_405 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 197:80]
wire _T_406 = _T_402 | _T_405; // @[el2_lib.scala 197:25]
wire _T_408 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_409 = _T_408 & _T_325; // @[el2_lib.scala 197:43]
wire _T_412 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 197:80]
wire _T_413 = _T_409 | _T_412; // @[el2_lib.scala 197:25]
wire _T_415 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_416 = _T_415 & _T_325; // @[el2_lib.scala 197:43]
wire _T_419 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 197:80]
wire _T_420 = _T_416 | _T_419; // @[el2_lib.scala 197:25]
wire _T_422 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_423 = _T_422 & _T_325; // @[el2_lib.scala 197:43]
wire _T_426 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 197:80]
wire _T_427 = _T_423 | _T_426; // @[el2_lib.scala 197:25]
wire _T_429 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_430 = _T_429 & _T_325; // @[el2_lib.scala 197:43]
wire _T_433 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 197:80]
wire _T_434 = _T_430 | _T_433; // @[el2_lib.scala 197:25]
wire _T_436 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_437 = _T_436 & _T_325; // @[el2_lib.scala 197:43]
wire _T_440 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 197:80]
wire _T_441 = _T_437 | _T_440; // @[el2_lib.scala 197:25]
wire _T_443 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_444 = _T_443 & _T_325; // @[el2_lib.scala 197:43]
wire _T_447 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 197:80]
wire _T_448 = _T_444 | _T_447; // @[el2_lib.scala 197:25]
wire _T_450 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_451 = _T_450 & _T_325; // @[el2_lib.scala 197:43]
wire _T_454 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 197:80]
wire _T_455 = _T_451 | _T_454; // @[el2_lib.scala 197:25]
wire _T_457 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_458 = _T_457 & _T_325; // @[el2_lib.scala 197:43]
wire _T_461 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 197:80]
wire _T_462 = _T_458 | _T_461; // @[el2_lib.scala 197:25]
wire _T_464 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_465 = _T_464 & _T_325; // @[el2_lib.scala 197:43]
wire _T_468 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 197:80]
wire _T_469 = _T_465 | _T_468; // @[el2_lib.scala 197:25]
wire _T_471 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_472 = _T_471 & _T_325; // @[el2_lib.scala 197:43]
wire _T_475 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 197:80]
wire _T_476 = _T_472 | _T_475; // @[el2_lib.scala 197:25]
wire _T_478 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_479 = _T_478 & _T_325; // @[el2_lib.scala 197:43]
wire _T_482 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 197:80]
wire _T_483 = _T_479 | _T_482; // @[el2_lib.scala 197:25]
wire _T_485 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_486 = _T_485 & _T_325; // @[el2_lib.scala 197:43]
wire _T_489 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 197:80]
wire _T_490 = _T_486 | _T_489; // @[el2_lib.scala 197:25]
wire _T_492 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_493 = _T_492 & _T_325; // @[el2_lib.scala 197:43]
wire _T_496 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 197:80]
wire _T_497 = _T_493 | _T_496; // @[el2_lib.scala 197:25]
wire _T_499 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_500 = _T_499 & _T_325; // @[el2_lib.scala 197:43]
wire _T_503 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 197:80]
wire _T_504 = _T_500 | _T_503; // @[el2_lib.scala 197:25]
wire _T_506 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_507 = _T_506 & _T_325; // @[el2_lib.scala 197:43]
wire _T_510 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 197:80]
wire _T_511 = _T_507 | _T_510; // @[el2_lib.scala 197:25]
wire _T_513 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_514 = _T_513 & _T_325; // @[el2_lib.scala 197:43]
wire _T_517 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 197:80]
wire _T_518 = _T_514 | _T_517; // @[el2_lib.scala 197:25]
wire _T_520 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_521 = _T_520 & _T_325; // @[el2_lib.scala 197:43]
wire _T_524 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 197:80]
wire _T_525 = _T_521 | _T_524; // @[el2_lib.scala 197:25]
wire _T_527 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_528 = _T_527 & _T_325; // @[el2_lib.scala 197:43]
wire _T_531 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 197:80]
wire _T_532 = _T_528 | _T_531; // @[el2_lib.scala 197:25]
wire _T_534 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_535 = _T_534 & _T_325; // @[el2_lib.scala 197:43]
wire _T_538 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 197:80]
wire _T_539 = _T_535 | _T_538; // @[el2_lib.scala 197:25]
wire _T_541 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_542 = _T_541 & _T_325; // @[el2_lib.scala 197:43]
wire _T_545 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 197:80]
wire _T_546 = _T_542 | _T_545; // @[el2_lib.scala 197:25]
wire [7:0] _T_553 = {_T_378,_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329}; // @[el2_lib.scala 198:14]
wire [15:0] _T_561 = {_T_434,_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_553}; // @[el2_lib.scala 198:14]
wire [7:0] _T_568 = {_T_490,_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441}; // @[el2_lib.scala 198:14]
wire [31:0] _T_577 = {_T_546,_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_568,_T_561}; // @[el2_lib.scala 198:14]
wire [31:0] _GEN_6 = {{31'd0}, _T_320}; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _T_578 = _GEN_6 & _T_577; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _GEN_7 = {{31'd0}, _T_317}; // @[el2_lsu_trigger.scala 21:141]
wire [31:0] _T_579 = _GEN_7 | _T_578; // @[el2_lsu_trigger.scala 21:141]
wire _T_582 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 21:120]
wire _T_583 = _T_49 & _T_582; // @[el2_lsu_trigger.scala 21:89]
wire _T_584 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 22:33]
wire _T_586 = _T_584 & _T_29; // @[el2_lsu_trigger.scala 22:53]
wire _T_589 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 194:45]
wire _T_590 = ~_T_589; // @[el2_lib.scala 194:39]
wire _T_591 = io_trigger_pkt_any_2_match_ & _T_590; // @[el2_lib.scala 194:37]
wire _T_594 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 195:52]
wire _T_595 = _T_591 | _T_594; // @[el2_lib.scala 195:41]
wire _T_597 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_598 = _T_597 & _T_591; // @[el2_lib.scala 197:43]
wire _T_601 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 197:80]
wire _T_602 = _T_598 | _T_601; // @[el2_lib.scala 197:25]
wire _T_604 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_605 = _T_604 & _T_591; // @[el2_lib.scala 197:43]
wire _T_608 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 197:80]
wire _T_609 = _T_605 | _T_608; // @[el2_lib.scala 197:25]
wire _T_611 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_612 = _T_611 & _T_591; // @[el2_lib.scala 197:43]
wire _T_615 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 197:80]
wire _T_616 = _T_612 | _T_615; // @[el2_lib.scala 197:25]
wire _T_618 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_619 = _T_618 & _T_591; // @[el2_lib.scala 197:43]
wire _T_622 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 197:80]
wire _T_623 = _T_619 | _T_622; // @[el2_lib.scala 197:25]
wire _T_625 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_626 = _T_625 & _T_591; // @[el2_lib.scala 197:43]
wire _T_629 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 197:80]
wire _T_630 = _T_626 | _T_629; // @[el2_lib.scala 197:25]
wire _T_632 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_633 = _T_632 & _T_591; // @[el2_lib.scala 197:43]
wire _T_636 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 197:80]
wire _T_637 = _T_633 | _T_636; // @[el2_lib.scala 197:25]
wire _T_639 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_640 = _T_639 & _T_591; // @[el2_lib.scala 197:43]
wire _T_643 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 197:80]
wire _T_644 = _T_640 | _T_643; // @[el2_lib.scala 197:25]
wire _T_646 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_647 = _T_646 & _T_591; // @[el2_lib.scala 197:43]
wire _T_650 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 197:80]
wire _T_651 = _T_647 | _T_650; // @[el2_lib.scala 197:25]
wire _T_653 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_654 = _T_653 & _T_591; // @[el2_lib.scala 197:43]
wire _T_657 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 197:80]
wire _T_658 = _T_654 | _T_657; // @[el2_lib.scala 197:25]
wire _T_660 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_661 = _T_660 & _T_591; // @[el2_lib.scala 197:43]
wire _T_664 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 197:80]
wire _T_665 = _T_661 | _T_664; // @[el2_lib.scala 197:25]
wire _T_667 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_668 = _T_667 & _T_591; // @[el2_lib.scala 197:43]
wire _T_671 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 197:80]
wire _T_672 = _T_668 | _T_671; // @[el2_lib.scala 197:25]
wire _T_674 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_675 = _T_674 & _T_591; // @[el2_lib.scala 197:43]
wire _T_678 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 197:80]
wire _T_679 = _T_675 | _T_678; // @[el2_lib.scala 197:25]
wire _T_681 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_682 = _T_681 & _T_591; // @[el2_lib.scala 197:43]
wire _T_685 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 197:80]
wire _T_686 = _T_682 | _T_685; // @[el2_lib.scala 197:25]
wire _T_688 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_689 = _T_688 & _T_591; // @[el2_lib.scala 197:43]
wire _T_692 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 197:80]
wire _T_693 = _T_689 | _T_692; // @[el2_lib.scala 197:25]
wire _T_695 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_696 = _T_695 & _T_591; // @[el2_lib.scala 197:43]
wire _T_699 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 197:80]
wire _T_700 = _T_696 | _T_699; // @[el2_lib.scala 197:25]
wire _T_702 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_703 = _T_702 & _T_591; // @[el2_lib.scala 197:43]
wire _T_706 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 197:80]
wire _T_707 = _T_703 | _T_706; // @[el2_lib.scala 197:25]
wire _T_709 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_710 = _T_709 & _T_591; // @[el2_lib.scala 197:43]
wire _T_713 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 197:80]
wire _T_714 = _T_710 | _T_713; // @[el2_lib.scala 197:25]
wire _T_716 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_717 = _T_716 & _T_591; // @[el2_lib.scala 197:43]
wire _T_720 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 197:80]
wire _T_721 = _T_717 | _T_720; // @[el2_lib.scala 197:25]
wire _T_723 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_724 = _T_723 & _T_591; // @[el2_lib.scala 197:43]
wire _T_727 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 197:80]
wire _T_728 = _T_724 | _T_727; // @[el2_lib.scala 197:25]
wire _T_730 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_731 = _T_730 & _T_591; // @[el2_lib.scala 197:43]
wire _T_734 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 197:80]
wire _T_735 = _T_731 | _T_734; // @[el2_lib.scala 197:25]
wire _T_737 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_738 = _T_737 & _T_591; // @[el2_lib.scala 197:43]
wire _T_741 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 197:80]
wire _T_742 = _T_738 | _T_741; // @[el2_lib.scala 197:25]
wire _T_744 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_745 = _T_744 & _T_591; // @[el2_lib.scala 197:43]
wire _T_748 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 197:80]
wire _T_749 = _T_745 | _T_748; // @[el2_lib.scala 197:25]
wire _T_751 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_752 = _T_751 & _T_591; // @[el2_lib.scala 197:43]
wire _T_755 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 197:80]
wire _T_756 = _T_752 | _T_755; // @[el2_lib.scala 197:25]
wire _T_758 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_759 = _T_758 & _T_591; // @[el2_lib.scala 197:43]
wire _T_762 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 197:80]
wire _T_763 = _T_759 | _T_762; // @[el2_lib.scala 197:25]
wire _T_765 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_766 = _T_765 & _T_591; // @[el2_lib.scala 197:43]
wire _T_769 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 197:80]
wire _T_770 = _T_766 | _T_769; // @[el2_lib.scala 197:25]
wire _T_772 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_773 = _T_772 & _T_591; // @[el2_lib.scala 197:43]
wire _T_776 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 197:80]
wire _T_777 = _T_773 | _T_776; // @[el2_lib.scala 197:25]
wire _T_779 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_780 = _T_779 & _T_591; // @[el2_lib.scala 197:43]
wire _T_783 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 197:80]
wire _T_784 = _T_780 | _T_783; // @[el2_lib.scala 197:25]
wire _T_786 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_787 = _T_786 & _T_591; // @[el2_lib.scala 197:43]
wire _T_790 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 197:80]
wire _T_791 = _T_787 | _T_790; // @[el2_lib.scala 197:25]
wire _T_793 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_794 = _T_793 & _T_591; // @[el2_lib.scala 197:43]
wire _T_797 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 197:80]
wire _T_798 = _T_794 | _T_797; // @[el2_lib.scala 197:25]
wire _T_800 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_801 = _T_800 & _T_591; // @[el2_lib.scala 197:43]
wire _T_804 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 197:80]
wire _T_805 = _T_801 | _T_804; // @[el2_lib.scala 197:25]
wire _T_807 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_808 = _T_807 & _T_591; // @[el2_lib.scala 197:43]
wire _T_811 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 197:80]
wire _T_812 = _T_808 | _T_811; // @[el2_lib.scala 197:25]
wire [7:0] _T_819 = {_T_644,_T_637,_T_630,_T_623,_T_616,_T_609,_T_602,_T_595}; // @[el2_lib.scala 198:14]
wire [15:0] _T_827 = {_T_700,_T_693,_T_686,_T_679,_T_672,_T_665,_T_658,_T_651,_T_819}; // @[el2_lib.scala 198:14]
wire [7:0] _T_834 = {_T_756,_T_749,_T_742,_T_735,_T_728,_T_721,_T_714,_T_707}; // @[el2_lib.scala 198:14]
wire [31:0] _T_843 = {_T_812,_T_805,_T_798,_T_791,_T_784,_T_777,_T_770,_T_763,_T_834,_T_827}; // @[el2_lib.scala 198:14]
wire [31:0] _GEN_8 = {{31'd0}, _T_586}; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _T_844 = _GEN_8 & _T_843; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _GEN_9 = {{31'd0}, _T_583}; // @[el2_lsu_trigger.scala 21:141]
wire [31:0] _T_845 = _GEN_9 | _T_844; // @[el2_lsu_trigger.scala 21:141]
wire _T_848 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 21:120]
wire _T_849 = _T_49 & _T_848; // @[el2_lsu_trigger.scala 21:89]
wire _T_850 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 22:33]
wire _T_852 = _T_850 & _T_38; // @[el2_lsu_trigger.scala 22:53]
wire _T_855 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 194:45]
wire _T_856 = ~_T_855; // @[el2_lib.scala 194:39]
wire _T_857 = io_trigger_pkt_any_3_match_ & _T_856; // @[el2_lib.scala 194:37]
wire _T_860 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 195:52]
wire _T_861 = _T_857 | _T_860; // @[el2_lib.scala 195:41]
wire _T_863 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 197:38]
wire _T_864 = _T_863 & _T_857; // @[el2_lib.scala 197:43]
wire _T_867 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 197:80]
wire _T_868 = _T_864 | _T_867; // @[el2_lib.scala 197:25]
wire _T_870 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 197:38]
wire _T_871 = _T_870 & _T_857; // @[el2_lib.scala 197:43]
wire _T_874 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 197:80]
wire _T_875 = _T_871 | _T_874; // @[el2_lib.scala 197:25]
wire _T_877 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 197:38]
wire _T_878 = _T_877 & _T_857; // @[el2_lib.scala 197:43]
wire _T_881 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 197:80]
wire _T_882 = _T_878 | _T_881; // @[el2_lib.scala 197:25]
wire _T_884 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 197:38]
wire _T_885 = _T_884 & _T_857; // @[el2_lib.scala 197:43]
wire _T_888 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 197:80]
wire _T_889 = _T_885 | _T_888; // @[el2_lib.scala 197:25]
wire _T_891 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 197:38]
wire _T_892 = _T_891 & _T_857; // @[el2_lib.scala 197:43]
wire _T_895 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 197:80]
wire _T_896 = _T_892 | _T_895; // @[el2_lib.scala 197:25]
wire _T_898 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 197:38]
wire _T_899 = _T_898 & _T_857; // @[el2_lib.scala 197:43]
wire _T_902 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 197:80]
wire _T_903 = _T_899 | _T_902; // @[el2_lib.scala 197:25]
wire _T_905 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 197:38]
wire _T_906 = _T_905 & _T_857; // @[el2_lib.scala 197:43]
wire _T_909 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 197:80]
wire _T_910 = _T_906 | _T_909; // @[el2_lib.scala 197:25]
wire _T_912 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 197:38]
wire _T_913 = _T_912 & _T_857; // @[el2_lib.scala 197:43]
wire _T_916 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 197:80]
wire _T_917 = _T_913 | _T_916; // @[el2_lib.scala 197:25]
wire _T_919 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 197:38]
wire _T_920 = _T_919 & _T_857; // @[el2_lib.scala 197:43]
wire _T_923 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 197:80]
wire _T_924 = _T_920 | _T_923; // @[el2_lib.scala 197:25]
wire _T_926 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 197:38]
wire _T_927 = _T_926 & _T_857; // @[el2_lib.scala 197:43]
wire _T_930 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 197:80]
wire _T_931 = _T_927 | _T_930; // @[el2_lib.scala 197:25]
wire _T_933 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 197:38]
wire _T_934 = _T_933 & _T_857; // @[el2_lib.scala 197:43]
wire _T_937 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 197:80]
wire _T_938 = _T_934 | _T_937; // @[el2_lib.scala 197:25]
wire _T_940 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 197:38]
wire _T_941 = _T_940 & _T_857; // @[el2_lib.scala 197:43]
wire _T_944 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 197:80]
wire _T_945 = _T_941 | _T_944; // @[el2_lib.scala 197:25]
wire _T_947 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 197:38]
wire _T_948 = _T_947 & _T_857; // @[el2_lib.scala 197:43]
wire _T_951 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 197:80]
wire _T_952 = _T_948 | _T_951; // @[el2_lib.scala 197:25]
wire _T_954 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 197:38]
wire _T_955 = _T_954 & _T_857; // @[el2_lib.scala 197:43]
wire _T_958 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 197:80]
wire _T_959 = _T_955 | _T_958; // @[el2_lib.scala 197:25]
wire _T_961 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 197:38]
wire _T_962 = _T_961 & _T_857; // @[el2_lib.scala 197:43]
wire _T_965 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 197:80]
wire _T_966 = _T_962 | _T_965; // @[el2_lib.scala 197:25]
wire _T_968 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 197:38]
wire _T_969 = _T_968 & _T_857; // @[el2_lib.scala 197:43]
wire _T_972 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 197:80]
wire _T_973 = _T_969 | _T_972; // @[el2_lib.scala 197:25]
wire _T_975 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 197:38]
wire _T_976 = _T_975 & _T_857; // @[el2_lib.scala 197:43]
wire _T_979 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 197:80]
wire _T_980 = _T_976 | _T_979; // @[el2_lib.scala 197:25]
wire _T_982 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 197:38]
wire _T_983 = _T_982 & _T_857; // @[el2_lib.scala 197:43]
wire _T_986 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 197:80]
wire _T_987 = _T_983 | _T_986; // @[el2_lib.scala 197:25]
wire _T_989 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 197:38]
wire _T_990 = _T_989 & _T_857; // @[el2_lib.scala 197:43]
wire _T_993 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 197:80]
wire _T_994 = _T_990 | _T_993; // @[el2_lib.scala 197:25]
wire _T_996 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 197:38]
wire _T_997 = _T_996 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1000 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 197:80]
wire _T_1001 = _T_997 | _T_1000; // @[el2_lib.scala 197:25]
wire _T_1003 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 197:38]
wire _T_1004 = _T_1003 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1007 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 197:80]
wire _T_1008 = _T_1004 | _T_1007; // @[el2_lib.scala 197:25]
wire _T_1010 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 197:38]
wire _T_1011 = _T_1010 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1014 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 197:80]
wire _T_1015 = _T_1011 | _T_1014; // @[el2_lib.scala 197:25]
wire _T_1017 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 197:38]
wire _T_1018 = _T_1017 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1021 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 197:80]
wire _T_1022 = _T_1018 | _T_1021; // @[el2_lib.scala 197:25]
wire _T_1024 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 197:38]
wire _T_1025 = _T_1024 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1028 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 197:80]
wire _T_1029 = _T_1025 | _T_1028; // @[el2_lib.scala 197:25]
wire _T_1031 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 197:38]
wire _T_1032 = _T_1031 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1035 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 197:80]
wire _T_1036 = _T_1032 | _T_1035; // @[el2_lib.scala 197:25]
wire _T_1038 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 197:38]
wire _T_1039 = _T_1038 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1042 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 197:80]
wire _T_1043 = _T_1039 | _T_1042; // @[el2_lib.scala 197:25]
wire _T_1045 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 197:38]
wire _T_1046 = _T_1045 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1049 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 197:80]
wire _T_1050 = _T_1046 | _T_1049; // @[el2_lib.scala 197:25]
wire _T_1052 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 197:38]
wire _T_1053 = _T_1052 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1056 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 197:80]
wire _T_1057 = _T_1053 | _T_1056; // @[el2_lib.scala 197:25]
wire _T_1059 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 197:38]
wire _T_1060 = _T_1059 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1063 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 197:80]
wire _T_1064 = _T_1060 | _T_1063; // @[el2_lib.scala 197:25]
wire _T_1066 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 197:38]
wire _T_1067 = _T_1066 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1070 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 197:80]
wire _T_1071 = _T_1067 | _T_1070; // @[el2_lib.scala 197:25]
wire _T_1073 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 197:38]
wire _T_1074 = _T_1073 & _T_857; // @[el2_lib.scala 197:43]
wire _T_1077 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 197:80]
wire _T_1078 = _T_1074 | _T_1077; // @[el2_lib.scala 197:25]
wire [7:0] _T_1085 = {_T_910,_T_903,_T_896,_T_889,_T_882,_T_875,_T_868,_T_861}; // @[el2_lib.scala 198:14]
wire [15:0] _T_1093 = {_T_966,_T_959,_T_952,_T_945,_T_938,_T_931,_T_924,_T_917,_T_1085}; // @[el2_lib.scala 198:14]
wire [7:0] _T_1100 = {_T_1022,_T_1015,_T_1008,_T_1001,_T_994,_T_987,_T_980,_T_973}; // @[el2_lib.scala 198:14]
wire [31:0] _T_1109 = {_T_1078,_T_1071,_T_1064,_T_1057,_T_1050,_T_1043,_T_1036,_T_1029,_T_1100,_T_1093}; // @[el2_lib.scala 198:14]
wire [31:0] _GEN_10 = {{31'd0}, _T_852}; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _T_1110 = _GEN_10 & _T_1109; // @[el2_lsu_trigger.scala 22:86]
wire [31:0] _GEN_11 = {{31'd0}, _T_849}; // @[el2_lsu_trigger.scala 21:141]
wire [31:0] _T_1111 = _GEN_11 | _T_1110; // @[el2_lsu_trigger.scala 21:141]
wire [127:0] _T_1114 = {_T_1111,_T_845,_T_579,_T_313}; // @[Cat.scala 29:58]
assign io_lsu_trigger_match_m = _T_1114[3:0]; // @[el2_lsu_trigger.scala 16:25 el2_lsu_trigger.scala 21:26]
endmodule

173
src/main/scala/dec/el2_dec_dec_ctl.scala
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@ -1,173 +0,0 @@
package dec
import chisel3._
import chisel3.util._
class el2_dec_pkt_t extends Bundle{
val alu = Bool()
val rs1 = Bool()
val rs2 = Bool()
val imm12 = Bool()
val rd = Bool()
val shimm5 = Bool()
val imm20 = Bool()
val pc = Bool()
val load = Bool()
val store = Bool()
val lsu = Bool()
val add = Bool()
val sub = Bool()
val land = Bool()
val lor = Bool()
val lxor = Bool()
val sll = Bool()
val sra = Bool()
val srl = Bool()
val slt = Bool()
val unsign = Bool()
val condbr = Bool()
val beq = Bool()
val bne = Bool()
val bge = Bool()
val blt = Bool()
val jal = Bool()
val by = Bool()
val half = Bool()
val word = Bool()
val csr_read = Bool()
val csr_clr = Bool()
val csr_set = Bool()
val csr_write = Bool()
val csr_imm = Bool()
val presync = Bool()
val postsync = Bool()
val ebreak = Bool()
val ecall = Bool()
val mret = Bool()
val mul = Bool()
val rs1_sign = Bool()
val rs2_sign = Bool()
val low = Bool()
val div = Bool()
val rem = Bool()
val fence = Bool()
val fence_i = Bool()
val pm_alu = Bool()
val legal = Bool()
}
class el2_dec_dec_ctl extends Module{
val io = IO (new Bundle{
val ins = Input(UInt(32.W))
val out = Output(new el2_dec_pkt_t)
})
def pattern(y : List[Int]) : Array[UInt] = {
val pat : Array[UInt] = new Array[UInt](y.size)
for (i <- 0 until y.size){
pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs)
}
pat
}
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) |
pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) |
pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) |
pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) |
pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) |
pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_)
io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_)
io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) |
pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_)
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_)
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
io.out.load := pattern(List(-5,-4,-2)).reduce(_&_)
io.out.store := pattern(List(-6,5,-4)).reduce(_&_)
io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_)
io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) |
pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_)
io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) |
pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_)
io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_)
io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) |
pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) |
pattern(List(14,13,-12,-5,-2)).reduce(_&_)
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_)
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_)
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_)
io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_)
io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) |
pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) |
pattern(List(25,14,12,-6,5,-2)).reduce(_&_)
io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_)
io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_)
io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_)
io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_)
io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_)
io.out.jal := pattern(List(6,2)).reduce(_&_)
io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_)
io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_)
io.out.word := pattern(List(13,-6,-4)).reduce(_&_)
io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) |
pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) |
pattern(List(11,6,4)).reduce(_&_)
io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) |
pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
pattern(List(19,-12,6,4)).reduce(_&_)
io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_)
io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) |
pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) |
pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_)
io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) |
pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) |
pattern(List(19,-12,6,4)).reduce(_&_)
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_)
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_)
io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_)
io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_)
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) |
pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_)
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_)
io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_)
io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_)
io.out.fence := pattern(List(-5,3)).reduce(_&_)
io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_)
io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) |
pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_)
io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) |
pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) |
pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) |
pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) |
pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) |
pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) |
pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_)
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) |
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) |
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) |
pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) |
pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) |
pattern(List(-6,4,-3,-2,1,0)).reduce(_&_)
}
//object dec extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl()))
//}

5
src/main/scala/ifu/el2_ifu.scala
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@ -1,5 +0,0 @@
package ifu
class el2_ifu {
}

19
src/main/scala/ifu/el2_ifu_bp_ctl.scala
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@ -1,19 +0,0 @@
package ifu
import lib._
import chisel3._
import chisel3.util._
class el2_ifu_bp_ctl extends Module with el2_lib {
val io = IO (new Bundle {
val in = Input(UInt(32.W))
val in2 = Input(UInt(32.W))
val out = Output(UInt())
})
io.out := el2_btb_ghr_hash(io.in,io.in2)
}
//object ifu_ic extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
//}

226
src/main/scala/ifu/el2_ifu_ic_mem.scala
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@ -1,226 +0,0 @@
package ifu
import lib._
import chisel3._
import chisel3.util._
class el2_ifu_ic_mem extends Module with param{
val io = IO(new Bundle{
val clk = Input(Bool())
val rst_l = Input(Bool())
val clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ic_rw_addr = Input(UInt(31.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(Bool())
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
val ic_debug_rd_en = Input(Bool())
val ic_debug_wr_en = Input(Bool())
val ic_debug_tag_array = Input(Bool())
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_premux_data = Input(UInt(64.W))
val ic_sel_premux_data = Input(Bool())
val ic_wr_data = Vec(ICACHE_BANKS_WAY, Input(UInt(71.W)))
val ic_rd_data = Output(UInt(64.W))
val ic_debug_rd_data = Output(UInt(71.W))
val ictag_debug_rd_data = Output(UInt(26.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Output(Bool())
val scan_mode = Input(Bool())
})
io.ic_tag_perr := 0.U
io.ic_rd_hit := 0.U
io.ic_parerr := 0.U
io.ic_eccerr := 0.U
io.ictag_debug_rd_data := 0.U
io.ic_debug_rd_data := 0.U
io.ic_rd_data := 0.U
//val icache_tag = Module(new kncpa)
}
/////////// ICACHE TAG
class EL2_IC_TAG extends Module with el2_lib with param {
val io = IO(new Bundle{
val clk = Input(Bool())
val rst_l = Input(Bool())
val clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool())
val ic_rw_addr = Input(UInt(32.W)) // TODO : In SV we have 31:3 what should we do here
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(Bool())
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+1).W))
val ic_debug_rd_en = Input(Bool())
val ic_debug_wr_en = Input(Bool())
val ic_debug_tag_array = Input(Bool())
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ictag_debug_rd_data = Output(UInt(26.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_tag_perr = Output(Bool())
val scan_mode = Input(Bool())
val test = Output(UInt(26.W))
val test_ecc_data_out = Output(Vec(ICACHE_NUM_WAYS,UInt(32.W)))
val test_ecc_out = Output(Vec(ICACHE_NUM_WAYS,UInt(7.W)))
val test_ecc_sb_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
val test_ecc_db_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
})
val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
repl(ICACHE_NUM_WAYS-1, 1.U))
val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en |
ic_debug_rd_way_en
val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U)
val ic_rw_addr_ff = RegNext(io.ic_rw_addr, init=0.U)
val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
val ic_tag_ecc = Wire(UInt(7.W))
val ic_tag_wr_data = Wire(UInt(26.W))
val ic_tag_parity = Wire(UInt(1.W))
ic_tag_ecc := 0.U
ic_tag_wr_data := 0.U
ic_tag_parity := 0.U
when((ICACHE_TAG_LO == 11).B){
when(ICACHE_ECC.B){
ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
}
.otherwise{
ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
Cat(ic_tag_ecc(4,0), io.ic_rw_addr(31,ICACHE_TAG_LO)))
}
}
.otherwise{
when(ICACHE_ECC.B){
ic_tag_ecc := rvecc_encode(Cat(repl(ICACHE_TAG_LO,0.U) , io.ic_rw_addr(31,ICACHE_TAG_LO)))
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
}
.otherwise{
ic_tag_parity := rveven_paritygen(io.ic_rw_addr(31,ICACHE_TAG_LO))
ic_tag_wr_data := Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)) ,
Cat(ic_tag_ecc(4,0), repl(PAD_BITS,0.U), io.ic_rw_addr(31,ICACHE_TAG_LO)))
}
}
val ic_rw_addr_q = Mux(io.ic_debug_rd_en | io.ic_debug_wr_en,
io.ic_debug_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO),
io.ic_rw_addr(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO))
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
val ic_way_tag = if(ICACHE_ECC) SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W)))
else SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
//val ic_tag_data_raw = if(ICACHE_ECC) Vec(ICACHE_NUM_WAYS, UInt(26.W)) else Vec(ICACHE_NUM_WAYS, UInt(22.W))
val write_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wr_data)
val mem_mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i => ic_tag_wren_q(i) & ic_tag_clken(i))
ic_way_tag.write(ic_rw_addr_q, write_data, mem_mask)
val ic_tag_data_raw = ic_way_tag.read(ic_rw_addr_q, 1.B)
//val w_tout = Wire(UInt(32.W))
val w_tout = if(ICACHE_ECC)ic_tag_data_raw.map(x=>Cat(ic_tag_data_raw(x)(25,21),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
else ic_tag_data_raw.map(x=>Cat(0.U(4.W),ic_tag_data_raw(x)(32),ic_tag_data_raw(x)(31-ICACHE_TAG_LO,0),0.U(13.W)))
val ecc_decode = new Array[rvecc_decode](ICACHE_NUM_WAYS)
val parcheck = new Array[UInt](ICACHE_NUM_WAYS)
val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W)))
val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W)))
val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
val ic_tag_way_perr = VecInit.tabulate(ICACHE_NUM_WAYS)(i => rveven_paritycheck(w_tout(i)(31,ICACHE_TAG_LO),w_tout(i)(31)))
for(i <- 0 until ICACHE_NUM_WAYS) {
ecc_decode(i) = Module(new rvecc_decode())
ecc_decode(i).io.en := ~io.dec_tlu_core_ecc_disable & ic_rd_en_ff
ecc_decode(i).io.sed_ded := 1.U
ecc_decode(i).io.din := Cat(0.U(11.W),ic_tag_data_raw(i)(20,0))
ecc_decode(i).io.ecc_in := Cat(0.U(2.W),ic_tag_data_raw(i)(25,21))
ic_tag_corrected_data_unc := io.test_ecc_data_out
ic_tag_corrected_ecc_unc := io.test_ecc_out
ic_tag_single_ecc_error := io.test_ecc_sb_out
ic_tag_double_ecc_error := io.test_ecc_db_out
io.test_ecc_data_out(i) := ecc_decode(i).io.dout
io.test_ecc_out(i) := ecc_decode(i).io.ecc_out
io.test_ecc_sb_out(i) := ecc_decode(i).io.single_ecc_error
io.test_ecc_db_out(i) := ecc_decode(i).io.double_ecc_error
ic_tag_way_perr(i) := ic_tag_single_ecc_error(i) | ic_tag_double_ecc_error(i)
}
val temp = if(ICACHE_ECC)
VecInit.tabulate(ICACHE_NUM_WAYS)(i=>repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)).reduce(_|_)
else
VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(0.U(4.W),repl(22,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i))).reduce(_|_)
for(i <- 0 until ICACHE_NUM_WAYS){
repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)
}
io.ictag_debug_rd_data := temp
io.test := w_tout.reduce(_&_)
io.ic_tag_perr := (ic_tag_way_perr.reduce(Cat(_,_)) & io.ic_tag_valid).orR
val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i))
io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reduce(Cat(_,_))
}
class EL2_IC_DATA extends Module with param{
val io = IO (new Bundle{
val rst_l = Input(UInt(1.W))
val clk_override = Input(UInt(1.W))
val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_en = Input(UInt(1.W))
val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W)))
val ic_rd_data = Output(UInt(64.W))
val ic_debug_wr_data = Input(UInt(71.W))
val ic_debug_rd_data = Output(UInt(71.W))
val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+3).W))
val ic_debug_rd_en = Input(UInt(1.W))
val ic_debug_wr_en = Input(UInt(1.W))
val ic_debug_tag_array = Input(UInt(1.W))
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_premux_data = Input(UInt(64.W))
val ic_sel_premux_data = Input(UInt(1.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val scan_mode = Input(UInt(1.W))
val mask = Input(Vec(2,Vec(2,Bool())))
})
// val data_memory = VecInit.tabulate(ICACHE_BANKS_WAY)(i => SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
// SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
val mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>1.U)
val data_mem = (SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))), SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
data_mem(0).write(io.ic_rw_addr,io.ic_wr_data,mask)
// ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask)
io.ic_debug_rd_data := 0.U
io.ic_rd_data := 0.U
io.ic_eccerr := 0.U
io.ic_parerr := 0.U
}
object ifu_ic extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
}

1
src/main/scala/ifu/test.sc
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@ -1 +0,0 @@
val a = 5

159
src/main/scala/lsu/el2_lsu_addrcheck.scala
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@ -1,159 +0,0 @@
package lsu
import include._
import lib._
import snapshot._
import chisel3._
import chisel3.util._
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import chisel3.experimental.ChiselEnum
import chisel3.experimental.{withClock, withReset, withClockAndReset}
import chisel3.experimental.BundleLiterals._
import chisel3.tester._
import chisel3.tester.RawTester.test
import chisel3.util.HasBlackBoxResource
class el2_lsu_addrcheck extends Module with RequireAsyncReset
{val io = IO(new Bundle{
val lsu_c2_m_clk = Input(Clock())
val start_addr_d = Input(UInt(32.W))
val end_addr_d = Input(UInt(32.W))
val lsu_pkt_d = Input(new el2_lsu_pkt_t)
val dec_tlu_mrac_ff = Input(UInt(32.W))
val rs1_region_d = Input(UInt(4.W))
val rs1_d = Input(UInt(32.W))
val is_sideeffects_m = Output(UInt(1.W))
val addr_in_dccm_d = Output(UInt(1.W))
val addr_in_pic_d = Output(UInt(1.W))
val addr_external_d = Output(UInt(1.W))
val access_fault_d = Output(UInt(1.W))
val misaligned_fault_d = Output(UInt(1.W))
val exc_mscause_d = Output(UInt(4.W))
val fir_dccm_access_error_d = Output(UInt(1.W))
val fir_nondccm_access_error_d = Output(UInt(1.W))
val scan_mode = Input(UInt(1.W))})
val start_addr_in_dccm_d = WireInit(0.U(1.W))
val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
val end_addr_in_dccm_d = WireInit(0.U(1.W))
val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
//DCCM check
// Start address check
if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt.DCCM_SADR,pt1.DCCM_SIZE))
start_addr_dccm_rangecheck.io.addr := io.start_addr_d
start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
// End address check
val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt.DCCM_SADR,pt1.DCCM_SIZE))
end_addr_dccm_rangecheck.io.addr := io.end_addr_d
end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
}
else{ //Gen_dccm_disable
start_addr_in_dccm_d := 0.U
start_addr_in_dccm_region_d := 0.U
end_addr_in_dccm_d := 0.U
end_addr_in_dccm_region_d := 0.U
}
val addr_in_iccm = WireInit(0.U(1.W))
if(pt1.ICCM_ENABLE == 1){ //check_iccm
addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
}
else{
addr_in_iccm := 1.U
}
//PIC memory check
//start address check
val start_addr_pic_rangecheck = Module(new rvrangecheck(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
//End address check
val end_addr_pic_rangecheck = Module(new rvrangecheck(pt.PIC_BASE_ADDR,pt1.PIC_SIZE))
end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === pt.DCCM_REGION) | (io.rs1_region_d(3,0) === pt.PIC_REGION) //base region
io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
val csr_idx = Cat(io.start_addr_d(31,28),"b1".U)
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === "b00".U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === "b0".U)) | io.lsu_pkt_d.by
val non_dccm_access_ok = (~(Cat(pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,
pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7)).orR) |
(((pt.DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | //0111
(pt.DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | //1111
(pt.DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | //1011
(pt.DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | //1000
(pt.DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
(pt.DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
(pt.DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
(pt.DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))
&
((pt.DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) |
(pt.DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) |
(pt.DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) |
(pt.DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) |
(pt.DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
(pt.DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
(pt.DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
(pt.DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))))
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) != 0.U(2.W)) | ~io.lsu_pkt_d.word))
val unmapped_access_fault_d = WireInit(1.U(1.W))
val mpu_access_fault_d = WireInit(1.U(1.W))
if(pt1.DCCM_REGION == pt1.PIC_REGION){
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
// 0. Addr in dccm/pic region but not in dccm/pic offset
(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
// 0. Addr in dccm/pic region but not in dccm/pic offset
(start_addr_in_dccm_d & end_addr_in_pic_d) |
// 0. DCCM -> PIC cross when DCCM/PIC in same region
(start_addr_in_pic_d & end_addr_in_dccm_d))
// 0. DCCM -> PIC cross when DCCM/PIC in same region
mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
// 3. Address is not in a populated non-dccm region
}
else{
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
(start_addr_in_pic_region_d & ~start_addr_in_pic_d) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d))
mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
// 3. Address is not in a populated non-dccm region
}
//check width of access_fault_mscause_d
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
}
//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck))
object main extends App{
println("Generate Verilog")
chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck)
}

203
src/main/scala/lsu/el2_lsu_bus_buffer.scala
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@ -1,203 +0,0 @@
package lsu
import chisel3._
import chisel3.util._
import lib._
import include._
import snapshot._
class el2_lsu_bus_buffer extends Module
{
val io = IO (new Bundle {
//val clk = Input(Clock()) //implicit
//val rst_l = Input(1.W) //implicit
val scan_mode = Input(Bool())
val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals
val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing
val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus
val dec_tlu_force_halt = Input(Bool())
// various clocks needed for the bus reads and writes
// val lsu_c1_m_clk = Input(Clock())
// val lsu_c1_r_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock())
val lsu_bus_obuf_c1_clk = Input(Clock())
val lsu_bus_buf_c1_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock())
// val free_clk = Input(Clock())
val lsu_busm_clk = Input(Clock())
val dec_lsu_valid_raw_d = Input(Bool())
// val lsu_pkt_m = new el2_lsu_pkt_t
// val lsu_pkt_r = new el2_lsu_pkt_t
val lsu_addr_m = Input(UInt(32.W))
val end_addr_m = Input(UInt(32.W))
val lsu_addr_r = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W))
val store_data_r = Input(UInt(32.W))
// val dec_tlu_force_halt = Input(Bool())
val no_word_merge_r = Input(Bool())
val no_dword_merge_r = Input(Bool())
val lsu_busreq_m = Input(Bool())
val lsu_busreq_r = Output(Bool())
val ld_full_hit_m = Input(Bool())
val flush_m_up = Input(Bool())
val flush_r = Input(Bool())
val lsu_commit_r = Input(Bool())
val is_sideeffects_r = Input(Bool())
val ldst_dual_d = Input(Bool())
val ldst_dual_m = Input(Bool())
val ldst_dual_r = Input(Bool())
val ldst_byteen_ext_m = Input(UInt(8.W))
val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool())
val lsu_bus_idle_any = Output(Bool())
val ld_byte_hit_buf_lo = Output((UInt(8.W)))
val ld_byte_hit_buf_hi = Output((UInt(8.W)))
val ld_fwddata_buf_lo = Output((UInt(32.W)))
val ld_fwddata_buf_hi = Output((UInt(32.W)))
val lsu_imprecise_error_load_any = Output(Bool())
val lsu_imprecise_error_store_any = Output(Bool())
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
val lsu_nonblock_load_valid_m = Output(Bool())
val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_inv_r = Output(Bool())
val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data_valid = Output(Bool())
val lsu_nonblock_load_data_error = Output(UInt(32.W))
val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_pmu_bus_trxn = Output(Bool())
val lsu_pmu_bus_misaligned = Output(Bool())
val lsu_pmu_bus_error = Output(Bool())
val lsu_pmu_bus_busy = Output(Bool())
val lsu_axi_awvalid = Output(Bool())
val lsu_axi_awready = Input(Bool())
val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(Bool())
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(Bool())
val lsu_axi_wready = Input(Bool())
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(Bool())
val lsu_axi_bvalid = Input(Bool())
val lsu_axi_bready = Output(Bool())
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(Bool())
val lsu_axi_arready = Input(Bool())
val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(Bool())
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(Bool())
val lsu_axi_rready = Output(Bool())
val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Input(UInt(2.W))
val lsu_axi_rlast = Input(Bool())
val lsu_bus_clk_en = Input(Bool())
val lsu_bus_clk_en_q = Input(Bool())
})
val lsu_pkt_m = new el2_lsu_pkt_t()
val lsu_pkt_r = new el2_lsu_pkt_t()
io.lsu_busreq_r := 0.U
io.lsu_bus_buffer_pend_any := 0.U
io.lsu_bus_buffer_full_any := 0.U
io.lsu_bus_buffer_empty_any := 0.U
io.lsu_bus_idle_any := 0.U
io.ld_byte_hit_buf_lo := 0.U
io.ld_byte_hit_buf_hi := 0.U
io.ld_fwddata_buf_lo := 0.U
io.ld_fwddata_buf_hi := 0.U
io.lsu_imprecise_error_load_any := 0.U
io.lsu_imprecise_error_store_any := 0.U
io.lsu_imprecise_error_addr_any := 0.U
io.lsu_nonblock_load_valid_m := 0.U
io.lsu_nonblock_load_tag_m := 0.U
io.lsu_nonblock_load_inv_r := 0.U
io.lsu_nonblock_load_inv_tag_r := 0.U
io.lsu_nonblock_load_data_valid := 0.U
io.lsu_nonblock_load_data_error := 0.U
io.lsu_nonblock_load_data_tag := 0.U
io.lsu_nonblock_load_data := 0.U
io.lsu_pmu_bus_trxn := 0.U
io.lsu_pmu_bus_misaligned := 0.U
io.lsu_pmu_bus_error := 0.U
io.lsu_pmu_bus_busy := 0.U
io.lsu_axi_awvalid := 0.U
io.lsu_axi_awid := 0.U
io.lsu_axi_awaddr := 0.U
io.lsu_axi_awregion := 0.U
io.lsu_axi_awlen := 0.U
io.lsu_axi_awsize := 0.U
io.lsu_axi_awburst := 0.U
io.lsu_axi_awlock := 0.U
io.lsu_axi_awcache := 0.U
io.lsu_axi_awprot := 0.U
io.lsu_axi_awqos := 0.U
io.lsu_axi_wvalid := 0.U
io.lsu_axi_wdata := 0.U
io.lsu_axi_wstrb := 0.U
io.lsu_axi_wlast := 0.U
io.lsu_axi_bready := 0.U
io.lsu_axi_arvalid := 0.U
io.lsu_axi_arid := 0.U
io.lsu_axi_araddr := 0.U
io.lsu_axi_arregion := 0.U
io.lsu_axi_arlen := 0.U
io.lsu_axi_arsize := 0.U
io.lsu_axi_arburst := 0.U
io.lsu_axi_arlock := 0.U
io.lsu_axi_arcache := 0.U
io.lsu_axi_arprot := 0.U
io.lsu_axi_arqos := 0.U
io.lsu_axi_rready := 0.U
}
object busbufferMain extends App {
println(chisel3.Driver.emitVerilog(new el2_lsu_bus_buffer))
}

184
src/main/scala/lsu/el2_lsu_bus_intf.scala
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@ -1,184 +0,0 @@
package lsu
import chisel3._
import chisel3.util._
import lib._
import include._
import snapshot._
class el2_lsu_lsc_ctl extends Module
{
val io = IO (new Bundle {
//val clk = Input(Clock()) //implicit
//val rst_l = Input(1.W) //implicit
val scan_mode = Input(UInt(1.W))
val dec_tlu_external_ldfwd_disable = Input(UInt(1.W)) // disable load to load forwarding for externals
val dec_tlu_wb_coalescing_disable = Input(UInt(1.W)) // disable write buffer coalescing
val dec_tlu_sideeffect_posted_disable = Input(UInt(1.W)) // disable the posted sideeffect load store to the bus
// various clocks needed for the bus reads and writes
val lsu_c1_m_clk = Input(Clock())
val lsu_c1_r_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock())
val lsu_bus_ibuf_c1_clk = Input(Clock())
val lsu_bus_obuf_c1_clk = Input(Clock())
val lsu_bus_buf_c1_clk = Input(Clock())
val lsu_free_c2_clk = Input(Clock())
val free_clk = Input(Clock())
val lsu_busm_clk = Input(Clock())
val dec_lsu_valid_raw_d = Input(UInt(1.W))
val lsu_busreq_m = Input(UInt(1.W))
val lsu_addr_d = Input(UInt(32.W))
val lsu_addr_m = Input(UInt(32.W))
val lsu_addr_r = Input(UInt(32.W))
val end_addr_d = Input(UInt(32.W))
val end_addr_m = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W))
val store_data_m = Input(UInt(32.W))
val dec_tlu_force_halt = Input(UInt(1.W))
val lsu_commit_r = Input(UInt(1.W))
val is_sideeffects_m = Input(UInt(1.W))
val flush_m_up = Input(UInt(1.W))
val flush_r = Input(UInt(1.W))
val lsu_busreq_r = Output(UInt(1.W))
val lsu_bus_buffer_pend_any = Output(UInt(1.W))
val lsu_bus_buffer_full_any = Output(UInt(1.W))
val lsu_bus_buffer_empty_any = Output(UInt(1.W))
val lsu_bus_idle_any = Output(UInt(1.W))
val bus_read_data_m = Output(UInt(32.W))
val lsu_imprecise_error_load_any = Output(UInt(1.W))
val lsu_imprecise_error_store_any = Output(UInt(1.W))
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
val lsu_nonblock_load_valid_m = Output(UInt(1.W))
val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_inv_r = Output(UInt(1.W))
val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data_valid = Output(UInt(1.W))
val lsu_nonblock_load_data_error = Output(UInt(32.W))
val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
val lsu_nonblock_load_data = Output(UInt(32.W))
val lsu_pmu_bus_trxn = Output(UInt(1.W))
val lsu_pmu_bus_misaligned = Output(UInt(1.W))
val lsu_pmu_bus_error = Output(UInt(1.W))
val lsu_pmu_bus_busy = Output(UInt(1.W))
val lsu_axi_awvalid = Output(UInt(1.W))
val lsu_axi_awready = Input(UInt(1.W))
val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_awaddr = Output(UInt(32.W))
val lsu_axi_awregion = Output(UInt(4.W))
val lsu_axi_awlen = Output(UInt(8.W))
val lsu_axi_awsize = Output(UInt(3.W))
val lsu_axi_awburst = Output(UInt(2.W))
val lsu_axi_awlock = Output(UInt(1.W))
val lsu_axi_awcache = Output(UInt(4.W))
val lsu_axi_awprot = Output(UInt(3.W))
val lsu_axi_awqos = Output(UInt(4.W))
val lsu_axi_wvalid = Output(UInt(1.W))
val lsu_axi_wready = Input(UInt(1.W))
val lsu_axi_wdata = Output(UInt(64.W))
val lsu_axi_wstrb = Output(UInt(8.W))
val lsu_axi_wlast = Output(UInt(1.W))
val lsu_axi_bvalid = Input(UInt(1.W))
val lsu_axi_bready = Output(UInt(1.W))
val lsu_axi_bresp = Input(UInt(2.W))
val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_arvalid = Output(UInt(1.W))
val lsu_axi_arready = Input(UInt(1.W))
val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_araddr = Output(UInt(32.W))
val lsu_axi_arregion = Output(UInt(4.W))
val lsu_axi_arlen = Output(UInt(8.W))
val lsu_axi_arsize = Output(UInt(3.W))
val lsu_axi_arburst = Output(UInt(2.W))
val lsu_axi_arlock = Output(UInt(1.W))
val lsu_axi_arcache = Output(UInt(4.W))
val lsu_axi_arprot = Output(UInt(3.W))
val lsu_axi_arqos = Output(UInt(4.W))
val lsu_axi_rvalid = Input(UInt(1.W))
val lsu_axi_rready = Output(UInt(1.W))
val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W))
val lsu_axi_rdata = Input(UInt(64.W))
val lsu_axi_rresp = Intput(UInt(2.W))
val lsu_axi_rlast = Intput(UInt(1.W))
val lsu_bus_clk_en = Intput(UInt(1.W))
})
val lsu_pkt_m = new el2_lsu_pkt_t()
val lsu_pkt_r = new el2_lsu_pkt_t()
io.lsu_busreq_r := 0.U
io.lsu_bus_buffer_pend_any := 0.U
io.lsu_bus_buffer_full_any := 0.U
io.lsu_bus_buffer_empty_any := 0.U
io.lsu_bus_idle_any := 0.U
io.bus_read_data_m := 0.U
io.lsu_imprecise_error_load_any := 0.U
io.lsu_imprecise_error_store_any := 0.U
io.lsu_imprecise_error_addr_any := 0.U
io.lsu_nonblock_load_valid_m := 0.U
io.lsu_nonblock_load_tag_m := 0.U
io.lsu_nonblock_load_inv_r := 0.U
io.lsu_nonblock_load_inv_tag_r := 0.U
io.lsu_nonblock_load_data_valid := 0.U
io.lsu_nonblock_load_data_error := 0.U
io.lsu_nonblock_load_data_tag := 0.U
io.lsu_nonblock_load_data := 0.U
io.lsu_pmu_bus_trxn := 0.U
io.lsu_pmu_bus_misaligned := 0.U
io.lsu_pmu_bus_error := 0.U
io.lsu_pmu_bus_busy := 0.U
io.lsu_axi_awvalid := 0.U
io.lsu_axi_awid := 0.U
io.lsu_axi_awaddr := 0.U
io.lsu_axi_awregion := 0.U
io.lsu_axi_awlen := 0.U
io.lsu_axi_awsize := 0.U
io.lsu_axi_awburst := 0.U
io.lsu_axi_awlock := 0.U
io.lsu_axi_awcache := 0.U
io.lsu_axi_awprot := 0.U
io.lsu_axi_awqos := 0.U
io.lsu_axi_wvalid := 0.U
io.lsu_axi_wdata := 0.U
io.lsu_axi_wstrb := 0.U
io.lsu_axi_wlast := 0.U
io.lsu_axi_bready := 0.U
io.lsu_axi_arvalid := 0.U
io.lsu_axi_arid := 0.U
io.lsu_axi_araddr := 0.U
io.lsu_axi_arregion := 0.U
io.lsu_axi_arlen := 0.U
io.lsu_axi_arsize := 0.U
io.lsu_axi_arburst := 0.U
io.lsu_axi_arlock := 0.U
io.lsu_axi_arcache := 0.U
io.lsu_axi_arprot := 0.U
io.lsu_axi_arqos := 0.U
io.lsu_axi_rready := 0.U
}

122
src/main/scala/lsu/el2_lsu_clkdomain.scala
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@ -1,122 +0,0 @@
package lsu
import chisel3._
import chisel3.util._
import lib._
import include._
import snapshot._
//noinspection ScalaStyle
class el2_lsu_clkdomain extends Module {
val io = IO (new Bundle {
/* Implicit
val clk = Input(Clock()) // clock
val rst_l = Input(1.W) // reset
*/
val free_clk = Input(Clock()) // clock
// Inputs
val clk_override = Input(Bool()) // chciken bit to turn off clock gating
val addr_in_dccm_m = Input(Bool()) // address in dccm
val dma_dccm_req = Input(Bool()) // dma is active
val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
val stbuf_reqvld_any = Input(Bool()) // stbuf is draining
val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed
val lsu_busreq_r = Input(Bool()) // busreq in r
val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry
val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty
val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty
val lsu_bus_clk_en = Input(Bool()) // bus clock enable
val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode
val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d
val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m
val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r
// Outputs
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock
val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock
val lsu_store_c1_m_clk = Output(Clock()) // store in m
val lsu_store_c1_r_clk = Output(Clock()) // store in r
val lsu_stbuf_c1_clk = Output(Clock())
val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock
val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock
val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock
val lsu_busm_clk = Output(Clock()) // bus clock
val lsu_free_c2_clk = Output(Clock())
val scan_mode = Input(Bool())
})
//-------------------------------------------------------------------------------------------
// Clock Enable Logic
//-------------------------------------------------------------------------------------------
val lsu_c1_d_clken_q = Wire(Bool())
val lsu_c1_m_clken_q = Wire(Bool())
val lsu_c1_r_clken_q = Wire(Bool())
val lsu_free_c1_clken_q = Wire(Bool())
val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override
val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override
val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override
val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override
val lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override
val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.store) | io.clk_override)
val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.store) | io.clk_override)
val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override
val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
val lsu_bus_buf_c1_clken = ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override
val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override
val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)}
lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)}
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
val lsu_c1m_cgc = Module(new rvclkhdr); lsu_c1m_cgc.io.en := lsu_c1_m_clken ; io.lsu_c1_m_clk := lsu_c1m_cgc.io.l1clk
val lsu_c1r_cgc = Module(new rvclkhdr); lsu_c1r_cgc.io.en := lsu_c1_r_clken ; io.lsu_c1_r_clk := lsu_c1r_cgc.io.l1clk
val lsu_c2m_cgc = Module(new rvclkhdr); lsu_c2m_cgc.io.en := lsu_c2_m_clken ; io.lsu_c2_m_clk := lsu_c2m_cgc.io.l1clk
val lsu_c2r_cgc = Module(new rvclkhdr); lsu_c2r_cgc.io.en := lsu_c2_r_clken ; io.lsu_c2_r_clk := lsu_c2r_cgc.io.l1clk
val lsu_store_c1m_cgc = Module(new rvclkhdr); lsu_store_c1m_cgc.io.en := lsu_store_c1_m_clken ; io.lsu_store_c1_m_clk := lsu_store_c1m_cgc.io.l1clk
val lsu_store_c1r_cgc = Module(new rvclkhdr); lsu_store_c1r_cgc.io.en := lsu_store_c1_r_clken ; io.lsu_store_c1_r_clk := lsu_store_c1r_cgc.io.l1clk
val lsu_stbuf_c1_cgc = Module(new rvclkhdr); lsu_stbuf_c1_cgc.io.en := lsu_stbuf_c1_clken ; io.lsu_stbuf_c1_clk := lsu_stbuf_c1_cgc.io.l1clk
val lsu_bus_ibuf_c1_cgc = Module(new rvclkhdr); lsu_bus_ibuf_c1_cgc.io.en := lsu_bus_ibuf_c1_clken; io.lsu_bus_ibuf_c1_clk := lsu_bus_ibuf_c1_cgc.io.l1clk
val lsu_bus_obuf_c1_cgc = Module(new rvclkhdr); lsu_bus_obuf_c1_cgc.io.en := lsu_bus_obuf_c1_clken; io.lsu_bus_obuf_c1_clk := lsu_bus_obuf_c1_cgc.io.l1clk
val lsu_bus_buf_c1_cgc = Module(new rvclkhdr); lsu_bus_buf_c1_cgc.io.en := lsu_bus_buf_c1_clken ; io.lsu_bus_buf_c1_clk := lsu_bus_buf_c1_cgc.io.l1clk
val lsu_busm_cgc = Module(new rvclkhdr); lsu_busm_cgc.io.en := io.lsu_bus_clk_en ; io.lsu_busm_clk := lsu_busm_cgc.io.l1clk
val lsu_free_cgc = Module(new rvclkhdr); lsu_free_cgc.io.en := lsu_free_c2_clken ; io.lsu_free_c2_clk := lsu_free_cgc.io.l1clk
lsu_c1m_cgc.io.clk := clock; lsu_c1m_cgc.io.scan_mode := io.scan_mode
lsu_c1r_cgc.io.clk := clock; lsu_c1r_cgc.io.scan_mode := io.scan_mode
lsu_c2m_cgc.io.clk := clock; lsu_c2m_cgc.io.scan_mode := io.scan_mode
lsu_c2r_cgc.io.clk := clock; lsu_c2r_cgc.io.scan_mode := io.scan_mode
lsu_store_c1m_cgc.io.clk := clock; lsu_store_c1m_cgc.io.scan_mode := io.scan_mode
lsu_store_c1r_cgc.io.clk := clock; lsu_store_c1r_cgc.io.scan_mode := io.scan_mode
lsu_stbuf_c1_cgc.io.clk := clock; lsu_stbuf_c1_cgc.io.scan_mode := io.scan_mode
lsu_bus_ibuf_c1_cgc.io.clk := clock; lsu_bus_ibuf_c1_cgc.io.scan_mode := io.scan_mode
lsu_bus_obuf_c1_cgc.io.clk := clock; lsu_bus_obuf_c1_cgc.io.scan_mode := io.scan_mode
lsu_bus_buf_c1_cgc.io.clk := clock; lsu_bus_buf_c1_cgc.io.scan_mode := io.scan_mode
lsu_busm_cgc.io.clk := clock; lsu_busm_cgc.io.scan_mode := io.scan_mode
lsu_free_cgc.io.clk := clock; lsu_free_cgc.io.scan_mode := io.scan_mode
}
object cgcmain extends App{
println("Generate Verilog")
chisel3.Driver.execute(args, ()=> new el2_lsu_clkdomain)
}

104
src/main/scala/lsu/el2_lsu_ecc.scala
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@ -1,104 +0,0 @@
class el2_lsu_ecc extends Module {
val io = IO(new Bundle{
val lsu_c2_r_clk = Input(Clock())
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
val stbuf_data_any = Input(UInt(32.W))
val dec_tlu_core_ecc_disable = Input(UInt(1.W))
val lsu_dccm_rden_r = Input(UInt(1.W))
val addr_in_dccm_r = Input(UInt(1.W))
val lsu_addr_r = Input(UInt(16.W))
val end_addr_r = Input(UInt(16.W))
val lsu_addr_m = Input(UInt(16.W))
val end_addr_m = Input(UInt(16.W))
val dccm_rdata_hi_r = Input(UInt(32.W))
val dccm_rdata_lo_r = Input(UInt(32.W))
val dccm_rdata_hi_m = Input(UInt(32.W))
val dccm_rdata_lo_m = Input(UInt(32.W))
val dccm_data_ecc_hi_r = Input(UInt(7.W))
val dccm_data_ecc_lo_r = Input(UInt(7.W))
val dccm_data_ecc_hi_m = Input(UInt(7.W))
val dccm_data_ecc_lo_m = Input(UInt(7.W))
val ld_single_ecc_error_r = Input(UInt(1.W))
val ld_single_ecc_error_r_ff = Input(UInt(1.W))
val lsu_dccm_rden_m = Input(UInt(1.W))
val addr_in_dccm_m = Input(UInt(1.W))
val dma_dccm_wen = Input(UInt(1.W))
val dma_dccm_wdata_lo = Input(UInt(32.W))
val dma_dccm_wdata_hi = Input(UInt(32.W))
val scan_mode = Input(UInt(1.W))
//Outputs
val sec_data_hi_r = Output(UInt(32.W))
val sec_data_lo_r = Output(UInt(32.W))
val sec_data_hi_m = Output(UInt(32.W))
val sec_data_lo_m = Output(UInt(32.W))
val sec_data_hi_r_ff = Output(UInt(32.W))
val sec_data_lo_r_ff = Output(UInt(32.W))
val dma_dccm_wdata_ecc_hi = Output(UInt(7.W))
val dma_dccm_wdata_ecc_lo = Output(UInt(7.W))
val stbuf_ecc_any = Output(UInt(7.W))
val sec_data_ecc_hi_r_ff = Output(UInt(7.W))
val sec_data_ecc_lo_r_ff = Output(UInt(7.W))
val single_ecc_error_hi_r = Output(UInt(1.W))
val single_ecc_error_lo_r = Output(UInt(1.W))
val lsu_single_ecc_error_r = Output(UInt(1.W))
val lsu_double_ecc_error_r = Output(UInt(1.W))
val lsu_single_ecc_error_m = Output(UInt(1.W))
val lsu_double_ecc_error_m = Output(UInt(1.W))
})
val is_ldst_r = WireInit(0.U(1.W))
val is_ldst_hi_any = WireInit(0.U(1.W))
val is_ldst_lo_any = WireInit(0.U(1.W))
val dccm_wdata_hi_any = WireInit(0.U(32.W))
val dccm_wdata_lo_any = WireInit(0.U(32.W))
val dccm_rdata_hi_any = WireInit(0.U(32.W))
val dccm_rdata_lo_any = WireInit(0.U(32.W))
val sec_data_hi_any = WireInit(0.U(32.W))
val sec_data_lo_any = WireInit(0.U(32.W))
val dccm_wdata_ecc_hi_any = WireInit(0.U(7.W))
val dccm_wdata_ecc_lo_any = WireInit(0.U(7.W))
val dccm_data_ecc_hi_any = WireInit(0.U(7.W))
val dccm_data_ecc_lo_any = WireInit(0.U(7.W))
val single_ecc_error_hi_any = WireInit(0.U(1.W))
val single_ecc_error_lo_any = WireInit(0.U(1.W))
val double_ecc_error_hi_any = WireInit(0.U(1.W))
val double_ecc_error_lo_any = WireInit(0.U(1.W))
val double_ecc_error_hi_m = WireInit(0.U(1.W))
val double_ecc_error_lo_m = WireInit(0.U(1.W))
val double_ecc_error_hi_r = WireInit(0.U(1.W))
val double_ecc_error_lo_r = WireInit(0.U(1.W))
val ecc_out_hi_nc = WireInit(0.U(7.W))
val ecc_out_lo_nc = WireInit(0.U(7.W))
io.sec_data_hi_r :=0.U
io.sec_data_lo_r :=0.U
io.sec_data_hi_m :=0.U
io.sec_data_lo_m :=0.U
io.sec_data_hi_r_ff :=0.U
io.sec_data_lo_r_ff :=0.U
io.dma_dccm_wdata_ecc_hi :=0.U
io.dma_dccm_wdata_ecc_lo :=0.U
io.stbuf_ecc_any :=0.U
io.sec_data_ecc_hi_r_ff :=0.U
io.sec_data_ecc_lo_r_ff :=0.U
io.single_ecc_error_hi_r :=0.U
io.single_ecc_error_lo_r :=0.U
io.lsu_single_ecc_error_r :=0.U
io.lsu_double_ecc_error_r :=0.U
io.lsu_single_ecc_error_m :=0.U
io.lsu_double_ecc_error_m :=0.U
}

541
src/main/scala/lsu/el2_lsu_lsc_ctl.scala
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@ -1,541 +0,0 @@
package lsu
import include._
import lib._
import snapshot._
import chisel3._
import chisel3.util._
import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
import chisel3.experimental.ChiselEnum
import chisel3.experimental.{withClock, withReset, withClockAndReset}
import chisel3.experimental.BundleLiterals._
import chisel3.tester._
import chisel3.tester.RawTester.test
import chisel3.util.HasBlackBoxResource
class el2_lsu_lsc_ctl extends Module
{
val io = IO(new Bundle{
//val rst_l = IO(Input(1.W)) //implicit
val lsu_c1_m_clk = Input(Clock())
val lsu_c1_r_clk = Input(Clock())
val lsu_c2_m_clk = Input(Clock())
val lsu_c2_r_clk = Input(Clock())
val lsu_store_c1_m_clk = Input(Clock())
val lsu_ld_data_r = Input(UInt(32.W)) //DCCM data
val lsu_ld_data_corr_r = Input(UInt(32.W)) // ECC corrected data
val lsu_single_ecc_error_r = Input(UInt(1.W))
val lsu_double_ecc_error_r = Input(UInt(1.W))
val lsu_ld_data_m = Input(UInt(32.W))
val lsu_single_ecc_error_m = Input(UInt(1.W))
val lsu_double_ecc_error_m = Input(UInt(1.W))
val flush_m_up = Input(UInt(1.W))
val flush_r = Input(UInt(1.W))
val exu_lsu_rs1_d = Input(UInt(32.W)) // address
val exu_lsu_rs2_d = Input(UInt(32.W)) // store data
val lsu_p = Input(new el2_lsu_pkt_t()) // lsu control packet //coming from decode
val dec_lsu_valid_raw_d = Input(UInt(1.W)) // Raw valid for address computation
val dec_lsu_offset_d = Input(UInt(12.W))
val picm_mask_data_m = Input(UInt(32.W))
val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface
val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF
// lsu address down the pipe
val lsu_addr_d = Output(UInt(32.W))
val lsu_addr_m = Output(UInt(32.W))
val lsu_addr_r = Output(UInt(32.W))
// lsu address down the pipe - needed to check unaligned
val end_addr_d = Output(UInt(32.W))
val end_addr_m = Output(UInt(32.W))
val end_addr_r = Output(UInt(32.W))
// store data down the pipe
val store_data_m = Output(UInt(32.W))
val dec_tlu_mrac_ff = Input(UInt(32.W)) // CSR read
val lsu_exc_m = Output(UInt(1.W))
val is_sideeffects_m = Output(UInt(1.W))
val lsu_commit_r = Output(UInt(1.W))
val lsu_single_ecc_error_incr = Output(UInt(1.W))
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t())
val lsu_fir_addr = Output(UInt(32.W)) //(31:1) in sv // fast interrupt address TBD
val lsu_fir_error = Output(UInt(2.W)) // Error during fast interrupt lookup TBD
// address in dccm/pic/external per pipe stage
val addr_in_dccm_d = Output(UInt(1.W))
val addr_in_dccm_m = Output(UInt(1.W))
val addr_in_dccm_r = Output(UInt(1.W))
val addr_in_pic_d = Output(UInt(1.W))
val addr_in_pic_m = Output(UInt(1.W))
val addr_in_pic_r = Output(UInt(1.W))
val addr_external_m = Output(UInt(1.W))
// DMA slave
val dma_dccm_req = Input(UInt(1.W))
val dma_mem_addr = Input(UInt(32.W))
val dma_mem_sz = Input(UInt(3.W))
val dma_mem_write = Input(UInt(1.W))
val dma_mem_wdata = Input(UInt(64.W))
// Store buffer related signals
val lsu_pkt_d = Output(new el2_lsu_pkt_t())
val lsu_pkt_m = Output(new el2_lsu_pkt_t())
val lsu_pkt_r = Output(new el2_lsu_pkt_t())
val scan_mode = Input(UInt(1.W))
})
val dma_pkt_d = Wire(new el2_lsu_pkt_t())
val lsu_pkt_m_in = Wire(new el2_lsu_pkt_t())
val lsu_pkt_r_in = Wire(new el2_lsu_pkt_t())
val lsu_error_pkt_m = Wire(new el2_lsu_error_pkt_t())
val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.exu_lsu_rs1_d,io.dma_mem_addr)
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
val rs1_d_raw = lsu_rs1_d
val offset_d = lsu_offset_d
val rs1_d = Mux(io.lsu_pkt_d.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw)
// generate the ls address
val lsadder = Module(new rvlsadder())
lsadder.io.rs1 := rs1_d
lsadder.io.offset := offset_d
val full_addr_d = lsadder.io.dout
val addr_offset_d = ((Fill(3,io.lsu_pkt_d.half)) & "b001".U) |
((Fill(3,io.lsu_pkt_d.word)) & "b011".U) |
((Fill(3,io.lsu_pkt_d.dword)) & "b111".U)
val end_addr_offset_d = Cat(offset_d(11),offset_d(11,0)) + Cat(Fill(9,"b0".U),addr_offset_d(2,0))
val full_end_addr_d = rs1_d(31,0) + Cat(Fill(19,end_addr_offset_d(12)),end_addr_offset_d(12,0))
io.end_addr_d := full_end_addr_d
//optimize with bulk operator
val addrcheck = Module(new el2_lsu_addrcheck())
addrcheck.io.lsu_c2_m_clk := io.lsu_c2_m_clk
//val rst_l = IO(Input(1.W)) //implicit
addrcheck.io.start_addr_d := full_addr_d
addrcheck.io.end_addr_d := full_end_addr_d
addrcheck.io.lsu_pkt_d := io.lsu_pkt_d
addrcheck.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
addrcheck.io.rs1_region_d := rs1_d(31,28)
addrcheck.io.rs1_d := rs1_d
io.is_sideeffects_m := addrcheck.io.is_sideeffects_m
io.addr_in_dccm_d := addrcheck.io.addr_in_dccm_d
io.addr_in_pic_d := addrcheck.io.addr_in_pic_d
val addr_external_d = addrcheck.io.addr_external_d
val access_fault_d = addrcheck.io.access_fault_d
val misaligned_fault_d = addrcheck.io.misaligned_fault_d
val exc_mscause_d = addrcheck.io.exc_mscause_d
val fir_dccm_access_error_d = addrcheck.io.fir_dccm_access_error_d
val fir_nondccm_access_error_d = addrcheck.io.fir_nondccm_access_error_d
addrcheck.io.scan_mode := io.scan_mode
val access_fault_r = WireInit(0.U(1.W))
val misaligned_fault_r = WireInit(0.U(1.W))
val exc_mscause_r = WireInit(0.U(4.W))
val fir_dccm_access_error_r = WireInit(0.U(1.W))
val fir_nondccm_access_error_r = WireInit(0.U(1.W))
//val access_fault_rff = Module(new rvdff(1,0))
val access_fault_mff = Module(new rvdff(1,0))
//val misaligned_fault_rff = Module(new rvdff(1,0))
val misaligned_fault_mff = Module(new rvdff(1,0))
// val exc_mscause_rff = Module(new rvdff(4,0))
val exc_mscause_mff = Module(new rvdff(4,0))
// val fir_dccm_access_error_mff = Module(new rvdff(1,0))
// val fir_nondccm_access_error_mff = Module(new rvdff(1,0))
//val lsu_error_pkt_rff = Module(new rvdff(6,0))
val lsu_fir_error_rff = Module(new rvdff(2,0))
val lsu_fir_error_m = WireInit(0.U(2.W))
val access_fault_m = WireInit(0.U(1.W))
val misaligned_fault_m = WireInit(0.U(1.W))
val exc_mscause_m = WireInit(0.U(4.W))
val fir_dccm_access_error_m = WireInit(0.U(1.W))
val fir_nondccm_access_error_m = WireInit(0.U(1.W))
io.lsu_exc_m := access_fault_m | misaligned_fault_m
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & ~io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.dma) & io.lsu_pkt_r.valid
if (pt1.LOAD_TO_USE_PLUS1 == 1){
// Generate exception packet
io.lsu_error_pkt_r.exc_valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & ~io.lsu_pkt_r.dma & ~io.lsu_pkt_r.fast_int //TBD(lsu_pkt_r.fast_int)
io.lsu_error_pkt_r.single_ecc_error := io.lsu_single_ecc_error_r & ~io.lsu_error_pkt_r.exc_valid & ~io.lsu_pkt_r.dma
io.lsu_error_pkt_r.inst_type := io.lsu_pkt_r.store
io.lsu_error_pkt_r.exc_type := ~misaligned_fault_r
io.lsu_error_pkt_r.mscause := Mux((io.lsu_double_ecc_error_r & ~misaligned_fault_r & ~access_fault_r).asBool,"b0001".U, exc_mscause_r(3,0))
io.lsu_error_pkt_r.addr := io.lsu_addr_r(31,0)//lsu_addr_d->lsu_full_addr
io.lsu_fir_error := Mux(fir_nondccm_access_error_r.asBool,"b11".U(2.W), Mux(fir_dccm_access_error_r.asBool,"b10".U(2.W), Mux((io.lsu_pkt_r.fast_int & io.lsu_double_ecc_error_r).asBool,"b01".U(2.W),"b00".U(2.W))))
//Access fault: Address checker module , etc
// access_fault_rff.io.din := access_fault_m
// access_fault_r := access_fault_rff.io.dout
access_fault_r := RegNext(access_fault_m)
misaligned_fault_r := RegNext(misaligned_fault_m)
// exc_mscause_rff.io.din := exc_mscause_m
// exc_mscause_r := exc_mscause_rff.io.dout
exc_mscause_r := RegNext(exc_mscause_m)
// fir_dccm_access_error_mff.io.din := fir_dccm_access_error_m
// fir_dccm_access_error_r := fir_dccm_access_error_mff.io.dout
fir_dccm_access_error_r := RegNext(fir_dccm_access_error_m)
// fir_nondccm_access_error_mff.io.din := fir_nondccm_access_error_m
// fir_nondccm_access_error_r := fir_nondccm_access_error_mff.io.dout
fir_nondccm_access_error_r := RegNext(fir_nondccm_access_error_m)
// lsu_error_pkt_rff.io.din := 0.U
}
else //L2U_Plus1_0
{
io.lsu_fir_error := 0.U
// Generate exception packet
lsu_error_pkt_m.exc_valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & ~io.lsu_pkt_m.dma & ~io.lsu_pkt_m.fast_int & ~io.flush_m_up //TBD(lsu_pkt_r.fast_int)
lsu_error_pkt_m.single_ecc_error := io.lsu_single_ecc_error_m & ~lsu_error_pkt_m.exc_valid & ~io.lsu_pkt_m.dma
lsu_error_pkt_m.inst_type := io.lsu_pkt_m.store
lsu_error_pkt_m.exc_type := ~misaligned_fault_m
lsu_error_pkt_m.mscause := Mux((io.lsu_double_ecc_error_m & ~misaligned_fault_m & ~access_fault_m).asBool,"b0001".U, exc_mscause_m(3,0))
lsu_error_pkt_m.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,"b11".U, Mux(fir_dccm_access_error_m.asBool,"b10".U, Mux((io.lsu_pkt_m.fast_int & io.lsu_double_ecc_error_m).asBool,"b01".U,"b00".U)))
// lsu_error_pkt_rff.io.din := lsu_error_pkt_m
// io.lsu_error_pkt_r := lsu_error_pkt_rff.io.dout
io.lsu_error_pkt_r := RegNext(lsu_error_pkt_m)
lsu_fir_error_rff.io.din := lsu_fir_error_m
lsu_fir_error_m := lsu_fir_error_rff.io.dout
access_fault_mff.io.din := access_fault_d
access_fault_m := access_fault_mff.io.dout
misaligned_fault_mff.io.din := misaligned_fault_d
misaligned_fault_m := misaligned_fault_mff.io.dout
exc_mscause_mff.io.din := exc_mscause_d
exc_mscause_m := exc_mscause_mff.io.dout
// fir_dccm_access_error_mff.io.din := fir_dccm_access_error_d
// fir_dccm_access_error_m := fir_dccm_access_error_mff.io.dout
fir_dccm_access_error_m := RegNext(fir_dccm_access_error_d)
// fir_nondccm_access_error_mff.io.din := fir_nondccm_access_error_d
// fir_nondccm_access_error_m := fir_nondccm_access_error_mff.io.dout
fir_nondccm_access_error_m := RegNext(fir_nondccm_access_error_d)
}
dma_pkt_d.unsign := 0.U
dma_pkt_d.fast_int := 0.U
dma_pkt_d.valid := io.dma_dccm_req
dma_pkt_d.dma := 1.U
dma_pkt_d.store := io.dma_mem_write
dma_pkt_d.load := ~io.dma_mem_write
dma_pkt_d.by := (io.dma_mem_sz(2,0) === "b000".U)
dma_pkt_d.half := (io.dma_mem_sz(2,0) === "b001".U)
dma_pkt_d.word := (io.dma_mem_sz(2,0) === "b010".U)
dma_pkt_d.dword := (io.dma_mem_sz(2,0) === "b011".U)
dma_pkt_d.store_data_bypass_d := 0.U
dma_pkt_d.load_ldst_bypass_d := 0.U
dma_pkt_d.store_data_bypass_m := 0.U
val lsu_pkt_vldmff = Module(new rvdff(1,0))
val lsu_pkt_vldrff = Module(new rvdff(1,0))
val lsu_ld_datafn_r = WireInit(0.U(32.W))
val lsu_ld_datafn_corr_r = WireInit(0.U(32.W))
val lsu_ld_datafn_m = WireInit(0.U(32.W))
io.lsu_pkt_d := Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_p,dma_pkt_d)
lsu_pkt_m_in := io.lsu_pkt_d
lsu_pkt_r_in := io.lsu_pkt_m
io.lsu_pkt_d.valid := (io.lsu_p.valid & ~(io.flush_m_up & ~io.lsu_p.fast_int)) | io.dma_dccm_req
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & ~(io.flush_m_up & ~io.lsu_pkt_d.dma)
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & ~(io.flush_m_up & ~io.lsu_pkt_m.dma)
lsu_pkt_vldmff.io.din := lsu_pkt_m_in.valid
io.lsu_pkt_m.valid := lsu_pkt_vldmff.io.dout
lsu_pkt_vldrff.io.din := lsu_pkt_r_in.valid
io.lsu_pkt_r.valid := lsu_pkt_vldrff.io.dout
//val lsu_pkt_mff = Module(new rvdff(12,0)) //recheck
//lsu_pkt_mff.io.din := lsu_pkt_m_in
//io.lsu_pkt_m <> lsu_pkt_mff.io.dout //recheck
io.lsu_pkt_m := RegNext(lsu_pkt_m_in)
//val lsu_pkt_rff = Module(new rvdff(12,0)) //recheck
//lsu_pkt_rff.io.din := lsu_pkt_r_in
//io.lsu_pkt_r <> lsu_pkt_rff.io.dout //recheck
io.lsu_pkt_r := RegNext(lsu_pkt_r_in)
val dma_mem_wdata_shifted = io.dma_mem_wdata(63,0) >> Cat(io.dma_mem_addr(2,0), "b000".U) // Shift the dma data to lower bits to make it consistent to lsu stores
val store_data_d = Mux(io.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
val store_data_m_in = Mux(io.lsu_pkt_d.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0))
val sdmff= Module(new rvdff(32,0))
sdmff.io.din := store_data_m_in
val store_data_pre_m = sdmff.io.dout
val samff= Module(new rvdff(32,0))
samff.io.din := io.lsu_addr_d
io.lsu_addr_m := samff.io.dout
val sarff= Module(new rvdff(32,0))
sarff.io.din := io.lsu_addr_m
io.lsu_addr_r := sarff.io.dout
val end_addr_mff = Module(new rvdff(32,0))
end_addr_mff.io.din := io.end_addr_d
io.end_addr_m := end_addr_mff.io.dout
val end_addr_rff = Module(new rvdff(32,0))
end_addr_rff.io.din := io.end_addr_m
io.end_addr_r := end_addr_rff.io.dout
val addr_in_dccm_mff = Module(new rvdff(1,0))
addr_in_dccm_mff.io.din := io.addr_in_dccm_d
io.addr_in_dccm_m := addr_in_dccm_mff.io.dout
val addr_in_dccm_rff = Module(new rvdff(1,0))
addr_in_dccm_rff.io.din := io.addr_in_dccm_m
io.addr_in_dccm_r := addr_in_dccm_rff.io.dout
val addr_in_pic_mff = Module(new rvdff(1,0))
addr_in_pic_mff.io.din := io.addr_in_pic_d
io.addr_in_pic_m := addr_in_pic_mff.io.dout
val addr_in_pic_rff = Module(new rvdff(1,0))
addr_in_pic_rff.io.din := io.addr_in_pic_m
io.addr_in_pic_r := addr_in_pic_rff.io.dout
val addr_external_mff = Module(new rvdff(1,0))
addr_external_mff.io.din := addr_external_d
io.addr_external_m := addr_external_mff.io.dout
val addr_external_rff = Module(new rvdff(1,0))
addr_external_rff.io.din := io.addr_external_m
val addr_external_r = addr_external_rff.io.dout
val bus_read_data_r_ff = Module(new rvdff(32,0))
bus_read_data_r_ff.io.din := io.bus_read_data_m
val bus_read_data_r = bus_read_data_r_ff.io.dout
// Fast interrupt address
io.lsu_fir_addr := io.lsu_ld_data_corr_r(31,0) //original (31,1) TBD
// absence load/store all 0's
io.lsu_addr_d := full_addr_d
// Interrupt as a flush source allows the WB to occur
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.store | io.lsu_pkt_r.load) & ~io.flush_r & ~io.lsu_pkt_r.dma
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,~io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
if (pt1.LOAD_TO_USE_PLUS1 == 1){
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
lsu_ld_datafn_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r)
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
// this is really R stage but don't want to make all the changes to support M,R buses
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat("h000000".U,lsu_ld_datafn_r(7,0))) |
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat("h0000".U,lsu_ld_datafn_r(15,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_r(31,0))
// this signal is used for gpr update
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat("h000000".U,lsu_ld_datafn_corr_r(7,0))) |
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat("h0000".U,lsu_ld_datafn_corr_r(15,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
}
else {
lsu_ld_datafn_m := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m)
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat("h000000".U,lsu_ld_datafn_m(7,0))) |
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat("h0000".U,lsu_ld_datafn_m(15,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_m(31,0))
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat("h000000".U,lsu_ld_datafn_corr_r(7,0))) |
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat("h0000".U,lsu_ld_datafn_corr_r(15,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
((Fill(32,~io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
}
/*
io.lsu_result_m :=0.U
io.lsu_result_corr_r :=0.U
io.lsu_addr_d :=0.U
io.lsu_addr_m :=0.U
io.lsu_addr_r :=0.U
io.end_addr_d :=0.U
io.end_addr_m :=0.U
io.end_addr_r :=0.U
io.store_data_m := 0.U
io.dec_tlu_mrac_ff := 0.U
io.lsu_exc_m :=0.U
// io.is_sideeffects_m :=0.U
io.lsu_commit_r :=0.U
io.lsu_single_ecc_error_incr :=0.U
io.lsu_error_pkt_r.exc_valid :=0.U
io.lsu_error_pkt_r.single_ecc_error :=0.U
io.lsu_error_pkt_r.inst_type :=0.U //0: Load, 1: Store
io.lsu_error_pkt_r.exc_type :=0.U //0: MisAligned, 1: Access Fault
io.lsu_error_pkt_r.mscause :=0.U
io.lsu_error_pkt_r.addr :=0.U
io.lsu_fir_addr :=0.U
io.lsu_fir_error :=0.U
// io.addr_in_dccm_d :=0.U
io.addr_in_dccm_m :=0.U
io.addr_in_dccm_r :=0.U
// io.addr_in_pic_d :=0.U
io.addr_in_pic_m :=0.U
io.addr_in_pic_r :=0.U
io.addr_external_m :=0.U
io.lsu_pkt_d.fast_int :=0.U
io.lsu_pkt_d.by :=0.U
io.lsu_pkt_d.half :=0.U
io.lsu_pkt_d.word :=0.U
io.lsu_pkt_d.dword :=0.U
io.lsu_pkt_d.load :=0.U
io.lsu_pkt_d.store :=0.U
io.lsu_pkt_d.unsign :=0.U
io.lsu_pkt_d.dma :=0.U
io.lsu_pkt_d.store_data_bypass_d :=0.U
io.lsu_pkt_d.load_ldst_bypass_d :=0.U
io.lsu_pkt_d.store_data_bypass_m :=0.U
io.lsu_pkt_d.valid :=0.U
io.lsu_pkt_m.fast_int :=0.U
io.lsu_pkt_m.by :=0.U
io.lsu_pkt_m.half :=0.U
io.lsu_pkt_m.word :=0.U
io.lsu_pkt_m.dword :=0.U
io.lsu_pkt_m.load :=0.U
io.lsu_pkt_m.store :=0.U
io.lsu_pkt_m.unsign :=0.U
io.lsu_pkt_m.dma :=0.U
io.lsu_pkt_m.store_data_bypass_d :=0.U
io.lsu_pkt_m.load_ldst_bypass_d :=0.U
io.lsu_pkt_m.store_data_bypass_m :=0.U
io.lsu_pkt_m.valid :=0.U
io.lsu_pkt_r.fast_int :=0.U
io.lsu_pkt_r.by :=0.U
io.lsu_pkt_r.half :=0.U
io.lsu_pkt_r.word :=0.U
io.lsu_pkt_r.dword :=0.U
io.lsu_pkt_r.load :=0.U
io.lsu_pkt_r.store :=0.U
io.lsu_pkt_r.unsign :=0.U
io.lsu_pkt_r.dma :=0.U
io.lsu_pkt_r.store_data_bypass_d :=0.U
io.lsu_pkt_r.load_ldst_bypass_d :=0.U
io.lsu_pkt_r.store_data_bypass_m :=0.U
io.lsu_pkt_r.valid :=0.U
*/
}
//println(chisel3.Driver.emitVerilog(new el2_lsu_lsc_ctl))
/*
object main extends App{
println("Generate Verilog")
chisel3.Driver.execute(args, ()=> new el2_lsu_lsc_ctl)
}*/

370
src/main/scala/lsu/el2_lsu_stbuf.scala
View File

@ -1,126 +1,258 @@
class el2_lsu_stbuf extends Module { package lsu
val io = IO (new Bundle { import lib._
val lsu_c1_m_clk = Input(Clock()) import chisel3._
val lsu_c1_r_clk = Input(Clock()) import chisel3.util._
val lsu_stbuf_c1_clk = Input(Clock()) import include._
val lsu_free_c2_clk = Input(Clock())
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
val store_stbuf_reqvld_r = Input(UInt(1.W))
val lsu_commit_r = Input(UInt(1.W))
val dec_lsu_valid_raw_d = Input(UInt(1.W))
val store_data_hi_r = Input(UInt(32.W))
val store_data_lo_r = Input(UInt(32.W))
val store_datafn_hi_r = Input(UInt(32.W))
val store_datafn_lo_r = Input(UInt(32.W))
val lsu_stbuf_commit_any = Input(UInt(1.W))
val lsu_addr_d = Input(UInt(16.W))
val lsu_addr_m = Input(UInt(32.W))
val lsu_addr_r = Input(UInt(32.W))
val end_addr_d = Input(UInt(16.W))
val end_addr_m = Input(UInt(32.W))
val end_addr_r = Input(UInt(32.W))
val addr_in_dccm_m = Input(UInt(1.W))
val addr_in_dccm_r = Input(UInt(1.W))
val lsu_cmpen_m = Input(UInt(1.W))
val scan_mode = Input(UInt(1.W))
//Outputs class el2_lsu_stbuf extends Module with param {
val stbuf_reqvld_any = Output(UInt(1.W)) val io = IO (new Bundle {
val stbuf_reqvld_flushed_any = Output(UInt(1.W)) val lsu_c1_m_clk = Input(Clock())
val stbuf_addr_any = Output(UInt(16.W)) val lsu_c1_r_clk = Input(Clock())
val stbuf_data_any = Output(UInt(32.W)) val lsu_stbuf_c1_clk = Input(Clock())
val lsu_stbuf_full_any = Output(UInt(1.W)) val lsu_free_c2_clk = Input(Clock())
val lsu_stbuf_empty_any = Output(UInt(1.W)) val lsu_pkt_m = Input(new el2_lsu_pkt_t)
val ldst_stbuf_reqvld_r = Output(UInt(1.W)) val lsu_pkt_r = Input(new el2_lsu_pkt_t)
val stbuf_fwddata_hi_m = Output(UInt(32.W)) val store_stbuf_reqvld_r = Input(Bool())
val stbuf_fwddata_lo_m = Output(UInt(32.W)) val lsu_commit_r = Input(Bool())
val stbuf_fwdbyteen_hi_m = Output(UInt(4.W)) val dec_lsu_valid_raw_d = Input(Bool())
val stbuf_fwdbyteen_lo_m = Output(UInt(32.W)) val store_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
}) val store_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
val stbuf_wr_en = WireInit(0.U(1.W)) val store_datafn_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
val stbuf_vld = WireInit(0.U(1.W)) val store_datafn_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
val stbuf_dma_kill_en = WireInit(0.U(1.W)) val lsu_stbuf_commit_any = Input(Bool())
val stbuf_dma_kill = WireInit(0.U(1.W)) val lsu_addr_d = Input(UInt(LSU_SB_BITS.W))
val sel_lo = WireInit(0.U(4.W)) val lsu_addr_m = Input(UInt(32.W))
val stbuf_reset = WireInit(0.U(4.W)) val lsu_addr_r = Input(UInt(32.W))
val store_byteen_ext_r = WireInit(0.U(8.W)) val end_addr_d = Input(UInt(LSU_SB_BITS.W))
val store_byteen_hi_r = WireInit(0.U(4.W)) val end_addr_m = Input(UInt(32.W))
val store_byteen_lo_r = WireInit(0.U(4.W)) val end_addr_r = Input(UInt(32.W))
val stbuf_addr = Vec(4,UInt(16.W))
val stbuf_byteen = Vec(4,UInt(4.W))
val stbuf_data = Vec(4,UInt(32.W))
val stbuf_addrin = Vec(4,UInt(16.W))
val stbuf_datain = Vec(4,UInt(32.W))
val stbuf_byteenin = Vec(4,UInt(4.W))
val store_matchvec_lo_r = WireInit(0.U(4.W))
val store_matchvec_hi_r = WireInit(0.U(4.W))
val store_coalesce_lo_r = WireInit(0.U(1.W))
val store_coalesce_hi_r = WireInit(0.U(1.W))
val WrPtrEn = WireInit(0.U(1.W))
val RdPtrEn = WireInit(0.U(1.W))
val WrPtr = WireInit(0.U(4.W))
val RdPtr = WireInit(0.U(4.W))
val NxtWrPtr = WireInit(0.U(4.W))
val NxtRdPtr = WireInit(0.U(4.W))
val WrPtrPlus1 = WireInit(0.U(4.W))
val WrPtrPlus2 = WireInit(0.U(4.W))
val RdPtrPlus1 = WireInit(0.U(4.W))
val ldst_dual_d = WireInit(0.U(1.W))
val ldst_dual_m = WireInit(0.U(1.W))
val ldst_dual_r = WireInit(0.U(1.W))
val dual_stbuf_write_r = WireInit(0.U(1.W))
val isdccmst_m = WireInit(0.U(1.W))
val isdccmst_r = WireInit(0.U(1.W))
val stbuf_numvld_any = WireInit(0.U(4.W))
val stbuf_specvld_any = WireInit(0.U(4.W))
val stbuf_specvld_m = WireInit(0.U(2.W))
val stbuf_specvld_r = WireInit(0.U(2.W))
val cmpen_hi_m = WireInit(0.U(1.W))
val cmpen_lo_m = WireInit(0.U(1.W))
val cmpaddr_hi_m = WireInit(0.U(12.W))
val cmpaddr_lo_m = WireInit(0.U(12.W))
val stbuf_match_hi = WireInit(0.U(4.W))
val stbuf_match_lo = WireInit(0.U(4.W))
val stbuf_fwdbyteenvec_hi = Vec(4,UInt(4.W))
val stbuf_fwdbyteenvec_lo = Vec(4,UInt(4.W))
val stbuf_fwdata_hi_pre_m = WireInit(0.U(32.W))
val stbuf_fwdata_lo_pre_m = WireInit(0.U(32.W))
val stbuf_fwdbyteen_hi_pre_m = WireInit(0.U(4.W))
val stbuf_fwdbyteen_lo_pre_m = WireInit(0.U(4.W))
val ld_byte_rhit_lo_lo = WireInit(0.U(4.W))
val ld_byte_rhit_hi_lo = WireInit(0.U(4.W))
val ld_byte_rhit_lo_hi = WireInit(0.U(4.W))
val ld_byte_rhit_hi_hi = WireInit(0.U(4.W))
val ld_addr_rhit_lo_lo = WireInit(0.U(1.W))
val ld_addr_rhit_hi_lo = WireInit(0.U(1.W))
val ld_addr_rhit_lo_hi = WireInit(0.U(1.W))
val ld_addr_rhit_hi_hi = WireInit(0.U(1.W))
val ld_byte_hit_lo = WireInit(0.U(4.W))
val ld_byte_rhit_lo = WireInit(0.U(4.W))
val ld_byte_hit_hi = WireInit(0.U(4.W))
val ld_byte_rhit_hi = WireInit(0.U(4.W))
val ldst_byteen_hi_r = WireInit(0.U(4.W))
val ldst_byteen_lo_r = WireInit(0.U(4.W))
val ldst_byteen_r = WireInit(0.U(8.W))
val ldst_byteen_ext_r = WireInit(0.U(8.W))
val ld_fwddata_rpipe_lo = WireInit(0.U(32.W))
val ld_fwddata_rpipe_hi = WireInit(0.U(32.W))
val addr_in_dccm_m = Input(Bool())
val addr_in_dccm_r = Input(Bool())
val lsu_cmpen_m = Input(Bool())
val scan_mode = Input(Bool())
io.stbuf_reqvld_any := 0.U //Outputs
io.stbuf_reqvld_flushed_any := 0.U val stbuf_reqvld_any = Output(Bool())
val stbuf_reqvld_flushed_any = Output(Bool())
val stbuf_addr_any = Output(UInt(LSU_SB_BITS.W))
val stbuf_data_any = Output(UInt(DCCM_DATA_WIDTH.W))
val lsu_stbuf_full_any = Output(Bool())
val lsu_stbuf_empty_any = Output(Bool())
val ldst_stbuf_reqvld_r = Output(Bool())
val stbuf_fwddata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
val stbuf_fwddata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
val stbuf_fwdbyteen_hi_m = Output(UInt(DCCM_BYTE_WIDTH.W))
val stbuf_fwdbyteen_lo_m = Output(UInt(DCCM_BYTE_WIDTH.W))
// val testout = Output(Vec(LSU_STBUF_DEPTH, UInt(8.W)))
})
io.stbuf_reqvld_any := 0.U
io.stbuf_reqvld_flushed_any := 0.U
io.stbuf_addr_any := 0.U io.stbuf_addr_any := 0.U
io.stbuf_data_any := 0.U io.stbuf_data_any := 0.U
io.lsu_stbuf_full_any := 0.U io.lsu_stbuf_full_any := 0.U
io.lsu_stbuf_empty_any := 0.U io.lsu_stbuf_empty_any := 0.U
io.ldst_stbuf_reqvld_r := 0.U io.ldst_stbuf_reqvld_r := 0.U
io.stbuf_fwddata_hi_m := 0.U io.stbuf_fwddata_hi_m := 0.U
io.stbuf_fwddata_lo_m := 0.U io.stbuf_fwddata_lo_m := 0.U
io.stbuf_fwdbyteen_hi_m := 0.U io.stbuf_fwdbyteen_hi_m := 0.U
io.stbuf_fwdbyteen_lo_m := 0.U io.stbuf_fwdbyteen_lo_m := 0.U
val stbuf_vld = Wire(Vec(LSU_STBUF_DEPTH, Bool()))
val stbuf_dma_kill_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
val stbuf_dma_kill = Wire(Vec(LSU_STBUF_DEPTH, Bool()))
val stbuf_reset = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
val store_byteen_ext_r = WireInit(UInt(8.W), init= 0.U)
val stbuf_addr = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W)))
stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val stbuf_byteen = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W)))
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val stbuf_data = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W)))
stbuf_data := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val stbuf_addrin = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W)))
stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val stbuf_datain = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W)))
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val stbuf_byteenin = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W)))
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
val ldst_dual_m = WireInit(Bool(),init = 0.U)
val ldst_dual_r = WireInit(Bool(),init = 0.U)
val cmpaddr_hi_m = WireInit(0.U(16.W))
val stbuf_specvld_m = WireInit(0.U(2.W))
val stbuf_specvld_r = WireInit(0.U(2.W))
val cmpaddr_lo_m = WireInit(0.U(16.W))
val stbuf_fwdata_hi_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val stbuf_fwdata_lo_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val ld_byte_rhit_lo_lo = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val ld_byte_rhit_hi_lo = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val ld_byte_rhit_lo_hi = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val ld_byte_rhit_hi_hi = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
val ld_byte_hit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
val ld_byte_rhit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
val ld_byte_hit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
val ld_byte_rhit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
val ldst_byteen_ext_r = WireInit(UInt(8.W),init = 0.U)
val ld_fwddata_rpipe_lo = WireInit(UInt(32.W),init = 0.U)
val ld_fwddata_rpipe_hi = WireInit(UInt(32.W),init = 0.U)
//
val datain1 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
val datain2 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
val datain3 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
val datain4 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
//////////////////////////////////////Code Start here///////////////////////////////
val ldst_byteen_r = Fill(8,io.lsu_pkt_r.by) & "b00000001".U |
Fill(8,io.lsu_pkt_r.half) & "b00000011".U |
Fill(8,io.lsu_pkt_r.word) & "b00001111".U |
Fill(8,io.lsu_pkt_r.dword) & "b11111111".U
val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2)
val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r
store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_m.store)
val store_byteen_lo_r = store_byteen_ext_r (3,0) & Fill(4, io.lsu_pkt_m.store)
val RdPtrPlus1 = RdPtr + "b01".U
val WrPtrPlus1 = WrPtr + "b01".U
val WrPtrPlus2 = WrPtr + "b10".U
io.ldst_stbuf_reqvld_r := io.lsu_commit_r & io.store_stbuf_reqvld_r
val store_matchvec_lo_r = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH)) === io.lsu_addr_r(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))) & stbuf_vld(i) & !stbuf_dma_kill(i) & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
val store_matchvec_hi_r = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH)) === io.end_addr_r(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))) & stbuf_vld(i) & !stbuf_dma_kill(i) & dual_stbuf_write_r & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
val store_coalesce_lo_r = store_matchvec_lo_r.orR
val store_coalesce_hi_r = store_matchvec_hi_r.orR
val stbuf_wr_en= (0 until LSU_STBUF_DEPTH).map(i=> (io.ldst_stbuf_reqvld_r & ((i == WrPtr).asBool & !store_coalesce_lo_r) | ((i == WrPtr).asBool & !dual_stbuf_write_r & !store_coalesce_hi_r) |
((i == WrPtrPlus1).asBool & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) | store_matchvec_lo_r(i) | store_matchvec_hi_r(i)).asUInt).reverse.reduce(Cat(_,_))
stbuf_reset := (0 until LSU_STBUF_DEPTH).map(i=> (io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any) & (i == RdPtr).asBool.asUInt).reverse.reduce(Cat(_,_))
val sel_lo = (0 until LSU_STBUF_DEPTH).map(i=> (!ldst_dual_r | io.store_stbuf_reqvld_r) & (i == WrPtr).asBool & !store_coalesce_lo_r | store_matchvec_lo_r(i).asUInt).reverse.reduce(Cat(_,_))
stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), io.lsu_addr_r, io.end_addr_r).asUInt).reverse
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt).reverse
datain1 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(0) | store_byteen_lo_r(0), io.store_datafn_lo_r(7, 0), stbuf_data(i)(7, 0)),
Mux(!stbuf_byteen(i)(0) | store_byteen_hi_r(0), io.store_datafn_hi_r(7, 0), stbuf_data(i)(7, 0))).asUInt).reverse
datain2 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(1) | store_byteen_lo_r(1), io.store_datafn_lo_r(15, 8), stbuf_data(i)(15, 8)),
Mux(!stbuf_byteen(i)(1) | store_byteen_hi_r(1), io.store_datafn_hi_r(15, 8), stbuf_data(i)(15, 8))).asUInt).reverse
datain3 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(2) | store_byteen_lo_r(2), io.store_datafn_lo_r(23, 16), stbuf_data(i)(23, 16)),
Mux(!stbuf_byteen(i)(2) | store_byteen_hi_r(2), io.store_datafn_hi_r(23, 16), stbuf_data(i)(23, 16))).asUInt).reverse
datain4 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(3) | store_byteen_lo_r(3), io.store_datafn_lo_r(31, 24), stbuf_data(i)(31, 24)),
Mux(!stbuf_byteen(i)(3) | store_byteen_hi_r(3), io.store_datafn_hi_r(31, 24), stbuf_data(i)(31, 24))).asUInt).reverse
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i=>Cat(datain4(i), datain3(i), datain2(i), datain1(i)))
// io.testout := datain3
for (i<- 0 until LSU_STBUF_DEPTH) {
withClock(io.lsu_free_c2_clk){ stbuf_vld(i) := RegEnable(1.U & !stbuf_reset(i), 0.U, stbuf_wr_en(i))}
withClock(io.lsu_free_c2_clk){ stbuf_dma_kill(i) := RegEnable(1.U & !stbuf_reset(i), 0.U, stbuf_dma_kill_en(i).asBool)}
stbuf_addr(i) := RegEnable(stbuf_addrin(i), 0.U, stbuf_wr_en(i))
withClock(io.lsu_stbuf_c1_clk){ stbuf_byteen(i) := RegEnable( stbuf_byteenin(i) & Fill(stbuf_byteenin(i).getWidth, !stbuf_reset(i)), 0.U, stbuf_wr_en(i))}
stbuf_data(i) := RegEnable(stbuf_datain(i), 0.U, stbuf_wr_en(i))
} }
println(chisel3.Driver.emitVerilog(new el2_lsu_stbuf)) withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)}
withClock(io.lsu_c1_r_clk){ldst_dual_r := RegNext(ldst_dual_m,0.U)}
// Store Buffer drain logic
io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr)
io.stbuf_reqvld_any := stbuf_vld(RdPtr) & !stbuf_dma_kill(RdPtr) & !stbuf_dma_kill_en.orR
io.stbuf_addr_any := stbuf_addr(RdPtr)
io.stbuf_data_any := stbuf_data(RdPtr)
val WrPtrEn = ((io.ldst_stbuf_reqvld_r & !dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)) |
(io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r & store_coalesce_lo_r))).asBool
val NxtWrPtr = Mux((io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)).asBool, WrPtrPlus2, WrPtrPlus1)
val RdPtrEn = io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any
val NxtRdPtr = RdPtrPlus1
val stbuf_numvld_any = VecInit.tabulate(LSU_STBUF_DEPTH)(i=>Cat(0.U(3.W), stbuf_vld(i))).reduce (_+_)
val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.addr_in_dccm_m & !io.lsu_pkt_m.dma
val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_dccm_r & !io.lsu_pkt_r.dma
stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m)
stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r)
val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r)
io.lsu_stbuf_full_any := Mux((!ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,stbuf_specvld_any >= LSU_STBUF_DEPTH.U,stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U)
io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U
val cmpen_hi_m = io.lsu_cmpen_m & ldst_dual_m
cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))
val cmpen_lo_m = io.lsu_cmpen_m
cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))
val stbuf_match_hi = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH)) === cmpaddr_hi_m(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
val stbuf_match_lo = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH)) === cmpaddr_lo_m(LSU_SB_BITS-1,log2Ceil(LSU_STBUF_DEPTH))) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.dma & io.lsu_pkt_m.store).asUInt).reverse.reduce(Cat(_,_))
val stbuf_fwdbyteenvec_hi = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_hi(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt()).reverse.reduce(Cat(_,_)))
val stbuf_fwdbyteenvec_lo = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_lo(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt()).reverse.reduce(Cat(_,_)))
val stbuf_fwdbyteen_hi_pre_m = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_fwdbyteenvec_hi(i)(j).asUInt()).reverse.reduce(_|_))
val stbuf_fwdbyteen_lo_pre_m = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_fwdbyteenvec_lo(i)(j).asUInt()).reverse.reduce(_|_))
val stbuf_fwddata_hi_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_hi(i)) & stbuf_data(i)).reduce(_|_)
val stbuf_fwddata_lo_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_lo(i)) & stbuf_data(i)).reduce(_|_)
ldst_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
val ldst_byteen_hi_r = ldst_byteen_ext_r(7,4)
val ldst_byteen_lo_r = ldst_byteen_ext_r(3,0)
val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
ld_byte_rhit_lo_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
ld_byte_rhit_lo_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
ld_byte_rhit_hi_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_))
ld_byte_rhit_hi_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_))
ld_byte_rhit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_))
ld_byte_rhit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_))
val fwdpipe1_lo = (Fill(8, ld_byte_rhit_lo_lo(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_lo(0)) & io.store_data_hi_r(7,0))
val fwdpipe2_lo = (Fill(8, ld_byte_rhit_lo_lo(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_lo(1)) & io.store_data_hi_r(15,8))
val fwdpipe3_lo = (Fill(8, ld_byte_rhit_lo_lo(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_lo(2)) & io.store_data_hi_r(23,16))
val fwdpipe4_lo = (Fill(8, ld_byte_rhit_lo_lo(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_lo(3)) & io.store_data_hi_r(31,8))
ld_fwddata_rpipe_lo := Cat(fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo)
val fwdpipe1_hi = (Fill(8, ld_byte_rhit_lo_hi(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_hi(0)) & io.store_data_hi_r(7,0))
val fwdpipe2_hi = (Fill(8, ld_byte_rhit_lo_hi(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_hi(1)) & io.store_data_hi_r(15,8))
val fwdpipe3_hi = (Fill(8, ld_byte_rhit_lo_hi(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_hi(2)) & io.store_data_hi_r(23,16))
val fwdpipe4_hi = (Fill(8, ld_byte_rhit_lo_hi(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_hi(3)) & io.store_data_hi_r(31,8))
ld_fwddata_rpipe_hi := Cat(fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi)
io.stbuf_fwdbyteen_hi_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_hi(i) | stbuf_fwdbyteen_hi_pre_m(i)).asUInt).reverse.reduce(Cat(_,_))
io.stbuf_fwdbyteen_lo_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_lo(i) | stbuf_fwdbyteen_lo_pre_m(i)).asUInt).reverse.reduce(Cat(_,_))
// Pipe vs Store Queue priority
val stbuf_fwdpipe1_lo = Mux(ld_byte_rhit_lo(0),ld_fwddata_rpipe_lo(7,0),stbuf_fwddata_lo_pre_m(7,0))
val stbuf_fwdpipe2_lo = Mux(ld_byte_rhit_lo(1),ld_fwddata_rpipe_lo(15,8),stbuf_fwddata_lo_pre_m(15,8))
val stbuf_fwdpipe3_lo = Mux(ld_byte_rhit_lo(2),ld_fwddata_rpipe_lo(23,16),stbuf_fwddata_lo_pre_m(23,16))
val stbuf_fwdpipe4_lo = Mux(ld_byte_rhit_lo(3),ld_fwddata_rpipe_lo(31,24),stbuf_fwddata_lo_pre_m(31,24))
io.stbuf_fwddata_lo_m := Cat(stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo,stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo)
// Pipe vs Store Queue priority
val stbuf_fwdpipe1_hi = Mux(ld_byte_rhit_hi(0),ld_fwddata_rpipe_hi(7,0),stbuf_fwddata_hi_pre_m(7,0))
val stbuf_fwdpipe2_hi = Mux(ld_byte_rhit_hi(1),ld_fwddata_rpipe_hi(15,8),stbuf_fwddata_hi_pre_m(15,8))
val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
withClock(io.lsu_stbuf_c1_clk){ WrPtr := RegEnable(NxtWrPtr, 0.U, WrPtrEn)}
withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)}
}
object stbmain extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_stbuf()))
}

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src/main/scala/lsu/el2_lsu_trigger.scala
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package lsu package lsu
// HEY
import chisel3._ import chisel3._
import lib._ import lib._
import chisel3.util._ import chisel3.util._

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