Read fixed
This commit is contained in:
waleed-lm
parent
5862a40dcd
commit
2a45774194
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@ -135,7 +135,6 @@ circuit el2_ifu_iccm_mem :
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read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28]
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wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19]
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node _T_93 = bits(write_vec[0], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_93 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_94 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:69]
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@ -156,446 +155,470 @@ circuit el2_ifu_iccm_mem :
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infer mport _T_100 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_100[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_101 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15]
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node _T_102 = mux(_T_101, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_103 = iccm_mem[UInt<1>("h00")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_104 = bits(addr_bank_0, 1, 0)
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node _T_105 = and(_T_102, _T_103[_T_104]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_106 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15]
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node _T_107 = mux(_T_106, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_108 = iccm_mem[UInt<1>("h01")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_109 = bits(addr_bank_1, 1, 0)
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node _T_110 = and(_T_107, _T_108[_T_109]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_111 = bits(read_enable[2], 0, 0) @[Bitwise.scala 72:15]
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node _T_112 = mux(_T_111, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_113 = iccm_mem[UInt<2>("h02")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_114 = bits(addr_bank_2, 1, 0)
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node _T_115 = and(_T_112, _T_113[_T_114]) @[el2_ifu_iccm_mem.scala 51:67]
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node _T_116 = bits(read_enable[3], 0, 0) @[Bitwise.scala 72:15]
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node _T_117 = mux(_T_116, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_118 = iccm_mem[UInt<2>("h03")], clock @[el2_ifu_iccm_mem.scala 51:77]
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node _T_119 = bits(addr_bank_3, 1, 0)
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node _T_120 = and(_T_117, _T_118[_T_119]) @[el2_ifu_iccm_mem.scala 51:67]
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inter[0] <= _T_105 @[el2_ifu_iccm_mem.scala 51:9]
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inter[1] <= _T_110 @[el2_ifu_iccm_mem.scala 51:9]
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inter[2] <= _T_115 @[el2_ifu_iccm_mem.scala 51:9]
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inter[3] <= _T_120 @[el2_ifu_iccm_mem.scala 51:9]
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reg _T_121 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_121 <= inter[0] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[0] <= _T_121 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_122 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_122 <= inter[1] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[1] <= _T_122 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_123 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_123 <= inter[2] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[2] <= _T_123 @[el2_ifu_iccm_mem.scala 52:52]
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reg _T_124 : UInt, clock @[el2_ifu_iccm_mem.scala 52:62]
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_T_124 <= inter[3] @[el2_ifu_iccm_mem.scala 52:62]
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iccm_bank_dout[3] <= _T_124 @[el2_ifu_iccm_mem.scala 52:52]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 54:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 54:21]
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infer mport _T_101 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 51:68]
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wire _T_102 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115]
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_T_102[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_102[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_102[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_102[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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reg _T_103 : UInt<39>[4], clock with : (reset => (reset, _T_102)) @[el2_ifu_iccm_mem.scala 51:59]
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_T_103[0] <= _T_101[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_103[1] <= _T_101[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_103[2] <= _T_101[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_103[3] <= _T_101[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_103[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_103[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_103[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_103[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_104 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 51:68]
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wire _T_105 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115]
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_T_105[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_105[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_105[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_105[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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reg _T_106 : UInt<39>[4], clock with : (reset => (reset, _T_105)) @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[0] <= _T_104[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[1] <= _T_104[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[2] <= _T_104[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[3] <= _T_104[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_106[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_106[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_106[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_106[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_107 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 51:68]
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wire _T_108 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115]
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_T_108[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_108[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_108[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_108[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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reg _T_109 : UInt<39>[4], clock with : (reset => (reset, _T_108)) @[el2_ifu_iccm_mem.scala 51:59]
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_T_109[0] <= _T_107[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_109[1] <= _T_107[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_109[2] <= _T_107[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_109[3] <= _T_107[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_109[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_109[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_109[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_109[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_110 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 51:68]
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wire _T_111 : UInt<1>[4] @[el2_ifu_iccm_mem.scala 51:115]
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_T_111[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_111[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_111[2] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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_T_111[3] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:115]
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reg _T_112 : UInt<39>[4], clock with : (reset => (reset, _T_111)) @[el2_ifu_iccm_mem.scala 51:59]
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_T_112[0] <= _T_110[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_112[1] <= _T_110[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_112[2] <= _T_110[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_112[3] <= _T_110[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_112[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_112[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_112[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_112[3] @[el2_ifu_iccm_mem.scala 51:49]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 56:21]
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wire redundant_valid : UInt<2>
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redundant_valid <= UInt<1>("h00")
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 60:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:21]
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node _T_125 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_126 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_127 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_128 = eq(_T_126, _T_127) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_129 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_131 = and(_T_128, _T_130) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_132 = and(_T_125, _T_131) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_133 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_136 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_137 = eq(_T_136, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_139 = or(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_140 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_141 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_142 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_143 = eq(_T_141, _T_142) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_144 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_145 = eq(_T_144, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_146 = and(_T_143, _T_145) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_147 = and(_T_140, _T_146) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_148 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_151 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_152 = eq(_T_151, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_154 = or(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_155 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_156 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_157 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_158 = eq(_T_156, _T_157) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_159 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_160 = eq(_T_159, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_161 = and(_T_158, _T_160) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_162 = and(_T_155, _T_161) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_163 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_164 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_165 = eq(_T_163, _T_164) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_166 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_167 = eq(_T_166, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_168 = and(_T_165, _T_167) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_169 = or(_T_162, _T_168) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_170 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 63:67]
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node _T_171 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
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node _T_172 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
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node _T_173 = eq(_T_171, _T_172) @[el2_ifu_iccm_mem.scala 63:105]
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node _T_174 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
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node _T_175 = eq(_T_174, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 63:169]
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node _T_176 = and(_T_173, _T_175) @[el2_ifu_iccm_mem.scala 63:145]
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node _T_177 = and(_T_170, _T_176) @[el2_ifu_iccm_mem.scala 63:71]
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node _T_178 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
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node _T_179 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
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node _T_180 = eq(_T_178, _T_179) @[el2_ifu_iccm_mem.scala 64:37]
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node _T_181 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
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node _T_182 = eq(_T_181, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 64:99]
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node _T_183 = and(_T_180, _T_182) @[el2_ifu_iccm_mem.scala 64:77]
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node _T_184 = or(_T_177, _T_183) @[el2_ifu_iccm_mem.scala 63:179]
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node _T_185 = cat(_T_184, _T_169) @[Cat.scala 29:58]
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node _T_186 = cat(_T_185, _T_154) @[Cat.scala 29:58]
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node sel_red1 = cat(_T_186, _T_139) @[Cat.scala 29:58]
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node _T_187 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_188 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_189 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_190 = eq(_T_188, _T_189) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_191 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_193 = and(_T_190, _T_192) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_194 = and(_T_187, _T_193) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_195 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_198 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_201 = or(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_202 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_203 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_204 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_205 = eq(_T_203, _T_204) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_206 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_207 = eq(_T_206, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_208 = and(_T_205, _T_207) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_209 = and(_T_202, _T_208) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_210 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_213 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_216 = or(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_217 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_218 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_219 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_220 = eq(_T_218, _T_219) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_221 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_222 = eq(_T_221, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_223 = and(_T_220, _T_222) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_224 = and(_T_217, _T_223) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_225 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_226 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_227 = eq(_T_225, _T_226) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_228 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_229 = eq(_T_228, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_231 = or(_T_224, _T_230) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_232 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_233 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_234 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_235 = eq(_T_233, _T_234) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_236 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_237 = eq(_T_236, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_238 = and(_T_235, _T_237) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_239 = and(_T_232, _T_238) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_240 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_241 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_242 = eq(_T_240, _T_241) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_243 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_244 = eq(_T_243, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_246 = or(_T_239, _T_245) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_247 = cat(_T_246, _T_231) @[Cat.scala 29:58]
|
||||
node _T_248 = cat(_T_247, _T_216) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_248, _T_201) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 68:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 68:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 69:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 69:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 70:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 71:18]
|
||||
node _T_249 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_251 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 74:47]
|
||||
node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
||||
node _T_253 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_254 = not(_T_253) @[el2_ifu_iccm_mem.scala 75:36]
|
||||
node _T_255 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:64]
|
||||
node _T_256 = not(_T_255) @[el2_ifu_iccm_mem.scala 75:53]
|
||||
node _T_257 = and(_T_254, _T_256) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_258 = bits(_T_257, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
||||
node _T_259 = mux(_T_250, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_260 = mux(_T_252, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_261 = mux(_T_258, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_262 = or(_T_259, _T_260) @[Mux.scala 27:72]
|
||||
node _T_263 = or(_T_262, _T_261) @[Mux.scala 27:72]
|
||||
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 62:31]
|
||||
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
|
||||
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
|
||||
node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58]
|
||||
node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58]
|
||||
node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58]
|
||||
node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58]
|
||||
node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 70:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 70:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 71:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 71:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 72:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
|
||||
node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
|
||||
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_263 @[Mux.scala 27:72]
|
||||
node _T_264 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_266 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 74:47]
|
||||
node _T_267 = bits(_T_266, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
||||
node _T_268 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_269 = not(_T_268) @[el2_ifu_iccm_mem.scala 75:36]
|
||||
node _T_270 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:64]
|
||||
node _T_271 = not(_T_270) @[el2_ifu_iccm_mem.scala 75:53]
|
||||
node _T_272 = and(_T_269, _T_271) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
||||
node _T_274 = mux(_T_265, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_275 = mux(_T_267, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_276 = mux(_T_273, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_277 = or(_T_274, _T_275) @[Mux.scala 27:72]
|
||||
node _T_278 = or(_T_277, _T_276) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72]
|
||||
node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72]
|
||||
node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_278 @[Mux.scala 27:72]
|
||||
node _T_279 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_281 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 74:47]
|
||||
node _T_282 = bits(_T_281, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
||||
node _T_283 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_284 = not(_T_283) @[el2_ifu_iccm_mem.scala 75:36]
|
||||
node _T_285 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:64]
|
||||
node _T_286 = not(_T_285) @[el2_ifu_iccm_mem.scala 75:53]
|
||||
node _T_287 = and(_T_284, _T_286) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_288 = bits(_T_287, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
||||
node _T_289 = mux(_T_280, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_290 = mux(_T_282, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_291 = mux(_T_288, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_292 = or(_T_289, _T_290) @[Mux.scala 27:72]
|
||||
node _T_293 = or(_T_292, _T_291) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72]
|
||||
node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72]
|
||||
node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_293 @[Mux.scala 27:72]
|
||||
node _T_294 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_295 = bits(_T_294, 0, 0) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_296 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 74:47]
|
||||
node _T_297 = bits(_T_296, 0, 0) @[el2_ifu_iccm_mem.scala 74:51]
|
||||
node _T_298 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_299 = not(_T_298) @[el2_ifu_iccm_mem.scala 75:36]
|
||||
node _T_300 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:64]
|
||||
node _T_301 = not(_T_300) @[el2_ifu_iccm_mem.scala 75:53]
|
||||
node _T_302 = and(_T_299, _T_301) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_303 = bits(_T_302, 0, 0) @[el2_ifu_iccm_mem.scala 75:69]
|
||||
node _T_304 = mux(_T_295, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_305 = mux(_T_297, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_306 = mux(_T_303, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_307 = or(_T_304, _T_305) @[Mux.scala 27:72]
|
||||
node _T_308 = or(_T_307, _T_306) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72]
|
||||
node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_295 = or(_T_292, _T_293) @[Mux.scala 27:72]
|
||||
node _T_296 = or(_T_295, _T_294) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_308 @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72]
|
||||
wire redundant_lru : UInt<1>
|
||||
redundant_lru <= UInt<1>("h00")
|
||||
node _T_309 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 77:20]
|
||||
node r0_addr_en = and(_T_309, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 77:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:35]
|
||||
node _T_310 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 79:63]
|
||||
node _T_311 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 79:78]
|
||||
node _T_312 = or(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 79:67]
|
||||
node _T_313 = and(_T_312, io.iccm_rden) @[el2_ifu_iccm_mem.scala 79:83]
|
||||
node _T_314 = and(_T_313, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 79:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_314) @[el2_ifu_iccm_mem.scala 79:50]
|
||||
node _T_315 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:55]
|
||||
node _T_316 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 80:84]
|
||||
node _T_317 = mux(_T_316, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 80:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_315, _T_317) @[el2_ifu_iccm_mem.scala 80:29]
|
||||
reg _T_318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 79:20]
|
||||
node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 79:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 80:35]
|
||||
node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 81:63]
|
||||
node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 81:78]
|
||||
node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 81:67]
|
||||
node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 81:83]
|
||||
node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 81:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 81:50]
|
||||
node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:55]
|
||||
node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 82:84]
|
||||
node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 82:29]
|
||||
reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when redundant_lru_en : @[Reg.scala 28:19]
|
||||
_T_318 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
_T_306 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_lru <= _T_318 @[el2_ifu_iccm_mem.scala 81:17]
|
||||
node _T_319 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 82:52]
|
||||
reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 83:17]
|
||||
node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 84:52]
|
||||
reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_320 <= _T_319 @[Reg.scala 28:23]
|
||||
_T_308 <= _T_307 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[0] <= _T_320 @[el2_ifu_iccm_mem.scala 82:24]
|
||||
node _T_321 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 83:52]
|
||||
node _T_322 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 83:85]
|
||||
reg _T_323 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_322 : @[Reg.scala 28:19]
|
||||
_T_323 <= _T_321 @[Reg.scala 28:23]
|
||||
redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 84:24]
|
||||
node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 85:52]
|
||||
node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 85:85]
|
||||
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_310 : @[Reg.scala 28:19]
|
||||
_T_311 <= _T_309 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[1] <= _T_323 @[el2_ifu_iccm_mem.scala 83:24]
|
||||
node _T_324 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:57]
|
||||
reg _T_325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_324 : @[Reg.scala 28:19]
|
||||
_T_325 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 85:24]
|
||||
node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 86:57]
|
||||
reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_312 : @[Reg.scala 28:19]
|
||||
_T_313 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
reg _T_326 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_326 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
_T_314 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_327 = cat(_T_325, _T_326) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_327 @[el2_ifu_iccm_mem.scala 84:19]
|
||||
node _T_328 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45]
|
||||
node _T_329 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 86:85]
|
||||
node _T_330 = eq(_T_328, _T_329) @[el2_ifu_iccm_mem.scala 86:61]
|
||||
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22]
|
||||
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:48]
|
||||
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 87:26]
|
||||
node _T_334 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70]
|
||||
node _T_335 = eq(_T_334, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75]
|
||||
node _T_336 = or(_T_333, _T_335) @[el2_ifu_iccm_mem.scala 87:52]
|
||||
node _T_337 = and(_T_330, _T_336) @[el2_ifu_iccm_mem.scala 86:102]
|
||||
node _T_338 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 87:101]
|
||||
node _T_339 = and(_T_337, _T_338) @[el2_ifu_iccm_mem.scala 87:84]
|
||||
node _T_340 = and(_T_339, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105]
|
||||
node _T_341 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6]
|
||||
node _T_342 = and(_T_341, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21]
|
||||
node redundant_data0_en = or(_T_340, _T_342) @[el2_ifu_iccm_mem.scala 87:121]
|
||||
node _T_343 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49]
|
||||
node _T_344 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:73]
|
||||
node _T_345 = and(_T_343, _T_344) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
node _T_346 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:100]
|
||||
node _T_347 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122]
|
||||
node _T_348 = eq(_T_347, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127]
|
||||
node _T_349 = and(_T_346, _T_348) @[el2_ifu_iccm_mem.scala 89:104]
|
||||
node _T_350 = or(_T_345, _T_349) @[el2_ifu_iccm_mem.scala 89:78]
|
||||
node _T_351 = bits(_T_350, 0, 0) @[el2_ifu_iccm_mem.scala 89:137]
|
||||
node _T_352 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20]
|
||||
node _T_353 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44]
|
||||
node redundant_data0_in = mux(_T_351, _T_352, _T_353) @[el2_ifu_iccm_mem.scala 89:31]
|
||||
node _T_354 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78]
|
||||
reg _T_355 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_354 : @[Reg.scala 28:19]
|
||||
_T_355 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 86:19]
|
||||
node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 88:45]
|
||||
node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 88:85]
|
||||
node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 88:61]
|
||||
node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:22]
|
||||
node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:48]
|
||||
node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 89:26]
|
||||
node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:70]
|
||||
node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:75]
|
||||
node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 88:102]
|
||||
node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 89:101]
|
||||
node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 89:84]
|
||||
node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 89:105]
|
||||
node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 90:6]
|
||||
node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 90:21]
|
||||
node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 89:121]
|
||||
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 91:49]
|
||||
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:73]
|
||||
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 91:52]
|
||||
node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:100]
|
||||
node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 91:122]
|
||||
node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 91:127]
|
||||
node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 91:104]
|
||||
node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 91:78]
|
||||
node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 91:137]
|
||||
node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 92:20]
|
||||
node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 92:44]
|
||||
node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 91:31]
|
||||
node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 93:78]
|
||||
reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_342 : @[Reg.scala 28:19]
|
||||
_T_343 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[0] <= _T_355 @[el2_ifu_iccm_mem.scala 91:21]
|
||||
node _T_356 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45]
|
||||
node _T_357 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 93:85]
|
||||
node _T_358 = eq(_T_356, _T_357) @[el2_ifu_iccm_mem.scala 93:61]
|
||||
node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22]
|
||||
node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:48]
|
||||
node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 94:26]
|
||||
node _T_362 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70]
|
||||
node _T_363 = eq(_T_362, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75]
|
||||
node _T_364 = or(_T_361, _T_363) @[el2_ifu_iccm_mem.scala 94:52]
|
||||
node _T_365 = and(_T_358, _T_364) @[el2_ifu_iccm_mem.scala 93:102]
|
||||
node _T_366 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 94:101]
|
||||
node _T_367 = and(_T_365, _T_366) @[el2_ifu_iccm_mem.scala 94:84]
|
||||
node _T_368 = and(_T_367, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105]
|
||||
node _T_369 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6]
|
||||
node _T_370 = and(_T_369, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21]
|
||||
node redundant_data1_en = or(_T_368, _T_370) @[el2_ifu_iccm_mem.scala 94:121]
|
||||
node _T_371 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49]
|
||||
node _T_372 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:73]
|
||||
node _T_373 = and(_T_371, _T_372) @[el2_ifu_iccm_mem.scala 96:52]
|
||||
node _T_374 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:100]
|
||||
node _T_375 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122]
|
||||
node _T_376 = eq(_T_375, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127]
|
||||
node _T_377 = and(_T_374, _T_376) @[el2_ifu_iccm_mem.scala 96:104]
|
||||
node _T_378 = or(_T_373, _T_377) @[el2_ifu_iccm_mem.scala 96:78]
|
||||
node _T_379 = bits(_T_378, 0, 0) @[el2_ifu_iccm_mem.scala 96:137]
|
||||
node _T_380 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20]
|
||||
node _T_381 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44]
|
||||
node redundant_data1_in = mux(_T_379, _T_380, _T_381) @[el2_ifu_iccm_mem.scala 96:31]
|
||||
node _T_382 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78]
|
||||
reg _T_383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_382 : @[Reg.scala 28:19]
|
||||
_T_383 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 93:21]
|
||||
node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 95:45]
|
||||
node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 95:85]
|
||||
node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 95:61]
|
||||
node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:22]
|
||||
node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:48]
|
||||
node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 96:26]
|
||||
node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:70]
|
||||
node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:75]
|
||||
node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 96:52]
|
||||
node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 95:102]
|
||||
node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 96:101]
|
||||
node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 96:84]
|
||||
node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 96:105]
|
||||
node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:6]
|
||||
node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 97:21]
|
||||
node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 96:121]
|
||||
node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 98:49]
|
||||
node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:73]
|
||||
node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 98:52]
|
||||
node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:100]
|
||||
node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 98:122]
|
||||
node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 98:127]
|
||||
node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 98:104]
|
||||
node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 98:78]
|
||||
node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 98:137]
|
||||
node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 99:20]
|
||||
node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 99:44]
|
||||
node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 98:31]
|
||||
node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 100:78]
|
||||
reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_370 : @[Reg.scala 28:19]
|
||||
_T_371 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[1] <= _T_383 @[el2_ifu_iccm_mem.scala 98:21]
|
||||
node _T_384 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 100:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 100:34]
|
||||
iccm_rd_addr_lo_q <= _T_384 @[el2_ifu_iccm_mem.scala 100:34]
|
||||
node _T_385 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 101:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 101:34]
|
||||
iccm_rd_addr_hi_q <= _T_385 @[el2_ifu_iccm_mem.scala 101:34]
|
||||
node _T_386 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 103:86]
|
||||
node _T_387 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
|
||||
node _T_388 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 103:86]
|
||||
node _T_389 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
|
||||
node _T_390 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 103:86]
|
||||
node _T_391 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
|
||||
node _T_392 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:86]
|
||||
node _T_393 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 103:115]
|
||||
node _T_394 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_395 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_396 = mux(_T_390, _T_391, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_397 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_398 = or(_T_394, _T_395) @[Mux.scala 27:72]
|
||||
node _T_399 = or(_T_398, _T_396) @[Mux.scala 27:72]
|
||||
node _T_400 = or(_T_399, _T_397) @[Mux.scala 27:72]
|
||||
wire _T_401 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_401 <= _T_400 @[Mux.scala 27:72]
|
||||
node _T_402 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
|
||||
node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 104:77]
|
||||
node _T_404 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
|
||||
node _T_405 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
|
||||
node _T_406 = eq(_T_405, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 104:77]
|
||||
node _T_407 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
|
||||
node _T_408 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
|
||||
node _T_409 = eq(_T_408, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 104:77]
|
||||
node _T_410 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
|
||||
node _T_411 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 104:59]
|
||||
node _T_412 = eq(_T_411, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 104:77]
|
||||
node _T_413 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 104:106]
|
||||
node _T_414 = mux(_T_403, _T_404, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_415 = mux(_T_406, _T_407, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_416 = mux(_T_409, _T_410, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_417 = mux(_T_412, _T_413, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_418 = or(_T_414, _T_415) @[Mux.scala 27:72]
|
||||
node _T_419 = or(_T_418, _T_416) @[Mux.scala 27:72]
|
||||
node _T_420 = or(_T_419, _T_417) @[Mux.scala 27:72]
|
||||
wire _T_421 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_421 <= _T_420 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_401, _T_421) @[Cat.scala 29:58]
|
||||
node _T_422 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 105:43]
|
||||
node _T_423 = bits(_T_422, 0, 0) @[el2_ifu_iccm_mem.scala 105:53]
|
||||
node _T_424 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_425 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 105:89]
|
||||
node _T_426 = cat(_T_424, _T_425) @[Cat.scala 29:58]
|
||||
node _T_427 = mux(_T_423, _T_426, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 105:25]
|
||||
io.iccm_rd_data <= _T_427 @[el2_ifu_iccm_mem.scala 105:19]
|
||||
node _T_428 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:85]
|
||||
node _T_429 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:85]
|
||||
node _T_430 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:85]
|
||||
node _T_431 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:85]
|
||||
node _T_432 = mux(_T_428, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_433 = mux(_T_429, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_434 = mux(_T_430, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_435 = mux(_T_431, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_436 = or(_T_432, _T_433) @[Mux.scala 27:72]
|
||||
node _T_437 = or(_T_436, _T_434) @[Mux.scala 27:72]
|
||||
node _T_438 = or(_T_437, _T_435) @[Mux.scala 27:72]
|
||||
wire _T_439 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_439 <= _T_438 @[Mux.scala 27:72]
|
||||
node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
|
||||
node _T_441 = eq(_T_440, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 107:79]
|
||||
node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
|
||||
node _T_443 = eq(_T_442, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 107:79]
|
||||
node _T_444 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
|
||||
node _T_445 = eq(_T_444, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 107:79]
|
||||
node _T_446 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 107:61]
|
||||
node _T_447 = eq(_T_446, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 107:79]
|
||||
node _T_448 = mux(_T_441, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_449 = mux(_T_443, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_450 = mux(_T_445, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_451 = mux(_T_447, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_452 = or(_T_448, _T_449) @[Mux.scala 27:72]
|
||||
node _T_453 = or(_T_452, _T_450) @[Mux.scala 27:72]
|
||||
node _T_454 = or(_T_453, _T_451) @[Mux.scala 27:72]
|
||||
wire _T_455 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_455 <= _T_454 @[Mux.scala 27:72]
|
||||
node _T_456 = cat(_T_439, _T_455) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_456 @[el2_ifu_iccm_mem.scala 106:23]
|
||||
redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
|
||||
node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
|
||||
iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34]
|
||||
node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
|
||||
iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 103:34]
|
||||
node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_385 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_386 = or(_T_382, _T_383) @[Mux.scala 27:72]
|
||||
node _T_387 = or(_T_386, _T_384) @[Mux.scala 27:72]
|
||||
node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72]
|
||||
wire _T_389 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_389 <= _T_388 @[Mux.scala 27:72]
|
||||
node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_405 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_406 = or(_T_402, _T_403) @[Mux.scala 27:72]
|
||||
node _T_407 = or(_T_406, _T_404) @[Mux.scala 27:72]
|
||||
node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72]
|
||||
wire _T_409 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_409 <= _T_408 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58]
|
||||
node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 107:43]
|
||||
node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 107:53]
|
||||
node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 107:89]
|
||||
node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
|
||||
node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 107:25]
|
||||
io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 107:19]
|
||||
node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_423 = mux(_T_419, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_424 = or(_T_420, _T_421) @[Mux.scala 27:72]
|
||||
node _T_425 = or(_T_424, _T_422) @[Mux.scala 27:72]
|
||||
node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
|
||||
wire _T_427 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_427 <= _T_426 @[Mux.scala 27:72]
|
||||
node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_439 = mux(_T_435, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_440 = or(_T_436, _T_437) @[Mux.scala 27:72]
|
||||
node _T_441 = or(_T_440, _T_438) @[Mux.scala 27:72]
|
||||
node _T_442 = or(_T_441, _T_439) @[Mux.scala 27:72]
|
||||
wire _T_443 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_443 <= _T_442 @[Mux.scala 27:72]
|
||||
node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 108:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -41,14 +41,14 @@ module el2_ifu_iccm_mem(
|
|||
reg [31:0] _RAND_18;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_110_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_110_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -66,14 +66,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_0__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_110_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_110_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -91,14 +91,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_1__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_110_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_110_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -116,14 +116,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_2__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_108_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_108_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_113_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_113_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_118_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_118_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_110_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_110_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -142,8 +142,8 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_3__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
|
||||
wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
|
||||
wire [14:0] _GEN_47 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_47; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
|
||||
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
|
||||
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
|
||||
|
|
@ -179,202 +179,170 @@ module el2_ifu_iccm_mem(
|
|||
wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 36:72]
|
||||
wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
|
||||
wire [11:0] _T_59 = _T_12 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_66 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_73 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_80 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire _T_85 = ~wren_bank_0; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_0 = iccm_clken_0 & _T_85; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_87 = ~wren_bank_1; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_1 = iccm_clken_1 & _T_87; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_89 = ~wren_bank_2; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_2 = iccm_clken_2 & _T_89; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_91 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_3 = iccm_clken_3 & _T_91; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire [38:0] _T_102 = read_enable_0 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_24 = iccm_mem_0__T_103_data; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_25 = 2'h1 == addr_bank_0[1:0] ? iccm_mem_1__T_103_data : _GEN_24; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_26 = 2'h2 == addr_bank_0[1:0] ? iccm_mem_2__T_103_data : _GEN_25; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_27 = 2'h3 == addr_bank_0[1:0] ? iccm_mem_3__T_103_data : _GEN_26; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _T_107 = read_enable_1 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_28 = iccm_mem_0__T_108_data; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_29 = 2'h1 == addr_bank_1[1:0] ? iccm_mem_1__T_108_data : _GEN_28; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_30 = 2'h2 == addr_bank_1[1:0] ? iccm_mem_2__T_108_data : _GEN_29; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_31 = 2'h3 == addr_bank_1[1:0] ? iccm_mem_3__T_108_data : _GEN_30; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _T_112 = read_enable_2 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_32 = iccm_mem_0__T_113_data; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_33 = 2'h1 == addr_bank_2[1:0] ? iccm_mem_1__T_113_data : _GEN_32; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_34 = 2'h2 == addr_bank_2[1:0] ? iccm_mem_2__T_113_data : _GEN_33; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_35 = 2'h3 == addr_bank_2[1:0] ? iccm_mem_3__T_113_data : _GEN_34; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _T_117 = read_enable_3 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_36 = iccm_mem_0__T_118_data; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_37 = 2'h1 == addr_bank_3[1:0] ? iccm_mem_1__T_118_data : _GEN_36; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_38 = 2'h2 == addr_bank_3[1:0] ? iccm_mem_2__T_118_data : _GEN_37; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
wire [38:0] _GEN_39 = 2'h3 == addr_bank_3[1:0] ? iccm_mem_3__T_118_data : _GEN_38; // @[el2_ifu_iccm_mem.scala 51:67]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 52:62]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 52:62]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 52:62]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 52:62]
|
||||
reg _T_325; // @[Reg.scala 27:20]
|
||||
reg _T_326; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_325,_T_326}; // @[Cat.scala 29:58]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg _T_313; // @[Reg.scala 27:20]
|
||||
reg _T_314; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
|
||||
wire _T_128 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 63:105]
|
||||
wire _T_131 = _T_128 & _T_10; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_132 = redundant_valid[1] & _T_131; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_135 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 64:37]
|
||||
wire _T_138 = _T_135 & _T_12; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_139 = _T_132 | _T_138; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_146 = _T_128 & _T_15; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_147 = redundant_valid[1] & _T_146; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_153 = _T_135 & _T_17; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_154 = _T_147 | _T_153; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_161 = _T_128 & _T_20; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_162 = redundant_valid[1] & _T_161; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_168 = _T_135 & _T_22; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_169 = _T_162 | _T_168; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_176 = _T_128 & _T_25; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_177 = redundant_valid[1] & _T_176; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_183 = _T_135 & _T_27; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_184 = _T_177 | _T_183; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire [3:0] sel_red1 = {_T_184,_T_169,_T_154,_T_139}; // @[Cat.scala 29:58]
|
||||
wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 65:105]
|
||||
wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 66:37]
|
||||
wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
|
||||
wire _T_190 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 65:105]
|
||||
wire _T_193 = _T_190 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_194 = redundant_valid[0] & _T_193; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_197 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 66:37]
|
||||
wire _T_200 = _T_197 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_201 = _T_194 | _T_200; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_208 = _T_190 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_209 = redundant_valid[0] & _T_208; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_215 = _T_197 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_216 = _T_209 | _T_215; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_223 = _T_190 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_224 = redundant_valid[0] & _T_223; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_230 = _T_197 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_231 = _T_224 | _T_230; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_238 = _T_190 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_239 = redundant_valid[0] & _T_238; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_245 = _T_197 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_246 = _T_239 | _T_245; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire [3:0] sel_red0 = {_T_246,_T_231,_T_216,_T_201}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 68:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 69:27]
|
||||
wire _T_254 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 75:36]
|
||||
wire _T_256 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 75:53]
|
||||
wire _T_257 = _T_254 & _T_256; // @[el2_ifu_iccm_mem.scala 75:51]
|
||||
wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 67:105]
|
||||
wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 68:37]
|
||||
wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 70:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 71:27]
|
||||
wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_259 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_260 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_261 = _T_257 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_262 = _T_259 | _T_260; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_262 | _T_261; // @[Mux.scala 27:72]
|
||||
wire _T_269 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 75:36]
|
||||
wire _T_271 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 75:53]
|
||||
wire _T_272 = _T_269 & _T_271; // @[el2_ifu_iccm_mem.scala 75:51]
|
||||
wire [38:0] _T_274 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_275 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_276 = _T_272 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_277 = _T_274 | _T_275; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_277 | _T_276; // @[Mux.scala 27:72]
|
||||
wire _T_284 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 75:36]
|
||||
wire _T_286 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 75:53]
|
||||
wire _T_287 = _T_284 & _T_286; // @[el2_ifu_iccm_mem.scala 75:51]
|
||||
wire [38:0] _T_289 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_290 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_291 = _T_287 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_292 = _T_289 | _T_290; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_292 | _T_291; // @[Mux.scala 27:72]
|
||||
wire _T_299 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 75:36]
|
||||
wire _T_301 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 75:53]
|
||||
wire _T_302 = _T_299 & _T_301; // @[el2_ifu_iccm_mem.scala 75:51]
|
||||
wire [38:0] _T_304 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_305 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_306 = _T_302 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_307 = _T_304 | _T_305; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_307 | _T_306; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_248 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72]
|
||||
wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72]
|
||||
wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72]
|
||||
wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72]
|
||||
reg redundant_lru; // @[Reg.scala 27:20]
|
||||
wire _T_309 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 77:20]
|
||||
wire r0_addr_en = _T_309 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 77:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 78:35]
|
||||
wire _T_310 = |sel_red0; // @[el2_ifu_iccm_mem.scala 79:63]
|
||||
wire _T_311 = |sel_red1; // @[el2_ifu_iccm_mem.scala 79:78]
|
||||
wire _T_312 = _T_310 | _T_311; // @[el2_ifu_iccm_mem.scala 79:67]
|
||||
wire _T_313 = _T_312 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 79:83]
|
||||
wire _T_314 = _T_313 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 79:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_314; // @[el2_ifu_iccm_mem.scala 79:50]
|
||||
wire _GEN_43 = r1_addr_en | _T_325; // @[Reg.scala 28:19]
|
||||
wire _GEN_44 = r0_addr_en | _T_326; // @[Reg.scala 28:19]
|
||||
wire _T_330 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 86:61]
|
||||
wire _T_333 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 87:26]
|
||||
wire _T_336 = _T_333 | _T_1; // @[el2_ifu_iccm_mem.scala 87:52]
|
||||
wire _T_337 = _T_330 & _T_336; // @[el2_ifu_iccm_mem.scala 86:102]
|
||||
wire _T_339 = _T_337 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 87:84]
|
||||
wire _T_340 = _T_339 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 87:105]
|
||||
wire redundant_data0_en = _T_340 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 87:121]
|
||||
wire _T_349 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 89:104]
|
||||
wire _T_350 = _T_333 | _T_349; // @[el2_ifu_iccm_mem.scala 89:78]
|
||||
wire _T_358 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 93:61]
|
||||
wire _T_361 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 94:26]
|
||||
wire _T_364 = _T_361 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52]
|
||||
wire _T_365 = _T_358 & _T_364; // @[el2_ifu_iccm_mem.scala 93:102]
|
||||
wire _T_367 = _T_365 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 94:84]
|
||||
wire _T_368 = _T_367 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105]
|
||||
wire redundant_data1_en = _T_368 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121]
|
||||
wire _T_377 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104]
|
||||
wire _T_378 = _T_361 | _T_377; // @[el2_ifu_iccm_mem.scala 96:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 100:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 101:34]
|
||||
wire _T_386 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 103:86]
|
||||
wire _T_388 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 103:86]
|
||||
wire _T_390 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 103:86]
|
||||
wire _T_392 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 103:86]
|
||||
wire [31:0] _T_394 = _T_386 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_395 = _T_388 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_396 = _T_390 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_397 = _T_392 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_398 = _T_394 | _T_395; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_399 = _T_398 | _T_396; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_400 = _T_399 | _T_397; // @[Mux.scala 27:72]
|
||||
wire _T_403 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 104:77]
|
||||
wire _T_406 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 104:77]
|
||||
wire _T_409 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 104:77]
|
||||
wire _T_412 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 104:77]
|
||||
wire [31:0] _T_414 = _T_403 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_415 = _T_406 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_416 = _T_409 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_417 = _T_412 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_418 = _T_414 | _T_415; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_419 = _T_418 | _T_416; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_420 = _T_419 | _T_417; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_400,_T_420}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_426 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_432 = _T_386 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_433 = _T_388 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_434 = _T_390 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_435 = _T_392 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_436 = _T_432 | _T_433; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_437 = _T_436 | _T_434; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_438 = _T_437 | _T_435; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_448 = _T_403 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_449 = _T_406 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_450 = _T_409 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_451 = _T_412 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_452 = _T_448 | _T_449; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_453 = _T_452 | _T_450; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_454 = _T_453 | _T_451; // @[Mux.scala 27:72]
|
||||
assign iccm_mem_0__T_103_addr = 12'h0;
|
||||
assign iccm_mem_0__T_103_data = iccm_mem_0[iccm_mem_0__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_108_addr = 12'h1;
|
||||
assign iccm_mem_0__T_108_data = iccm_mem_0[iccm_mem_0__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_113_addr = 12'h2;
|
||||
assign iccm_mem_0__T_113_data = iccm_mem_0[iccm_mem_0__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_118_addr = 12'h3;
|
||||
assign iccm_mem_0__T_118_data = iccm_mem_0[iccm_mem_0__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 79:20]
|
||||
wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 79:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 80:35]
|
||||
wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 81:63]
|
||||
wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 81:78]
|
||||
wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 81:67]
|
||||
wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 81:83]
|
||||
wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 81:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 81:50]
|
||||
wire _GEN_27 = r1_addr_en | _T_313; // @[Reg.scala 28:19]
|
||||
wire _GEN_28 = r0_addr_en | _T_314; // @[Reg.scala 28:19]
|
||||
wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 88:61]
|
||||
wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 89:26]
|
||||
wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 89:52]
|
||||
wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 88:102]
|
||||
wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 89:84]
|
||||
wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 89:105]
|
||||
wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 89:121]
|
||||
wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 91:104]
|
||||
wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 91:78]
|
||||
wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 95:61]
|
||||
wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 96:26]
|
||||
wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 96:52]
|
||||
wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 95:102]
|
||||
wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 96:84]
|
||||
wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 96:105]
|
||||
wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
|
||||
wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
|
||||
wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
|
||||
wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_378 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_380 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire [31:0] _T_382 = _T_374 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_383 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_384 = _T_378 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_385 = _T_380 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
|
||||
wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_405 = _T_400 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_406 = _T_402 | _T_403; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_407 = _T_406 | _T_404; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_408 = _T_407 | _T_405; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_388,_T_408}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_414 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_420 = _T_374 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_421 = _T_376 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_422 = _T_378 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_423 = _T_380 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_424 = _T_420 | _T_421; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_425 = _T_424 | _T_422; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_436 = _T_391 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_437 = _T_394 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_438 = _T_397 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_439 = _T_400 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_440 = _T_436 | _T_437; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_441 = _T_440 | _T_438; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72]
|
||||
assign iccm_mem_0__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_101_data = iccm_mem_0[iccm_mem_0__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_104_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_0__T_104_data = iccm_mem_0[iccm_mem_0__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_107_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_0__T_107_data = iccm_mem_0[iccm_mem_0__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_110_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_0__T_110_data = iccm_mem_0[iccm_mem_0__T_110_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_94_data = io_iccm_wr_data[38:0];
|
||||
assign iccm_mem_0__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_94_mask = 1'h1;
|
||||
|
|
@ -391,14 +359,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_0__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_0__T_100_mask = 1'h0;
|
||||
assign iccm_mem_0__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_1__T_103_addr = 12'h0;
|
||||
assign iccm_mem_1__T_103_data = iccm_mem_1[iccm_mem_1__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_108_addr = 12'h1;
|
||||
assign iccm_mem_1__T_108_data = iccm_mem_1[iccm_mem_1__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_113_addr = 12'h2;
|
||||
assign iccm_mem_1__T_113_data = iccm_mem_1[iccm_mem_1__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_118_addr = 12'h3;
|
||||
assign iccm_mem_1__T_118_data = iccm_mem_1[iccm_mem_1__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_101_data = iccm_mem_1[iccm_mem_1__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_104_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_1__T_104_data = iccm_mem_1[iccm_mem_1__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_107_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_1__T_107_data = iccm_mem_1[iccm_mem_1__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_110_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_1__T_110_data = iccm_mem_1[iccm_mem_1__T_110_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_94_data = 39'h0;
|
||||
assign iccm_mem_1__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_94_mask = 1'h0;
|
||||
|
|
@ -415,14 +383,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_1__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_1__T_100_mask = 1'h0;
|
||||
assign iccm_mem_1__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_2__T_103_addr = 12'h0;
|
||||
assign iccm_mem_2__T_103_data = iccm_mem_2[iccm_mem_2__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_108_addr = 12'h1;
|
||||
assign iccm_mem_2__T_108_data = iccm_mem_2[iccm_mem_2__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_113_addr = 12'h2;
|
||||
assign iccm_mem_2__T_113_data = iccm_mem_2[iccm_mem_2__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_118_addr = 12'h3;
|
||||
assign iccm_mem_2__T_118_data = iccm_mem_2[iccm_mem_2__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_101_data = iccm_mem_2[iccm_mem_2__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_104_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_2__T_104_data = iccm_mem_2[iccm_mem_2__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_107_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_2__T_107_data = iccm_mem_2[iccm_mem_2__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_110_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_2__T_110_data = iccm_mem_2[iccm_mem_2__T_110_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_94_data = 39'h0;
|
||||
assign iccm_mem_2__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_94_mask = 1'h0;
|
||||
|
|
@ -439,14 +407,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_2__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_2__T_100_mask = 1'h0;
|
||||
assign iccm_mem_2__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_3__T_103_addr = 12'h0;
|
||||
assign iccm_mem_3__T_103_data = iccm_mem_3[iccm_mem_3__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_108_addr = 12'h1;
|
||||
assign iccm_mem_3__T_108_data = iccm_mem_3[iccm_mem_3__T_108_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_113_addr = 12'h2;
|
||||
assign iccm_mem_3__T_113_data = iccm_mem_3[iccm_mem_3__T_113_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_118_addr = 12'h3;
|
||||
assign iccm_mem_3__T_118_data = iccm_mem_3[iccm_mem_3__T_118_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_101_data = iccm_mem_3[iccm_mem_3__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_104_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_3__T_104_data = iccm_mem_3[iccm_mem_3__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_107_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_3__T_107_data = iccm_mem_3[iccm_mem_3__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_110_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_3__T_110_data = iccm_mem_3[iccm_mem_3__T_110_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_94_data = 39'h0;
|
||||
assign iccm_mem_3__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_94_mask = 1'h0;
|
||||
|
|
@ -463,12 +431,12 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_3__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_3__T_100_mask = 1'h1;
|
||||
assign iccm_mem_3__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_426 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 105:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_438,_T_454}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 106:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 54:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 54:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 54:21]
|
||||
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 54:21]
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_414 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 107:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_426,_T_442}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 108:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -527,9 +495,9 @@ initial begin
|
|||
_RAND_7 = {2{`RANDOM}};
|
||||
iccm_bank_dout_3 = _RAND_7[38:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
_T_325 = _RAND_8[0:0];
|
||||
_T_313 = _RAND_8[0:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
_T_326 = _RAND_9[0:0];
|
||||
_T_314 = _RAND_9[0:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
redundant_address_1 = _RAND_10[13:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
|
|
@ -604,19 +572,35 @@ end // initial
|
|||
if(iccm_mem_3__T_100_en & iccm_mem_3__T_100_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_100_addr] <= iccm_mem_3__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
iccm_bank_dout_0 <= _T_102 & _GEN_27;
|
||||
iccm_bank_dout_1 <= _T_107 & _GEN_31;
|
||||
iccm_bank_dout_2 <= _T_112 & _GEN_35;
|
||||
iccm_bank_dout_3 <= _T_117 & _GEN_39;
|
||||
if (reset) begin
|
||||
_T_325 <= 1'h0;
|
||||
iccm_bank_dout_0 <= 39'h0;
|
||||
end else begin
|
||||
_T_325 <= _GEN_43;
|
||||
iccm_bank_dout_0 <= iccm_mem_0__T_110_data;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_326 <= 1'h0;
|
||||
iccm_bank_dout_1 <= 39'h0;
|
||||
end else begin
|
||||
_T_326 <= _GEN_44;
|
||||
iccm_bank_dout_1 <= iccm_mem_1__T_110_data;
|
||||
end
|
||||
if (reset) begin
|
||||
iccm_bank_dout_2 <= 39'h0;
|
||||
end else begin
|
||||
iccm_bank_dout_2 <= iccm_mem_2__T_110_data;
|
||||
end
|
||||
if (reset) begin
|
||||
iccm_bank_dout_3 <= 39'h0;
|
||||
end else begin
|
||||
iccm_bank_dout_3 <= iccm_mem_3__T_110_data;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_313 <= 1'h0;
|
||||
end else begin
|
||||
_T_313 <= _GEN_27;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_314 <= 1'h0;
|
||||
end else begin
|
||||
_T_314 <= _GEN_28;
|
||||
end
|
||||
if (reset) begin
|
||||
redundant_address_1 <= 14'h0;
|
||||
|
|
@ -641,7 +625,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_1 <= 39'h0;
|
||||
end else if (redundant_data1_en) begin
|
||||
if (_T_378) begin
|
||||
if (_T_366) begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -650,7 +634,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_0 <= 39'h0;
|
||||
end else if (redundant_data0_en) begin
|
||||
if (_T_350) begin
|
||||
if (_T_338) begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -660,9 +644,9 @@ end // initial
|
|||
redundant_lru <= 1'h0;
|
||||
end else if (redundant_lru_en) begin
|
||||
if (io_iccm_buf_correct_ecc) begin
|
||||
redundant_lru <= _T_309;
|
||||
redundant_lru <= _T_297;
|
||||
end else begin
|
||||
redundant_lru <= _T_310;
|
||||
redundant_lru <= _T_298;
|
||||
end
|
||||
end
|
||||
if (reset) begin
|
||||
|
|
|
|||
|
|
@ -44,12 +44,14 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
|
|||
val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i)))
|
||||
|
||||
val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
//val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
|
||||
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i).asBool){iccm_mem(addr_bank(i))(i) :=iccm_bank_wr_data(i)}
|
||||
|
||||
inter := (0 until ICCM_NUM_BANKS).map(i=>Fill(39,read_enable(i))& iccm_mem(i)(addr_bank(i)))
|
||||
for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout(i) := RegNext(inter(i))
|
||||
for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout := RegNext(iccm_mem(addr_bank(i)),VecInit.tabulate(ICCM_NUM_BANKS)(i=>0.U))
|
||||
//(0 until ICCM_NUM_BANKS).map(i=> )
|
||||
|
||||
// iccm_bank_dout(i) := RegNext(inter(i))
|
||||
|
||||
io.iccm_bank_addr := addr_bank
|
||||
|
||||
|
|
|
|||
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Reference in New Issue