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This commit is contained in:
waleed-lm 2020-12-10 12:31:00 +05:00
parent 0a6000b99d
commit 2a79511a72
105 changed files with 1099 additions and 116830 deletions
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2
.idea/modules/chisel-module-template-build.iml
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, /home/abdulhameed.akram/.ivy2/cache|ivy|Local cache, https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, file:/home/abdulhameed.akram/.sbt/preloaded|maven|local-preloaded, https://repo1.maven.org/maven2/|maven|public" type="SBT_MODULE" version="4"> <module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
<component name="NewModuleRootManager"> <component name="NewModuleRootManager">
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" /> <output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" /> <output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />

2
.idea/modules/chisel-module-template.iml
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="swerv-chislified_withlsu [file:/home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4"> <module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8"> <component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" /> <output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" /> <output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />

6
firrtl_black_box_resource_files.f
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@ -1,3 +1,3 @@
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/gated_latch.v /home/waleedbinehsan/Desktop/Quasar/gated_latch.v
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/dmi_wrapper.sv /home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/mem.sv /home/waleedbinehsan/Desktop/Quasar/mem.sv

367
ifu.anno.json
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@ -1,367 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_wr_size",
"sources":[
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_sz",
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_rden",
"sources":[
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ifu_dec_dec_aln_ifu_pmu_instr_aligned",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_rd_en",
"sources":[
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_mrac_ff",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start",
"sources":[
"~ifu|ifu>io_ic_eccerr",
"~ifu|ifu>io_ic_tag_perr",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_dma_sb_error",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall",
"sources":[
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_wr_data",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_rd_en",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_wr_en",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_addr",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_wr_data",
"sources":[
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_wdata",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_tag_array",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_ready",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_sel_premux_data",
"sources":[
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_premux_data",
"sources":[
"~ifu|ifu>io_iccm_rd_data",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_debug_way",
"sources":[
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_tag_valid",
"sources":[
"~ifu|ifu>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_wren",
"sources":[
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_write",
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err",
"sources":[
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_iccm_rw_addr",
"sources":[
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_mem_addr",
"~ifu|ifu>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable",
"~ifu|ifu>io_iccm_rd_data_ecc",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb",
"~ifu|ifu>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt",
"~ifu|ifu>io_ic_rd_data",
"~ifu|ifu>io_ifu_r_bits_id",
"~ifu|ifu>io_ifu_r_valid",
"~ifu|ifu>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu|ifu>io_ic_rw_addr",
"sources":[
"~ifu|ifu>io_exu_flush_path_final",
"~ifu|ifu>io_exu_flush_final",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu|ifu>io_exu_ifu_exu_bp_exu_i0_br_index_r",
"~ifu|ifu>io_ic_rd_hit",
"~ifu|ifu>io_ifu_dec_dec_bp_dec_tlu_bpred_disable"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ifu.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ifu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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sbt.internal.DslEntry

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338581136 38779017

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23355001 -1413115869

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[debug] "not up to date. inChanged = true, force = false [debug] "not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")... [debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...
[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build") [debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")

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[debug] Copy resource mappings:  [debug] Copy resource mappings:
[debug]   [debug]

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src/main/scala/lib/param.scala
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@ -21,7 +21,7 @@ trait param {
val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_HI = 0x19
val BTB_INDEX3_LO = 0x12 val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200 val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x1 val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x1 val BUILD_AXI4 = 0x1
val BUILD_AXI_NATIVE = 0x1 val BUILD_AXI_NATIVE = 0x1
val BUS_PRTY_DEFAULT = 0x3 val BUS_PRTY_DEFAULT = 0x3

3
src/main/scala/lsu/lsu_bus_buffer.scala
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@ -548,7 +548,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)),
(!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)),
(lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn))
bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable)
bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
(BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) (BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
@ -616,4 +616,3 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
} }

121
src/main/scala/quasar.scala
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@ -289,11 +289,55 @@ class quasar extends Module with RequireAsyncReset with lib {
io.ifu_axi <> ifu.io.ifu io.ifu_axi <> ifu.io.ifu
io.dma_axi <> dma_ctrl.io.dma_axi io.dma_axi <> dma_ctrl.io.dma_axi
// lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
// lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
// lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
// lsu.io.axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp)
// lsu.io.axi.b.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id)
// lsu.io.axi.ar.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready)
// lsu.io.axi.r.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid)
// lsu.io.axi.r.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id)
// lsu.io.axi.r.bits.data := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data)
// lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp)
// lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last)
//
// ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready)
// ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready)
// ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready)
// ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid)
// ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id)
// ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data)
// ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp)
// ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last)
//
// dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready)
// dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready)
// dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid)
// dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp)
// dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready)
// dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid)
// dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id)
// dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data)
// dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp)
//
// dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid)
// dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id)
// dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr)
// dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size)
// dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid)
// dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data)
// dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb)
// dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready)
// dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid)
// dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id)
// dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr)
// dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size)
// dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready)
when(BUILD_AHB_LITE.B) { /*when(BUILD_AHB_LITE.B) {
val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) val lsu_axi4_to_ahb = Module(new axi4_to_ahb())
lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid
lsu_axi4_to_ahb.io.scan_mode := io.scan_mode lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
@ -404,50 +448,7 @@ class quasar extends Module with RequireAsyncReset with lib {
dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata
dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel
dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin
lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
lsu.io.axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp)
lsu.io.axi.b.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id)
lsu.io.axi.ar.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready)
lsu.io.axi.r.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid)
lsu.io.axi.r.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id)
lsu.io.axi.r.bits.data := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data)
lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp)
lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last)
ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready)
ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready)
ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready)
ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid)
ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id)
ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data)
ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp)
ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last)
dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready)
dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready)
dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid)
dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp)
dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready)
dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid)
dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id)
dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data)
dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp)
dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid)
dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id)
dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid)
dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data)
dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb)
dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready)
dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid)
dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id)
dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready)
// AHB Signals // AHB Signals
io.haddr := ifu_axi4_to_ahb.io.ahb_haddr io.haddr := ifu_axi4_to_ahb.io.ahb_haddr
io.hburst := ifu_axi4_to_ahb.io.ahb_hburst io.hburst := ifu_axi4_to_ahb.io.ahb_hburst
@ -513,6 +514,38 @@ class quasar extends Module with RequireAsyncReset with lib {
io.dma_hreadyout := 0.U io.dma_hreadyout := 0.U
io.dma_hresp := 0.U io.dma_hresp := 0.U
} }
io.dmi_reg_rdata := 0.U*/
io.haddr := 0.U
io.hburst := 0.U
io.hmastlock := 0.U
io.hprot := 0.U
io.hsize := 0.U
io.htrans := 0.U
io.hwrite := 0.U
io.lsu_haddr := 0.U
io.lsu_hburst := 0.U
io.lsu_hmastlock := 0.U
io.lsu_hprot := 0.U
io.lsu_hsize := 0.U
io.lsu_htrans := 0.U
io.lsu_hwrite := 0.U
io.lsu_hwdata := 0.U
io.sb_haddr := 0.U
io.sb_hburst := 0.U
io.sb_hmastlock := 0.U
io.sb_hprot := 0.U
io.sb_hsize := 0.U
io.sb_htrans := 0.U
io.sb_hwrite := 0.U
io.sb_hwdata := 0.U
io.dma_hrdata := 0.U
io.dma_hreadyout := 0.U
io.dma_hresp := 0.U
io.dmi_reg_rdata := 0.U io.dmi_reg_rdata := 0.U
} }

1
target/.history
View File

@ -3,3 +3,4 @@
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameedakram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameedakram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure

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1157466029 882153738

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["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/build.sbt","a7487a9519e56bfaf46b5c1967a665ac0baa0b73"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}] ["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/build.sbt","a7487a9519e56bfaf46b5c1967a665ac0baa0b73"],["/home/waleedbinehsan/Desktop/Quasar/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}]

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[debug] Checking for meta build source updates [debug] Checking for meta build source updates

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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.scalamacros\",\"name\":\"paradise\",\"revision\":\"2.1.0\",\"configurations\":\"plugin->default(compile)\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Full\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/abdulhameed.akram/Documents/SweRV-Chislified/build.sbt","range":{"$fields":["start","end"],"start":42,"end":43}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chisel-iotesters\",\"revision\":\"1.4.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/abdulhameed.akram/Documents/SweRV-Chislified/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chiseltest\",\"revision\":\"0.2.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/abdulhameed.akram/Documents/SweRV-Chislified/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"}} {"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.scalamacros\",\"name\":\"paradise\",\"revision\":\"2.1.0\",\"configurations\":\"plugin->default(compile)\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Full\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":42,"end":43}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chisel-iotesters\",\"revision\":\"1.4.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chiseltest\",\"revision\":\"0.2.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"}}

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[debug] "not up to date. inChanged = true, force = false [debug] "not up to date. inChanged = true, force = false
[debug] Updating ... [debug] Updating ...
[info] Updating  [debug] Done updating
[info] Resolved dependencies
[info] Updating 
[info] Resolved dependencies
[info] Fetching artifacts of 
[info] Fetched artifacts of 
[debug] Done updating 

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[warn] paradise_2.12.10-2.1.0-sources.jar no longer exists at /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0-sources.jar
[debug] "not up to date. inChanged = false, force = false [debug] "not up to date. inChanged = false, force = false
[debug] Updating ProjectRef(uri("file:/home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/"), "swerv-chislified_withlsu")... [debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/"), "quasar")...
[debug] Done updating ProjectRef(uri("file:/home/abdulhameed.akram/Downloads/SweRV-Chislified_withlsu/"), "swerv-chislified_withlsu") [debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/"), "quasar")

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/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar 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